generate.sh in cores/rocket seems to be outdated, as it cannot be used to build the Rocket chip and use RVFI on it.

The first culprit is the line git clone --recurse-submodules [email protected]:sifive/rocket-chip-grand-central.git rocket-chip, as the repository sifive/rocket-chip-grand-central does not exist. I haven't been able to track down the repo on archive.org / via a google search either. Is it related to the LLVM Grand Central API?

• I have attempted to fix this by simply fetching chipsalliance/rocket-chip instead.

Secondly, the riscv-tools setup is broken, as the riscv-tools hash included in chipsalliance/rocket-chip does not map to any known commit on riscv-tools.

• I have attempted to fix this by simply fetching the newest version of the tools.

By using the two "fixes" mentioned above, I am able to start building the rocket chip. However, after compiling all Scala sources, the following error is generated

cd /home/kasper/riscv-formal/cores/rocket/rocket-chip && java -Xmx2G -Xss8M -cp /home/kasper/riscv-formal/cores/rocket/rocket-chip/rocketchip.jar freechips.rocketchip.system.Generator -td /home/kasper/riscv-formal/cores/rocket/rocket-chip/vsim/generated-src -T freechips.rocketchip.system.TestHarness -C DefaultConfigWithRVFIMonitors
[ERROR HERE -->] Exception in thread "main" java.lang.Exception: Unable to find part "DefaultConfigWithRVFIMonitors" from "ArrayBuffer(DefaultConfigWithRVFIMonitors)", did you misspell it or specify the wrong package path?

It seems that the config with RVFI monitors was specified in the grand-central version of rocket-chip, but is not included in the current release?