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Description
Hello, I am running into failing csrw checks that do not seem to make sense. It seems that one of the assertions does not take the write mask into account where I think it should. For the MISA csr, I am failing the following assertion from rvfi_csrw_check.sv:
assert ((csr_insn_cmask & effective_csr_insn_wdata) == 0);
I've been investigating the trace.vcd counter example that sby produced. It executes the instruction 0x30125173 (csrrwi x2, misa, 4).
Since the MISA csr is read only in this implementation, the write mask rvfi_csr_misa_wmask
is hardwired to 0. As such, the effective_csr_insn_wdata
is the hardwired constant value that the CSR contained out of reset.
since the csr_insn_arg
is 4 from the immediate, the write mask is 0x0000_0000, and funct3[1:0] == 2'b01, the following assignment makes csr_insn_cmask
0x0ffff_fffb:
wire [`RISCV_FORMAL_XLEN-1:0] csr_insn_cmask =
/* CSRRW, CSRRWI */ (rvfi.insn[13:12] == 1) ? ~csr_insn_arg :
/* CSRCS, CSRRCI */ (rvfi.insn[13:12] == 3) ? csr_insn_arg : 0;
Then, since csr_insn_cmask
is nearly all 1s, and the MISA CSR contains a 0x40801104, the above assertion fails.
While I understand that for writable CSRs, this assertion checks that there are no cleared bits that are still 1 in the resultant CSR values, in this case I think the all zero write mask should have some bearing.
Let me know if there is something I am missing, or how I can change the check generation flow to fix this.
Thanks!