Skip to content

Commit 455935c

Browse files
akospasztorakospasztor
committed
Release v1.08
2 parents 828341e + 056d48c commit 455935c

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

45 files changed

+35757
-1985
lines changed

Diff for: ‎CHANGELOG.md

+84
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,84 @@
1+
# Changelog for STM32 Bootloader
2+
3+
## [Unreleased]
4+
- Check checksum of application found on SD card before programming
5+
- Switch to semantic versioning
6+
7+
8+
## [1.08](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.08) - 2018-04-18
9+
### Added
10+
- Verify flash content after programming
11+
- Introduced changelog file
12+
### Changed
13+
- The bootloader is now optimized for a new hardware. Due to new pinout of LEDs, user button and SD card switch, the appropriate defines have been changed in main.h file.
14+
- Bootloader sequence with richer error and debug messages
15+
- Updated SD card driver with DMA support
16+
- Project now uses IAR CMSIS pack
17+
- Updated STM32L4xx CMSIS to 1.4.2
18+
- Updated STM32L4xx HAL library to 1.8.2
19+
### Fixed
20+
- Changed appropriate variable types
21+
- Updated README and sequence graph
22+
- Updated header files
23+
24+
25+
## [1.07](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.07) - 2017-12-08
26+
### Added
27+
- SD card power on/off support
28+
### Changed
29+
- As a result of recent hardware changes introduced in a device that is developed as part of our ongoing projects, the SD card is now powered on/off with a FET controlled by the MCU to minimize energy consumption. Therefore, the SD card has to be manually powered on during initialization.
30+
31+
32+
## [1.06](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.06) - 2017-11-13
33+
### Added
34+
- Introduced RAM_SIZE define to precisely check whether the flash contains valid application upon startup
35+
### Fixed
36+
- CheckForApplication() function
37+
38+
39+
## [1.05](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.05) - 2017-10-30
40+
### Added
41+
- Application-specific configuration defines
42+
### Changed
43+
- Updated STM32L4xx CMSIS to 1.4.1
44+
- Updated STM32L4xx HAL library to 1.8.1
45+
46+
47+
## [1.04](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.04) - 2017-10-16
48+
### Added
49+
- Option to skip programming after flash erase operation
50+
### Changed
51+
- Better visual feedback when no application is found in flash
52+
### Fixed
53+
- General improvements
54+
55+
56+
## [1.03](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.03) - 2017-09-21
57+
### Added
58+
- Support for STM32L496VG MCU
59+
- Multiple build configurations for each supported microcontroller
60+
- Change between different builds with a single click
61+
### Changed
62+
- Updated FatFs to R0.12c
63+
- Updated Cortex-M CMSIS to 4.5
64+
- Updated STM32L4xx CMSIS to 1.4.0
65+
- Updated STM32L4xx HAL library to 1.8.0
66+
67+
68+
## [1.02](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.02) - 2017-08-11
69+
### Fixed
70+
- General improvements
71+
72+
73+
## [1.01](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.01) - 2017-07-25
74+
### Added
75+
- Option for clearing reset flags after startup
76+
### Fixed
77+
- Bootloader sequence graph
78+
- Readme updates
79+
- General improvements
80+
81+
82+
## [1.00](https://github.com/akospasztor/stm32-bootloader/releases/tag/v1.00) - 2017-05-21
83+
### Added
84+
Initial release

Diff for: ‎Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l476xx.h

+1-3
Original file line numberDiff line numberDiff line change
@@ -862,12 +862,10 @@ typedef struct
862862
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
863863
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
864864
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
865-
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
865+
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
866866
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
867867
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
868868
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
869-
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
870-
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
871869
} SPI_TypeDef;
872870

873871

Diff for: ‎Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l496xx.h

+4-7
Original file line numberDiff line numberDiff line change
@@ -505,9 +505,9 @@ typedef struct
505505
__IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
506506
__IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
507507
__IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
508-
uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
509-
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
510-
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
508+
uint32_t RESERVED[236]; /*!< Reserved, Address offset: 0x50-0x3FF */
509+
__IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:0x400-0x7FF */
510+
__IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:0x800-0xBFF */
511511
} DMA2D_TypeDef;
512512

513513
/**
@@ -934,12 +934,10 @@ typedef struct
934934
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
935935
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
936936
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
937-
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
937+
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
938938
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
939939
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
940940
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
941-
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
942-
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
943941
} SPI_TypeDef;
944942

945943

@@ -7777,7 +7775,6 @@ typedef struct
77777775
#define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
77787776
#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
77797777

7780-
77817778
/******************** Bit definition for DMA2D_FGCLUT register **************/
77827779

77837780
/******************** Bit definition for DMA2D_BGCLUT register **************/

Diff for: ‎Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@
118118
*/
119119
#define __STM32L4_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
120120
#define __STM32L4_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */
121-
#define __STM32L4_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
121+
#define __STM32L4_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
122122
#define __STM32L4_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
123123
#define __STM32L4_CMSIS_VERSION ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
124124
|(__STM32L4_CMSIS_VERSION_SUB1 << 16)\

Diff for: ‎Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+41-3
Original file line numberDiff line numberDiff line change
@@ -431,12 +431,12 @@
431431
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
432432
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
433433

434-
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
434+
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
435435
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
436436
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
437437
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
438438
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
439-
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
439+
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
440440

441441
#if defined(STM32L1)
442442
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@@ -2119,6 +2119,21 @@
21192119
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
21202120
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
21212121
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
2122+
2123+
#if defined(STM32WB)
2124+
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
2125+
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
2126+
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
2127+
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
2128+
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
2129+
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
2130+
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
2131+
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
2132+
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
2133+
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
2134+
#define QSPI_IRQHandler QUADSPI_IRQHandler
2135+
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
2136+
21222137
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
21232138
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
21242139
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2787,7 +2802,9 @@
27872802
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
27882803
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
27892804

2790-
#if defined(STM32WB) || defined(STM32G0)
2805+
#if defined(STM32L4)
2806+
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
2807+
#elif defined(STM32WB) || defined(STM32G0)
27912808
#else
27922809
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
27932810
#endif
@@ -3038,6 +3055,16 @@
30383055
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
30393056
#endif
30403057

3058+
#if defined(STM32H7)
3059+
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
3060+
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
3061+
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
3062+
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
3063+
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
3064+
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
3065+
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
3066+
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
3067+
#endif
30413068
/**
30423069
* @}
30433070
*/
@@ -3252,6 +3279,17 @@
32523279
* @}
32533280
*/
32543281

3282+
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
3283+
* @{
3284+
*/
3285+
#if defined(STM32H7)
3286+
#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
3287+
#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
3288+
#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
3289+
#endif
3290+
/**
3291+
* @}
3292+
*/
32553293

32563294
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
32573295
* @{

0 commit comments

Comments
 (0)