diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index da7cb86b..62b4e1f2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -80,7 +80,7 @@ typedef struct { __IO uint32_t erfoks; /**< \b 0x18: FCR ERFOKS Register */ __IO uint32_t intfl; /**< \b 0x1C: FCR INTFL Register */ __IO uint32_t inten; /**< \b 0x20: FCR INTEN Register */ - __R uint32_t rsv_0x24; + __IO uint32_t erfoctrl; /**< \b 0x24: FCR ERFOCTRL Register */ __IO uint32_t frqcntctrl; /**< \b 0x28: FCR FRQCNTCTRL Register */ __IO uint32_t frqcntcmp; /**< \b 0x2C: FCR FRQCNTCMP Register */ __I uint32_t refclk; /**< \b 0x30: FCR REFCLK Register */ @@ -101,6 +101,7 @@ typedef struct { #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: 0x0018 */ #define MXC_R_FCR_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ #define MXC_R_FCR_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ +#define MXC_R_FCR_ERFOCTRL ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: 0x0024 */ #define MXC_R_FCR_FRQCNTCTRL ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: 0x0028 */ #define MXC_R_FCR_FRQCNTCMP ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: 0x002C */ #define MXC_R_FCR_REFCLK ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: 0x0030 */ @@ -236,6 +237,23 @@ typedef struct { /**@} end of group FCR_INTEN_Register */ +/** + * @ingroup fcr_registers + * @defgroup FCR_ERFOCTRL FCR_ERFOCTRL + * @brief ERFO Control Register. + * @{ + */ +#define MXC_F_FCR_ERFOCTRL_CAP_X1_POS 0 /**< ERFOCTRL_CAP_X1 Position */ +#define MXC_F_FCR_ERFOCTRL_CAP_X1 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X1_POS)) /**< ERFOCTRL_CAP_X1 Mask */ + +#define MXC_F_FCR_ERFOCTRL_CAP_X2_POS 7 /**< ERFOCTRL_CAP_X2 Position */ +#define MXC_F_FCR_ERFOCTRL_CAP_X2 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X2_POS)) /**< ERFOCTRL_CAP_X2 Mask */ + +#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS 14 /**< ERFOCTRL_CAP_BYPASS Position */ +#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS ((uint32_t)(0x1UL << MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS)) /**< ERFOCTRL_CAP_BYPASS Mask */ + +/**@} end of group FCR_ERFOCTRL_Register */ + /** * @ingroup fcr_registers * @defgroup FCR_FRQCNTCTRL FCR_FRQCNTCTRL diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 3b2350d7..d49be0aa 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -563,48 +563,48 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 0 /**< BTLELDOCTRL_RF_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 1 /**< BTLELDOCTRL_RF_PD_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 2 /**< BTLELDOCTRL_RF_VSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 4 /**< BTLELDOCTRL_BB_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 0 /**< BTLELDOCTRL_BB_EN Position */ #define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 5 /**< BTLELDOCTRL_BB_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 1 /**< BTLELDOCTRL_BB_PD_EN Position */ #define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 6 /**< BTLELDOCTRL_BB_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 2 /**< BTLELDOCTRL_BB_VSEL Position */ #define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */ -#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 8 /**< BTLELDOCTRL_BB_BP_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 4 /**< BTLELDOCTRL_RF_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 9 /**< BTLELDOCTRL_BB_DISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 5 /**< BTLELDOCTRL_RF_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 10 /**< BTLELDOCTRL_RF_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 6 /**< BTLELDOCTRL_RF_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 8 /**< BTLELDOCTRL_RF_BP_EN Position */ #define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 11 /**< BTLELDOCTRL_RF_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 9 /**< BTLELDOCTRL_RF_DISCH Position */ #define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 12 /**< BTLELDOCTRL_RF_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 10 /**< BTLELDOCTRL_BB_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 11 /**< BTLELDOCTRL_BB_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 13 /**< BTLELDOCTRL_BB_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 12 /**< BTLELDOCTRL_BB_EN_DLY Position */ #define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 13 /**< BTLELDOCTRL_RF_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */ #define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */ + /**@} end of group GCR_BTLELDOCTRL_Register */ /** diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index b9ee605e..9b494050 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -1537,6 +1537,32 @@ + + ERFOCTRL + ERFO Control Register. + 0x24 + read-write + + + CAP_X1 + Load capacitor tuning bit for X1. + 0 + 7 + + + CAP_X2 + Load capacitor tuning bit for X2. + 7 + 7 + + + CAP_BYPASS + Bypass (disable) load capacitors. + 14 + 1 + + + FRQCNTCTRL Frequency Counter Control Register. @@ -2766,86 +2792,86 @@ 0x74 - RF_EN - LDO RF enable. + BB_EN + LDO BB enable. 0 1 - RF_PD_EN - LDO RF Pull Down. + BB_PD_EN + LDO BB Pull Down. 1 1 - RF_VSEL - Voltage Selection for RF LDO + BB_VSEL + Voltage Selection for BB LDO. 2 2 - BB_EN - LDOBB enable. + RF_EN + LDO RF enable. 4 1 - BB_PD_EN - LDO BB Pull DOwn. + RF_PD_EN + LDO RF Pull DOwn. 5 1 - BB_VSEL - LDO BB Voltage Setting. + RF_VSEL + LDO RF Voltage Setting. 6 2 - BB_BP_EN - LDO BB Bypass Enable. + RF_BP_EN + LDO RF Bypass Enable. 8 1 - BB_DISCH - LDO BB Discharge. + RF_DISCH + LDO RF Discharge. 9 1 - RF_BP_EN - LDO RF Bypass Enable. + BB_BP_EN + LDO BB Bypass Enable. 10 1 - RF_DISCH - LDO RF Discharge. + BB_DISCH + LDO BB Discharge. 11 1 - RF_EN_DLY - LDO RF Enable Delay. + BB_EN_DLY + LDO BB Enable Delay. 12 1 - BB_EN_DLY - LDO BB Enable Delay. + RF_EN_DLY + LDO RF Enable Delay. 13 1 - BB_BP_EN_DLY - LDO BB Bypass Enable Delay. + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. 14 1 - RF_BP_EN_DLY - LDO RF Bypass Enable Delay. + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. 15 1 @@ -3515,2530 +3541,78 @@ FAST Fast Slew Rate selected. - 0 - - - SLOW - Slow Slew Rate selected. - 1 - - - - - - - DS0 - GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB0 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - ld - GPIO port pin is in low-drive mode. - 0 - - - hd - GPIO port pin is in high-drive mode. - 1 - - - - - - - DS1 - GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB4 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - PSSEL - GPIO Pull Select Mode. - 0xB8 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - VSSEL - GPIO Voltage Select. - 0xC0 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - - - - I3C0 - Improved Inter-Integrated Circuit. - I3C - 0x50018000 - 32 - - 0x00 - 0x1000 - registers - - - I3C0 - I3C0 IRQ - 26 - - - - CONT_CTRL0 - Controller Control 0 (Configuration) Register. - 0x000 - - - EN - I3C Device Enable. - [1:0] - read-write - - - OFF - Off. - 0 - - - ON - On. - 1 - - - CAP - I23 Bug Target with secondary controller capability. - 2 - - - - - TO_DIS - Disable Timeout error. - [3:3] - read-write - - - HKEEP - High-keepr implementation. - [5:4] - read-write - - - OFF - No high-keeper support. - 0 - - - ON_CHIP - On-chip high-keeper support. - 1 - - - EXT_SDA - External high-keeper support for SDA. - 2 - - - EXT_SCL_SDA - External high-keeper support for SCL and SDA. - 3 - - - - - OD_STOP - Use open-drain speed for STOP. - [6:6] - read-write - - - PP_BAUD - SCL Frequency for push-pull drive. - [11:8] - read-write - - - 1_FCLK - SCL High Period is one FCLK Period. - 0 - - - 2_FCLK - SCL High Period is two FLCK Periods. - 1 - - - 3_FCLK - SCL High Period is three FCLK Period. - 2 - - - 4_FCLK - SCL High Period is four FCLK Period. - 3 - - - 5_FCLK - SCL High Period is five FCLK Period. - 4 - - - 6_FCLK - SCL High Period is six FCLK Period. - 5 - - - 7_FCLK - SCL High Period is seven FCLK Period. - 6 - - - 8_FCLK - SCL High Period is eight FCLK Period. - 7 - - - 9_FCLK - SCL High Period is nine FCLK Period. - 8 - - - 10_FCLK - SCL High Period is ten FCLK Period. - 9 - - - 11_FCLK - SCL High Period is eleven FCLK Period. - 10 - - - 12_FCLK - SCL High Period is twelve FCLK Period. - 11 - - - 13_FCLK - SCL High Period is thirteen FCLK Period. - 12 - - - 14_FCLK - SCL High Period is fourteen FCLK Period. - 13 - - - 15_FCLK - SCL High Period is fifthteen FCLK Period. - 14 - - - 16_FCLK - SCL High Period is sixteen FCLK Period. - 15 - - - - - PP_ADD_LBAUD - Number of FCLK periods to add to the base of SCL low period. - [15:12] - read-write - - - 0_FCLK - Adds zero FCLK periods to the SCL low period. - 0 - - - 1_FCLK - Adds one FCLK period to the SCL low period. - 1 - - - 2_FCLK - Adds two FCLK periods to the SCL low period. - 2 - - - 3_FCLK - Adds three FCLK periods to the SCL low period. - 3 - - - 4_FCLK - Adds four FCLK periods to the SCL low period. - 4 - - - 5_FCLK - Adds five FCLK periods to the SCL low period. - 5 - - - 6_FCLK - Adds six FCLK periods to the SCL low period. - 6 - - - 7_FCLK - Adds seven FCLK periods to the SCL low period. - 7 - - - 8_FCLK - Adds eight FCLK periods to the SCL low period. - 8 - - - 9_FCLK - Adds nine FCLK periods to the SCL low period. - 9 - - - 10_FCLK - Adds ten FCLK periods to the SCL low period. - 10 - - - 11_FCLK - Adds eleven FCLK periods to the SCL low period. - 11 - - - 12_FCLK - Adds twelve FCLK periods to the SCL low period. - 12 - - - 13_FCLK - Adds thirteen FCLK periods to the SCL low period. - 13 - - - 14_FCLK - Adds fourteen FCLK periods to the SCL low period. - 14 - - - 15_FCLK - Adds fifthteen FCLK periods to the SCL low period. - 15 - - - - - OD_LBAUD - Number of PP_BAUD periods minus 1 to make one SCL low period for I3C open-dran periods. - [23:16] - read-write - - - OD_HP - Controls SCL high period for I3C oepn-drain operation. - [24:24] - read-write - - - PP_SKEW - Number of FCLK periods to delay the SDA value change from the SCL edge for I3C push-pull operation. - [27:25] - read-write - - - I2C_BAUD - Detyermines SCL high and low pweriods for I2C mode, in units of OD_BAUD period. - [31:28] - read-write - - - - - TARG_CTRL0 - Target Control 0 (Configuration) Register. - 0x004 - - - EN - Target device enable. - [0:0] - read-write - - - MATCHSS - Match STOP and START. - [2:2] - read-write - - - TO_IGN - Ignore Timeout Errors. - [3:3] - read-write - - - OFFLINE - Rejoin I3C bus with existing dynamic address. - [9:9] - read-write - - - - - TARG_STATUS - Target Status Register. - 0x008 - - - BUSY - Not stopped. - [0:0] - read-only - - - LIST_RESP - Message status - listening/responding or not. - [1:1] - read-only - - - CCCH - CCC is being handled. - [2:2] - read-only - - - RX_SDR - SDR Read. - [3:3] - - - TX_SDR - SDR Write. - [4:4] - - - DAA - Dynamic Address Assignment Mode. - [5:5] - read-only - - - HDR - HDR Mode. - [6:6] - read-only - - - START - START Detected. - [8:8] - read-write - - - ADDRMATCH - Address Matched. - [9:9] - read-write - - - STOP - STOP Detected. - [10:10] - read-write - - - RX_RDY - Receive data ready. - [11:11] - read-only - - - TX_NFULL - TX FIFO is not full, ready to accept more data. - [12:12] - read-write - - - DYNADDR_CHG - Dynamic address changed. - [13:13] - read-write - - - CCC - CCC received. - [14:14] - read-write - - - ERRWARN - An error or warning has occurred. - [15:15] - read-only - - - CCCH_DONE - CCC Handled. - [17:17] - read-write - - - EVENT_REQ - Event Requested. - [18:18] - read-write - - - TARG_RST - Target Reset. - [19:19] - read-write - - - EVENT - Event Status. - [21:20] - read-only - - - NONE - No event. - 0 - - - REQ_PEND - Request not yet sent. - 1 - - - REQ_NACK - Request was sent and NACKed and will be tried again. - 2 - - - REQ_ACK - Request was sent and ACKed. - 3 - - - - - IBI_DIS - Indicates whether IBI events are disabled. - [24:24] - read-only - - - CONTREQ_DIS - Indicates whether bus controller request events are disabled. - [25:25] - read-only - - - HJ_DIS - Indicates whether Hot-Joinevents are disabled. - [27:27] - read-only - - - ACTSTATE - Holds the current activity state. - [29:28] - read-only - - - NORMAL - No latency, normal bus operation. - 0 - - - 1MS_LAT - 1 ms latency. - 1 - - - 100MS_LAT - 100 ms latency. - 2 - - - 10S_LAT - 10 s latency. - 3 - - - - - TIMECTRL - Time Control mode. - [31:30] - read-only - - - DIS - No timing control mode is enabled. - 0 - - - SYNC - Synchronous Mode is enabled. - 1 - - - ASYNC - Asynchronous Mode is enabled. - 2 - - - BOTH - Both synchronous and asynchronous modes are enabled. - 3 - - - - - - - TARG_CTRL1 - Target Control 1 Register. - 0x00C - - - EVENT - Sets respecive I3C target event request. - [1:0] - read-write - - - NORMAL - Normal mode. - 0 - - - IBI - Generate an IBI on the I3C bus. - 1 - - - CONTREQ - Request control of the I3C bus. - 2 - - - HJ - Generate a Hot-Join request. - 3 - - - - - EXTIBI - Indicates there are extended IBI data bytes. - [3:3] - read-write - - - DYNADDR_IDX - Index of dynamic address for the current IBI request. - [7:4] - read-write - - - IBIDATA - Contains the mandatory data byte to be sent when generating an IBI. - [15:8] - read-write - - - - - TARG_INTEN - Target Interrupt Enable Register. - 0x010 - read-write - - - START - START detected. - [8:8] - - - ADDRMATCH - Address matched interrupt. - [9:9] - - - STOP - STOP detected. - [10:10] - - - RX_RDY - Receive data ready. - [11:11] - - - TX_NFULL - Ready for transmit data, - [12:12] - - - DYNADDR_CHG - Dynamic Address Changed interrupt enable. - [13:13] - - - CCC - CCC Reveived Interrupt. - [14:14] - - - ERRWARN - Error or warning interrupt. - [15:15] - - - CCCH_DONE - CCC Handled Interrupt. - [17:17] - - - EVENT_REQ - Event Reqeusted Interrupt. - [18:18] - - - TARG_RST - I3C Target Reset Interrupt. - [19:19] - - - - - TARG_INTCLR - Target Interrupt Clear Register. - 0x014 - write-only - - - START - START detected. - [8:8] - - - ADDRMATCH - Address matched interrupt. - [9:9] - - - STOP - STOP detected. - [10:10] - - - RX_RDY - Receive data ready. - [11:11] - - - TX_NFULL - Ready for transmit data, - [12:12] - - - DYNADDR_CHG - Dynamic Address Changed interrupt enable. - [13:13] - - - CCC - CCC Reveived Interrupt. - [14:14] - - - ERRWARN - Error or warning interrupt. - [15:15] - - - CCCH_DONE - CCC Handled Interrupt. - [17:17] - - - EVENT_REQ - Event Reqeusted Interrupt. - [18:18] - - - TARG_RST - I3C Target Reset Interrupt. - [19:19] - - - - - TARG_INTFL - Target Interrupt Flag Register. - 0x018 - read-only - - - START - START detected. - [8:8] - - - ADDRMATCH - Address matched interrupt. - [9:9] - - - STOP - STOP detected. - [10:10] - - - RX_RDY - Receive data ready. - [11:11] - - - TX_NFULL - Ready for transmit data, - [12:12] - - - DYNADDR_CHG - Dynamic Address Changed interrupt enable. - [13:13] - - - CCC - CCC Reveived Interrupt. - [14:14] - - - ERRWARN - Error or warning interrupt. - [15:15] - - - CCCH_DONE - CCC Handled Interrupt. - [17:17] - - - EVENT_REQ - Event Reqeusted Interrupt. - [18:18] - - - TARG_RST - I3C Target Reset Interrupt. - [19:19] - - - - - TARG_ERRWARN - Target Error and Warning Register. - 0x01C - read-write - - - OVR - Internal FIFO overrun flag. - [0:0] - - - UNR - Internal FIFO underrun flag. - [1:1] - - - UNR_NACK - I3C or I2C mode address emitted by the IP was NACKed by the targets. - [2:2] - - - CONT_RX_TERM - Controller terminated read in message mode. - [3:3] - - - INVSTART - Invalid START. - [4:4] - - - SDR_PAR - SDR Parity Error. - [8:8] - - - TO - Timeout Error. - [11:11] - - - RX_UNR - Read data underrun. - [16:16] - - - TX_OVR - Write data overrun. - [17:17] - - - - - TARG_DMACTRL - Target DMA Control Register. - 0x020 - read-write - - - RX_EN - DMA read enable. - [1:0] - - - DIS - Disable DMA. - 0 - - - ONE_FR - Enable DMA for one frame. - 1 - - - EN - Enable DMA until disabled by setting this field to 0b00. - 2 - - - - - TX_EN - DMA write enable. - [3:2] - - - DIS - Disable DMA. - 0 - - - ONE_FR - Enable DMA for one frame. - 1 - - - EN - Enable DMA until disabled by setting this field to 0b00. - 2 - - - - - WIDTH - Selects the data width for DMA transfers. - [5:4] - - - BYTE - Byte size. - 0 - - - HALFWORD - Halfword size. - 2 - - - - - - - TARG_FIFOCTRL - Target FIFO Control Register. - 0x02C - - - TX_FLUSH - Flush TX FIFO. - [0:0] - write-only - - - RX_FLUSH - Flush RX FIFO. - [1:1] - write-only - - - UNLOCK - Unlock FIFO Triggers. - [3:3] - write-only - - - TX_THD_LVL - TX FIFO trigger level. - [5:4] - read-write - - - EMPTY - Trigger when empty. - 0 - - - QUARTER_FULL - Trigger when quarter full or less. - 1 - - - HALF_FULL - Trigger when half full or less. - 2 - - - ALMOST_FULL - Trigger when almost full or less. - 3 - - - - - RX_THD_LVL - RX FIFO trigger level. - [7:6] - read-write - - - NOT_EMPTY - Trigger when empty. - 0 - - - QUARTER_FULL - Trigger when quarter full or less. - 1 - - - HALF_FULL - Trigger when half full or less. - 2 - - - 3_QUARTER_FULL - Trigger when 3 quarters full or less. - 3 - - - - - TX_LVL - Number of messages in TX FIFO. - [21:16] - read-only - - - RX_LVL - Number of messages in RX FIFO. - [29:24] - read-only - - - TX_FULL - TX FIFO Full flag. - [30:30] - read-only - - - RX_EM - RX FIFO Empty Flag. - [31:31] - read-only - - - - - TARG_TXFIFO8 - Target Write Byte Data Register. - 0x030 - write-only - - - DATA - Data byte to send. - [7:0] - - - END - End of data. - [8:8] - - - END2 - End of data. - [16:16] - - - - - TARG_TXFIFO8E - Target Write Byte Data as End Register. - 0x034 - write-only - - - DATA - Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. - [7:0] - - - - - TARG_TXFIFO16 - Target Write Half-Word Data Register. - 0x038 - write-only - - - DATA - Data halfword to send. - [15:0] - - - END - End of data. - [16:16] - - - - - TARG_TXFIFO16E - Target Write Half-Word Data as End Register. - 0x03C - write-only - - - DATA - Data halfword to send. - [15:0] - - - - - TARG_RXFIFO8 - Target Read Byte Data Register. - 0x040 - read-only - - - DATA - Read data byte from RX FIFO. - [7:0] - - - - - TARG_RXFIFO16 - Target Read Half-Word Data Register. - 0x048 - read-only - - - DATA - Read data hyalfword from RX FIFO. - [15:0] - - - - - TARG_TXFIFO8O - Target Byte-Only Write Byte Data Register. - 0x054 - write-only - - - DATA - Data byte to send. - [7:0] - - - - - TARG_CAP0 - Target Capabilities 0 Register. - 0x05C - read-only - - - MAPCNT - Number of mapped target addresses supported. - [3:0] - - - I2C_10BADDR - I2C 10-bit address support. - [4:4] - - - I2C_SWRST - I2C Software Reset Support. - [5:5] - - - I2C_DEVID - I2C Device ID Support. - [6:6] - - - FIFO32_REG - FIFO 32 registers available. - [7:7] - - - EXTIBI - Extended IBI data support. - [8:8] - - - EXTIBI_REG - Extended IBI data register support. - [9:9] - - - HDRBT_LANES - Multi-lane support for HDR-BT mode. - [13:12] - - - CCC_V1_1 - CCC V1.1 Support. - [16:16] - - - TARG_RST - Target Reset Support. - [17:17] - - - GROUPADDR - Group address support. - [19:18] - - - AASA_CCC - SETAASA CCC Support. - [21:21] - - - T2T_SUBSC - Target-to-target subscriber support. - [22:22] - - - T2T_WR - Target-to-target write support. - [23:23] - - - - - TARG_CAP1 - TARG_Capabilities 1 Register. - 0x060 - read-only - - - PROVID - Provisioned ID implementation. - [1:0] - - - PROVID_REG - Provision ID, Bus Characteristics, Device Characteristics implementation. - [5:2] - - - HDR_MODES - Supported HDR modes. - [8:6] - - - CONT - Controller mode capable. - [9:9] - - - STATADDR - I2C-style static address implementation. - [11:10] - - - CCCH - CCC Handled by IP. - [15:12] - - - BASIC - Basic CCCs. - 1 - - - LIMITS - CCCs related to maximum transfer lengths and speed. - 2 - - - INTACT - Pending Interrupt and Activity Mode fields of GETSTATUS CCC. - 4 - - - VENDOR - Vendor Reserved field of GETSTATUS CCC. - 8 - - - - - IBI_EVENTS - Supported IBI events. - [20:16] - - - IBI - IBI support. - 1 - - - PAYLOAD - IBI has payload. - 2 - - - CONTREQ - Controller request support. - 4 - - - HJ - Hot-Join support. - 8 - - - BAMATCH - Use BAMATCH field of CONFIG register to measure 1us Bus Available timing. - 16 - - - - - TIMECTRL - Timing Control Support. - [21:21] - - - EXTFIFO - External FIFO configuration. - [25:23] - - - TXFIFO_CFG - TX FIFO configuration. - [27:26] - - - RXFIFO_CFG - RX FIFO configuration. - [29:28] - - - INTR - Interrupt support. - [30:30] - - - DMA - DMA support. - [31:31] - - - - - TARG_DYNADDR - Target Dynamic Address Register. - 0x064 - read-write - - - VALID - Address valid check. - [0:0] - - - ADDR - The assigned dynamic address. - [7:1] - - - CAUSE - Indicates how the last primary dynnamic address value change occurred. - [10:8] - - - - - TARG_MAXLIMITS - Maximum Limits Register. - 0x068 - read-write - - - RX - The maximum number of bytes that the I3C controller may read from this I3C target device per message. - [11:0] - - - TX - The maximum number of bytes that the I3C controller may write from this I3C target device per message. - [27:16] - - - - - TARG_IDEXT - ID Extension Register. - 0x070 - read-write - - - DEVCHAR - Device Characteristics Register. - [15:8] - - - BUSCHAR - Bus Characteristics Register. - [23:16] - - - - - TARG_MSGLAST - Target Matching Address Index Register. - 0x07C - read-only - - - IDX - Index or group number of last matched address. - [3:0] - - - STATADDR - Last matched address was a I2C static address. - [4:4] - - - GROUP - Last matched address was a group address. - [5:5] - - - MODE - Indicates the mode of the last access. - [7:6] - - - DYN_STAT_ADDR - I3C SDR or I2C - 0 - - - HDR_DDR - HDR-DDR. - 1 - - - HDR_BT - HDR-BT. - 2 - - - - - PREV_IDX - Index or group number of previous matched address. - [11:8] - - - PREV_GROUP - Last matched address was a previous group address. - [13:13] - - - PREV_MODE - Indicates the mode of the previous access. - [15:14] - - - DYN_STAT_ADDR - I3C SDR or I2C - 0 - - - HDR_DDR - HDR-DDR. - 1 - - - HDR_BT - HDR-BT. - 2 - - - - - SECPREV_IDX - Index or group number of secondary previous matched address. - [19:16] - - - SECPREV_GROUP - Last matched address was a secondary previous group address. - [21:21] - - - SECPREV_MODE - Indicates the mode of the secondary previous access. - [23:22] - - - DYN_STAT_ADDR - I3C SDR or I2C - 0 - - - HDR_DDR - HDR-DDR. - 1 - - - HDR_BT - HDR-BT. - 2 - - - - - - - CONT_CTRL1 - Controller Control 1 Register. - 0x084 - - - REQ - Requests an I3C or I2C bus operation. - [2:0] - read-write - - - NONE - None operation. - 0 - - - EMIT_START - Emit a START with address and read-write bit from stopped state or in the middle of an SDR message. - 1 - - - EMIT_STOP - Emit a STOP. - 2 - - - IBI_ACKNACK - Manually ACK or NACK an IBI. - 3 - - - PROCESS_DAA - Process Dynamic Address Assignment. - 4 - - - EXIT_RST - Emit HDR Exit Pattern or Target Reset pattern. - 6 - - - AUTO_IBI - Automatic IBI response. - 7 - - - - - TYPE - Controls type of operation for REQ field. - [5:4] - read-write - - - IBIRESP - Response to use when an IBI occurs. - [7:6] - read-write - - - RDWR_DIR - Direction of the transfer. - [8:8] - read-write - - - ADDR - Address to send with START. - [15:9] - read-write - - - TERM_RD - Termination count for read. - [23:16] - read-write - - - - - CONT_STATUS - Controller Status Register. - 0x088 - - - STATE - Current working state. - [2:0] - read-only - - - IDLE - Bus Idle. - 0 - - - TARG_REQ - I3C Bus i stopped and a target is holding SDA low. - 1 - - - SDR_TXSDRMSG - SDR Message Mode using SDRMSG registers. - 2 - - - SDR_NORM - Normal SDR message mode. - 3 - - - DDR - DDR Message mode - 4 - - - DAA - Dynamic Address Assignment mode. - 5 - - - IBI_ACKNACK - IP is waiting for the application to provide an ACK or NACK decision. - 6 - - - IBI_RX - IP is receiving an IBI. - 7 - - - - - WAIT - Depending on STATE, WAIT is 1 when it's waiting in an intermediary state. - [4:4] - read-only - - - NACK - Address was NACKed. - [5:5] - read-only - - - IBITYPE - The type of event for which arbitration was last won. - [7:6] - - - NONE - None. - 0 - - - IBI - In-band Interrupt. - 1 - - - CONT_REQ - Controller request. - 2 - - - HOTJOIN_REQ - Hot-Join request. - 3 - - - - - TARG_START - Target START detected. - [8:8] - - - REQ_DONE - CTRL1 Request completed. - [9:9] - read-only - - - DONE - Message completed. - [10:10] - read-write - - - RX_RDY - Receive data ready. - [11:11] - read-only - - - TX_NFULL - TX FIFO Not Full flag. - [12:12] - read-only - - - IBI_WON - IBI Arbitration won. - [13:13] - read-write - - - ERRWARN - Error or warning status. - [15:15] - read-only - - - CONT_TRANS - IP transitioned from I3C target to controller. - [19:19] - read-write - - - IBI_ADDR - The address of a received IBI or dcontroller request. - [30:24] - read-only - - - - - CONT_IBIRULES - Controller IBI Registry and Rules Register. - 0x08C - - - ADDR0 - Target 0 dynamic address. - [5:0] - read-write - - - ADDR1 - Target 1 dynamic address. - [11:6] - read-write - - - ADDR2 - Target 2 dynamic address. - [17:12] - read-write - - - ADDR3 - Target 3 dynamic address. - [23:18] - read-write - - - ADDR4 - Target 4 dynamic address. - [29:24] - read-write - - - MSB0 - Implementation of MSb for I3C dynamic addresses. - [30:30] - read-write - - - NOBYTE - Specifies the function of ADDR0 to ADDR4 - [31:31] - read-write - - - - - CONT_INTEN - Controller Interrupt Enable Register. - 0x090 - read-write - - - TARG_START - Target Start Detected. - [8:8] - - - REQ_DONE - CTRL request completed. - [9:9] - - - DONE - Message complete. - [10:10] - - - RX_RDY - Receive data ready. - [11:11] - - - TX_NFULL - Ready for transmit data, - [12:12] - - - IBI_WON - IBI arbitration won. - [13:13] - - - ERRWARN - Error or warning interrupt. - [15:15] - - - NOW_CONT - The IP transitioned from I3C bus target to I3C bus controller. - [19:19] - - - - - CONT_INTCLR - Controller Interrupt Clear Register. - 0x094 - write-only - - - TARG_START - Target Start Detected. - [8:8] - - - REQ_DONE - CTRL request completed. - [9:9] - - - DONE - Message complete. - [10:10] - - - RX_RDY - Receive data ready. - [11:11] - - - TX_NFULL - Ready for transmit data, - [12:12] - - - IBI_WON - IBI arbitration won. - [13:13] - - - ERRWARN - Error or warning interrupt. - [15:15] - - - NOW_CONT - The IP transitioned from I3C bus target to I3C bus controller. - [19:19] - - - - - CONT_INTFL - Controller Interrupt Flag Register. - 0x098 - read-only - - - TARG_START - Target Start Detected. - [8:8] - - - REQ_DONE - CTRL request completed. - [9:9] - - - DONE - Message complete. - [10:10] - - - RX_RDY - Receive data ready. - [11:11] - - - TX_NFULL - Ready for transmit data, - [12:12] - - - IBI_WON - IBI arbitration won. - [13:13] - - - ERRWARN - Error or warning interrupt. - [15:15] - - - NOW_CONT - The IP transitioned from I3C bus target to I3C bus controller. - [19:19] - - - - - CONT_ERRWARN - Controller Error and Warning Register. - 0x09C - read-write - - - NACK - I3C or I2C mode address emitted by the IP was NACKed by the targets. - [2:2] - - - TX_ABT - Write aborted due to data NACK. - [3:3] - - - RX_TERM - Controller terminated read in messaage mode. - [4:4] - - - HDR_PAR - HDR Parity Error. - [9:9] - - - HDR_CRC - HDR-DDR CRC Error. - [10:10] - - - RX_UNR - Read data underrun. - [16:16] - - - TX_OVR - Write data overrun. - [17:17] - - - MSG - Message mode error. - [18:18] - - - INV_REQ - Invalid use of request from CTRL register. - [19:19] - - - TO - Timeout error. - [20:20] - - - - - CONT_DMACTRL - Controller DMA Control Register. - 0x0A0 - read-write - - - RX_EN - DMA read enable. - [1:0] - - - DIS - Disable DMA. - 0 - - - ONE_FR - Enable DMA for one frame. - 1 - - - EN - Enable DMA until disabled by setting this field to 0b00. - 2 - - - - - TX_EN - DMA write enable. - [3:2] - - - DIS - Disable DMA. - 0 - - - ONE_FR - Enable DMA for one frame. - 1 - - - EN - Enable DMA until disabled by setting this field to 0b00. - 2 - - - - - WIDTH - Selects the data width for DMA transfers. - [5:4] - - - BYTE - Byte size. - 0 - - - HALFWORD - Halfword size. - 2 - - - - - - - CONT_FIFOCTRL - Controller FIFO Control Register. - 0x0AC - - - TX_FLUSH - Flush TX FIFO. - [0:0] - write-only - - - RX_FLUSH - Flush RX FIFO. - [1:1] - write-only - - - UNLOCK - Unlock FIFO Triggers. - [3:3] - write-only - - - TX_THD_LVL - TX FIFO trigger level. - [5:4] - read-write - - - EMPTY - Trigger when empty. - 0 - - - QUARTER_FULL - Trigger when quarter full or less. - 1 - - - HALF_FULL - Trigger when half full or less. - 2 - - - ALMOST_FULL - Trigger when almost full or less. - 3 - - - - - RX_THD_LVL - RX FIFO trigger level. - [7:6] - read-write - - - NOT_EMPTY - Trigger when empty. - 0 - - - QUARTER_FULL - Trigger when quarter full or less. - 1 - - - HALF_FULL - Trigger when half full or less. - 2 - - - 3_QUARTER_FULL - Trigger when 3 quarters full or less. - 3 - - - - - TX_LVL - Number of messages in TX FIFO. - [21:16] - read-only - - - RX_LVL - Number of messages in RX FIFO. - [29:24] - read-only - - - TX_FULL - TX FIFO Full flag. - [30:30] - read-only - - - RX_EM - RX FIFO Empty Flag. - [31:31] - read-only - - - - - CONT_TXFIFO8 - Controller Write Byte Data Register. - 0x0B0 - write-only - - - DATA - Data byte to send. - [7:0] - - - END - End of data. - [8:8] - - - END2 - End of data. - [16:16] - - - - - CONT_TXFIFO8E - Controller Write Byte Data as End Register. - 0x0B4 - write-only - - - DATA - Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. - [7:0] - - - - - CONT_TXFIFO16 - Controller Write Half-Word Data Register. - 0x0B8 - write-only - - - DATA - Data halfword to send. - [15:0] - - - END - End of data. - [16:16] - - - - - CONT_TXFIFO16E - Controller Write Half-Word Data as End Register. - 0x0BC - write-only - - - DATA - Data halfword to send. - [15:0] - - - - - CONT_RXFIFO8 - Controller Read Byte Data Register. - 0x0C0 - read-only - - - DATA - Read data byte from RX FIFO. - [7:0] - - - - - CONT_RXFIFO16 - Controller Read Half-Word Data Register. - 0x0C8 - read-only - - - DATA - Read data hyalfword from RX FIFO. - [15:0] - - - - - CONT_TXFIFO8O - Controller Byte-Only Write Byte Data Register. - 0x0CC - write-only - - - DATA - Data byte to send. - [7:0] - - - - - CONT_TXSDRMSG_CTRL - Controller Start or Continue SDR Message Register. - 0x0D0 - read-write - - - RDWR_DIR - Direction of the transfer. - [0:0] - - - ADDR - Destination address of message. - [7:1] - - - END - Select how to end message. - [8:8] - - - I2C_EN - I2C Mode Enable. - [10:10] - - - LEN - Message length in bytes. - [15:11] - - - - - CONT_TXSDRMSG_FIFO - Controller Start or Continue SDR Message Register. - 0x0D0 - write-only - - - DATA - Data for SDR write message after control information has been written. - [15:0] - - - - - CONT_RXSDRMSG - Controller Read SDR Message Data Register. - 0x0D4 - read-only - - - DATA - Data for SDR write message after control information has been written. - [15:0] - - - - - CONT_TXDDRMSG - Controller Start or Continue DDR Message Register. - 0x0D8 - write-only - - - MSG - Data, address/command, and control information. - [15:0] - - - - - CONT_RXDDR16 - Controller Read DDR Message Data Register. - 0x0DC - read-only - - - DATA - Read data (16bits). - [15:0] - - - - - CONT_DYNADDR - Controller Dynamic Address Register. - 0x0E4 - read-write - - - ADDR - The assigned dynamic address. - [7:1] - - - VALID - Address valid check. - [8:8] + 0 + + + SLOW + Slow Slew Rate selected. + 1 + + - TARG_GROUPDEF - Target Group Definition Register. - 0x114 - read-only + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 - ADDR_EN - Group Address enable. - [0:0] - - - ADDR - Group Address . - [7:1] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + - TARG_MAPCTRL0 - Target Primary Map Control Register. - 0x11C - read-write + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 - DYNADDR_EN - Dynamic address is enabled. - [0:0] - - - DYNADDR - Dynamic address. - [7:1] - - - CAUSE - Indicates how the last primary dynamic address value change occurred. - [10:8] + ALL + Mask of all of the pins on the port. + 0 + 32 - TARG_MAPCTRL1 - Target Map Control 1 Register. - 0x120 - read-write + PSSEL + GPIO Pull Select Mode. + 0xB8 - EN - Mapped address slot is enabled. - [0:0] - - - ADDR - Static or Dynamic address. - [7:1] - - - STATADDR_EN - ADDR field contains the I2C static address if enabled. - [8:8] - - - STATADDR_10B - Contains the upper 3 bits of a 10-bit I2C Static Address. - [11:9] - - - NACK - Indicates how the last primary dynamic address value change occurred. - [12:12] + ALL + Mask of all of the pins on the port. + 0 + 32 - TARG_MAPCTRL2 - Target Map Control 2 Register. - 0x124 - read-write + VSSEL + GPIO Voltage Select. + 0xC0 - EN - Mapped address slot is enabled. - [0:0] - - - ADDR - Static or Dynamic address. - [7:1] - - - STATADDR_EN - ADDR field contains the I2C static address if enabled. - [8:8] - - - NACK - Indicates how the last primary dynamic address value change occurred. - [12:12] - - - AUTO_EN - Enable slot for automatic dynamic address assignment. - [13:13] - - - PID - Indicates how the last primary dynamic address value change occurred. - [31:14] + ALL + Mask of all of the pins on the port. + 0 + 32 @@ -6046,9 +3620,11 @@ - ICC - Instruction Cache Controller Registers - 0x4002A000 + I3C0 + Improved Inter-Integrated Circuit. + I3C + 0x50018000 + 32 0x00 0x1000 @@ -8755,12 +6331,6 @@ 0 1 - - RSTZ - Reset RSTZ Controller. - 1 - 1 - @@ -8783,7 +6353,7 @@ CLKSEL - Clock select for RTC, WUTs, and Timers. + Clcok Select for the RTC, System, WUT, and Timer. 0 2 @@ -8793,49 +6363,49 @@ 0 - INRO + INRO_DIV4 INRO as clock source. 1 - EXTCLK + RTC_IN_DIV8 P0.12 div 8 as clock source. 2 - ERTCO_32KHZ_EN - Enable ERTCO 32KHz while ERTCO_EN. + ERTCO32K_EN + Enable the 32KHz ERTCO. 3 1 ERTCO_EN - Enable ERTCO 4KHz. + Enable the ERTCO. 5 1 - BBREG0 - Battery Back Reg0. + BYPASS0 + This register is used by firmware to bypass chain of trust on a Warm Boot. 0x30 - BBREG1 - Battery Back Reg1. + BYPASS1 + This register is used by firmware to bypass chain of trust on a Warm Boot. 0x34 - BBDATA0 - Battery Back Data0 Register. + DATA0 + Battery Back Data0 Register. Retains value in all modes. 0x40 - BBDATA1 - Battery Back Data1 Register. + DATA1 + Battery Back Data1 Register. Retains value in all modes. 0x44 @@ -12661,7 +10231,7 @@ TRIMSIR - Trim System Initilazation Registers + Trim System Initilazation Registers. 0x50005400 0x00 @@ -12670,167 +10240,29 @@ - RTC - RTC Trim System Initialization Register. - 0x08 - - - X1TRIM - RTC X1 Trim. - 16 - 5 - - - X2TRIM - RTC X2 Trim. - 21 - 5 - - - LOCK - Lock. - 31 - 1 - - - - - SIMO - SIMO Trim System Initialization Register. - 0x34 - read-only - - - CLKDIV - SIMO Clock Divide. - 0 - 3 - - - DIV1 - 0 - - - DIV16 - 1 - - - DIV32 - 3 - - - DIV64 - 5 - - - DIV128 - 7 - - - - - - - IPOLO - IPO Low Trim System Initialization Register. + RTCX1 + RTC X2 Capacitor Setting. 0x3C read-only - IPO_LIMITLO - IPO Low Limit Trim. - 0 - 8 - - - - - CTRL - Control Trim System Initialization Register. - 0x40 - - - VDDA_LIMITLO - VDDA Low Trim Limit. + CAP + RTC X1 Load Capacitor Setting. 0 - 7 - - - VDDA_LIMITHI - VDDA High Trim Limit. - 8 - 7 - - - IPO_LIMITHI - IPO High Trim Limit. - 15 - 9 - - - INRO_SEL - INRO Clock Select. - 24 - 2 - - - 8KHZ - 0 - - - 16KHZ - 1 - - - 30KHZ - 2 - - - - - INRO_TRIM - INRO Clock Trim. - 29 - 3 + 5 - INRO - RTC Trim System Initialization Register. + RTCX2 + RTC X2 Capacitor Setting. 0x44 - TRIM16K - INRO 16KHz Trim. + CAP + RTC X2 Load Capacitor Setting. 0 - 3 - - - TRIM30K - INRO 30KHz Trim. - 3 - 3 - - - LPCLKSEL - INRO Low Power Mode Clock Select. - 6 - 2 - - - 8KHZ - 0 - - - 16KHZ - 1 - - - 30KHZ - 2 - - + 5 @@ -14502,4 +11934,4 @@ - + \ No newline at end of file diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index 0334c680..039c7940 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -78,11 +78,11 @@ typedef struct { __R uint32_t rsv_0xc; __IO uint32_t ctrl; /**< \b 0x10: MCR CTRL Register */ __R uint32_t rsv_0x14_0x2f[7]; - __IO uint32_t bbreg0; /**< \b 0x30: MCR BBREG0 Register */ - __IO uint32_t bbreg1; /**< \b 0x34: MCR BBREG1 Register */ + __IO uint32_t bypass0; /**< \b 0x30: MCR BYPASS0 Register */ + __IO uint32_t bypass1; /**< \b 0x34: MCR BYPASS1 Register */ __R uint32_t rsv_0x38_0x3f[2]; - __IO uint32_t bbdata0; /**< \b 0x40: MCR BBDATA0 Register */ - __IO uint32_t bbdata1; /**< \b 0x44: MCR BBDATA1 Register */ + __IO uint32_t data0; /**< \b 0x40: MCR DATA0 Register */ + __IO uint32_t data1; /**< \b 0x44: MCR DATA1 Register */ } mxc_mcr_regs_t; /* Register offsets for module MCR */ @@ -95,10 +95,10 @@ typedef struct { #define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ -#define MXC_R_MCR_BBREG0 ((uint32_t)0x00000030UL) /**< Offset from MCR Base Address: 0x0030 */ -#define MXC_R_MCR_BBREG1 ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: 0x0034 */ -#define MXC_R_MCR_BBDATA0 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: 0x0040 */ -#define MXC_R_MCR_BBDATA1 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: 0x0044 */ +#define MXC_R_MCR_BYPASS0 ((uint32_t)0x00000030UL) /**< Offset from MCR Base Address: 0x0030 */ +#define MXC_R_MCR_BYPASS1 ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: 0x0034 */ +#define MXC_R_MCR_DATA0 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: 0x0040 */ +#define MXC_R_MCR_DATA1 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: 0x0044 */ /**@} end of group mcr_registers */ /** @@ -110,9 +110,6 @@ typedef struct { #define MXC_F_MCR_RST_BOOST_POS 0 /**< RST_BOOST Position */ #define MXC_F_MCR_RST_BOOST ((uint32_t)(0x1UL << MXC_F_MCR_RST_BOOST_POS)) /**< RST_BOOST Mask */ -#define MXC_F_MCR_RST_RSTZ_POS 1 /**< RST_RSTZ Position */ -#define MXC_F_MCR_RST_RSTZ ((uint32_t)(0x1UL << MXC_F_MCR_RST_RSTZ_POS)) /**< RST_RSTZ Mask */ - /**@} end of group MCR_RST_Register */ /** @@ -136,13 +133,13 @@ typedef struct { #define MXC_F_MCR_CTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ #define MXC_V_MCR_CTRL_CLKSEL_ERTCO ((uint32_t)0x0UL) /**< CTRL_CLKSEL_ERTCO Value */ #define MXC_S_MCR_CTRL_CLKSEL_ERTCO (MXC_V_MCR_CTRL_CLKSEL_ERTCO << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ERTCO Setting */ -#define MXC_V_MCR_CTRL_CLKSEL_INRO ((uint32_t)0x1UL) /**< CTRL_CLKSEL_INRO Value */ -#define MXC_S_MCR_CTRL_CLKSEL_INRO (MXC_V_MCR_CTRL_CLKSEL_INRO << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_INRO Setting */ -#define MXC_V_MCR_CTRL_CLKSEL_EXTCLK ((uint32_t)0x2UL) /**< CTRL_CLKSEL_EXTCLK Value */ -#define MXC_S_MCR_CTRL_CLKSEL_EXTCLK (MXC_V_MCR_CTRL_CLKSEL_EXTCLK << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_EXTCLK Setting */ +#define MXC_V_MCR_CTRL_CLKSEL_INRO_DIV4 ((uint32_t)0x1UL) /**< CTRL_CLKSEL_INRO_DIV4 Value */ +#define MXC_S_MCR_CTRL_CLKSEL_INRO_DIV4 (MXC_V_MCR_CTRL_CLKSEL_INRO_DIV4 << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_INRO_DIV4 Setting */ +#define MXC_V_MCR_CTRL_CLKSEL_RTC_IN_DIV8 ((uint32_t)0x2UL) /**< CTRL_CLKSEL_RTC_IN_DIV8 Value */ +#define MXC_S_MCR_CTRL_CLKSEL_RTC_IN_DIV8 (MXC_V_MCR_CTRL_CLKSEL_RTC_IN_DIV8 << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_RTC_IN_DIV8 Setting */ -#define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS 3 /**< CTRL_ERTCO_32KHZ_EN Position */ -#define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS)) /**< CTRL_ERTCO_32KHZ_EN Mask */ +#define MXC_F_MCR_CTRL_ERTCO32K_EN_POS 3 /**< CTRL_ERTCO32K_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO32K_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO32K_EN_POS)) /**< CTRL_ERTCO32K_EN Mask */ #define MXC_F_MCR_CTRL_ERTCO_EN_POS 5 /**< CTRL_ERTCO_EN Position */ #define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h index 701e00c7..bd2d9012 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -64,7 +64,7 @@ extern "C" { * @ingroup trimsir * @defgroup trimsir_registers TRIMSIR_Registers * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. - * @details Trim System Initilazation Registers + * @details Trim System Initilazation Registers. */ /** @@ -72,14 +72,10 @@ extern "C" { * Structure type to access the TRIMSIR Registers. */ typedef struct { - __R uint32_t rsv_0x0_0x7[2]; - __IO uint32_t rtc; /**< \b 0x08: TRIMSIR RTC Register */ - __R uint32_t rsv_0xc_0x33[10]; - __I uint32_t simo; /**< \b 0x34: TRIMSIR SIMO Register */ - __R uint32_t rsv_0x38; - __I uint32_t ipolo; /**< \b 0x3C: TRIMSIR IPOLO Register */ - __IO uint32_t ctrl; /**< \b 0x40: TRIMSIR CTRL Register */ - __IO uint32_t inro; /**< \b 0x44: TRIMSIR INRO Register */ + __R uint32_t rsv_0x0_0x3b[15]; + __I uint32_t rtcx1; /**< \b 0x3C: TRIMSIR RTCX1 Register */ + __R uint32_t rsv_0x40; + __IO uint32_t rtcx2; /**< \b 0x44: TRIMSIR RTCX2 Register */ } mxc_trimsir_regs_t; /* Register offsets for module TRIMSIR */ @@ -89,113 +85,31 @@ typedef struct { * @brief TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address. * @{ */ -#define MXC_R_TRIMSIR_RTC ((uint32_t)0x00000008UL) /**< Offset from TRIMSIR Base Address: 0x0008 */ -#define MXC_R_TRIMSIR_SIMO ((uint32_t)0x00000034UL) /**< Offset from TRIMSIR Base Address: 0x0034 */ -#define MXC_R_TRIMSIR_IPOLO ((uint32_t)0x0000003CUL) /**< Offset from TRIMSIR Base Address: 0x003C */ -#define MXC_R_TRIMSIR_CTRL ((uint32_t)0x00000040UL) /**< Offset from TRIMSIR Base Address: 0x0040 */ -#define MXC_R_TRIMSIR_INRO ((uint32_t)0x00000044UL) /**< Offset from TRIMSIR Base Address: 0x0044 */ +#define MXC_R_TRIMSIR_RTCX1 ((uint32_t)0x0000003CUL) /**< Offset from TRIMSIR Base Address: 0x003C */ +#define MXC_R_TRIMSIR_RTCX2 ((uint32_t)0x00000044UL) /**< Offset from TRIMSIR Base Address: 0x0044 */ /**@} end of group trimsir_registers */ /** * @ingroup trimsir_registers - * @defgroup TRIMSIR_RTC TRIMSIR_RTC - * @brief RTC Trim System Initialization Register. + * @defgroup TRIMSIR_RTCX1 TRIMSIR_RTCX1 + * @brief RTC X2 Capacitor Setting. * @{ */ -#define MXC_F_TRIMSIR_RTC_X1TRIM_POS 16 /**< RTC_X1TRIM Position */ -#define MXC_F_TRIMSIR_RTC_X1TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X1TRIM_POS)) /**< RTC_X1TRIM Mask */ +#define MXC_F_TRIMSIR_RTCX1_CAP_POS 0 /**< RTCX1_CAP Position */ +#define MXC_F_TRIMSIR_RTCX1_CAP ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTCX1_CAP_POS)) /**< RTCX1_CAP Mask */ -#define MXC_F_TRIMSIR_RTC_X2TRIM_POS 21 /**< RTC_X2TRIM Position */ -#define MXC_F_TRIMSIR_RTC_X2TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X2TRIM_POS)) /**< RTC_X2TRIM Mask */ - -#define MXC_F_TRIMSIR_RTC_LOCK_POS 31 /**< RTC_LOCK Position */ -#define MXC_F_TRIMSIR_RTC_LOCK ((uint32_t)(0x1UL << MXC_F_TRIMSIR_RTC_LOCK_POS)) /**< RTC_LOCK Mask */ - -/**@} end of group TRIMSIR_RTC_Register */ - -/** - * @ingroup trimsir_registers - * @defgroup TRIMSIR_SIMO TRIMSIR_SIMO - * @brief SIMO Trim System Initialization Register. - * @{ - */ -#define MXC_F_TRIMSIR_SIMO_CLKDIV_POS 0 /**< SIMO_CLKDIV Position */ -#define MXC_F_TRIMSIR_SIMO_CLKDIV ((uint32_t)(0x7UL << MXC_F_TRIMSIR_SIMO_CLKDIV_POS)) /**< SIMO_CLKDIV Mask */ -#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< SIMO_CLKDIV_DIV1 Value */ -#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV1 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV1 Setting */ -#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 ((uint32_t)0x1UL) /**< SIMO_CLKDIV_DIV16 Value */ -#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV16 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV16 Setting */ -#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< SIMO_CLKDIV_DIV32 Value */ -#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV32 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV32 Setting */ -#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 ((uint32_t)0x5UL) /**< SIMO_CLKDIV_DIV64 Value */ -#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV64 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV64 Setting */ -#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< SIMO_CLKDIV_DIV128 Value */ -#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV128 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV128 Setting */ - -/**@} end of group TRIMSIR_SIMO_Register */ - -/** - * @ingroup trimsir_registers - * @defgroup TRIMSIR_IPOLO TRIMSIR_IPOLO - * @brief IPO Low Trim System Initialization Register. - * @{ - */ -#define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS 0 /**< IPOLO_IPO_LIMITLO Position */ -#define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO ((uint32_t)(0xFFUL << MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS)) /**< IPOLO_IPO_LIMITLO Mask */ - -/**@} end of group TRIMSIR_IPOLO_Register */ +/**@} end of group TRIMSIR_RTCX1_Register */ /** * @ingroup trimsir_registers - * @defgroup TRIMSIR_CTRL TRIMSIR_CTRL - * @brief Control Trim System Initialization Register. + * @defgroup TRIMSIR_RTCX2 TRIMSIR_RTCX2 + * @brief RTC X2 Capacitor Setting. * @{ */ -#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS 0 /**< CTRL_VDDA_LIMITLO Position */ -#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS)) /**< CTRL_VDDA_LIMITLO Mask */ - -#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS 8 /**< CTRL_VDDA_LIMITHI Position */ -#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS)) /**< CTRL_VDDA_LIMITHI Mask */ - -#define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS 15 /**< CTRL_IPO_LIMITHI Position */ -#define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI ((uint32_t)(0x1FFUL << MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS)) /**< CTRL_IPO_LIMITHI Mask */ - -#define MXC_F_TRIMSIR_CTRL_INRO_SEL_POS 24 /**< CTRL_INRO_SEL Position */ -#define MXC_F_TRIMSIR_CTRL_INRO_SEL ((uint32_t)(0x3UL << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS)) /**< CTRL_INRO_SEL Mask */ -#define MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ ((uint32_t)0x0UL) /**< CTRL_INRO_SEL_8KHZ Value */ -#define MXC_S_TRIMSIR_CTRL_INRO_SEL_8KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_8KHZ Setting */ -#define MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ ((uint32_t)0x1UL) /**< CTRL_INRO_SEL_16KHZ Value */ -#define MXC_S_TRIMSIR_CTRL_INRO_SEL_16KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_16KHZ Setting */ -#define MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ ((uint32_t)0x2UL) /**< CTRL_INRO_SEL_30KHZ Value */ -#define MXC_S_TRIMSIR_CTRL_INRO_SEL_30KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_30KHZ Setting */ - -#define MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS 29 /**< CTRL_INRO_TRIM Position */ -#define MXC_F_TRIMSIR_CTRL_INRO_TRIM ((uint32_t)(0x7UL << MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS)) /**< CTRL_INRO_TRIM Mask */ +#define MXC_F_TRIMSIR_RTCX2_CAP_POS 0 /**< RTCX2_CAP Position */ +#define MXC_F_TRIMSIR_RTCX2_CAP ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTCX2_CAP_POS)) /**< RTCX2_CAP Mask */ -/**@} end of group TRIMSIR_CTRL_Register */ - -/** - * @ingroup trimsir_registers - * @defgroup TRIMSIR_INRO TRIMSIR_INRO - * @brief RTC Trim System Initialization Register. - * @{ - */ -#define MXC_F_TRIMSIR_INRO_TRIM16K_POS 0 /**< INRO_TRIM16K Position */ -#define MXC_F_TRIMSIR_INRO_TRIM16K ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM16K_POS)) /**< INRO_TRIM16K Mask */ - -#define MXC_F_TRIMSIR_INRO_TRIM30K_POS 3 /**< INRO_TRIM30K Position */ -#define MXC_F_TRIMSIR_INRO_TRIM30K ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM30K_POS)) /**< INRO_TRIM30K Mask */ - -#define MXC_F_TRIMSIR_INRO_LPCLKSEL_POS 6 /**< INRO_LPCLKSEL Position */ -#define MXC_F_TRIMSIR_INRO_LPCLKSEL ((uint32_t)(0x3UL << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS)) /**< INRO_LPCLKSEL Mask */ -#define MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ ((uint32_t)0x0UL) /**< INRO_LPCLKSEL_8KHZ Value */ -#define MXC_S_TRIMSIR_INRO_LPCLKSEL_8KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_8KHZ Setting */ -#define MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ ((uint32_t)0x1UL) /**< INRO_LPCLKSEL_16KHZ Value */ -#define MXC_S_TRIMSIR_INRO_LPCLKSEL_16KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_16KHZ Setting */ -#define MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ ((uint32_t)0x2UL) /**< INRO_LPCLKSEL_30KHZ Value */ -#define MXC_S_TRIMSIR_INRO_LPCLKSEL_30KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_30KHZ Setting */ - -/**@} end of group TRIMSIR_INRO_Register */ +/**@} end of group TRIMSIR_RTCX2_Register */ #ifdef __cplusplus } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h index 630c490b..5e11de9b 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h @@ -88,7 +88,7 @@ typedef struct { __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd index 0972ba6c..8f1abdaf 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd @@ -4336,13 +4336,13 @@ LDOTXBYPENENDLY - LDORX Bypass Enable Delay + LDOTX Bypass Enable Delay 14 1 LDORXBYPENENDLY - LDOTX Bypass Enable Delay + LDORX Bypass Enable Delay 15 1 diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h index f4c0d699..604e6d57 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h @@ -29,13 +29,6 @@ #include -// TODO(ADI): Remove below after grace period. Temporarily added these includes to resolve errors -// for grace period before eventually removing support for deprecated features. 10-24-2022 -//>>> -#include "trimsir_regs.h" -#include "aes_regs.h" -//<<< - #ifndef FALSE #define FALSE (0) #endif @@ -314,10 +307,6 @@ typedef enum { #define MXC_BASE_AES ((uint32_t)0x40207400UL) #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) -// DEPRECATED(10-24-2022): Scheduled for removal. -typedef __attribute__((deprecated( - "Use MXC_AES (mxc_aes_regs_t), not the deprecated MXC_SYS_AES (mxc_sys_aes_regs_t) instance name and struct. 10-24-2022"))) -mxc_aes_regs_t mxc_sys_aes_regs_t; #define MXC_SYS_AES ((mxc_sys_aes_regs_t *)MXC_BASE_AES) /******************************************************************************/ diff --git a/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c b/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c index 3b2c9a93..ead2ecec 100644 --- a/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c @@ -58,7 +58,7 @@ void MXC_LP_EnterBackupMode(void) // Should never reach this line - device will jump to backup vector on exit from background mode. } -void MXC_LP_EnterPowerDownMode(void) +void MXC_LP_EnterShutDownMode(void) { MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN; diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c index aed74ee5..45e710c7 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c @@ -46,6 +46,7 @@ unsigned int MXC_SDHC_Get_Clock_Config(void) /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT mxc_gpio_regs_t *gpio = gpio_cfg_sdhc.port; // Startup the IPO clock if it's not on already @@ -62,6 +63,7 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio->ds0 |= gpio_cfg_sdhc.mask; MXC_GPIO_Config(&gpio_cfg_sdhc); +#endif return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c index a50a1597..a7b54a61 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c @@ -37,6 +37,7 @@ /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SDHC); MXC_GPIO_Config(&gpio_cfg_sdhc_0); @@ -44,6 +45,7 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio_cfg_sdhc_1.port->vssel |= gpio_cfg_sdhc_1.mask; gpio_cfg_sdhc_0.port->ds_sel0 |= gpio_cfg_sdhc_0.mask; gpio_cfg_sdhc_1.port->ds_sel0 |= gpio_cfg_sdhc_1.mask; +#endif return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c index 96c1d99a..4b4cd58b 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c @@ -45,6 +45,7 @@ unsigned int MXC_SDHC_Get_Clock_Config(void) /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT mxc_gpio_regs_t *gpio = gpio_cfg_sdhc.port; // Startup the HIRC96M clock if it's not on already @@ -61,6 +62,8 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio->ds |= gpio_cfg_sdhc.mask; MXC_GPIO_Config(&gpio_cfg_sdhc); +#endif + return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c index fb96f3fa..41332259 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c @@ -46,6 +46,7 @@ unsigned int MXC_SDHC_Get_Clock_Config(void) /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT mxc_gpio_regs_t *gpio = gpio_cfg_sdhc.port; // Startup the HIRC96M clock if it's not on already @@ -62,6 +63,8 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio->ds0 |= gpio_cfg_sdhc.mask; MXC_GPIO_Config(&gpio_cfg_sdhc); +#endif + return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd index b40c329b..005effeb 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -288,6 +288,32 @@ + + ERFOCTRL + ERFO Control Register. + 0x24 + read-write + + + CAP_X1 + Load capacitor tuning bit for X1. + 0 + 7 + + + CAP_X2 + Load capacitor tuning bit for X2. + 7 + 7 + + + CAP_BYPASS + Bypass (disable) load capacitors. + 14 + 1 + + + FRQCNTCTRL Frequency Counter Control Register. diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd index 52a915dc..f147d782 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd @@ -1864,281 +1864,281 @@ BTLE LDO Control Register 0x74 - - LDORXEN - LDORX Enable - 0 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXOPULLD - LDORX PULL Disable - 1 - 1 - - - en - enabled. - 0 - - - dis - disabled. - 1 - - - - - LDORXVSEL - LDORX Voltage Setting - 2 - 2 - - - 0_85 - 0.85V - 0 - - - 0_9 - 0.9V - 1 - - - 1_0 - 1.0V - 2 - - - 1_1 - 1.1V - 3 - - - - - LDOTXEN - LDOTX Enable - 4 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXPULLD - LDOTX Pulldown - 5 - 1 - - - en - enabled. - 0 - - - dis - disabled. - 1 - - - - - LDOTXVSEL - LDOTX Output Voltage Setting - 6 - 2 - - - 0_85 - 0.85V - 0 - - - 0_9 - 0.9V - 1 - - - 1_0 - 1.0V - 2 - - - 1_1 - 1.1V - 3 - - - - - LDOTXBYP - LDOTX Bypass Enable - 8 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXDISCH - LDOTX Discharge - 9 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXBYP - LDORX Bypass Enable - 10 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXDISCH - LDORX Discharge - 11 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXENDLY - LDORX Enable Delay - 12 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXENDLY - LDOTX Enable Delay - 13 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXBYPENENDLY - LDORX Bypass Enable Delay - 14 - 1 - - - LDORXBYPENENDLY - LDOTX Bypass Enable Delay - 15 - 1 - + + LDORXEN + LDORX Enable + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXOPULLD + LDORX PULL Disable + 1 + 1 + + + en + enabled. + 0 + + + dis + disabled. + 1 + + + + + LDORXVSEL + LDORX Voltage Setting + 2 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDOTXEN + LDOTX Enable + 4 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXPULLD + LDOTX Pulldown + 5 + 1 + + + en + enabled. + 0 + + + dis + disabled. + 1 + + + + + LDOTXVSEL + LDOTX Output Voltage Setting + 6 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDOTXBYP + LDOTX Bypass Enable + 8 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXDISCH + LDOTX Discharge + 9 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXBYP + LDORX Bypass Enable + 10 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXDISCH + LDORX Discharge + 11 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXENDLY + LDORX Enable Delay + 12 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXENDLY + LDOTX Enable Delay + 13 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXBYPENENDLY + LDOTX Bypass Enable Delay + 14 + 1 + + + LDORXBYPENENDLY + LDORX Bypass Enable Delay + 15 + 1 + - - + + BTLE_LDODCR BTLE LDO Delay Register 0x78 - - BYPDLYCNT - Bypass Delay Count. Count delay base on PCLK. - 0 - 8 - - - LDOTXDLYCNT - LDOTX Delay Count. Count delay base on PCLK/128. - 8 - 9 - - - LDORXDLYCNT - LDORX Delay Count. Count delay base on PCLK/128. - 20 - 9 - + + BYPDLYCNT + Bypass Delay Count. Count delay base on PCLK. + 0 + 8 + + + LDOTXDLYCNT + LDOTX Delay Count. Count delay base on PCLK/128. + 8 + 9 + + + LDORXDLYCNT + LDORX Delay Count. Count delay base on PCLK/128. + 20 + 9 + - + GP0 General Purpose Register 0 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index b499495b..a580c6ad 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -880,86 +880,86 @@ 0x74 - RF_EN - LDO RF enable. + BB_EN + LDO BB enable. 0 1 - RF_PD_EN - LDO RF Pull Down. + BB_PD_EN + LDO BB Pull Down. 1 1 - RF_VSEL - Voltage Selection for RF LDO + BB_VSEL + Voltage Selection for BB LDO. 2 2 - BB_EN - LDOBB enable. + RF_EN + LDO RF enable. 4 1 - BB_PD_EN - LDO BB Pull DOwn. + RF_PD_EN + LDO RF Pull DOwn. 5 1 - BB_VSEL - LDO BB Voltage Setting. + RF_VSEL + LDO RF Voltage Setting. 6 2 - BB_BP_EN - LDO BB Bypass Enable. + RF_BP_EN + LDO RF Bypass Enable. 8 1 - BB_DISCH - LDO BB Discharge. + RF_DISCH + LDO RF Discharge. 9 1 - RF_BP_EN - LDO RF Bypass Enable. + BB_BP_EN + LDO BB Bypass Enable. 10 1 - RF_DISCH - LDO RF Discharge. + BB_DISCH + LDO BB Discharge. 11 1 - RF_EN_DLY - LDO RF Enable Delay. + BB_EN_DLY + LDO BB Enable Delay. 12 1 - BB_EN_DLY - LDO BB Enable Delay. + RF_EN_DLY + LDO RF Enable Delay. 13 1 - BB_BP_EN_DLY - LDO BB Bypass Enable Delay. + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. 14 1 - RF_BP_EN_DLY - LDO RF Bypass Enable Delay. + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. 15 1 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd index fcca217a..814c4e73 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd @@ -21,12 +21,6 @@ 0 1 - - RSTZ - Reset RSTZ Controller. - 1 - 1 - @@ -49,7 +43,7 @@ CLKSEL - Clock select for RTC, WUTs, and Timers. + Clcok Select for the RTC, System, WUT, and Timer. 0 2 @@ -59,49 +53,49 @@ 0 - INRO + INRO_DIV4 INRO as clock source. 1 - EXTCLK + RTC_IN_DIV8 P0.12 div 8 as clock source. 2 - ERTCO_32KHZ_EN - Enable ERTCO 32KHz while ERTCO_EN. + ERTCO32K_EN + Enable the 32KHz ERTCO. 3 1 ERTCO_EN - Enable ERTCO 4KHz. + Enable the ERTCO. 5 1 - BBREG0 - Battery Back Reg0. + BYPASS0 + This register is used by firmware to bypass chain of trust on a Warm Boot. 0x30 - BBREG1 - Battery Back Reg1. + BYPASS1 + This register is used by firmware to bypass chain of trust on a Warm Boot. 0x34 - BBDATA0 - Battery Back Data0 Register. + DATA0 + Battery Back Data0 Register. Retains value in all modes. 0x40 - BBDATA1 - Battery Back Data1 Register. + DATA1 + Battery Back Data1 Register. Retains value in all modes. 0x44 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd index 570df3a7..d2c572d5 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd @@ -2,7 +2,7 @@ TRIMSIR - Trim System Initilazation Registers + Trim System Initilazation Registers. 0x40005400 0x00 @@ -11,171 +11,33 @@ - RTC - RTC Trim System Initialization Register. - 0x08 - - - X1TRIM - RTC X1 Trim. - 16 - 5 - - - X2TRIM - RTC X2 Trim. - 21 - 5 - - - LOCK - Lock. - 31 - 1 - - - - - SIMO - SIMO Trim System Initialization Register. - 0x34 - read-only - - - CLKDIV - SIMO Clock Divide. - 0 - 3 - - - DIV1 - 0 - - - DIV16 - 1 - - - DIV32 - 3 - - - DIV64 - 5 - - - DIV128 - 7 - - - - - - - IPOLO - IPO Low Trim System Initialization Register. + RTCX1 + RTC X2 Capacitor Setting. 0x3C read-only - IPO_LIMITLO - IPO Low Limit Trim. + CAP + RTC X1 Load Capacitor Setting. 0 - 8 - - - - - CTRL - Control Trim System Initialization Register. - 0x40 - - - VDDA_LIMITLO - VDDA Low Trim Limit. - 0 - 7 - - - VDDA_LIMITHI - VDDA High Trim Limit. - 8 - 7 - - - IPO_LIMITHI - IPO High Trim Limit. - 15 - 9 - - - INRO_SEL - INRO Clock Select. - 24 - 2 - - - 8KHZ - 0 - - - 16KHZ - 1 - - - 30KHZ - 2 - - - - - INRO_TRIM - INRO Clock Trim. - 29 - 3 + 5 - INRO - RTC Trim System Initialization Register. + RTCX2 + RTC X2 Capacitor Setting. 0x44 - TRIM16K - INRO 16KHz Trim. + CAP + RTC X2 Load Capacitor Setting. 0 - 3 - - - TRIM30K - INRO 30KHz Trim. - 3 - 3 - - - LPCLKSEL - INRO Low Power Mode Clock Select. - 6 - 2 - - - 8KHZ - 0 - - - 16KHZ - 1 - - - 30KHZ - 2 - - + 5 - + \ No newline at end of file diff --git a/MAX/msdk_sha b/MAX/msdk_sha index 1c17af17..21080447 100644 --- a/MAX/msdk_sha +++ b/MAX/msdk_sha @@ -1 +1 @@ -8b51c1f4ade8be8120efaf9d9620c403a4a40650 +b99a9213997c3bfbfacb43554ff4722ff851ef2f