diff --git a/Documentation/platforms/arm/imx9/boards/imx95-evk/index.rst b/Documentation/platforms/arm/imx9/boards/imx95-evk/index.rst new file mode 100644 index 0000000000000..571eef84c8a7d --- /dev/null +++ b/Documentation/platforms/arm/imx9/boards/imx95-evk/index.rst @@ -0,0 +1,85 @@ +=============== +IMX95LPD5EVK-19 +=============== + +The IMX95LPD5EVK-19 board is a platform designed to show the most commonly +used features of the i.MX 95 automotive applications processor. + +Features +======== + +- Multicore Processing [1]_ + - 1x Arm Cortex-M7 + - 6x Arm Cortex-A55 multicore complex + - 1x Arm Cortex-M33 +- Memory + - On-Chip Memory + - 1376kB SRAM (ECC) + - External Memory + - Up to 6.4GT/s x32 LPDDR5/LPDDR4X (with Inline ECC & Inline Encrpytion) + - 1x Octal SPI, including support for SPI NOR and SPI NAND memories +- Connectivity + - CAN FD + - UART/USART/Profibus, I²C, SPI + - Messaging Units (MU) to support IPC between heterogeneous cores + +.. [1] NuttX is currently supported exclusively on the Cortex-M7 core of the + i.MX95 + +Serial Console +============== + +The IMX95LPD5EVK-19 board features a high-speed USB-to-UART/MPSSE device, +FT4232H (U70) that provides a debug interface for the i.MX95 processor through +the USB type-C connector (J31). The device acts as a bridge to enable +communication between the target processor and the host computer, which +connects to the USB connector (J31) through a USB cable. + +Channel A is used as UART port to provide USB-to-UART option for debugging the +Arm Cortex-M7 core of the i.MX 95 processor (default option). + +J-Link External Debug Probe +=========================== + +The IMX95LPD5EVK-19 board provides a 2x5-pin Samtec FTSH-105-01-L-DV-K header +(J30) for connecting a JTAG debugger (external JTAG) for debugging the i.MX95 +processor. The FT4234H JTAG provides the remote debug option for the i.MX95 +processor. + +Configurations +============== + +nsh +--- + +Configures the NuttShell (nsh) located at examples/nsh. This NSH +configuration is focused on low level, command-line driver testing. Built-in +applications are supported, but none are enabled. This configuration does not +support a network. + +This configuration can be used in combination with the default sd-card image +that is shipped with the EVK. + +rpmsg +----- + +This configuration is similar to nsh but in addition it offers the Remote +Processing Messaging (RPMsg) service to enable heterogeneous inter-core +communication. A virtual UART (CONFIG_RPMSG_UART) is made available on which +an OS running on the A55 cores can connect. There is also an option to use +the filesystem client feature in which a remote directory can be mounted to +a local directory (CONFIG_FS_RPMSGFS). + +The rpmsg configuration executes the code from DDR since its code memory +footprint is bigger than the ITCM size. In the case of using the default +sd-card image from the EVK, adaptations are needed on the software running on +the M33 and A55 cores. + + - `System Manager `_ (M33) should give + the M7 access to the DDR region + - `linux-imx `_ (A55) should reserve + the DDR region by specifying it in the device tree so linux won't make + use of it + - `linux-imx `_ (A55) needs the + NuttX compatible rpmsg_tty and rpmsg_fs drivers. See `dev mailing list + `_ \ No newline at end of file diff --git a/Documentation/platforms/arm/imx9/index.rst b/Documentation/platforms/arm/imx9/index.rst new file mode 100644 index 0000000000000..3d802e0fe4675 --- /dev/null +++ b/Documentation/platforms/arm/imx9/index.rst @@ -0,0 +1,12 @@ +=================== +NXP i.MX9 +=================== + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* \ No newline at end of file diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 464b1ad9ffa24..dd2de8f876247 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -183,6 +183,20 @@ config ARCH_CHIP_IMX6 ---help--- Freescale iMX.6 architectures (Cortex-A9) +config ARCH_CHIP_IMX9_CORTEX_M + bool "NXP iMX.9 Cortex-M7" + select ARCH_CORTEXM7 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_RAMFUNCS + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_SPI_CS_CONTROL + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + ---help--- + iMX.9 architectures (Cortex-M7) + config ARCH_CHIP_IMXRT bool "NXP/Freescale iMX.RT" select ARCH_CORTEXM7 @@ -1124,6 +1138,7 @@ config ARCH_CHIP default "gd32f4" if ARCH_CHIP_GD32F4 default "imx1" if ARCH_CHIP_IMX1 default "imx6" if ARCH_CHIP_IMX6 + default "imx9" if ARCH_CHIP_IMX9_CORTEX_M default "imxrt" if ARCH_CHIP_IMXRT default "kinetis" if ARCH_CHIP_KINETIS default "kl" if ARCH_CHIP_KL @@ -1536,6 +1551,9 @@ endif if ARCH_CHIP_IMX6 source "arch/arm/src/imx6/Kconfig" endif +if ARCH_CHIP_IMX9_CORTEX_M +source "arch/arm/src/imx9/Kconfig" +endif if ARCH_CHIP_IMXRT source "arch/arm/src/imxrt/Kconfig" endif diff --git a/arch/arm/include/imx9/chip.h b/arch/arm/include/imx9/chip.h new file mode 100644 index 0000000000000..0b46efc38271e --- /dev/null +++ b/arch/arm/include/imx9/chip.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/include/imx9/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_IMX9_CHIP_H +#define __ARCH_ARM_INCLUDE_IMX9_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds an 8-bit priority value, 0-15. The lower the + * value, the greater the priority of the corresponding interrupt. The i.MX + * RT processor implements only bits[7:4] of each field, bits[3:0] read as + * zero and ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */ + +#define IMX9_GPIO_NPORTS 4 + +#endif /* __ARCH_ARM_INCLUDE_IMX9_CHIP_H */ diff --git a/arch/arm/include/imx9/imx95_irq.h b/arch/arm/include/imx9/imx95_irq.h new file mode 100644 index 0000000000000..9300ac65d43ac --- /dev/null +++ b/arch/arm/include/imx9/imx95_irq.h @@ -0,0 +1,420 @@ +/**************************************************************************** + * arch/arm/include/imx9/imx95_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H +#define __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H + +#define IMX9_IRQ_RESERVED16 (IMX9_IRQ_EXTINT + 0) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED17 (IMX9_IRQ_EXTINT + 1) /* DAP interrupt */ +#define IMX9_IRQ_RESERVED18 (IMX9_IRQ_EXTINT + 2) /* CTI trigger outputs from CM7 platform */ +#define IMX9_IRQ_RESERVED19 (IMX9_IRQ_EXTINT + 3) /* CTI trigger outputs from CM33 platform */ +#define IMX9_IRQ_RESERVED20 (IMX9_IRQ_EXTINT + 4) /* CTI trigger outputs from CA55 platform */ +#define IMX9_IRQ_RESERVED21 (IMX9_IRQ_EXTINT + 5) /* Performance Unit Interrupts from CA55 platform */ +#define IMX9_IRQ_RESERVED22 (IMX9_IRQ_EXTINT + 6) /* ECC error from CA55 platform cache */ +#define IMX9_IRQ_RESERVED23 (IMX9_IRQ_EXTINT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ +#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXTINT + 8) /* CAN1 interrupt */ +#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXTINT + 9) /* CAN1 error interrupt */ +#define IMX9_IRQ_GPIO1_0 (IMX9_IRQ_EXTINT + 10) /* General Purpose Input/Output 1 interrupt 0 */ +#define IMX9_IRQ_GPIO1_1 (IMX9_IRQ_EXTINT + 11) /* General Purpose Input/Output 1 interrupt 1 */ +#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXTINT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */ +#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXTINT + 13) /* Low Power Inter-Integrated Circuit module 1 */ +#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXTINT + 14) /* Low Power Inter-Integrated Circuit module 2 */ +#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXTINT + 15) /* Low Power Periodic Interrupt Timer 1 */ +#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXTINT + 16) /* Low Power Serial Peripheral Interface 1 */ +#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXTINT + 17) /* Low Power Serial Peripheral Interface 2 */ +#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXTINT + 18) /* Low Power Timer 1 */ +#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXTINT + 19) /* Low Power UART 1 */ +#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXTINT + 20) /* Low Power UART 2 */ +#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXTINT + 21) /* AONMIX Sentinel MU0 SideA interrupt */ +#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXTINT + 22) /* AONMIX Sentinel MU1 SideA interrupt */ +#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXTINT + 23) /* AONMIX Sentinel MU2 SideA interrupt */ +#define IMX9_IRQ_RESERVED40 (IMX9_IRQ_EXTINT + 24) /* AONMIX Sentinel MU3 SideA interrupt */ +#define IMX9_IRQ_RESERVED41 (IMX9_IRQ_EXTINT + 25) /* AONMIX Sentinel MU4 SideA interrupt */ +#define IMX9_IRQ_RESERVED42 (IMX9_IRQ_EXTINT + 26) /* AONMIX Sentinel MU5 SideA interrupt */ +#define IMX9_IRQ_V2X_FH_APCH0 (IMX9_IRQ_EXTINT + 27) /* V2X-FH MU APCH0 (APP0) interrupt */ +#define IMX9_IRQ_V2X_FH_APHSM1 (IMX9_IRQ_EXTINT + 28) /* V2X-FH MU APHSM1 (HSM1) interrupt */ +#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXTINT + 29) /* Timer PWM module 1 */ +#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXTINT + 30) /* Timer PWM module 2 */ +#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXTINT + 31) /* Watchdog 1 Interrupt */ +#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXTINT + 32) /* Watchdog 2 Interrupt */ +#define IMX9_IRQ_TRDC_MGR_A (IMX9_IRQ_EXTINT + 33) /* AONMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXTINT + 34) /* Serial Audio Interface 1 */ +#define IMX9_IRQ_RESERVED51 (IMX9_IRQ_EXTINT + 35) /* AONMIX M33 PS Error */ +#define IMX9_IRQ_RESERVED52 (IMX9_IRQ_EXTINT + 36) /* AONMIX M33 TCM Error interrupt */ +#define IMX9_IRQ_RESERVED53 (IMX9_IRQ_EXTINT + 37) /* M7MIX ECC Multi-bit error */ +#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXTINT + 38) /* CAN2 interrupt */ +#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXTINT + 39) /* CAN2 error interrupt */ +#define IMX9_IRQ_CAN3 (IMX9_IRQ_EXTINT + 40) /* CAN3 interrupt */ +#define IMX9_IRQ_CAN3_ERROR (IMX9_IRQ_EXTINT + 41) /* CAN3 error interrupt */ +#define IMX9_IRQ_CAN4 (IMX9_IRQ_EXTINT + 42) /* CAN4 interrupt */ +#define IMX9_IRQ_CAN4_ERROR (IMX9_IRQ_EXTINT + 43) /* CAN4 error interrupt */ +#define IMX9_IRQ_CAN5 (IMX9_IRQ_EXTINT + 44) /* CAN5 interrupt */ +#define IMX9_IRQ_CAN5_ERROR (IMX9_IRQ_EXTINT + 45) /* CAN5 error interrupt */ +#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXTINT + 46) /* Flexible IO 1 interrupt */ +#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXTINT + 47) /* Flexible IO 2 interrupt */ +#define IMX9_IRQ_FlexSPI1 (IMX9_IRQ_EXTINT + 48) /* FlexSPI controller interface interrupt 1 */ +#define IMX9_IRQ_GPIO2_0 (IMX9_IRQ_EXTINT + 49) /* General Purpose Input/Output 2 interrupt 0 */ +#define IMX9_IRQ_GPIO2_1 (IMX9_IRQ_EXTINT + 50) /* General Purpose Input/Output 2 interrupt 1 */ +#define IMX9_IRQ_GPIO3_0 (IMX9_IRQ_EXTINT + 51) /* General Purpose Input/Output 3 interrupt 0 */ +#define IMX9_IRQ_GPIO3_1 (IMX9_IRQ_EXTINT + 52) /* General Purpose Input/Output 3 interrupt 1 */ +#define IMX9_IRQ_GPIO4_0 (IMX9_IRQ_EXTINT + 53) /* General Purpose Input/Output 4 interrupt 0 */ +#define IMX9_IRQ_GPIO4_1 (IMX9_IRQ_EXTINT + 54) /* General Purpose Input/Output 4 interrupt 1 */ +#define IMX9_IRQ_GPIO5_0 (IMX9_IRQ_EXTINT + 55) /* General Purpose Input/Output 5 interrupt 0 */ +#define IMX9_IRQ_GPIO5_1 (IMX9_IRQ_EXTINT + 56) /* General Purpose Input/Output 5 interrupt 1 */ +#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXTINT + 57) /* Improved Inter-Integrated Circuit 2 interrupt */ +#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXTINT + 58) /* Low Power Inter-Integrated Circuit module 3 */ +#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXTINT + 59) /* Low Power Inter-Integrated Circuit module 4 */ +#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXTINT + 60) /* Low Power Periodic Interrupt Timer 2 */ +#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXTINT + 61) /* Low Power Serial Peripheral Interface 3 */ +#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXTINT + 62) /* Low Power Serial Peripheral Interface 4 */ +#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXTINT + 63) /* Low Power Timer 2 */ +#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXTINT + 64) /* Low Power UART 3 */ +#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXTINT + 65) /* Low Power UART 4 */ +#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXTINT + 66) /* Low Power UART 5 */ +#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXTINT + 67) /* Low Power UART 6 */ +#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXTINT + 68) /* Low Power UART 7 */ +#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXTINT + 69) /* Low Power UART 8 */ +#define IMX9_IRQ_RESERVED86 (IMX9_IRQ_EXTINT + 70) /* MTR Master error interrupt */ +#define IMX9_IRQ_RESERVED87 (IMX9_IRQ_EXTINT + 71) /* BBNSM Non-Secure interrupt */ +#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXTINT + 72) /* System Counter compare interrupt */ +#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXTINT + 73) /* Timer PWM module 3 */ +#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXTINT + 74) /* Timer PWM module 4 */ +#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXTINT + 75) /* Timer PWM module 5 */ +#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXTINT + 76) /* Timer PWM module 6 */ +#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXTINT + 77) /* Watchdog 3 Interrupt */ +#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXTINT + 78) /* Watchdog 4 Interrupt */ +#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXTINT + 79) /* Watchdog 5 Interrupt */ +#define IMX9_IRQ_TMPSNS1_THR1 (IMX9_IRQ_EXTINT + 80) /* ANAMIX TempSensor non-secure interrupt from Threshold 1 */ +#define IMX9_IRQ_TMPSNS1_THR2 (IMX9_IRQ_EXTINT + 81) /* ANAMIX TempSensor non-secure interrupt from Threshold 2 */ +#define IMX9_IRQ_TMPSNS1_DRDY (IMX9_IRQ_EXTINT + 82) /* ANAMIX TempSensor non-secure data ready interrupt */ +#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXTINT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */ +#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXTINT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */ +#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXTINT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */ +#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */ +#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */ +#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 90) /* NOCMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED107 (IMX9_IRQ_EXTINT + 91) /* DRAM controller Performance Monitor Interrupt */ +#define IMX9_IRQ_RESERVED108 (IMX9_IRQ_EXTINT + 92) /* DRAM controller Critical Interrupt */ +#define IMX9_IRQ_RESERVED109 (IMX9_IRQ_EXTINT + 93) /* DRAM Phy Critical Interrupt */ +#define IMX9_IRQ_RESERVED110 (IMX9_IRQ_EXTINT + 94) /* Reserved */ +#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXTINT + 95) /* eDMA1 error interrupt */ +#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXTINT + 96) /* eDMA1 channel 0 interrupt */ +#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXTINT + 97) /* eDMA1 channel 1 interrupt */ +#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXTINT + 98) /* eDMA1 channel 2 interrupt */ +#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXTINT + 99) /* eDMA1 channel 3 interrupt */ +#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXTINT + 100) /* eDMA1 channel 4 interrupt */ +#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXTINT + 101) /* eDMA1 channel 5 interrupt */ +#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXTINT + 102) /* eDMA1 channel 6 interrupt */ +#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXTINT + 103) /* eDMA1 channel 7 interrupt */ +#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXTINT + 104) /* eDMA1 channel 8 interrupt */ +#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXTINT + 105) /* eDMA1 channel 9 interrupt */ +#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXTINT + 106) /* eDMA1 channel 10 interrupt */ +#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXTINT + 107) /* eDMA1 channel 11 interrupt */ +#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXTINT + 108) /* eDMA1 channel 12 interrupt */ +#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXTINT + 109) /* eDMA1 channel 13 interrupt */ +#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXTINT + 110) /* eDMA1 channel 14 interrupt */ +#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXTINT + 111) /* eDMA1 channel 15 interrupt */ +#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXTINT + 112) /* eDMA1 channel 16 interrupt */ +#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXTINT + 113) /* eDMA1 channel 17 interrupt */ +#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXTINT + 114) /* eDMA1 channel 18 interrupt */ +#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXTINT + 115) /* eDMA1 channel 19 interrupt */ +#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXTINT + 116) /* eDMA1 channel 20 interrupt */ +#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXTINT + 117) /* eDMA1 channel 21 interrupt */ +#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXTINT + 118) /* eDMA1 channel 22 interrupt */ +#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXTINT + 119) /* eDMA1 channel 23 interrupt */ +#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXTINT + 120) /* eDMA1 channel 24 interrupt */ +#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXTINT + 121) /* eDMA1 channel 25 interrupt */ +#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXTINT + 122) /* eDMA1 channel 26 interrupt */ +#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXTINT + 123) /* eDMA1 channel 27 interrupt */ +#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXTINT + 124) /* eDMA1 channel 28 interrupt */ +#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXTINT + 125) /* eDMA1 channel 29 interrupt */ +#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXTINT + 126) /* eDMA1 channel 30 interrupt */ +#define IMX9_IRQ_DMA5_2_ERROR (IMX9_IRQ_EXTINT + 127) /* eDMA2 error interrupt */ +#define IMX9_IRQ_DMA5_2_0_1 (IMX9_IRQ_EXTINT + 128) /* eDMA2 channel 0/1 interrupt */ +#define IMX9_IRQ_DMA5_2_2_3 (IMX9_IRQ_EXTINT + 129) /* eDMA2 channel 2/3 interrupt */ +#define IMX9_IRQ_DMA5_2_4_5 (IMX9_IRQ_EXTINT + 130) /* eDMA2 channel 4/5 interrupt */ +#define IMX9_IRQ_DMA5_2_6_7 (IMX9_IRQ_EXTINT + 131) /* eDMA2 channel 6/7 interrupt */ +#define IMX9_IRQ_DMA5_2_8_9 (IMX9_IRQ_EXTINT + 132) /* eDMA2 channel 8/9 interrupt */ +#define IMX9_IRQ_DMA5_2_10_11 (IMX9_IRQ_EXTINT + 133) /* eDMA2 channel 10/11 interrupt */ +#define IMX9_IRQ_DMA5_2_12_13 (IMX9_IRQ_EXTINT + 134) /* eDMA2 channel 12/13 interrupt */ +#define IMX9_IRQ_DMA5_2_14_15 (IMX9_IRQ_EXTINT + 135) /* eDMA2 channel 14/15 interrupt */ +#define IMX9_IRQ_DMA5_2_16_17 (IMX9_IRQ_EXTINT + 136) /* eDMA2 channel 16/17 interrupt */ +#define IMX9_IRQ_DMA5_2_18_19 (IMX9_IRQ_EXTINT + 137) /* eDMA2 channel 18/19 interrupt */ +#define IMX9_IRQ_DMA5_2_20_21 (IMX9_IRQ_EXTINT + 138) /* eDMA2 channel 20/21 interrupt */ +#define IMX9_IRQ_DMA5_2_22_23 (IMX9_IRQ_EXTINT + 139) /* eDMA2 channel 22/23 interrupt */ +#define IMX9_IRQ_DMA5_2_24_25 (IMX9_IRQ_EXTINT + 140) /* eDMA2 channel 24/25 interrupt */ +#define IMX9_IRQ_DMA5_2_26_27 (IMX9_IRQ_EXTINT + 141) /* eDMA2 channel 26/27 interrupt */ +#define IMX9_IRQ_DMA5_2_28_29 (IMX9_IRQ_EXTINT + 142) /* eDMA2 channel 28/29 interrupt */ +#define IMX9_IRQ_DMA5_2_30_31 (IMX9_IRQ_EXTINT + 143) /* eDMA2 channel 30/31 interrupt */ +#define IMX9_IRQ_DMA5_2_32_33 (IMX9_IRQ_EXTINT + 144) /* eDMA2 channel 32/33 interrupt */ +#define IMX9_IRQ_DMA5_2_34_35 (IMX9_IRQ_EXTINT + 145) /* eDMA2 channel 34/35 interrupt */ +#define IMX9_IRQ_DMA5_2_36_37 (IMX9_IRQ_EXTINT + 146) /* eDMA2 channel 36/37 interrupt */ +#define IMX9_IRQ_DMA5_2_38_39 (IMX9_IRQ_EXTINT + 147) /* eDMA2 channel 38/39 interrupt */ +#define IMX9_IRQ_DMA5_2_40_41 (IMX9_IRQ_EXTINT + 148) /* eDMA2 channel 40/41 interrupt */ +#define IMX9_IRQ_DMA5_2_42_43 (IMX9_IRQ_EXTINT + 149) /* eDMA2 channel 42/43 interrupt */ +#define IMX9_IRQ_DMA5_2_44_45 (IMX9_IRQ_EXTINT + 150) /* eDMA2 channel 44/45 interrupt */ +#define IMX9_IRQ_DMA5_2_46_47 (IMX9_IRQ_EXTINT + 151) /* eDMA2 channel 46/47 interrupt */ +#define IMX9_IRQ_DMA5_2_48_49 (IMX9_IRQ_EXTINT + 152) /* eDMA2 channel 48/49 interrupt */ +#define IMX9_IRQ_DMA5_2_50_51 (IMX9_IRQ_EXTINT + 153) /* eDMA2 channel 50/51 interrupt */ +#define IMX9_IRQ_DMA5_2_52_53 (IMX9_IRQ_EXTINT + 154) /* eDMA2 channel 52/53 interrupt */ +#define IMX9_IRQ_DMA5_2_54_55 (IMX9_IRQ_EXTINT + 155) /* eDMA2 channel 54/55 interrupt */ +#define IMX9_IRQ_DMA5_2_56_57 (IMX9_IRQ_EXTINT + 156) /* eDMA2 channel 56/57 interrupt */ +#define IMX9_IRQ_DMA5_2_58_59 (IMX9_IRQ_EXTINT + 157) /* eDMA2 channel 58/59 interrupt */ +#define IMX9_IRQ_DMA5_2_60_61 (IMX9_IRQ_EXTINT + 158) /* eDMA2 channel 60/61 interrupt */ +#define IMX9_IRQ_DMA5_2_62_63 (IMX9_IRQ_EXTINT + 159) /* eDMA2 channel 62/63 interrupt */ +#define IMX9_IRQ_RESERVED176 (IMX9_IRQ_EXTINT + 160) /* Sentinel Group 1 reset source if no s500 reference clock is detected. Output synchronized to 32khz clk. */ +#define IMX9_IRQ_RESERVED177 (IMX9_IRQ_EXTINT + 161) /* Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */ +#define IMX9_IRQ_RESERVED178 (IMX9_IRQ_EXTINT + 162) /* Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */ +#define IMX9_IRQ_RESERVED179 (IMX9_IRQ_EXTINT + 163) /* JTAGSW DAP MDM-AP SRC reset source */ +#define IMX9_IRQ_RESERVED180 (IMX9_IRQ_EXTINT + 164) /* JTAGC SRC reset source */ +#define IMX9_IRQ_RESERVED181 (IMX9_IRQ_EXTINT + 165) /* CM33 SYSREQRST SRC reset source */ +#define IMX9_IRQ_RESERVED182 (IMX9_IRQ_EXTINT + 166) /* CM33 LOCKUP SRC reset source */ +#define IMX9_IRQ_RESERVED183 (IMX9_IRQ_EXTINT + 167) /* CM7 SYSREQRST SRC reset source */ +#define IMX9_IRQ_RESERVED184 (IMX9_IRQ_EXTINT + 168) /* CM7 LOCKUP SRC reset source */ +#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXTINT + 169) /* Serial Audio Interface 2 */ +#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXTINT + 170) /* Serial Audio Interface 3 */ +#define IMX9_IRQ_SAI4 (IMX9_IRQ_EXTINT + 171) /* Serial Audio Interface 4 */ +#define IMX9_IRQ_SAI5 (IMX9_IRQ_EXTINT + 172) /* Serial Audio Interface 5 */ +#define IMX9_IRQ_RESERVED189 (IMX9_IRQ_EXTINT + 173) /* USB-1 Wake-up Interrupt */ +#define IMX9_IRQ_RESERVED190 (IMX9_IRQ_EXTINT + 174) /* USB-2 Wake-up Interrupt */ +#define IMX9_IRQ_USB1 (IMX9_IRQ_EXTINT + 175) /* USB-1 Interrupt */ +#define IMX9_IRQ_USB2 (IMX9_IRQ_EXTINT + 176) /* USB-2 Interrupt */ +#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXTINT + 177) /* Low Power Serial Peripheral Interface 5 */ +#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXTINT + 178) /* Low Power Serial Peripheral Interface 6 */ +#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXTINT + 179) /* Low Power Serial Peripheral Interface 7 */ +#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXTINT + 180) /* Low Power Serial Peripheral Interface 8 */ +#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXTINT + 181) /* Low Power Inter-Integrated Circuit module 5 */ +#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXTINT + 182) /* Low Power Inter-Integrated Circuit module 6 */ +#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXTINT + 183) /* Low Power Inter-Integrated Circuit module 7 */ +#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXTINT + 184) /* Low Power Inter-Integrated Circuit module 8 */ +#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXTINT + 185) /* PDM interrupt */ +#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXTINT + 186) /* PDM interrupt */ +#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXTINT + 187) /* PDM interrupt */ +#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 188) /* PDM interrupt */ +#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 189) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 190) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */ +#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 192) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXTINT + 193) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 194) /* CM33 MCM interrupt */ +#define IMX9_IRQ_RESERVED211 (IMX9_IRQ_EXTINT + 195) /* ANAMIX SFA interrupt */ +#define IMX9_IRQ_RESERVED212 (IMX9_IRQ_EXTINT + 196) /* GIC700 Fault */ +#define IMX9_IRQ_RESERVED213 (IMX9_IRQ_EXTINT + 197) /* GIC700 Error */ +#define IMX9_IRQ_RESERVED214 (IMX9_IRQ_EXTINT + 198) /* GIC700 PMU Counter Overflow */ +#define IMX9_IRQ_ADC_ER (IMX9_IRQ_EXTINT + 199) /* ADC interrupt */ +#define IMX9_IRQ_ADC_WD (IMX9_IRQ_EXTINT + 200) /* ADC interrupt */ +#define IMX9_IRQ_ADC_EOC (IMX9_IRQ_EXTINT + 201) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXTINT + 202) /* s500 glue logic IRQ */ +#define IMX9_IRQ_RESERVED219 (IMX9_IRQ_EXTINT + 203) /* I3C1 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED220 (IMX9_IRQ_EXTINT + 204) /* I3C2 wakeup irq after double sync */ +#define IMX9_IRQ_MU5_A (IMX9_IRQ_EXTINT + 205) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU6_A (IMX9_IRQ_EXTINT + 206) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU7_B (IMX9_IRQ_EXTINT + 207) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU8_B (IMX9_IRQ_EXTINT + 208) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_RESERVED225 (IMX9_IRQ_EXTINT + 209) /* WAKEUPMIX XSPI Responder */ +#define IMX9_IRQ_RESERVED226 (IMX9_IRQ_EXTINT + 210) /* AONMIX FCCU Interrupt Reaction 0 */ +#define IMX9_IRQ_RESERVED227 (IMX9_IRQ_EXTINT + 211) /* AONMIX FCCU Interrupt Reaction 1 */ +#define IMX9_IRQ_RESERVED228 (IMX9_IRQ_EXTINT + 212) /* AONMIX FCCU Interrupt Reaction 2 */ +#define IMX9_IRQ_RESERVED229 (IMX9_IRQ_EXTINT + 213) /* AONMIX STCU Selftest end Interrupt */ +#define IMX9_IRQ_DISP_IRQSTEER0 (IMX9_IRQ_EXTINT + 214) /* DISPLAYMIX IRQSTEER 0 */ +#define IMX9_IRQ_DISP_IRQSTEER1 (IMX9_IRQ_EXTINT + 215) /* DISPLAYMIX IRQSTEER 1 */ +#define IMX9_IRQ_DISP_IRQSTEER2 (IMX9_IRQ_EXTINT + 216) /* DISPLAYMIX IRQSTEER 2 */ +#define IMX9_IRQ_DISP_IRQSTEER3 (IMX9_IRQ_EXTINT + 217) /* DISPLAYMIX IRQSTEER 3 */ +#define IMX9_IRQ_DISP_IRQSTEER4 (IMX9_IRQ_EXTINT + 218) /* DISPLAYMIX IRQSTEER 4 */ +#define IMX9_IRQ_DISP_IRQSTEER7 (IMX9_IRQ_EXTINT + 219) /* DISPLAYMIX IRQSTEER 7 */ +#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXTINT + 220) /* CAMERAMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_ISI (IMX9_IRQ_EXTINT + 221) /* CAMERAMIX ISI interrupt Channel 0 */ +#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXTINT + 222) /* ISP Processing Interrupt - Context 0 */ +#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXTINT + 223) /* M7MIX MCM interrupt */ +#define IMX9_IRQ_IRQSTEER_0 (IMX9_IRQ_EXTINT + 224) /* IRQSTEER0 interrupt */ +#define IMX9_IRQ_IRQSTEER_1 (IMX9_IRQ_EXTINT + 225) /* IRQSTEER1 interrupt */ +#define IMX9_IRQ_IRQSTEER_2 (IMX9_IRQ_EXTINT + 226) /* IRQSTEER2 interrupt */ +#define IMX9_IRQ_IRQSTEER_3 (IMX9_IRQ_EXTINT + 227) /* IRQSTEER3 interrupt */ +#define IMX9_IRQ_IRQSTEER_4 (IMX9_IRQ_EXTINT + 228) /* IRQSTEER4 interrupt */ +#define IMX9_IRQ_IRQSTEER_5 (IMX9_IRQ_EXTINT + 229) /* IRQSTEER5 interrupt */ +#define IMX9_IRQ_IRQSTEER_6 (IMX9_IRQ_EXTINT + 230) /* IRQSTEER6 interrupt */ +#define IMX9_IRQ_IRQSTEER_7 (IMX9_IRQ_EXTINT + 231) /* IRQSTEER7 interrupt */ +#define IMX9_IRQ_IRQSTEER_8 (IMX9_IRQ_EXTINT + 232) /* IRQSTEER8 interrupt */ +#define IMX9_IRQ_IRQSTEER_9 (IMX9_IRQ_EXTINT + 233) /* IRQSTEER9 interrupt */ +#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXTINT + 234) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXTINT + 235) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXTINT + 236) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXTINT + 237) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU3_A (IMX9_IRQ_EXTINT + 238) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU3_B (IMX9_IRQ_EXTINT + 239) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU4_A (IMX9_IRQ_EXTINT + 240) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU4_B (IMX9_IRQ_EXTINT + 241) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU5_B (IMX9_IRQ_EXTINT + 242) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU6_B (IMX9_IRQ_EXTINT + 243) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */ +#define IMX9_IRQ_MU7_A (IMX9_IRQ_EXTINT + 244) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MU8_A (IMX9_IRQ_EXTINT + 245) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */ +#define IMX9_IRQ_MSGINTR1 (IMX9_IRQ_EXTINT + 246) /* MSGINTR Instance 1, Interrupt */ +#define IMX9_IRQ_MSGINTR2 (IMX9_IRQ_EXTINT + 247) /* MSGINTR Instance 2, Interrupts */ +#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXTINT + 248) /* V2X-FH MU APCH1 (APP1) interrupt */ +#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXTINT + 249) /* V2X-FH MU APHSM2 (HSM2) interrupt */ +#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXTINT + 250) /* CAMERAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXTINT + 251) /* DISPLAYMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXTINT + 252) /* NETCMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXTINT + 253) /* GPUMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXTINT + 254) /* HSIOMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXTINT + 255) /* VPUMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXTINT + 256) /* AONMIX ERM Single bit corrected ECC Error */ +#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXTINT + 257) /* M7MIX ERM Single bit corrected ECC Error */ +#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXTINT + 258) /* WAKEUPMIX ERM Single bit corrected ECC Error */ +#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXTINT + 259) /* NPUMIX ERM Single bit corrected ECC Error */ +#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXTINT + 260) /* WAKEUPMIX ACP EDMA error interrupt */ +#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXTINT + 261) /* OCRAM_C ECC multiple bit or address error */ +#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXTINT + 262) /* CAMERAMIX Cortex-M0+ Cache write-buffer error */ +#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXTINT + 263) /* CAMERAMIX Cortex-M0+ Cache data parity error */ +#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXTINT + 264) /* V2X-FH MU APSHE (SHE) interrupt */ +#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXTINT + 265) /* V2X-FH MU SCU/APDEBUG (DEBUG) interrupt */ +#define IMX9_IRQ_DMA5_3_0_1 (IMX9_IRQ_EXTINT + 266) /* eDMA3 channel 0/1 interrupt */ +#define IMX9_IRQ_DMA5_3_2_3 (IMX9_IRQ_EXTINT + 267) /* eDMA3 channel 2/3 interrupt */ +#define IMX9_IRQ_DMA5_3_4_5 (IMX9_IRQ_EXTINT + 268) /* eDMA3 channel 4/5 interrupt */ +#define IMX9_IRQ_DMA5_3_6_7 (IMX9_IRQ_EXTINT + 269) /* eDMA3 channel 6/7 interrupt */ +#define IMX9_IRQ_DMA5_3_8_9 (IMX9_IRQ_EXTINT + 270) /* eDMA3 channel 8/9 interrupt */ +#define IMX9_IRQ_DMA5_3_10_11 (IMX9_IRQ_EXTINT + 271) /* eDMA3 channel 10/11 interrupt */ +#define IMX9_IRQ_DMA5_3_12_13 (IMX9_IRQ_EXTINT + 272) /* eDMA3 channel 12/13 interrupt */ +#define IMX9_IRQ_DMA5_3_14_15 (IMX9_IRQ_EXTINT + 273) /* eDMA3 channel 14/15 interrupt */ +#define IMX9_IRQ_DMA5_3_16_17 (IMX9_IRQ_EXTINT + 274) /* eDMA3 channel 16/17 interrupt */ +#define IMX9_IRQ_DMA5_3_18_19 (IMX9_IRQ_EXTINT + 275) /* eDMA3 channel 18/19 interrupt */ +#define IMX9_IRQ_DMA5_3_20_21 (IMX9_IRQ_EXTINT + 276) /* eDMA3 channel 20/21 interrupt */ +#define IMX9_IRQ_DMA5_3_22_23 (IMX9_IRQ_EXTINT + 277) /* eDMA3 channel 22/23 interrupt */ +#define IMX9_IRQ_DMA5_3_24_25 (IMX9_IRQ_EXTINT + 278) /* eDMA3 channel 24/25 interrupt */ +#define IMX9_IRQ_DMA5_3_26_27 (IMX9_IRQ_EXTINT + 279) /* eDMA3 channel 26/27 interrupt */ +#define IMX9_IRQ_DMA5_3_28_29 (IMX9_IRQ_EXTINT + 280) /* eDMA3 channel 29/29 interrupt */ +#define IMX9_IRQ_DMA5_3_30_31 (IMX9_IRQ_EXTINT + 281) /* eDMA3 channel 30/31 interrupt */ +#define IMX9_IRQ_DMA5_3_32_33 (IMX9_IRQ_EXTINT + 282) /* eDMA3 channel 32/33 interrupt */ +#define IMX9_IRQ_DMA5_3_34_35 (IMX9_IRQ_EXTINT + 283) /* eDMA3 channel 34/35 interrupt */ +#define IMX9_IRQ_DMA5_3_36_37 (IMX9_IRQ_EXTINT + 284) /* eDMA3 channel 36/37 interrupt */ +#define IMX9_IRQ_DMA5_3_38_39 (IMX9_IRQ_EXTINT + 285) /* eDMA3 channel 38/39 interrupt */ +#define IMX9_IRQ_DMA5_3_40_41 (IMX9_IRQ_EXTINT + 286) /* eDMA3 channel 40/41 interrupt */ +#define IMX9_IRQ_DMA5_3_42_43 (IMX9_IRQ_EXTINT + 287) /* eDMA3 channel 42/43 interrupt */ +#define IMX9_IRQ_DMA5_3_44_45 (IMX9_IRQ_EXTINT + 288) /* eDMA3 channel 44/45 interrupt */ +#define IMX9_IRQ_DMA5_3_46_47 (IMX9_IRQ_EXTINT + 289) /* eDMA3 channel 46/47 interrupt */ +#define IMX9_IRQ_DMA5_3_48_49 (IMX9_IRQ_EXTINT + 290) /* eDMA3 channel 48/49 interrupt */ +#define IMX9_IRQ_DMA5_3_50_51 (IMX9_IRQ_EXTINT + 291) /* eDMA3 channel 50/51 interrupt */ +#define IMX9_IRQ_DMA5_3_52_53 (IMX9_IRQ_EXTINT + 292) /* eDMA3 channel 52/53 interrupt */ +#define IMX9_IRQ_DMA5_3_54_55 (IMX9_IRQ_EXTINT + 293) /* eDMA3 channel 54/55 interrupt */ +#define IMX9_IRQ_DMA5_3_56_57 (IMX9_IRQ_EXTINT + 294) /* eDMA3 channel 56/57 interrupt */ +#define IMX9_IRQ_DMA5_3_58_59 (IMX9_IRQ_EXTINT + 295) /* eDMA3 channel 58/59 interrupt */ +#define IMX9_IRQ_DMA5_3_60_61 (IMX9_IRQ_EXTINT + 296) /* eDMA3 channel 60/61 interrupt */ +#define IMX9_IRQ_DMA5_3_62_63 (IMX9_IRQ_EXTINT + 297) /* eDMA3 channel 62/63 interrupt */ +#define IMX9_IRQ_RESERVED314 (IMX9_IRQ_EXTINT + 298) /* GPUMIX GPU Interrupt */ +#define IMX9_IRQ_RESERVED315 (IMX9_IRQ_EXTINT + 299) /* GPUMIX Job Interrupt */ +#define IMX9_IRQ_RESERVED316 (IMX9_IRQ_EXTINT + 300) /* GPUMIX MMU Interrupt */ +#define IMX9_IRQ_RESERVED317 (IMX9_IRQ_EXTINT + 301) /* Reserved INTERRUPT */ +#define IMX9_IRQ_RESERVED318 (IMX9_IRQ_EXTINT + 302) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED319 (IMX9_IRQ_EXTINT + 303) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED320 (IMX9_IRQ_EXTINT + 304) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED321 (IMX9_IRQ_EXTINT + 305) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED322 (IMX9_IRQ_EXTINT + 306) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED323 (IMX9_IRQ_EXTINT + 307) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED324 (IMX9_IRQ_EXTINT + 308) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED325 (IMX9_IRQ_EXTINT + 309) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED326 (IMX9_IRQ_EXTINT + 310) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED327 (IMX9_IRQ_EXTINT + 311) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED328 (IMX9_IRQ_EXTINT + 312) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED329 (IMX9_IRQ_EXTINT + 313) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED330 (IMX9_IRQ_EXTINT + 314) /* NETC iEPRC PCI INT */ +#define IMX9_IRQ_RESERVED331 (IMX9_IRQ_EXTINT + 315) /* NETC iEPRC PCI INT */ +#define IMX9_IRQ_RESERVED332 (IMX9_IRQ_EXTINT + 316) /* PCIe Controller 1 INTA */ +#define IMX9_IRQ_RESERVED333 (IMX9_IRQ_EXTINT + 317) /* PCIe Controller 1 INTB */ +#define IMX9_IRQ_RESERVED334 (IMX9_IRQ_EXTINT + 318) /* PCIe Controller 1 INTC */ +#define IMX9_IRQ_RESERVED335 (IMX9_IRQ_EXTINT + 319) /* PCIe Controller 1 INTD */ +#define IMX9_IRQ_RESERVED336 (IMX9_IRQ_EXTINT + 320) /* PCIe interrupts */ +#define IMX9_IRQ_RESERVED337 (IMX9_IRQ_EXTINT + 321) /* PCIe Controller EDMA channel interrupt */ +#define IMX9_IRQ_RESERVED338 (IMX9_IRQ_EXTINT + 322) /* PCIe Controller 1 INTA */ +#define IMX9_IRQ_RESERVED339 (IMX9_IRQ_EXTINT + 323) /* PCIe Controller 1 INTB */ +#define IMX9_IRQ_RESERVED340 (IMX9_IRQ_EXTINT + 324) /* PCIe Controller 1 INTC */ +#define IMX9_IRQ_RESERVED341 (IMX9_IRQ_EXTINT + 325) /* PCIe Controller 1 INTD */ +#define IMX9_IRQ_RESERVED342 (IMX9_IRQ_EXTINT + 326) /* PCIe miscellaneous interrupts */ +#define IMX9_IRQ_RESERVED343 (IMX9_IRQ_EXTINT + 327) /* PCIe Controller EDMA channel interrupt */ +#define IMX9_IRQ_RESERVED344 (IMX9_IRQ_EXTINT + 328) /* Wakeup interrupt from CLKREQ#, WAKEUP#, BEACON_DET */ +#define IMX9_IRQ_RESERVED345 (IMX9_IRQ_EXTINT + 329) /* NPUMIX Functional interrupt */ +#define IMX9_IRQ_RESERVED346 (IMX9_IRQ_EXTINT + 330) /* DISPLAYMIX Real-time traffic TBU: Fault Handling RAS Interrupt for a contained error */ +#define IMX9_IRQ_RESERVED347 (IMX9_IRQ_EXTINT + 331) /* DISPLAYMIX Real-time traffic TBU: Error Handling RAS Interrupt for an uncontained error */ +#define IMX9_IRQ_RESERVED348 (IMX9_IRQ_EXTINT + 332) /* DISPLAYMIX Real-time traffic TBU: Critical Error Interrupt for an uncontainable error */ +#define IMX9_IRQ_RESERVED349 (IMX9_IRQ_EXTINT + 333) /* DISPLAYMIX Real-time traffic TBU: PMU Interrupt */ +#define IMX9_IRQ_RESERVED350 (IMX9_IRQ_EXTINT + 334) /* TCU Event queue, secure interrupt */ +#define IMX9_IRQ_RESERVED351 (IMX9_IRQ_EXTINT + 335) /* TCU Event queue, non-secure interrupt */ +#define IMX9_IRQ_RESERVED352 (IMX9_IRQ_EXTINT + 336) /* TCU SYNC complete, non-secure interrupt */ +#define IMX9_IRQ_RESERVED353 (IMX9_IRQ_EXTINT + 337) /* TCU SYNC complete, secure interrupt */ +#define IMX9_IRQ_RESERVED354 (IMX9_IRQ_EXTINT + 338) /* TCU global non-secure interrupt */ +#define IMX9_IRQ_RESERVED355 (IMX9_IRQ_EXTINT + 339) /* TCU global secure interrupt */ +#define IMX9_IRQ_RESERVED356 (IMX9_IRQ_EXTINT + 340) /* TCU fault handling RAS interrupt for a contained error */ +#define IMX9_IRQ_RESERVED357 (IMX9_IRQ_EXTINT + 341) /* TCU error recovery RAS interrupt for an uncontained error */ +#define IMX9_IRQ_RESERVED358 (IMX9_IRQ_EXTINT + 342) /* TCU critical error interrupt, for an uncontainable uncorrected error */ +#define IMX9_IRQ_RESERVED359 (IMX9_IRQ_EXTINT + 343) /* TCU PMU interrupt */ +#define IMX9_IRQ_RESERVED360 (IMX9_IRQ_EXTINT + 344) /* TCU Page Request Interface */ +#define IMX9_IRQ_RESERVED361 (IMX9_IRQ_EXTINT + 345) /* SRC GPC Low Power Handshake Gasket interrupt request for system management */ +#define IMX9_IRQ_RESERVED362 (IMX9_IRQ_EXTINT + 346) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED363 (IMX9_IRQ_EXTINT + 347) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED364 (IMX9_IRQ_EXTINT + 348) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED365 (IMX9_IRQ_EXTINT + 349) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED366 (IMX9_IRQ_EXTINT + 350) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED367 (IMX9_IRQ_EXTINT + 351) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED368 (IMX9_IRQ_EXTINT + 352) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED369 (IMX9_IRQ_EXTINT + 353) /* CAMERAMIX MU Ored of all */ +#define IMX9_IRQ_RESERVED370 (IMX9_IRQ_EXTINT + 354) /* CAMERAMIX ISI interrupt Channel 1 */ +#define IMX9_IRQ_RESERVED371 (IMX9_IRQ_EXTINT + 355) /* CAMERAMIX ISI interrupt Channel 2 */ +#define IMX9_IRQ_RESERVED372 (IMX9_IRQ_EXTINT + 356) /* CAMERAMIX ISI interrupt Channel 3 */ +#define IMX9_IRQ_RESERVED373 (IMX9_IRQ_EXTINT + 357) /* CAMERAMIX ISI interrupt Channel 4 */ +#define IMX9_IRQ_RESERVED374 (IMX9_IRQ_EXTINT + 358) /* CAMERAMIX ISI interrupt Channel 5 */ +#define IMX9_IRQ_RESERVED375 (IMX9_IRQ_EXTINT + 359) /* CAMERAMIX ISI interrupt Channel 6 */ +#define IMX9_IRQ_RESERVED376 (IMX9_IRQ_EXTINT + 360) /* CAMERAMIX ISI interrupt Channel 7 */ +#define IMX9_IRQ_DMA5_4_ERROR (IMX9_IRQ_EXTINT + 361) /* CAMERAMIX EDMA error interrupt */ +#define IMX9_IRQ_DMA5_4_0_1 (IMX9_IRQ_EXTINT + 362) /* CAMERAMIX EDMA channel 0 interrupt */ +#define IMX9_IRQ_DMA5_4_2_3 (IMX9_IRQ_EXTINT + 363) /* CAMERAMIX EDMA channel 2 interrupt */ +#define IMX9_IRQ_DMA5_4_4_5 (IMX9_IRQ_EXTINT + 364) /* CAMERAMIX EDMA channel 4 interrupt */ +#define IMX9_IRQ_DMA5_4_6_7 (IMX9_IRQ_EXTINT + 365) /* CAMERAMIX EDMA channel 6 interrupt */ +#define IMX9_IRQ_DMA5_4_8_9 (IMX9_IRQ_EXTINT + 366) /* CAMERAMIX EDMA channel 8 interrupt */ +#define IMX9_IRQ_DMA5_4_10_11 (IMX9_IRQ_EXTINT + 367) /* CAMERAMIX EDMA channel 10 interrupt */ +#define IMX9_IRQ_DMA5_4_12_13 (IMX9_IRQ_EXTINT + 368) /* CAMERAMIX EDMA channel 12 interrupt */ +#define IMX9_IRQ_DMA5_4_14_15 (IMX9_IRQ_EXTINT + 369) /* CAMERAMIX EDMA channel 14 interrupt */ +#define IMX9_IRQ_DMA5_4_16_17 (IMX9_IRQ_EXTINT + 370) /* CAMERAMIX EDMA channel 16 interrupt */ +#define IMX9_IRQ_DMA5_4_18_19 (IMX9_IRQ_EXTINT + 371) /* CAMERAMIX EDMA channel 18 interrupt */ +#define IMX9_IRQ_DMA5_4_20_21 (IMX9_IRQ_EXTINT + 372) /* CAMERAMIX EDMA channel 20 interrupt */ +#define IMX9_IRQ_DMA5_4_22_23 (IMX9_IRQ_EXTINT + 373) /* CAMERAMIX EDMA channel 22 interrupt */ +#define IMX9_IRQ_DMA5_4_24_25 (IMX9_IRQ_EXTINT + 374) /* CAMERAMIX EDMA channel 24 interrupt */ +#define IMX9_IRQ_DMA5_4_26_27 (IMX9_IRQ_EXTINT + 375) /* CAMERAMIX EDMA channel 26 interrupt */ +#define IMX9_IRQ_DMA5_4_28_29 (IMX9_IRQ_EXTINT + 376) /* CAMERAMIX EDMA channel 28 interrupt */ +#define IMX9_IRQ_DMA5_4_30_31 (IMX9_IRQ_EXTINT + 377) /* CAMERAMIX EDMA channel 30 interrupt */ +#define IMX9_IRQ_RESERVED394 (IMX9_IRQ_EXTINT + 378) /* CAMERAMIX CSI Formatting Unit 1: Buffer overflow */ +#define IMX9_IRQ_RESERVED395 (IMX9_IRQ_EXTINT + 379) /* CAMERAMIX CSI Formatting Unit 1: Interlaced Error */ +#define IMX9_IRQ_RESERVED396 (IMX9_IRQ_EXTINT + 380) /* CAMERAMIX CSI Formatting Unit 1: Pixel Data Type Error */ +#define IMX9_IRQ_RESERVED397 (IMX9_IRQ_EXTINT + 381) /* CAMERAMIX CSI Formatting Unit 2: Buffer overflow */ +#define IMX9_IRQ_RESERVED398 (IMX9_IRQ_EXTINT + 382) /* CAMERAMIX CSI Formatting Unit 2: Interlaced Error */ +#define IMX9_IRQ_RESERVED399 (IMX9_IRQ_EXTINT + 383) /* CAMERAMIX CSI Formatting Unit 2: Pixel Data Type Error */ +#define IMX9_IRQ_RESERVED400 (IMX9_IRQ_EXTINT + 384) /* CAMERAMIX CSI1 */ +#define IMX9_IRQ_RESERVED401 (IMX9_IRQ_EXTINT + 385) /* CAMERAMIX CSI2 */ + +#define IMX9_IRQ_NEXTINT (218) + +/* Total amount of entries in system vector table */ + +#define NR_IRQS (IMX9_IRQ_EXTINT + IMX9_IRQ_NEXTINT) + +#endif /* __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H */ diff --git a/arch/arm/include/imx9/irq.h b/arch/arm/include/imx9/irq.h new file mode 100644 index 0000000000000..2af7d08ff7260 --- /dev/null +++ b/arch/arm/include/imx9/irq.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/include/imx9/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_IMX9_IRQ_H +#define __ARCH_ARM_INCLUDE_IMX9_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include +#else +# error "Unrecognized i.MX9 architecture" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words + * of memory in the IRQ to handle mapping tables. + */ + +/* Common Processor Exceptions (vectors 0-15) */ + +#define IMX9_IRQ_RESERVED (0) /* Reserved vector .. only used with + * CONFIG_DEBUG_FEATURES */ + + /* Vector 0: Reset stack pointer value */ + + /* Vector 1: Reset(not handled by IRQ) */ + +#define IMX9_IRQ_NMI (2) /* Vector 2: Non-Maskable Int (NMI) */ +#define IMX9_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define IMX9_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define IMX9_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define IMX9_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ + +#define IMX9_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define IMX9_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ + +#define IMX9_IRQ_PENDSV (14) /* Vector 14: Pendable SSR */ +#define IMX9_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* Chip-Specific External interrupts */ + +#define IMX9_IRQ_EXTINT (16) /* Vector number of the first ext int */ +#define ARMV7M_PERIPHERAL_INTERRUPTS IMX9_IRQ_NEXTINT + +#endif /* __ARCH_ARM_INCLUDE_IMX9_IRQ_H */ diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index 2ef56cd2a87b7..6b38e160bead7 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -52,7 +52,7 @@ ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1 -static volatile cpu_set_t g_gic_init_done; +static atomic_t g_gic_init_done; #endif /**************************************************************************** @@ -72,11 +72,7 @@ static volatile cpu_set_t g_gic_init_done; #if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1 static void arm_gic_init_done(void) { - irqstate_t flags; - - flags = spin_lock_irqsave(NULL); - CPU_SET(this_cpu(), &g_gic_init_done); - spin_unlock_irqrestore(NULL, flags); + atomic_fetch_or(&g_gic_init_done, 1 << this_cpu()); } static void arm_gic_wait_done(cpu_set_t cpuset) @@ -85,7 +81,7 @@ static void arm_gic_wait_done(cpu_set_t cpuset) do { - CPU_AND(&tmpset, &g_gic_init_done, &cpuset); + tmpset = (cpu_set_t)atomic_read(&g_gic_init_done) & cpuset; } while (!CPU_EQUAL(&tmpset, &cpuset)); } diff --git a/arch/arm/src/common/CMakeLists.txt b/arch/arm/src/common/CMakeLists.txt index b0f87f4a78f69..4353c82435aa8 100644 --- a/arch/arm/src/common/CMakeLists.txt +++ b/arch/arm/src/common/CMakeLists.txt @@ -33,9 +33,7 @@ set(SRCS arm_getintstack.c arm_initialize.c arm_lowputs.c - arm_modifyreg8.c - arm_modifyreg16.c - arm_modifyreg32.c + arm_modifyreg.c arm_nputs.c arm_releasestack.c arm_registerdump.c diff --git a/arch/arm/src/common/Make.defs b/arch/arm/src/common/Make.defs index c099dbe02e7ce..1694083e28ae5 100644 --- a/arch/arm/src/common/Make.defs +++ b/arch/arm/src/common/Make.defs @@ -24,9 +24,8 @@ CMN_CSRCS += arm_allocateheap.c arm_createstack.c arm_exit.c CMN_CSRCS += arm_getintstack.c arm_initialize.c arm_lowputs.c -CMN_CSRCS += arm_modifyreg8.c arm_modifyreg16.c arm_modifyreg32.c CMN_CSRCS += arm_nputs.c arm_releasestack.c arm_registerdump.c -CMN_CSRCS += arm_stackframe.c +CMN_CSRCS += arm_stackframe.c arm_modifyreg.c CMN_CSRCS += arm_usestack.c arm_fork.c ifneq ($(CONFIG_ALARM_ARCH),y) diff --git a/arch/arm/src/common/arm_modifyreg.c b/arch/arm/src/common/arm_modifyreg.c new file mode 100644 index 0000000000000..c1818a7dc12bf --- /dev/null +++ b/arch/arm/src/common/arm_modifyreg.c @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/arm/src/common/arm_modifyreg.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg8 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) +{ + irqstate_t flags; + uint8_t regval; + + flags = spin_lock_irqsave(&g_modifyreg_lock); + regval = getreg8(addr); + regval &= ~clearbits; + regval |= setbits; + putreg8(regval, addr); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); +} + +/**************************************************************************** + * Name: modifyreg16 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) +{ + irqstate_t flags; + uint16_t regval; + + flags = spin_lock_irqsave(&g_modifyreg_lock); + regval = getreg16(addr); + regval &= ~clearbits; + regval |= setbits; + putreg16(regval, addr); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); +} + +/**************************************************************************** + * Name: modifyreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + uint32_t regval; + + flags = spin_lock_irqsave(&g_modifyreg_lock); + regval = getreg32(addr); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, addr); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); +} diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index 9e70547ba7750..560591923175b 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -134,6 +134,7 @@ struct efm32_leuart_s { const struct efm32_config_s *config; uint16_t ien; /* Interrupts enabled */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -212,6 +213,7 @@ static const struct efm32_config_s g_leuart0config = static struct efm32_leuart_s g_leuart0priv = { .config = &g_leuart0config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_leuart0port = @@ -247,6 +249,7 @@ static struct efm32_config_s g_leuart1config = static struct efm32_leuart_s g_leuart1priv = { .config = &g_leuart1config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_leuart1port = @@ -303,6 +306,17 @@ static inline void efm32_setuartint(struct efm32_leuart_s *priv) * Name: efm32_restoreuartint ****************************************************************************/ +static void efm32_restoreuartint_nolock(struct efm32_leuart_s *priv, + uint32_t ien) +{ + /* Re-enable/re-disable interrupts corresponding to the state of + * bits in ien. + */ + + priv->ien = ien; + efm32_setuartint(priv); +} + static void efm32_restoreuartint(struct efm32_leuart_s *priv, uint32_t ien) { irqstate_t flags; @@ -311,10 +325,9 @@ static void efm32_restoreuartint(struct efm32_leuart_s *priv, uint32_t ien) * bits in ien. */ - flags = spin_lock_irqsave(NULL); - priv->ien = ien; - efm32_setuartint(priv); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + efm32_restoreuartint_nolock(priv, len); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -325,14 +338,14 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ien) { *ien = priv->ien; } - efm32_restoreuartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + efm32_restoreuartint_nolock(priv, 0); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -607,7 +620,7 @@ static void efm32_rxint(struct uart_dev_s *dev, bool enable) struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&priv->lock); if (enable) { /* Receive an interrupt when there is anything in the Rx data register @@ -625,7 +638,7 @@ static void efm32_rxint(struct uart_dev_s *dev, bool enable) efm32_setuartint(priv); } - leave_critical_section(flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -673,7 +686,7 @@ static void efm32_txint(struct uart_dev_s *dev, bool enable) struct efm32_leuart_s *priv = (struct efm32_leuart_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&priv->lock); if (enable) { /* Enable the TX interrupt */ @@ -697,7 +710,7 @@ static void efm32_txint(struct uart_dev_s *dev, bool enable) efm32_setuartint(priv); } - leave_critical_section(flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index a2bfcbbe5fd9a..087465195d550 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -223,6 +223,7 @@ struct efm32_usart_s const struct efm32_config_s *config; #endif uint16_t ien; /* Interrupts enabled */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -303,7 +304,7 @@ static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; /* This describes the state of the EFM32 USART0 port. */ #ifdef CONFIG_EFM32_USART0_ISUART -static const struct efm32_usart_s g_usart0config = +static const struct efm32_config_s g_usart0config = { .uartbase = EFM32_USART0_BASE, .baud = CONFIG_USART0_BAUD, @@ -317,6 +318,7 @@ static const struct efm32_usart_s g_usart0config = static struct efm32_usart_s g_usart0priv = { .config = &g_usart0config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_usart0port = @@ -353,6 +355,7 @@ static struct efm32_config_s g_usart1config = static struct efm32_usart_s g_usart1priv = { .config = &g_usart1config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_usart1port = @@ -389,6 +392,7 @@ static struct efm32_config_s g_usart2config = static struct efm32_usart_s g_usart2priv = { .config = &g_usart2config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_usart2port = @@ -425,6 +429,7 @@ static struct efm32_config_s g_uart0config = static struct efm32_usart_s g_uart0priv = { .config = &g_uart0config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_uart0port = @@ -447,7 +452,7 @@ static struct uart_dev_s g_uart0port = /* This describes the state of the EFM32 UART1 port. */ #ifdef CONFIG_EFM32_UART1 -static struct efm32_usart_s g_uart1config = +static struct efm32_config_s g_uart1config = { .uartbase = EFM32_UART1_BASE, .baud = CONFIG_UART1_BAUD, @@ -461,6 +466,7 @@ static struct efm32_usart_s g_uart1config = static struct efm32_usart_s g_uart1priv = { .config = &g_uart1config, + .lock = SP_UNLOCKED }; static struct uart_dev_s g_uart1port = @@ -516,6 +522,13 @@ static inline void efm32_setuartint(struct efm32_usart_s *priv) * Name: efm32_restoreuartint ****************************************************************************/ +static void efm32_restoreuartint_nolock(struct efm32_usart_s *priv, + uint32_t ien) +{ + priv->ien = ien; + efm32_setuartint(priv); +} + static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien) { irqstate_t flags; @@ -524,10 +537,9 @@ static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien) * ien */ - flags = spin_lock_irqsave(NULL); - priv->ien = ien; - efm32_setuartint(priv); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + efm32_restoreuartint_nolock(priv, len); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -539,14 +551,14 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ien) { *ien = priv->ien; } - efm32_restoreuartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + efm32_restoreuartint_nolock(priv, 0); + spin_unlock_irqrestore(&priv->lock, flags); } #endif @@ -966,7 +978,7 @@ static void efm32_rxint(struct uart_dev_s *dev, bool enable) struct efm32_usart_s *priv = (struct efm32_usart_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&priv->lock); if (enable) { /* Receive an interrupt when their is anything in the Rx data register @@ -984,7 +996,7 @@ static void efm32_rxint(struct uart_dev_s *dev, bool enable) efm32_setuartint(priv); } - leave_critical_section(flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -1032,7 +1044,7 @@ static void efm32_txint(struct uart_dev_s *dev, bool enable) struct efm32_usart_s *priv = (struct efm32_usart_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&priv->lock); if (enable) { /* Enable the TX interrupt */ @@ -1056,7 +1068,7 @@ static void efm32_txint(struct uart_dev_s *dev, bool enable) efm32_setuartint(priv); } - leave_critical_section(flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 49176c6b52fc3..ad903b6c7a59d 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -131,6 +131,7 @@ struct up_dev_s uint8_t stop_2bits; /* True: Configure with 2 stop bits instead of 1 */ uint32_t tx_gpio; /* USART TX GPIO pin configuration */ uint32_t rx_gpio; /* USART RX GPIO pin configuration */ + spinlock_t lock; /* Spinlock */ # ifdef CONFIG_SERIAL_IFLOWCONTROL uint32_t rts_gpio; /* UART RTS GPIO pin configuration */ @@ -437,6 +438,7 @@ static struct up_dev_s g_usart0priv = .tx_gpio = GPIO_USART0_TX, .rx_gpio = GPIO_USART0_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART0_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART0_RTS, @@ -509,6 +511,7 @@ static struct up_dev_s g_usart1priv = .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART1_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART1_RTS, @@ -581,6 +584,7 @@ static struct up_dev_s g_usart2priv = .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART2_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART2_RTS, @@ -653,6 +657,7 @@ static struct up_dev_s g_usart5priv = .tx_gpio = GPIO_USART5_TX, .rx_gpio = GPIO_USART5_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART5_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_USART5_RTS, @@ -725,6 +730,7 @@ static struct up_dev_s g_uart3priv = .tx_gpio = GPIO_UART3_TX, .rx_gpio = GPIO_UART3_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART3_RTS, @@ -797,6 +803,7 @@ static struct up_dev_s g_uart4priv = .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART4_RTS, @@ -869,6 +876,7 @@ static struct up_dev_s g_uart6priv = .tx_gpio = GPIO_UART6_TX, .rx_gpio = GPIO_UART6_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART6_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART6_RTS, @@ -941,6 +949,7 @@ static struct up_dev_s g_uart7priv = .tx_gpio = GPIO_UART7_TX, .rx_gpio = GPIO_UART7_RX, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL) .iflow = true, .rts_gpio = GPIO_UART7_RTS, @@ -1127,7 +1136,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint32_t *ie) irqstate_t flags; uint32_t ctl_ie; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -1161,7 +1170,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint32_t *ie) ctl_ie = (USART_CFG_CTL_MASK << USART_CFG_SHIFT); up_setusartint(priv, ctl_ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -1172,11 +1181,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint32_t ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); up_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/imx6/imx_serial.c b/arch/arm/src/imx6/imx_serial.c index 99c7c384ea722..ae2948c90c1e7 100644 --- a/arch/arm/src/imx6/imx_serial.c +++ b/arch/arm/src/imx6/imx_serial.c @@ -196,6 +196,7 @@ struct imx_uart_s uint32_t ucr1; /* Saved UCR1 value */ uint8_t irq; /* IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ + spinlock_t lock; /* Spinlock */ uint8_t bits; /* Number of bits (7 or 8) */ uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ #ifdef CONFIG_SERIAL_IFLOWCONTROL @@ -295,6 +296,7 @@ static struct imx_uart_s g_uart1priv = .baud = CONFIG_UART1_BAUD, .irq = IMX_IRQ_UART1, .parity = CONFIG_UART1_PARITY, + .lock = SP_UNLOCKED, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, }; @@ -325,6 +327,7 @@ static struct imx_uart_s g_uart2priv = .baud = CONFIG_UART2_BAUD, .irq = IMX_IRQ_UART2, .parity = CONFIG_UART2_PARITY, + .lock = SP_UNLOCKED .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, }; @@ -353,6 +356,7 @@ static struct imx_uart_s g_uart3priv = .baud = IMX_UART3_VBASE, .irq = IMX_IRQ_UART3, .parity = CONFIG_UART3_PARITY, + .lock = SP_UNLOCKED .bits = CONFIG_UART3_BITS, .stopbits2 = CONFIG_UART3_2STOP, }; @@ -381,6 +385,7 @@ static struct imx_uart_s g_uart4priv = .baud = IMX_UART4_VBASE, .irq = IMX_IRQ_UART4, .parity = CONFIG_UART4_PARITY, + .lock = SP_UNLOCKED .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, }; @@ -409,6 +414,7 @@ static struct imx_uart_s g_uart5priv = .baud = IMX_UART5_VBASE, .irq = IMX_IRQ_UART5, .parity = CONFIG_UART5_PARITY, + .lock = SP_UNLOCKED .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, }; @@ -877,7 +883,7 @@ static int imx_ioctl(struct file *filep, int cmd, unsigned long arg) * implement TCSADRAIN / TCSAFLUSH */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); imx_disableuartint(priv, &ie); ret = imx_setup(dev); @@ -885,7 +891,7 @@ static int imx_ioctl(struct file *filep, int cmd, unsigned long arg) imx_restoreuartint(priv, ie); priv->ie = ie; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } } break; diff --git a/arch/arm/src/imx9/CMakeLists.txt b/arch/arm/src/imx9/CMakeLists.txt new file mode 100644 index 0000000000000..46a399cfce316 --- /dev/null +++ b/arch/arm/src/imx9/CMakeLists.txt @@ -0,0 +1,86 @@ +# ############################################################################## +# arch/arm/src/imx9/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS + imx9_allocateheap.c + imx9_start.c + imx9_clockconfig.c + imx9_gpio.c + imx9_iomuxc.c + imx9_irq.c + imx9_timerisr.c + imx9_idle.c) + +if(CONFIG_IMX9_SCMI) + list(APPEND SRCS imx9_scmi.c) + # NXP SDK SCMI interface for pinctrl and clocking +endif() + +if(CONFIG_RPTUN) + list(APPEND SRCS imx9_rsctable.c imx9_rptun.c) +endif() + +if(CONFIG_IMX9_MU) + list(APPEND SRCS imx9_mu.c) +endif() + +if(CONFIG_ARM_MPU) + list(APPEND SRCS imx9_mpuinit.c) +endif() + +if(CONFIG_IMX9_FLEXCAN) + list(APPEND SRCS imx9_flexcan.c) +endif() + +if(CONFIG_IMX9_LPUART) + list(APPEND SRCS imx9_lpuart.c imx9_lowputc.c) +endif() + +if(CONFIG_IMX9_GPIO_IRQ) + list(APPEND SRCS imx9_gpioirq.c) +endif() + +if(CONFIG_IMX9_FLEXIO_PWM) + list(APPEND SRCS imx9_flexio_pwm.c) +endif() + +if(CONFIG_IMX9_TPM_PWM) + list(APPEND SRCS imx9_tpm_pwm.c) +endif() + +if(CONFIG_IMX9_USBDEV) + list(APPEND SRCS imx9_usbdev.c) +endif() + +if(CONFIG_IMX9_LPI2C) + list(APPEND SRCS imx9_lpi2c.c) +endif() + +if(CONFIG_IMX9_LPSPI) + list(APPEND SRCS imx9_lpspi.c) +endif() + +if(CONFIG_IMX9_EDMA) + list(APPEND SRCS imx9_edma.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/imx9/Kconfig b/arch/arm/src/imx9/Kconfig new file mode 100644 index 0000000000000..3d58f0f850375 --- /dev/null +++ b/arch/arm/src/imx9/Kconfig @@ -0,0 +1,877 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_IMX9_CORTEX_M + +menu "i.MX9 Chip Selection" + +choice + prompt "i.MX9 Core Configuration" + default ARCH_CHIP_IMX95_M7 + +config ARCH_CHIP_IMX95_M7 + bool "i.MX95 Cortex-M7 Processor" + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARMV7M_HAVE_ICACHE + select ARMV7M_HAVE_DCACHE + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select IMX9_HAVE_MU + +endchoice # i.MX9 Chip Selection + +endmenu # "i.MX9 Chip Selection" + +config IMX9_HAVE_MU + bool + default n + +config IMX9_SCMI + bool "SCMI Interface" + default y + depends on IMX9_MU5 + +if IMX9_SCMI + +config IMX9_CLK_OVER_SCMI + bool "Configure CLK over SCMI" + default y + +config IMX9_IOMUX_OVER_SCMI + bool "Configure IOMUX over SCMI" + default n + +endif + +menu "i.MX9 Peripheral Selection" + +config IMX9_EDMA + bool "eDMA" + default n + select ARCH_DMA + +menu "FLEXCAN Peripherals" + +config IMX9_FLEXCAN + bool + default n + select NET_CAN_HAVE_TX_DEADLINE + select NET_CAN_HAVE_CANFD + +config IMX9_FLEXCAN1 + bool "FLEXCAN1" + default n + select IMX9_FLEXCAN + +config IMX9_FLEXCAN2 + bool "FLEXCAN2" + default n + select IMX9_FLEXCAN + +config IMX9_FLEXCAN3 + bool "FLEXCAN3" + default n + select IMX9_FLEXCAN + +config IMX9_FLEXCAN4 + bool "FLEXCAN4" + default n + select IMX9_FLEXCAN + +config IMX9_FLEXCAN5 + bool "FLEXCAN5" + default n + select IMX9_FLEXCAN + +if IMX9_FLEXCAN + +config IMX9_FLEXCAN_TXMB + int "Number of TX message buffers" + default 5 + ---help--- + This defines number of TX messages buffers. Please note that + maximum number of all message buffers is 20 + +config IMX9_FLEXCAN_RXMB + int "Number of RX message buffers" + default 15 + ---help--- + This defines number of RX messages buffers. Please note that + maximum number of all message buffers is 20 + +endif + +endmenu # FLEXCAN Peripherals + +menu "FLEXCAN1 Configuration" + depends on IMX9_FLEXCAN1 + +config FLEXCAN1_BITRATE + int "CAN bitrate" + depends on !(NET_CAN_CANFD) + default 1000000 + +config FLEXCAN1_SAMPLEP + int "CAN sample point" + depends on !(NET_CAN_CANFD) + default 80 + +config FLEXCAN1_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FLEXCAN1_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN1_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN1_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMX9_FLEXCAN1 + +menu "FLEXCAN2 Configuration" + depends on IMX9_FLEXCAN2 + +config FLEXCAN2_BITRATE + int "CAN bitrate" + depends on !(NET_CAN_CANFD && IMX9_FLEXCAN2_FD) + default 1000000 + +config FLEXCAN2_SAMPLEP + int "CAN sample point" + depends on !(NET_CAN_CANFD && IMX9_FLEXCAN2_FD) + default 80 + +config FLEXCAN2_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD + default 1000000 + +config FLEXCAN2_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD + default 80 + +config FLEXCAN2_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD + default 4000000 + +config FLEXCAN2_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD && IMX9_FLEXCAN2_FD + default 90 + +endmenu # IMX9_FLEXCAN2 + +menu "FLEXCAN3 Configuration" + depends on IMX9_FLEXCAN3 + +config FLEXCAN3_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FLEXCAN3_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config FLEXCAN3_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FLEXCAN3_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN3_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN3_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMX9_FLEXCAN3 + +menu "FLEXCAN4 Configuration" + depends on IMX9_FLEXCAN4 + +config FLEXCAN4_BITRATE + int "CAN bitrate" + depends on !(NET_CAN_CANFD) + default 4000000 + +config FLEXCAN4_SAMPLEP + int "CAN sample point" + depends on !(NET_CAN_CANFD) + default 80 + +config FLEXCAN4_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN4_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN4_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN4_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMX9_FLEXCAN4 + +menu "FLEXCAN5 Configuration" + depends on IMX9_FLEXCAN5 + +config FLEXCAN5_BITRATE + int "CAN bitrate" + depends on !(NET_CAN_CANFD) + default 5000000 + +config FLEXCAN5_SAMPLEP + int "CAN sample point" + depends on !(NET_CAN_CANFD) + default 80 + +config FLEXCAN5_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 5000000 + +config FLEXCAN5_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config FLEXCAN5_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config FLEXCAN5_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMX9_FLEXCAN5 + +menu "LPUART" + +config IMX9_LPUART + bool + default n + select ARCH_HAVE_SERIAL_TERMIOS + +config IMX9_LPUART1 + bool "LPUART1" + default n + select IMX9_LPUART + select LPUART1_SERIALDRIVER + +config IMX9_LPUART2 + bool "LPUART2" + default n + select IMX9_LPUART + select LPUART2_SERIALDRIVER + +config IMX9_LPUART3 + bool "LPUART3" + default n + select IMX9_LPUART + select LPUART3_SERIALDRIVER + +config IMX9_LPUART4 + bool "LPUART4" + default n + select IMX9_LPUART + select LPUART4_SERIALDRIVER + +config IMX9_LPUART5 + bool "LPUART5" + default n + select IMX9_LPUART + select LPUART5_SERIALDRIVER + +config IMX9_LPUART6 + bool "LPUART6" + default n + select IMX9_LPUART + select LPUART6_SERIALDRIVER + +config IMX9_LPUART7 + bool "LPUART7" + default n + select IMX9_LPUART + select LPUART7_SERIALDRIVER + +config IMX9_LPUART8 + bool "LPUART8" + default n + select IMX9_LPUART + select LPUART8_SERIALDRIVER + +menu "LPUART Configuration" + depends on IMX9_LPUART + +config IMX9_LPUART_INVERT + bool "Signal Invert Support" + default n + +config IMX9_LPUART_SINGLEWIRE + bool "Signal Wire Support" + default n + +config IMX9_SERIAL_RXDMA_BUFFER_SIZE + int "RX DMA buffer size" + default 64 + depends on LPUART1_RXDMA || LPUART2_RXDMA || LPUART3_RXDMA || LPUART4_RXDMA || \ + LPUART5_RXDMA || LPUART6_RXDMA || LPUART7_RXDMA || LPUART8_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half this number of bytes. + + Value given here will be rounded up to next multiple of 64 bytes. + +endmenu # LPUART Configuration + +endmenu # LPUART + +config IMX9_GPIO_IRQ + bool "GPIO Interrupt Support" + default n + +config IMX9_LPI2C + bool "LPI2C support" + default n + +config IMX9_LPSPI + bool "LPSPI support" + default n + +menu "LPI2C Peripherals" + +menuconfig IMX9_LPI2C1 + bool "LPI2C1" + default n + select IMX9_LPI2C + +if IMX9_LPI2C1 + +config IMX9_LPI2C1_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C1_DMA + bool "Enable DMA for I2C1" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C1_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C1_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C1 + +menuconfig IMX9_LPI2C2 + bool "LPI2C2" + default n + select IMX9_LPI2C + +if IMX9_LPI2C2 + +config IMX9_LPI2C2_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C2_DMA + bool "Enable DMA for I2C2" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C2_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C2_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C2 + +menuconfig IMX9_LPI2C3 + bool "LPI2C3" + default n + select IMX9_LPI2C + +if IMX9_LPI2C3 + +config IMX9_LPI2C3_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C3_DMA + bool "Enable DMA for I2C3" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C3_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C3_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C3 + +menuconfig IMX9_LPI2C4 + bool "LPI2C4" + default n + select IMX9_LPI2C + +if IMX9_LPI2C4 + +config IMX9_LPI2C4_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C4_DMA + bool "Enable DMA for I2C4" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C4_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C4_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C4 + +menuconfig IMX9_LPI2C5 + bool "LPI2C5" + default n + select IMX9_LPI2C + +if IMX9_LPI2C5 + +config IMX9_LPI2C5_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C5_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C5_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C5 + +menuconfig IMX9_LPI2C6 + bool "LPI2C6" + default n + select IMX9_LPI2C + +if IMX9_LPI2C6 + +config IMX9_LPI2C6_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C6_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C6_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C6 + +menuconfig IMX9_LPI2C7 + bool "LPI2C7" + default n + select IMX9_LPI2C + +if IMX9_LPI2C7 + +config IMX9_LPI2C7_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C7_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C7_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C7 + +menuconfig IMX9_LPI2C8 + bool "LPI2C8" + default n + select IMX9_LPI2C + +if IMX9_LPI2C8 + +config IMX9_LPI2C8_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C8_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C8_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C8 + +endmenu # LPI2C Peripherals + +menu "LPSPI Peripherals" + +menuconfig IMX9_LPSPI1 + bool "LPSPI1" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI2 + bool "LPSPI2" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI3 + bool "LPSPI3" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI4 + bool "LPSPI4" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI5 + bool "LPSPI5" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI6 + bool "LPSPI6" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI7 + bool "LPSPI7" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI8 + bool "LPSPI8" + default n + select IMX9_LPSPI + +endmenu # LPSPI Peripherals + +menu "eDMA Configuration" + depends on IMX9_EDMA + +config IMX9_EDMA_NTCD + int "Number of transfer descriptors" + default 0 + ---help--- + Number of pre-allocated transfer descriptors. Needed for scatter- + gather DMA. Make to be set to zero to disable in-memory TCDs in + which case only the TCD channel registers will be used and scatter- + will not be supported. + +config IMX9_EDMA_ELINK + bool "Channeling Linking" + default n + ---help--- + This option enables optional minor or major loop channel linking: + + Minor loop channel linking: As the channel completes the minor + loop, this flag enables linking to another channel. The link target + channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the specified + channel. + + If minor loop channel linking is disabled, this link mechanism is + suppressed in favor of the major loop channel linking. + + Major loop channel linking: As the channel completes the minor + loop, this option enables the linking to another channel. The link + target channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the linked channel. + +config IMX9_EDMA_ERCA + bool "Round Robin Channel Arbitration" + default n + ---help--- + Normally, a fixed priority arbitration is used for channel + selection. If this option is selected, round robin arbitration is + used for channel selection. + +config IMX9_EDMA_HOE + bool "Halt On Error" + default y + ---help--- + Any error causes the HALT bit to set. Subsequently, all service + requests are ignored until the HALT bit is cleared. + +config IMX9_EDMA_CLM + bool "Continuous Link Mode" + default n + ---help--- + By default, A minor loop channel link made to itself goes through + channel arbitration before being activated again. If this option is + selected, a minor loop channel link made to itself does not go + through channel arbitration before being activated again. Upon minor + loop completion, the channel activates again if that channel has a + minor loop channel link enabled and the link channel is itself. This + effectively applies the minor loop offsets and restarts the next + minor loop. + +config IMX9_EDMA_EMLIM + bool "Minor Loop Mapping" + default n + ---help--- + Normally TCD word 2 is a 32-bit NBYTES field. When this option is + enabled, TCD word 2 is redefined to include individual enable fields, + an offset field, and the NBYTES field. The individual enable fields + allow the minor loop offset to be applied to the source address, the + destination address, or both. The NBYTES field is reduced when either + offset is enabled. + +config IMX9_EDMA_EDBG + bool "Enable Debug" + default n + ---help--- + When in debug mode, the DMA stalls the start of a new channel. Executing + channels are allowed to complete. Channel execution resumes when the + system exits debug mode or the EDBG bit is cleared + +endmenu # eDMA Global Configuration + +menu "i.MX 95 Memory Configuration" + +config IMX9_OCRAM_HEAP + bool "Add OCRAM to heap" + depends on !IMX9_OCRAM_PRIMARY + ---help--- + Select to add the entire OCRAM to the heap + +config IMX9_INIT_ISRAM + bool "Calls out to the board code to set instruction RAM" + ---help--- + Some configuration will need to map instruction ram (ITCM) + this must be done prior to data/bss etc init. + +endmenu # i.MX 95 Heap Configuration + +menu "LPI2C Configuration" + depends on IMX9_LPI2C + +config IMX9_LPI2C_DMA + bool "I2C DMA Support" + default n + depends on IMX9_LPI2C && IMX9_EDMA && !I2C_POLLED + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value + for the I2C dma streams, else the default priority level is set to + medium. + +config IMX9_LPI2C_DMA_MAXMSG + int "Maximum number messages that will be DMAed" + default 8 + depends on IMX9_LPI2C_DMA + ---help--- + This option set the mumber of mesg that can be in a transfer. + It is used to allocate space for the 16 bit LPI2C commands + that will be DMA-ed to the LPI2C device. + +config IMX9_LPI2C_DYNTIMEO + bool "Use dynamic timeouts" + default n + depends on IMX9_LPI2C + +config IMX9_LPI2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + default 500 + depends on IMX9_LPI2C_DYNTIMEO + +config IMX9_LPI2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + default 1000 + depends on IMX9_LPI2C_DYNTIMEO + +config IMX9_LPI2C_TIMEOSEC + int "Timeout seconds" + default 0 + depends on IMX9_LPI2C + +config IMX9_LPI2C_TIMEOMS + int "Timeout Milliseconds" + default 500 + depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO + +config IMX9_LPI2C_TIMEOTICKS + int "Timeout for Done and Stop (ticks)" + default 500 + depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO + +endmenu # LPI2C Configuration + +menu "LPSPI Configuration" + depends on IMX9_LPSPI + +config IMX9_LPSPI_DMA + bool "LPSPI DMA" + depends on IMX9_EDMA + default n + ---help--- + Use DMA to improve LPSPI transfer performance. + +config IMX9_LPSPI_DMATHRESHOLD + int "LPSPI DMA threshold" + default 4 + depends on IMX9_LPSPI_DMA + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config IMX9_LPSPI_HWPCS + bool "Use native hardware peripheral chip selects instead of GPIO pins" + default n + +config IMX9_LPSPI1_DMA + bool "LPSPI1 DMA" + default n + depends on IMX9_LPSPI1 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve LPSPI1 transfer performance. + +config IMX9_LPSPI2_DMA + bool "LPSPI2 DMA" + default n + depends on IMX9_LPSPI2 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve LPSPI2 transfer performance. + +config IMX9_LPSPI3_DMA + bool "LPSPI3 DMA" + default n + depends on IMX9_LPSPI3 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve LPSPI3 transfer performance. + +config IMX9_LPSPI4_DMA + bool "LPSPI4 DMA" + default n + depends on IMX9_LPSPI4 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. + +config IMX9_LPSPI5_DMA + bool "LPSPI5 DMA" + default n + depends on IMX9_LPSPI5 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. + +config IMX9_LPSPI6_DMA + bool "LPSPI6 DMA" + default n + depends on IMX9_LPSPI6 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. + +config IMX9_LPSPI7_DMA + bool "LPSPI7 DMA" + default n + depends on IMX9_LPSPI7 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI7 transfer performance. + +config IMX9_LPSPI8_DMA + bool "LPSPI8 DMA" + default n + depends on IMX9_LPSPI8 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI8 transfer performance. + +endmenu # LPSPI Configuration + +menuconfig IMX9_MU + bool "Mailbox support" + default y + depends on IMX9_HAVE_MU + +if IMX9_MU + +config IMX9_MU5 + bool "MU5 M7 <-> M33" + default y + ---help--- + Enable mailbox 5 that operates between M7 and M33 cores + +config IMX9_MU7 + bool "MU7 M7 <-> A55" + default n + ---help--- + Enable mailbox 7 that operates between M7 and A55 cores + +config IMX9_MU8 + bool "MU8 M7 <-> A55" + default n + ---help--- + Enable mailbox 5 that operates between M7 and A55 cores + +endif # IMX9_MU Configuration + +endmenu # iMX Peripheral Selection + +endif # ARCH_CHIP_IMX9 + diff --git a/arch/arm/src/imx9/Make.defs b/arch/arm/src/imx9/Make.defs new file mode 100644 index 0000000000000..f1d9e369feb84 --- /dev/null +++ b/arch/arm/src/imx9/Make.defs @@ -0,0 +1,81 @@ +############################################################################ +# arch/arm/src/imx9/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileCopyrightText: 2024 NXP +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +# i.MX9-specific C source files + +CHIP_CSRCS = imx9_allocateheap.c imx9_start.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c imx9_irq.c imx9_timerisr.c imx9_idle.c + +ifeq ($(CONFIG_IMX9_SCMI),y) + CHIP_CSRCS += imx9_scmi.c + # NXP SDK SCMI interface for pinctrl and clocking +endif + +ifeq ($(CONFIG_RPTUN),y) + CHIP_CSRCS += imx9_rsctable.c imx9_rptun.c +endif + +ifeq ($(CONFIG_IMX9_MU),y) + CHIP_CSRCS += imx9_mu.c +endif + +ifeq ($(CONFIG_ARM_MPU),y) +CHIP_CSRCS += imx9_mpuinit.c +endif + +ifeq ($(CONFIG_IMX9_FLEXCAN),y) + CHIP_CSRCS += imx9_flexcan.c +endif + +ifeq ($(CONFIG_IMX9_LPUART),y) + CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c +endif + +ifeq ($(CONFIG_IMX9_GPIO_IRQ),y) + CHIP_CSRCS += imx9_gpioirq.c +endif + +ifeq ($(CONFIG_IMX9_FLEXIO_PWM),y) + CHIP_CSRCS += imx9_flexio_pwm.c +endif + +ifeq ($(CONFIG_IMX9_TPM_PWM),y) + CHIP_CSRCS += imx9_tpm_pwm.c +endif + +ifeq ($(CONFIG_IMX9_USBDEV),y) + CHIP_CSRCS += imx9_usbdev.c +endif + +ifeq ($(CONFIG_IMX9_LPI2C),y) + CHIP_CSRCS += imx9_lpi2c.c +endif + +ifeq ($(CONFIG_IMX9_LPSPI), y) + CHIP_CSRCS += imx9_lpspi.c +endif + +ifeq ($(CONFIG_IMX9_EDMA), y) + CHIP_CSRCS += imx9_edma.c +endif diff --git a/arch/arm/src/common/arm_modifyreg8.c b/arch/arm/src/imx9/chip.h similarity index 73% rename from arch/arm/src/common/arm_modifyreg8.c rename to arch/arm/src/imx9/chip.h index a3449951174c8..a1e999ef2fc7a 100644 --- a/arch/arm/src/common/arm_modifyreg8.c +++ b/arch/arm/src/imx9/chip.h @@ -1,7 +1,8 @@ /**************************************************************************** - * arch/arm/src/common/arm_modifyreg8.c + * arch/arm/src/imx9/chip.h * * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -20,40 +21,32 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_IMX9_CHIP_H +#define __ARCH_ARM_SRC_IMX9_CHIP_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include - -#include - -#include "arm_internal.h" +#ifndef __ASSEMBLY__ +# include +# include +# include +#endif /**************************************************************************** - * Public Functions + * Pre-processor Definitions ****************************************************************************/ +/* Cache line sizes (in bytes) for the i.MX 9 M7 Core */ + +#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */ +#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */ + /**************************************************************************** - * Name: modifyreg8 - * - * Description: - * Atomically modify the specified bits in a memory mapped register - * + * Macro Definitions ****************************************************************************/ -void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) -{ - irqstate_t flags; - uint8_t regval; - - flags = spin_lock_irqsave(NULL); - regval = getreg8(addr); - regval &= ~clearbits; - regval |= setbits; - putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); -} +#endif /* __ARCH_ARM_SRC_IMX9_CHIP_H */ diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_clock.h b/arch/arm/src/imx9/hardware/imx95/imx95_clock.h new file mode 100644 index 0000000000000..2d55f26d4a426 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_clock.h @@ -0,0 +1,827 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_clock.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_CLOCK_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_CLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +typedef enum +{ + EXT_CLK = 0, + OSC_32K_CLK = 1, + OSC_24M_CLK = 2, + FRO_CLK = 3, + SYS_PLL1_CTL = 4, + SYS_PLL1_DFS0_CTL = 5, + SYS_PLL1_DFS0_CLK = 6, + SYS_PLL1_DFS0_DIV2_CLK = 7, + SYS_PLL1_DFS1_CTL = 8, + SYS_PLL1_DFS1_CLK = 9, + SYS_PLL1_DFS1_DIV2_CLK = 10, + SYS_PLL1_DFS2_CTL = 11, + SYS_PLL1_DFS2_CLK = 12, + SYS_PLL1_DFS2_DIV2_CLK = 13, + AUDIO_PLL1_CTL = 14, + AUDIO_PLL1_CLK = 15, + AUDIO_PLL2_CTL = 16, + AUDIO_PLL2_CLK = 17, + VIDEO_PLL1_CTL = 18, + VIDEO_PLL1_CLK = 19, + VIDEO_PLL2_CTL = 20, + VIDEO_PLL2_CLK = 21, + VIDEO_PLL3_CTL = 22, + VIDEO_PLL3_CLK = 23, + ARM_PLL_CTL = 24, + ARM_PLL_DFS0_CTL = 25, + ARM_PLL_DFS0_CLK = 26, + ARM_PLL_DFS1_CTL = 27, + ARM_PLL_DFS1_CLK = 28, + ARM_PLL_DFS2_CTL = 29, + ARM_PLL_DFS2_CLK = 30, + ARM_PLL_DFS3_CTL = 31, + ARM_PLL_DFS3_CLK = 32, + DRAM_PLL_CTL = 33, + DRAM_PLL_CLK = 34, + HSIO_PLL_CTL = 35, + HSIO_PLL_CLK = 36, + LDB_PLL_CTL = 37, + LDB_PLL_CLK = 38, +} clock_id_e; + +#define CCM_CR_COUNT 122 + +typedef uint32_t clock_config_t; + +#define CLOCK_DIV_SHIFT (16) +#define CLOCK_DIV_MASK (0xff << CLOCK_DIV_SHIFT) +#define CLOCK_DIV(n) (((n) << CLOCK_DIV_SHIFT) & CLOCK_DIV_MASK) +#define GET_CLOCK_DIV(n) (((n) & CLOCK_DIV_MASK) >> CLOCK_DIV_SHIFT) + +#define CLOCK_ROOT_SHIFT (8) +#define CLOCK_ROOT_MASK (0x7f << CLOCK_ROOT_SHIFT) +#define CLOCK_ROOT(n) (((n) << CLOCK_ROOT_SHIFT) & CLOCK_ROOT_MASK) +#define GET_CLOCK_ROOT(n) (((n) & CLOCK_ROOT_MASK) >> CLOCK_ROOT_SHIFT) + +#define CLOCK_ID_SHIFT (3) +#define CLOCK_ID_MASK (0x1f << CLOCK_ID_SHIFT) +#define CLOCK_ID(n) (((n) << CLOCK_ID_SHIFT) & CLOCK_ID_MASK) +#define GET_CLOCK_ID(n) (((n) & CLOCK_ID_MASK) >> CLOCK_ID_SHIFT) + +#define ROOT_MUX_SHIFT (0) +#define ROOT_MUX_MASK (0x07 << ROOT_MUX_SHIFT) +#define ROOT_MUX(n) (((n) << ROOT_MUX_SHIFT) & ROOT_MUX_MASK) + +/* ADC_CLK_ROOT */ +#define ADC_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(0U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ADC_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(0U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define ADC_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(0U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define ADC_CLK_ROOT_FRO_CLK CLOCK_ROOT(0U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* TMU_CLK_ROOT */ +#define TMU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(1U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TMU_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(1U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define TMU_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(1U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define TMU_CLK_ROOT_FRO_CLK CLOCK_ROOT(1U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* BUS_AON_CLK_ROOT */ +#define BUS_AON_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(2U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define BUS_AON_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(2U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define BUS_AON_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(2U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define BUS_AON_CLK_ROOT_FRO_CLK CLOCK_ROOT(2U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAN1_CLK_ROOT */ +#define CAN1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(3U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAN1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(3U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define CAN1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(3U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define CAN1_CLK_ROOT_FRO_CLK CLOCK_ROOT(3U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* I3C1_CLK_ROOT */ +#define I3C1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(4U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define I3C1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(4U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define I3C1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(4U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define I3C1_CLK_ROOT_FRO_CLK CLOCK_ROOT(4U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* I3C1_SLOW_CLK_ROOT */ +#define I3C1_SLOW_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(5U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define I3C1_SLOW_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(5U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define I3C1_SLOW_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(5U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define I3C1_SLOW_CLK_ROOT_FRO_CLK CLOCK_ROOT(5U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C1_CLK_ROOT */ +#define LPI2C1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(6U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(6U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(6U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C1_CLK_ROOT_FRO_CLK CLOCK_ROOT(6U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C2_CLK_ROOT */ +#define LPI2C2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(7U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(7U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(7U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C2_CLK_ROOT_FRO_CLK CLOCK_ROOT(7U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI1_CLK_ROOT */ +#define LPSPI1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(8U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(8U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(8U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI1_CLK_ROOT_FRO_CLK CLOCK_ROOT(8U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI2_CLK_ROOT */ +#define LPSPI2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(9U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(9U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(9U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI2_CLK_ROOT_FRO_CLK CLOCK_ROOT(9U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPTMR1_CLK_ROOT */ +#define LPTMR1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(10U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPTMR1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(10U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPTMR1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(10U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPTMR1_CLK_ROOT_FRO_CLK CLOCK_ROOT(10U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART1_CLK_ROOT */ +#define LPUART1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(11U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(11U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(11U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART1_CLK_ROOT_FRO_CLK CLOCK_ROOT(11U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART2_CLK_ROOT */ +#define LPUART2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(12U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(12U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(12U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART2_CLK_ROOT_FRO_CLK CLOCK_ROOT(12U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* M33_CLK_ROOT */ +#define M33_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(13U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define M33_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(13U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define M33_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(13U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define M33_CLK_ROOT_FRO_CLK CLOCK_ROOT(13U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* M33_SYSTICK_CLK_ROOT */ +#define M33_SYSTICK_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(14U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define M33_SYSTICK_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(14U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define M33_SYSTICK_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(14U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define M33_SYSTICK_CLK_ROOT_FRO_CLK CLOCK_ROOT(14U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* MQS1_CLK_ROOT */ +#define MQS1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(15U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define MQS1_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(15U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define MQS1_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(15U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define MQS1_CLK_ROOT_EXT_CLK CLOCK_ROOT(15U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* PDM_CLK_ROOT */ +#define PDM_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(16U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define PDM_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(16U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define PDM_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(16U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define PDM_CLK_ROOT_EXT_CLK CLOCK_ROOT(16U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SAI1_CLK_ROOT */ +#define SAI1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(17U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SAI1_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(17U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define SAI1_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(17U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define SAI1_CLK_ROOT_EXT_CLK CLOCK_ROOT(17U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SENTINEL_CLK_ROOT */ +#define SENTINEL_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(18U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SENTINEL_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(18U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define SENTINEL_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(18U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define SENTINEL_CLK_ROOT_FRO_CLK CLOCK_ROOT(18U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* TPM2_CLK_ROOT */ +#define TPM2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(19U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TPM2_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(19U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define TPM2_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(19U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define TPM2_CLK_ROOT_EXT_CLK CLOCK_ROOT(19U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* TSTMR1_CLK_ROOT */ +#define TSTMR1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(20U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TSTMR1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(20U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define TSTMR1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(20U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define TSTMR1_CLK_ROOT_FRO_CLK CLOCK_ROOT(20U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAM_APB_CLK_ROOT */ +#define CAM_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(21U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAM_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(21U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define CAM_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(21U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define CAM_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(21U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAM_AXI_CLK_ROOT */ +#define CAM_AXI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(22U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAM_AXI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(22U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CAM_AXI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(22U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define CAM_AXI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(22U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* CAM_CM0_CLK_ROOT */ +#define CAM_CM0_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(23U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAM_CM0_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(23U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CAM_CM0_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(23U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define CAM_CM0_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(23U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* CAM_ISI_CLK_ROOT */ +#define CAM_ISI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(24U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAM_ISI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(24U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CAM_ISI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(24U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define CAM_ISI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(24U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* MIPI_PHY_CFG_CLK_ROOT */ +#define MIPI_PHY_CFG_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(25U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define MIPI_PHY_CFG_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(25U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define MIPI_PHY_CFG_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(25U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* MIPI_PHY_PLL_BYPASS_CLK_ROOT */ +#define MIPI_PHY_PLL_BYPASS_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(26U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define MIPI_PHY_PLL_BYPASS_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(26U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define MIPI_PHY_PLL_BYPASS_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(26U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* MIPI_PHY_PLL_REF_CLK_ROOT */ +#define MIPI_PHY_PLL_REF_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(27U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define MIPI_PHY_PLL_REF_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(27U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define MIPI_PHY_PLL_REF_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(27U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* MIPI_TEST_BYTE_CLK_ROOT */ +#define MIPI_TEST_BYTE_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(28U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define MIPI_TEST_BYTE_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(28U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define MIPI_TEST_BYTE_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(28U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* ARM_A55_CLK_ROOT */ +#define ARM_A55_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(29U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ARM_A55_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(29U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ARM_A55_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(29U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define ARM_A55_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(29U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* ARM_A55_MTR_BUS_CLK_ROOT */ +#define ARM_A55_MTR_BUS_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(30U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ARM_A55_MTR_BUS_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(30U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define ARM_A55_MTR_BUS_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(30U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define ARM_A55_MTR_BUS_CLK_ROOT_FRO_CLK CLOCK_ROOT(30U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* ARM_A55_PERIPH_CLK_ROOT */ +#define ARM_A55_PERIPH_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(31U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ARM_A55_PERIPH_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(31U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ARM_A55_PERIPH_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(31U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define ARM_A55_PERIPH_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(31U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* DRAM_ALT_CLK_ROOT */ +#define DRAM_ALT_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(32U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DRAM_ALT_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(32U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define DRAM_ALT_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(32U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define DRAM_ALT_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(32U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* DRAM_APB_CLK_ROOT */ +#define DRAM_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(33U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DRAM_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(33U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define DRAM_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(33U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define DRAM_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(33U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* DISP_APB_CLK_ROOT */ +#define DISP_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(34U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DISP_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(34U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define DISP_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(34U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define DISP_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(34U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* DISP_AXI_CLK_ROOT */ +#define DISP_AXI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(35U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DISP_AXI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(35U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define DISP_AXI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(35U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define DISP_AXI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(35U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* DISP_DP_CLK_ROOT */ +#define DISP_DP_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(36U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DISP_DP_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(36U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define DISP_DP_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(36U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define DISP_DP_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(36U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* DISP_OCRAM_CLK_ROOT */ +#define DISP_OCRAM_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(37U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DISP_OCRAM_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(37U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define DISP_OCRAM_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(37U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define DISP_OCRAM_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(37U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* DISP_USB31_CLK_ROOT */ +#define DISP_USB31_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(38U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DISP_USB31_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(38U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define DISP_USB31_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(38U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define DISP_USB31_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(38U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* DISP1_PIX_CLK_ROOT */ +#define DISP1_PIX_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(39U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define DISP1_PIX_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(39U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define DISP1_PIX_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(39U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* GPU_APB_CLK_ROOT */ +#define GPU_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(42U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define GPU_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(42U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define GPU_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(42U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define GPU_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(42U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* GPU_CLK_ROOT */ +#define GPU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(43U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define GPU_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(43U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define GPU_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(43U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define GPU_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(43U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* HSIO_ACSCAN_480M_CLK_ROOT */ +#define HSIO_ACSCAN_480M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(44U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_ACSCAN_480M_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(44U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define HSIO_ACSCAN_480M_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(44U) | ROOT_MUX(2U) | CLOCK_ID(VIDEO_PLL1_CLK) +#define HSIO_ACSCAN_480M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(44U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* HSIO_ACSCAN_80M_CLK_ROOT */ +#define HSIO_ACSCAN_80M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(45U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_ACSCAN_80M_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(45U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define HSIO_ACSCAN_80M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(45U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define HSIO_ACSCAN_80M_CLK_ROOT_FRO_CLK CLOCK_ROOT(45U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* HSIO_CLK_ROOT */ +#define HSIO_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(46U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(46U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define HSIO_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(46U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define HSIO_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(46U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* HSIO_PCIE_AUX_CLK_ROOT */ +#define HSIO_PCIE_AUX_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(47U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_PCIE_AUX_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(47U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define HSIO_PCIE_AUX_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(47U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define HSIO_PCIE_AUX_CLK_ROOT_FRO_CLK CLOCK_ROOT(47U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* HSIO_PCIE_TEST_160M_CLK_ROOT */ +#define HSIO_PCIE_TEST_160M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(48U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_PCIE_TEST_160M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(48U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define HSIO_PCIE_TEST_160M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(48U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define HSIO_PCIE_TEST_160M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(48U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* HSIO_PCIE_TEST_400M_CLK_ROOT */ +#define HSIO_PCIE_TEST_400M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(49U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_PCIE_TEST_400M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(49U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define HSIO_PCIE_TEST_400M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(49U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define HSIO_PCIE_TEST_400M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(49U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* HSIO_PCIE_TEST_500M_CLK_ROOT */ +#define HSIO_PCIE_TEST_500M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(50U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_PCIE_TEST_500M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(50U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define HSIO_PCIE_TEST_500M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(50U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define HSIO_PCIE_TEST_500M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(50U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* HSIO_USB_TEST_50M_CLK_ROOT */ +#define HSIO_USB_TEST_50M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(51U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_USB_TEST_50M_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(51U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define HSIO_USB_TEST_50M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(51U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define HSIO_USB_TEST_50M_CLK_ROOT_FRO_CLK CLOCK_ROOT(51U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* HSIO_USB_TEST_60M_CLK_ROOT */ +#define HSIO_USB_TEST_60M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(52U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define HSIO_USB_TEST_60M_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(52U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define HSIO_USB_TEST_60M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(52U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define HSIO_USB_TEST_60M_CLK_ROOT_FRO_CLK CLOCK_ROOT(52U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* BUS_M7_CLK_ROOT */ +#define BUS_M7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(53U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define BUS_M7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(53U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define BUS_M7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(53U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define BUS_M7_CLK_ROOT_FRO_CLK CLOCK_ROOT(53U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* M7_CLK_ROOT */ +#define M7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(54U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define M7_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(54U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define M7_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(54U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define M7_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(54U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* M7_SYSTICK_CLK_ROOT */ +#define M7_SYSTICK_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(55U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define M7_SYSTICK_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(55U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define M7_SYSTICK_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(55U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define M7_SYSTICK_CLK_ROOT_FRO_CLK CLOCK_ROOT(55U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* BUS_NETCMIX_CLK_ROOT */ +#define BUS_NETCMIX_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(56U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define BUS_NETCMIX_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(56U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define BUS_NETCMIX_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(56U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define BUS_NETCMIX_CLK_ROOT_FRO_CLK CLOCK_ROOT(56U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* ENET_CLK_ROOT */ +#define ENET_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(57U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ENET_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(57U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ENET_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(57U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define ENET_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(57U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* ENET_PHY_TEST_200M_CLK_ROOT */ +#define ENET_PHY_TEST_200M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(58U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ENET_PHY_TEST_200M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(58U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ENET_PHY_TEST_200M_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(58U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define ENET_PHY_TEST_200M_CLK_ROOT_FRO_CLK CLOCK_ROOT(58U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* ENET_PHY_TEST_500M_CLK_ROOT */ +#define ENET_PHY_TEST_500M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(59U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ENET_PHY_TEST_500M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(59U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ENET_PHY_TEST_500M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(59U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define ENET_PHY_TEST_500M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(59U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* ENET_PHY_TEST_667M_CLK_ROOT */ +#define ENET_PHY_TEST_667M_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(60U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ENET_PHY_TEST_667M_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(60U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ENET_PHY_TEST_667M_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(60U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define ENET_PHY_TEST_667M_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(60U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* ENET_REF_CLK_ROOT */ +#define ENET_REF_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(61U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ENET_REF_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(61U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define ENET_REF_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(61U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define ENET_REF_CLK_ROOT_FRO_CLK CLOCK_ROOT(61U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* ENET_TIMER1_CLK_ROOT */ +#define ENET_TIMER1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(62U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define ENET_TIMER1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(62U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define ENET_TIMER1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(62U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define ENET_TIMER1_CLK_ROOT_FRO_CLK CLOCK_ROOT(62U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* MQS2_CLK_ROOT */ +#define MQS2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(63U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define MQS2_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(63U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define MQS2_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(63U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define MQS2_CLK_ROOT_EXT_CLK CLOCK_ROOT(63U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SAI2_CLK_ROOT */ +#define SAI2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(64U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SAI2_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(64U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define SAI2_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(64U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define SAI2_CLK_ROOT_EXT_CLK CLOCK_ROOT(64U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* NOC_APB_CLK_ROOT */ +#define NOC_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(65U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define NOC_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(65U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define NOC_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(65U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define NOC_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(65U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* NOC_CLK_ROOT */ +#define NOC_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(66U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define NOC_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(66U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define NOC_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(66U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define NOC_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(66U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* NPU_APB_CLK_ROOT */ +#define NPU_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(67U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define NPU_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(67U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define NPU_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(67U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define NPU_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(67U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* NPU_CLK_ROOT */ +#define NPU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(68U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define NPU_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(68U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define NPU_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(68U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define NPU_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(68U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* CCM_CKO1_CLK_ROOT */ +#define CCM_CKO1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(69U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CCM_CKO1_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(69U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CCM_CKO1_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(69U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK) +#define CCM_CKO1_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(69U) | ROOT_MUX(3U) | CLOCK_ID(AUDIO_PLL1_CLK) + +/* CCM_CKO2_CLK_ROOT */ +#define CCM_CKO2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(70U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CCM_CKO2_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(70U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CCM_CKO2_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(70U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK) +#define CCM_CKO2_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(70U) | ROOT_MUX(3U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* CCM_CKO3_CLK_ROOT */ +#define CCM_CKO3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(71U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CCM_CKO3_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(71U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CCM_CKO3_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(71U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK) +#define CCM_CKO3_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(71U) | ROOT_MUX(3U) | CLOCK_ID(AUDIO_PLL2_CLK) + +/* CCM_CKO4_CLK_ROOT */ +#define CCM_CKO4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(72U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CCM_CKO4_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(72U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define CCM_CKO4_CLK_ROOT_OSC_32K_CLK CLOCK_ROOT(72U) | ROOT_MUX(2U) | CLOCK_ID(OSC_32K_CLK) +#define CCM_CKO4_CLK_ROOT_VIDEO_PLL1_CLK CLOCK_ROOT(72U) | ROOT_MUX(3U) | CLOCK_ID(VIDEO_PLL1_CLK) + +/* VPU_APB_CLK_ROOT */ +#define VPU_APB_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(73U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define VPU_APB_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(73U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define VPU_APB_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(73U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define VPU_APB_CLK_ROOT_FRO_CLK CLOCK_ROOT(73U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* VPU_CLK_ROOT */ +#define VPU_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(74U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define VPU_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(74U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define VPU_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(74U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define VPU_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(74U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* VPU_DSP_CLK_ROOT */ +#define VPU_DSP_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(75U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define VPU_DSP_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(75U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define VPU_DSP_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(75U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define VPU_DSP_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(75U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* VPU_JPEG_CLK_ROOT */ +#define VPU_JPEG_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(76U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define VPU_JPEG_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(76U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define VPU_JPEG_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(76U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define VPU_JPEG_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(76U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* AUDIO_XCVR_CLK_ROOT */ +#define AUDIO_XCVR_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(77U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define AUDIO_XCVR_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(77U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define AUDIO_XCVR_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(77U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define AUDIO_XCVR_CLK_ROOT_FRO_CLK CLOCK_ROOT(77U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* BUS_WAKEUP_CLK_ROOT */ +#define BUS_WAKEUP_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(78U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define BUS_WAKEUP_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(78U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define BUS_WAKEUP_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(78U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define BUS_WAKEUP_CLK_ROOT_FRO_CLK CLOCK_ROOT(78U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAN2_CLK_ROOT */ +#define CAN2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(79U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAN2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(79U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define CAN2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(79U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define CAN2_CLK_ROOT_FRO_CLK CLOCK_ROOT(79U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAN3_CLK_ROOT */ +#define CAN3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(80U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAN3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(80U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define CAN3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(80U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define CAN3_CLK_ROOT_FRO_CLK CLOCK_ROOT(80U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAN4_CLK_ROOT */ +#define CAN4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(81U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAN4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(81U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define CAN4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(81U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define CAN4_CLK_ROOT_FRO_CLK CLOCK_ROOT(81U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* CAN5_CLK_ROOT */ +#define CAN5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(82U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define CAN5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(82U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define CAN5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(82U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define CAN5_CLK_ROOT_FRO_CLK CLOCK_ROOT(82U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* FLEXIO1_CLK_ROOT */ +#define FLEXIO1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(83U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define FLEXIO1_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(83U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define FLEXIO1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(83U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define FLEXIO1_CLK_ROOT_FRO_CLK CLOCK_ROOT(83U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* FLEXIO2_CLK_ROOT */ +#define FLEXIO2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(84U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define FLEXIO2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(84U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define FLEXIO2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(84U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define FLEXIO2_CLK_ROOT_FRO_CLK CLOCK_ROOT(84U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* FLEXSPI1_CLK_ROOT */ +#define FLEXSPI1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(85U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define FLEXSPI1_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(85U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define FLEXSPI1_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(85U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define FLEXSPI1_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(85U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* I3C2_CLK_ROOT */ +#define I3C2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(86U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define I3C2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(86U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define I3C2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(86U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define I3C2_CLK_ROOT_FRO_CLK CLOCK_ROOT(86U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* I3C2_SLOW_CLK_ROOT */ +#define I3C2_SLOW_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(87U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define I3C2_SLOW_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(87U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define I3C2_SLOW_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(87U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define I3C2_SLOW_CLK_ROOT_FRO_CLK CLOCK_ROOT(87U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C3_CLK_ROOT */ +#define LPI2C3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(88U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(88U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(88U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C3_CLK_ROOT_FRO_CLK CLOCK_ROOT(88U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C4_CLK_ROOT */ +#define LPI2C4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(89U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(89U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(89U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C4_CLK_ROOT_FRO_CLK CLOCK_ROOT(89U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C5_CLK_ROOT */ +#define LPI2C5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(90U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(90U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(90U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C5_CLK_ROOT_FRO_CLK CLOCK_ROOT(90U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C6_CLK_ROOT */ +#define LPI2C6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(91U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C6_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(91U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C6_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(91U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C6_CLK_ROOT_FRO_CLK CLOCK_ROOT(91U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C7_CLK_ROOT */ +#define LPI2C7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(92U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(92U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(92U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C7_CLK_ROOT_FRO_CLK CLOCK_ROOT(92U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPI2C8_CLK_ROOT */ +#define LPI2C8_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(93U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPI2C8_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(93U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPI2C8_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(93U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPI2C8_CLK_ROOT_FRO_CLK CLOCK_ROOT(93U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI3_CLK_ROOT */ +#define LPSPI3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(94U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(94U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(94U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI3_CLK_ROOT_FRO_CLK CLOCK_ROOT(94U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI4_CLK_ROOT */ +#define LPSPI4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(95U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(95U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(95U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI4_CLK_ROOT_FRO_CLK CLOCK_ROOT(95U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI5_CLK_ROOT */ +#define LPSPI5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(96U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(96U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(96U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI5_CLK_ROOT_FRO_CLK CLOCK_ROOT(96U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI6_CLK_ROOT */ +#define LPSPI6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(97U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI6_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(97U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI6_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(97U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI6_CLK_ROOT_FRO_CLK CLOCK_ROOT(97U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI7_CLK_ROOT */ +#define LPSPI7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(98U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(98U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(98U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI7_CLK_ROOT_FRO_CLK CLOCK_ROOT(98U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPSPI8_CLK_ROOT */ +#define LPSPI8_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(99U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPSPI8_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(99U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPSPI8_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(99U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPSPI8_CLK_ROOT_FRO_CLK CLOCK_ROOT(99U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPTMR2_CLK_ROOT */ +#define LPTMR2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(100U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPTMR2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(100U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPTMR2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(100U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPTMR2_CLK_ROOT_FRO_CLK CLOCK_ROOT(100U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART3_CLK_ROOT */ +#define LPUART3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(101U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART3_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(101U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART3_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(101U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART3_CLK_ROOT_FRO_CLK CLOCK_ROOT(101U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART4_CLK_ROOT */ +#define LPUART4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(102U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART4_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(102U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART4_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(102U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART4_CLK_ROOT_FRO_CLK CLOCK_ROOT(102U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART5_CLK_ROOT */ +#define LPUART5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(103U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART5_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(103U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART5_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(103U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART5_CLK_ROOT_FRO_CLK CLOCK_ROOT(103U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART6_CLK_ROOT */ +#define LPUART6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(104U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART6_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(104U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART6_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(104U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART6_CLK_ROOT_FRO_CLK CLOCK_ROOT(104U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART7_CLK_ROOT */ +#define LPUART7_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(105U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART7_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(105U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART7_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(105U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART7_CLK_ROOT_FRO_CLK CLOCK_ROOT(105U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* LPUART8_CLK_ROOT */ +#define LPUART8_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(106U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define LPUART8_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(106U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define LPUART8_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(106U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define LPUART8_CLK_ROOT_FRO_CLK CLOCK_ROOT(106U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* SAI3_CLK_ROOT */ +#define SAI3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(107U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SAI3_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(107U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define SAI3_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(107U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define SAI3_CLK_ROOT_EXT_CLK CLOCK_ROOT(107U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SAI4_CLK_ROOT */ +#define SAI4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(108U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SAI4_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(108U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define SAI4_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(108U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define SAI4_CLK_ROOT_EXT_CLK CLOCK_ROOT(108U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SAI5_CLK_ROOT */ +#define SAI5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(109U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SAI5_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(109U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define SAI5_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(109U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define SAI5_CLK_ROOT_EXT_CLK CLOCK_ROOT(109U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SPDIF_CLK_ROOT */ +#define SPDIF_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(110U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SPDIF_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(110U) | ROOT_MUX(1U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define SPDIF_CLK_ROOT_AUDIO_PLL2_CLK CLOCK_ROOT(110U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL2_CLK) +#define SPDIF_CLK_ROOT_EXT_CLK CLOCK_ROOT(110U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* SWO_TRACE_CLK_ROOT */ +#define SWO_TRACE_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(111U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define SWO_TRACE_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(111U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define SWO_TRACE_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(111U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define SWO_TRACE_CLK_ROOT_FRO_CLK CLOCK_ROOT(111U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* TPM4_CLK_ROOT */ +#define TPM4_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(112U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TPM4_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(112U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define TPM4_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(112U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define TPM4_CLK_ROOT_EXT_CLK CLOCK_ROOT(112U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* TPM5_CLK_ROOT */ +#define TPM5_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(113U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TPM5_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(113U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define TPM5_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(113U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define TPM5_CLK_ROOT_EXT_CLK CLOCK_ROOT(113U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* TPM6_CLK_ROOT */ +#define TPM6_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(114U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TPM6_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(114U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define TPM6_CLK_ROOT_AUDIO_PLL1_CLK CLOCK_ROOT(114U) | ROOT_MUX(2U) | CLOCK_ID(AUDIO_PLL1_CLK) +#define TPM6_CLK_ROOT_EXT_CLK CLOCK_ROOT(114U) | ROOT_MUX(3U) | CLOCK_ID(EXT_CLK) + +/* TSTMR2_CLK_ROOT */ +#define TSTMR2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(115U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define TSTMR2_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(115U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define TSTMR2_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(115U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define TSTMR2_CLK_ROOT_FRO_CLK CLOCK_ROOT(115U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* USB_PHY_BURUNIN_CLK_ROOT */ +#define USB_PHY_BURUNIN_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(116U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define USB_PHY_BURUNIN_CLK_ROOT_SYS_PLL1_DFS0_DIV2_CLK CLOCK_ROOT(116U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_DIV2_CLK) +#define USB_PHY_BURUNIN_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK CLOCK_ROOT(116U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_DIV2_CLK) +#define USB_PHY_BURUNIN_CLK_ROOT_FRO_CLK CLOCK_ROOT(116U) | ROOT_MUX(3U) | CLOCK_ID(FRO_CLK) + +/* USDHC1_CLK_ROOT */ +#define USDHC1_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(117U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define USDHC1_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(117U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define USDHC1_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(117U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define USDHC1_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(117U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* USDHC2_CLK_ROOT */ +#define USDHC2_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(118U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define USDHC2_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(118U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define USDHC2_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(118U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define USDHC2_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(118U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* USDHC3_CLK_ROOT */ +#define USDHC3_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(119U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define USDHC3_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(119U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define USDHC3_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(119U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define USDHC3_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(119U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* V2X_PK_CLK_ROOT */ +#define V2X_PK_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(120U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define V2X_PK_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(120U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define V2X_PK_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(120U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define V2X_PK_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(120U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* WAKEUP_AXI_CLK_ROOT */ +#define WAKEUP_AXI_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(121U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define WAKEUP_AXI_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(121U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define WAKEUP_AXI_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(121U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define WAKEUP_AXI_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(121U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +/* XSPI_SLV_ROOT_CLK_ROOT */ +#define XSPI_SLV_ROOT_CLK_ROOT_OSC_24M_CLK CLOCK_ROOT(122U) | ROOT_MUX(0U) | CLOCK_ID(OSC_24M_CLK) +#define XSPI_SLV_ROOT_CLK_ROOT_SYS_PLL1_DFS0_CLK CLOCK_ROOT(122U) | ROOT_MUX(1U) | CLOCK_ID(SYS_PLL1_DFS0_CLK) +#define XSPI_SLV_ROOT_CLK_ROOT_SYS_PLL1_DFS1_CLK CLOCK_ROOT(122U) | ROOT_MUX(2U) | CLOCK_ID(SYS_PLL1_DFS1_CLK) +#define XSPI_SLV_ROOT_CLK_ROOT_SYS_PLL1_DFS2_CLK CLOCK_ROOT(122U) | ROOT_MUX(3U) | CLOCK_ID(SYS_PLL1_DFS2_CLK) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H */ \ No newline at end of file diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h b/arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h new file mode 100644 index 0000000000000..d8b9d3a3f74e5 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx95_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Identify channel MUX from 9th bit */ + +#define EDMA3_MUX_ID 0x0000 +#define EDMA4_MUX_ID 0x0100 +#define EDMA_MUX_ID_MASK 0xff00 +#define EDMA_MUX_MASK 0x00ff + +/* eDMA3 MUXs */ + +#define DMA_REQUEST_DISABLED (0 | EDMA3_MUX_ID) /**< DSisabled*/ +#define DMA_REQUEST_MUXCAN1 (1 | EDMA3_MUX_ID) /**< CAN1 */ +#define DMA_REQUEST_MUXLPTMR1REQUEST (2 | EDMA3_MUX_ID) /**< LPTMR1 Request */ +#define DMA_REQUEST_MUXELEREQUEST (3 | EDMA3_MUX_ID) /**< ELE Request */ +#define DMA_REQUEST_MUXTPM1OVERFLOWREQUEST (4 | EDMA3_MUX_ID) /**< TPM1 Overflow Request */ +#define DMA_REQUEST_MUXTPM2OVERFLOWREQUEST (5 | EDMA3_MUX_ID) /**< TPM2 Overflow Request */ +#define DMA_REQUEST_MUXPDMREQUEST (6 | EDMA3_MUX_ID) /**< PDM */ +#define DMA_REQUEST_MUXADC1REQUEST (7 | EDMA3_MUX_ID) /**< ADC1 */ +#define DMA_REQUEST_MUXGPIO1REQUEST0 (8 | EDMA3_MUX_ID) /**< GPIO1 channel 0 */ +#define DMA_REQUEST_MUXGPIO1REQUEST1 (9 | EDMA3_MUX_ID) /**< GPIO1 channel 1 */ +#define DMA_REQUEST_MUXI3C1TOBUSREQUEST (10 | EDMA3_MUX_ID) /**< I3C1 To-bus Request */ +#define DMA_REQUEST_MUXI3C1FROMBUSREQUEST (11 | EDMA3_MUX_ID) /**< I3C1 From-bus Request */ +#define DMA_REQUEST_MUXLPI2C1TX (12 | EDMA3_MUX_ID) /**< LPI2C1 */ +#define DMA_REQUEST_MUXLPI2C1RX (13 | EDMA3_MUX_ID) /**< LPI2C1 */ +#define DMA_REQUEST_MUXLPI2C2TX (14 | EDMA3_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPI2C2RX (15 | EDMA3_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPSPI1TX (16 | EDMA3_MUX_ID) /**< LPSPI1 Transmit */ +#define DMA_REQUEST_MUXLPSPI1RX (17 | EDMA3_MUX_ID) /**< LPSPI1 Receive */ +#define DMA_REQUEST_MUXLPSPI2TX (18 | EDMA3_MUX_ID) /**< LPSPI2 Transmit */ +#define DMA_REQUEST_MUXLPSPI2RX (19 | EDMA3_MUX_ID) /**< LPSPI2 Receive */ +#define DMA_REQUEST_MUXLPUART1TX (20 | EDMA3_MUX_ID) /**< LPUART1 Transmit */ +#define DMA_REQUEST_MUXLPUART1RX (21 | EDMA3_MUX_ID) /**< LPUART1 Receive */ +#define DMA_REQUEST_MUXLPUART2TX (22 | EDMA3_MUX_ID) /**< LPUART2 Transmit */ +#define DMA_REQUEST_MUXLPUART2RX (23 | EDMA3_MUX_ID) /**< LPUART2 Receive */ +#define DMA_REQUEST_MUXSAI1TX (24 | EDMA3_MUX_ID) /**< SAI1 Transmit */ +#define DMA_REQUEST_MUXSAI1RX (25 | EDMA3_MUX_ID) /**< SAI1 Receive */ +#define DMA_REQUEST_MUXTPM1REQUEST0REQUEST2 (26 | EDMA3_MUX_ID) /**< TPM1 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM1REQUEST1REQUEST3 (27 | EDMA3_MUX_ID) /**< TPM1 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM2REQUEST0REQUEST2 (28 | EDMA3_MUX_ID) /**< TPM2 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM2REQUEST1REQUEST3 (29 | EDMA3_MUX_ID) /**< TPM2 request 1 and request 3 */ +#define DMA3_REQUEST_MUX_COUNT (30) + +/* eDMA4 MUXs */ + +#define DMA_REQUEST_MUXCAN2 (1U | EDMA4_MUX_ID) /**< CAN2 */ +#define DMA_REQUEST_MUXGPIO2REQUEST0 (2U | EDMA4_MUX_ID) /**< GPIO2 channel 0 */ +#define DMA_REQUEST_MUXGPIO2REQUEST1 (3U | EDMA4_MUX_ID) /**< GPIO2 channel 1 */ +#define DMA_REQUEST_MUXGPIO3REQUEST0 (4U | EDMA4_MUX_ID) /**< GPIO3 channel 0 */ +#define DMA_REQUEST_MUXGPIO3REQUEST1 (5U | EDMA4_MUX_ID) /**< GPIO3 channel 1 */ +#define DMA_REQUEST_MUXI3C2TOBUSREQUEST (6U | EDMA4_MUX_ID) /**< I3C2 To-bus Request */ +#define DMA_REQUEST_MUXI3C2FROMBUSREQUEST (7U | EDMA4_MUX_ID) /**< I3C2 From-bus Request */ +#define DMA_REQUEST_MUXLPI2C3TX (8U | EDMA4_MUX_ID) /**< LPI2C3 */ +#define DMA_REQUEST_MUXLPI2C3RX (9U | EDMA4_MUX_ID) /**< LPI2C3 */ +#define DMA_REQUEST_MUXLPI2C4TX (10U | EDMA4_MUX_ID) /**< LPI2C4 */ +#define DMA_REQUEST_MUXLPI2C4RX (11U | EDMA4_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPSPI3TX (12U | EDMA4_MUX_ID) /**< LPSPI3 Transmit */ +#define DMA_REQUEST_MUXLPSPI3RX (13U | EDMA4_MUX_ID) /**< LPSPI3 Receive */ +#define DMA_REQUEST_MUXLPSPI4TX (14U | EDMA4_MUX_ID) /**< LPSPI4 Transmit */ +#define DMA_REQUEST_MUXLPSPI4RX (15U | EDMA4_MUX_ID) /**< LPSPI4 Receive */ +#define DMA_REQUEST_MUXLPTMR2REQUEST (16U | EDMA4_MUX_ID) /**< LPTMR2 Request */ +#define DMA_REQUEST_MUXLPUART3TX (17U | EDMA4_MUX_ID) /**< LPUART3 Transmit */ +#define DMA_REQUEST_MUXLPUART3RX (18U | EDMA4_MUX_ID) /**< LPUART3 Receive */ +#define DMA_REQUEST_MUXLPUART4TX (19U | EDMA4_MUX_ID) /**< LPUART4 Transmit */ +#define DMA_REQUEST_MUXLPUART4RX (20U | EDMA4_MUX_ID) /**< LPUART4 Receive */ +#define DMA_REQUEST_MUXLPUART5TX (21U | EDMA4_MUX_ID) /**< LPUART5 Transmit */ +#define DMA_REQUEST_MUXLPUART5RX (22U | EDMA4_MUX_ID) /**< LPUART5 Receive */ +#define DMA_REQUEST_MUXLPUART6TX (23U | EDMA4_MUX_ID) /**< LPUART6 Transmit */ +#define DMA_REQUEST_MUXLPUART6RX (24U | EDMA4_MUX_ID) /**< LPUART6 Receive */ +#define DMA_REQUEST_MUXTPM3REQUEST0REQUEST2 (25U | EDMA4_MUX_ID) /**< TPM3 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM3REQUEST1REQUEST3 (26U | EDMA4_MUX_ID) /**< TPM3 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM3OVERFLOWREQUEST (27U | EDMA4_MUX_ID) /**< TPM3 Overflow request */ +#define DMA_REQUEST_MUXTPM4REQUEST0REQUEST2 (28U | EDMA4_MUX_ID) /**< TPM4 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM4REQUEST1REQUEST3 (29U | EDMA4_MUX_ID) /**< TPM4 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM4OVERFLOWREQUEST (30U | EDMA4_MUX_ID) /**< TPM4 Overflow request */ +#define DMA_REQUEST_MUXTPM5REQUEST0REQUEST2 (31U | EDMA4_MUX_ID) /**< TPM5 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM5REQUEST1REQUEST3 (32U | EDMA4_MUX_ID) /**< TPM5 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM5OVERFLOWREQUEST (33U | EDMA4_MUX_ID) /**< TPM5 Overflow request */ +#define DMA_REQUEST_MUXTPM6REQUEST0REQUEST2 (34U | EDMA4_MUX_ID) /**< TPM6 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM6REQUEST1REQUEST3 (35U | EDMA4_MUX_ID) /**< TPM6 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM6OVERFLOWREQUEST (36U | EDMA4_MUX_ID) /**< TPM6 Overflow request */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST0 (37U | EDMA4_MUX_ID) /**< FlexIO1 Request0 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST1 (38U | EDMA4_MUX_ID) /**< FlexIO1 Request1 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST2 (39U | EDMA4_MUX_ID) /**< FlexIO1 Request2 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST3 (40U | EDMA4_MUX_ID) /**< FlexIO1 Request3 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST4 (41U | EDMA4_MUX_ID) /**< FlexIO1 Request4 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST5 (42U | EDMA4_MUX_ID) /**< FlexIO1 Request5 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST6 (43U | EDMA4_MUX_ID) /**< FlexIO1 Request6 */ +#define DMA_REQUEST_MUXFLEXIO1REQUEST7 (44U | EDMA4_MUX_ID) /**< FlexIO1 Request7 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST0 (45U | EDMA4_MUX_ID) /**< FlexIO2 Request0 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST1 (46U | EDMA4_MUX_ID) /**< FlexIO2 Request1 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST2 (47U | EDMA4_MUX_ID) /**< FlexIO2 Request2 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST3 (48U | EDMA4_MUX_ID) /**< FlexIO2 Request3 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST4 (49U | EDMA4_MUX_ID) /**< FlexIO2 Request4 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST5 (50U | EDMA4_MUX_ID) /**< FlexIO2 Request5 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST6 (51U | EDMA4_MUX_ID) /**< FlexIO2 Request6 */ +#define DMA_REQUEST_MUXFLEXIO2REQUEST7 (52U | EDMA4_MUX_ID) /**< FlexIO2 Request7 */ +#define DMA_REQUEST_MUXFLEXSPI1TX (53U | EDMA4_MUX_ID) /**< FlexSPI1 Transmit */ +#define DMA_REQUEST_MUXFLEXSPI1RX (54U | EDMA4_MUX_ID) /**< FlexSPI1 Receive */ +#define DMA_REQUEST_MUXGPIO5REQUEST0 (53U | EDMA4_MUX_ID) /**< GPIO5 Request0 */ +#define DMA_REQUEST_MUXGPIO5REQUEST1 (54U | EDMA4_MUX_ID) /**< GPIO5 Request1 */ +#define DMA_REQUEST_MUXCAN3 (57U | EDMA4_MUX_ID) /**< CAN3 */ +#define DMA_REQUEST_MUXSAI2TX (58U | EDMA4_MUX_ID) /**< SAI2 Transmit */ +#define DMA_REQUEST_MUXSAI2RX (59U | EDMA4_MUX_ID) /**< SAI2 Receive */ +#define DMA_REQUEST_MUXSAI3TX (60U | EDMA4_MUX_ID) /**< SAI3 Transmit */ +#define DMA_REQUEST_MUXSAI3RX (61U | EDMA4_MUX_ID) /**< SAI3 Receive */ +#define DMA_REQUEST_MUXGPIO4REQUEST0 (62U | EDMA4_MUX_ID) /**< GPIO4 Request0 */ +#define DMA_REQUEST_MUXGPIO4REQUEST1 (63U | EDMA4_MUX_ID) /**< GPIO4 Request1 */ +#define DMA_REQUEST_MUXEARCREQUEST0 (65U | EDMA4_MUX_ID) /**< eARC enhanced Audio Return Channel */ +#define DMA_REQUEST_MUXEARCREQUEST1 (66U | EDMA4_MUX_ID) /**< eARC enhanced Audio Return Channel */ +#define DMA_REQUEST_MUXSAI4TX (67U | EDMA4_MUX_ID) /**< SAI4 Transmit */ +#define DMA_REQUEST_MUXSAI4RX (68U | EDMA4_MUX_ID) /**< SAI4 Receive */ +#define DMA_REQUEST_MUXSAI5TX (69U | EDMA4_MUX_ID) /**< SAI5 Transmit */ +#define DMA_REQUEST_MUXSAI5RX (70U | EDMA4_MUX_ID) /**< SAI5 Receive */ +#define DMA_REQUEST_MUXLPI2C5TX (71U | EDMA4_MUX_ID) /**< LPI2C5 */ +#define DMA_REQUEST_MUXLPI2C5RX (72U | EDMA4_MUX_ID) /**< LPI2C5 */ +#define DMA_REQUEST_MUXLPI2C6TX (73U | EDMA4_MUX_ID) /**< LPI2C6 */ +#define DMA_REQUEST_MUXLPI2C6RX (74U | EDMA4_MUX_ID) /**< LPI2C6 */ +#define DMA_REQUEST_MUXLPI2C7TX (75U | EDMA4_MUX_ID) /**< LPI2C7 */ +#define DMA_REQUEST_MUXLPI2C7RX (76U | EDMA4_MUX_ID) /**< LPI2C7 */ +#define DMA_REQUEST_MUXLPI2C8TX (77U | EDMA4_MUX_ID) /**< LPI2C8 */ +#define DMA_REQUEST_MUXLPI2C8RX (78U | EDMA4_MUX_ID) /**< LPI2C8 */ +#define DMA_REQUEST_MUXLPSPI5TX (79U | EDMA4_MUX_ID) /**< LPSPI5 Transmit */ +#define DMA_REQUEST_MUXLPSPI5RX (80U | EDMA4_MUX_ID) /**< LPSPI5 Receive */ +#define DMA_REQUEST_MUXLPSPI6TX (81U | EDMA4_MUX_ID) /**< LPSPI6 Transmit */ +#define DMA_REQUEST_MUXLPSPI6RX (82U | EDMA4_MUX_ID) /**< LPSPI6 Receive */ +#define DMA_REQUEST_MUXLPSPI7TX (83U | EDMA4_MUX_ID) /**< LPSPI7 Transmit */ +#define DMA_REQUEST_MUXLPSPI7RX (84U | EDMA4_MUX_ID) /**< LPSPI7 Receive */ +#define DMA_REQUEST_MUXLPSPI8TX (85U | EDMA4_MUX_ID) /**< LPSPI8 Transmit */ +#define DMA_REQUEST_MUXLPSPI8RX (86U | EDMA4_MUX_ID) /**< LPSPI8 Receive */ +#define DMA_REQUEST_MUXLPUART7TX (87U | EDMA4_MUX_ID) /**< LPUART7 Transmit */ +#define DMA_REQUEST_MUXLPUART7RX (88U | EDMA4_MUX_ID) /**< LPUART7 Receive */ +#define DMA_REQUEST_MUXLPUART8TX (89U | EDMA4_MUX_ID) /**< LPUART8 Transmit */ +#define DMA_REQUEST_MUXLPUART8RX (90U | EDMA4_MUX_ID) /**< LPUART8 Receive */ +#define DMA_REQUEST_MUXCAN4 (91U | EDMA4_MUX_ID) /**< CAN4 */ +#define DMA_REQUEST_MUXCAN5 (92U | EDMA4_MUX_ID) /**< CAN5 */ + +#define DMA4_REQUEST_MUX_COUNT (95) + +/* Combined MUX count (eDMA3 and eDMA4) */ + +#define DMA_REQUEST_MUX_COUNT (DMA3_REQUEST_MUX_COUNT + DMA4_REQUEST_MUX_COUNT) + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dmamux_get_dmabase + * + * Description: + * Get DMA engine base address from MUX identifier. + * + * Input Parameters: + * dmamux - The DMA MUX identifier. + * + * Returned Value: + * Base address of the associated DMA engine. + * + ****************************************************************************/ + +static inline uintptr_t imx9_dmamux_get_dmabase(uint16_t dmamux) +{ + if ((dmamux & EDMA_MUX_ID_MASK) == EDMA3_MUX_ID) + { + return IMX9_DMA3_BASE; + } + else + { + return IMX9_EDMA5_2_BASE; + } +} + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H */ diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_edma.h b/arch/arm/src/imx9/hardware/imx95/imx95_edma.h new file mode 100644 index 0000000000000..592c918d29995 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_edma.h @@ -0,0 +1,445 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_edma.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imx95_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* eDMA3 / eDMA4 Register Offsets */ + +#define IMX9_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */ +#define IMX9_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */ +#define IMX9_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */ + +/* eDMA3 only */ + +#define IMX9_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */ +#define IMX9_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */ + +/* eDMA4 only */ + +#define IMX9_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */ +#define IMX9_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */ +#define IMX9_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */ +#define IMX9_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */ + +/* eDNA5 only */ +#define IMX9_EDMA_MP_CH_MUX_OFFSET(n) (0x000200 + ((n) << 2)) /* Channel Multiplexor Configuration (CH_MUX) */ + +/* eDMA3 / eDMA4 Register Addresses */ + +#define IMX9_EDMA_CSR(n) ((n) + IMX9_EDMA_CSR_OFFSET) +#define IMX9_EDMA_ES(n) ((n) + IMX9_EDMA_ES_OFFSET) +#define IMX9_EDMA_CH_GRPRI(n,c) ((n) + IMX9_EDMA_CH_GRPRI_OFFSET(n)) + +/* eDMA3 only */ + +#define IMX9_EDMA_INT (IMX9_DMA3_BASE + IMX9_EDMA_INT_OFFSET) +#define IMX9_EDMA_HRS (IMX9_DMA3_BASE + IMX9_EDMA_HRS_OFFSET) + +/* eDMA5 only */ + +#define IMX9_EDMA_INT_LOW (IMX9_EDMA5_2_BASE + IMX9_EDMA_INT_LOW_OFFSET) +#define IMX9_EDMA_INT_HIGH (IMX9_EDMA5_2_BASE + IMX9_EDMA_INT_HIGH_OFFSET) +#define IMX9_EDMA_HRS_LOW (IMX9_EDMA5_2_BASE + IMX9_EDMA_HRS_LOW_OFFSET) +#define IMX9_EDMA_HRS_HIGH (IMX9_EDMA5_2_BASE + IMX9_EDMA_HRS_HIGH_OFFSET) + +/* eDMA Transfer Control Descriptor (TCD) Register Offsets */ + +#define IMX9_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */ +#define IMX9_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */ +#define IMX9_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */ +#define IMX9_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */ +#define IMX9_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */ +#define IMX9_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */ +#define IMX9_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */ +#define IMX9_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */ +#define IMX9_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */ +#define IMX9_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */ +#define IMX9_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */ +#define IMX9_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */ +#define IMX9_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */ +#define IMX9_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */ +#define IMX9_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */ +#define IMX9_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/ +#define IMX9_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */ +#define IMX9_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */ + +/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */ + +#define IMX9_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */ +#define IMX9_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */ +#define IMX9_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */ +#define IMX9_EDMA_TCD_BASE(n) ((n) + IMX9_EDMA_TCD_BASE_OFFSET) +#define IMX9_EDMA_TCD_INST_OFFSET(n) ((n) == IMX9_DMA3_BASE ? IMX9_EDMA3_TCD_INST_OFFSET : IMX9_EDMA4_TCD_INST_OFFSET) +#define IMX9_EDMA_TCD(n,t) (IMX9_EDMA_TCD_BASE(n) + (t) * IMX9_EDMA_TCD_INST_OFFSET(n)) + +/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/ + +#define IMX9_EDMA_CH_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_CSR_OFFSET) +#define IMX9_EDMA_CH_ES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_ES_OFFSET) +#define IMX9_EDMA_CH_INT(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_INT_OFFSET) +#define IMX9_EDMA_CH_SBR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_SBR_OFFSET) +#define IMX9_EDMA_CH_PRI(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_PRI_OFFSET) +#define IMX9_EDMA_CH_MUX(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_MUX_OFFSET) +#define IMX9_EDMA_TCD_SADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SADDR_OFFSET) +#define IMX9_EDMA_TCD_SOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SOFF_OFFSET) +#define IMX9_EDMA_TCD_ATTR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_ATTR_OFFSET) +#define IMX9_EDMA_TCD_NBYTES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_NBYTES_OFFSET) +#define IMX9_EDMA_TCD_SLAST_SDA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SLAST_SDA_OFFSET) +#define IMX9_EDMA_TCD_DADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DADDR_OFFSET) +#define IMX9_EDMA_TCD_DOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DOFF_OFFSET) +#define IMX9_EDMA_TCD_CITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CITER_OFFSET) +#define IMX9_EDMA_TCD_DLAST_SGA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DLAST_SGA_OFFSET) +#define IMX9_EDMA_TCD_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CSR_OFFSET) +#define IMX9_EDMA_TCD_BITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_BITER_OFFSET) + +/* eDMA Register Bitfield Definitions ***************************************/ + +/* Management Page Control Register (CSR) */ + + /* Bit 0: Reserved */ +#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */ +#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */ + /* Bit 3: Reserved */ +#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */ +#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */ +#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */ +#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */ +#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */ +#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */ + /* Bits 10-23: Reserved */ +#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */ +#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */ + +/* Management Page Error Status Register (ES) */ + +#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ +#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */ + /* Bits 9-23: Reserved */ +#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */ +#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */ + +/* Management Page Interrupt Request Status Register (INT) */ + +#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */ + +/* Management Page Hardware Request Status Register (HRS) */ + +#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */ + +/* Channel n Arbitration Group Register (CHn_GRPRI) */ + +#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */ +#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT) + /* Bits 5-31: Reserved */ + +/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/ + +/* Channel n Control and Status Register (CHn_CSR) */ + +#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */ +#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */ +#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */ +#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */ + /* Bit 4-29: Reserved */ +#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */ +#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */ + +/* Channel n Error Status Register (CHn_ES) */ + +#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ + /* Bit 8-30: Reserved */ +#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */ + +/* Channel n Interrupt Status Register (CHn_INT) */ + +#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */ + /* Bits 1-31: Reserved */ + +/* Channel n System Bus Register (CHn_SBR) */ + +#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */ +#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT) + /* Bits 4-13: Reserved */ +#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */ +#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */ +#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */ +#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */ +#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT) + /* Bits 20-31: Reserved */ + +/* Channel n Priority Register (CHn_PRI) */ + +#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */ +#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT) + /* Bits 3-29: Reserved */ +#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */ +#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */ + +/* Channel Multiplexor Configuration (CHn_MUX) */ + +#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-6: Service Request Source */ +#define EDMA_CH_SRC_MASK (0x7f << EDMA_CH_SRC_SHIFT) + +/* TCDn Source Address Register (TCDn_SADDR) */ + +#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */ +#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT) + +/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */ + +#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */ +#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT) + +/* TCDn Transfer Attributes (TCDn_ATTR) */ + +#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */ +#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT) +#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK) +#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */ +#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT) +#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK) +#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */ +#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT) +#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK) +# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ +# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ +# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */ +# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */ +# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */ + +#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */ +#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT) +#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK) + +/* TCDn Transfer Size (TCDn_NBYTES) */ + +#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */ +#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */ +#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */ +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */ + +/* TCDn Last Source Address Adjustment / Store DADDR Address Register + * (TCDn_SLAST_SDA) + */ + +#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */ +#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT) + +/* TCDn Destination Address Register (TCDn_DADDR) */ + +#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */ +#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT) + +/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */ + +#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */ +#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT) + +/* TCDn Current Major Loop Count Register (TCDn_CITER) */ + +#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */ +#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */ +#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register + * (TCDn_DLAST_SGA) + */ + +#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */ +#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT) + +/* TCDn Control and Status Register (TCDn_CSR) */ + +#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */ +#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */ +#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */ +#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */ +#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */ +#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */ +#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */ +#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */ +#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */ +#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) +#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK) + /* Bit 13: Reserved */ +#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */ +#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT) +# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */ +# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */ +# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */ +# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */ + +/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */ + +#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */ +#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */ +#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT) +#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK) +#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* Amount of channels */ + +#define DMA3_CHANNEL_COUNT (31) +#define DMA4_CHANNEL_COUNT (64) +#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT) + +/* Amount of interrupt sources */ +#ifdef CONFIG_ARCH_CHIP_IMX95_M7 +#define DMA3_IRQ_COUNT (31) /* Error interrupt not counted */ +#else +#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */ +#endif +#define DMA4_IRQ_COUNT (32) /* Error interrupt not counted */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* In-memory representation of the 32-byte Transfer Control Descriptor + * (TCD) + */ + +struct imx9_edmatcd_s +{ + uint32_t saddr; /* Offset: 0x0000 TCD Source Address */ + uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */ + uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */ + uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */ + uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */ + uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */ + uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* Offset: 0x001c TCD Control and Status */ + uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */ +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_edma_tcdhasmux + * + * Description: + * Check if DMA TCD has TCD.MUX register. + * + * Input Parameters: + * dmabase - The eDMA base. + * + * Returned Value: + * true if TCD.MUX exists; false if not. + * + ****************************************************************************/ + +static inline bool imx9_edma_tcdhasmux(uintptr_t dmabase) +{ + /* Only eDMA5 has TCD.MUX register */ + + return dmabase == IMX9_EDMA5_2_BASE ? true : false; +} + +/**************************************************************************** + * Name: imx9_edma_choffset + * + * Description: + * Channel offset in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel offset. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_choffset(uintptr_t base) +{ + return base == IMX9_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT; +} + +/**************************************************************************** + * Name: imx9_edma_chmax + * + * Description: + * Max channel in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel max. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_chmax(uintptr_t base) +{ + return base == IMX9_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMX9_EDMA_NCHANNELS; +} + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H */ diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_gpio.h b/arch/arm/src/imx9/hardware/imx95/imx95_gpio.h new file mode 100644 index 0000000000000..f74bce9576f36 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_gpio.h @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx95_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */ +#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */ +#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */ +#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */ +#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */ +#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */ +#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */ +#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */ +#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */ +#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */ +#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */ +#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */ +#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */ +#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */ +#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */ +#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */ +#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */ +#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H */ diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_iomuxc.h b/arch/arm/src/imx9/hardware/imx95/imx95_iomuxc.h new file mode 100644 index 0000000000000..b0bfd4e918c6f --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_iomuxc.h @@ -0,0 +1,810 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_iomuxc.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOMUXC_MUX_CTL_DAP_TDI_OFFSET (0x0000) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET (0x0004) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET (0x0008) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET (0x000c) +#define IOMUXC_MUX_CTL_GPIO_IO00_OFFSET (0x0010) +#define IOMUXC_MUX_CTL_GPIO_IO01_OFFSET (0x0014) +#define IOMUXC_MUX_CTL_GPIO_IO02_OFFSET (0x0018) +#define IOMUXC_MUX_CTL_GPIO_IO03_OFFSET (0x001c) +#define IOMUXC_MUX_CTL_GPIO_IO04_OFFSET (0x0020) +#define IOMUXC_MUX_CTL_GPIO_IO05_OFFSET (0x0024) +#define IOMUXC_MUX_CTL_GPIO_IO06_OFFSET (0x0028) +#define IOMUXC_MUX_CTL_GPIO_IO07_OFFSET (0x002c) +#define IOMUXC_MUX_CTL_GPIO_IO08_OFFSET (0x0030) +#define IOMUXC_MUX_CTL_GPIO_IO09_OFFSET (0x0034) +#define IOMUXC_MUX_CTL_GPIO_IO10_OFFSET (0x0038) +#define IOMUXC_MUX_CTL_GPIO_IO11_OFFSET (0x003c) +#define IOMUXC_MUX_CTL_GPIO_IO12_OFFSET (0x0040) +#define IOMUXC_MUX_CTL_GPIO_IO13_OFFSET (0x0044) +#define IOMUXC_MUX_CTL_GPIO_IO14_OFFSET (0x0048) +#define IOMUXC_MUX_CTL_GPIO_IO15_OFFSET (0x004c) +#define IOMUXC_MUX_CTL_GPIO_IO16_OFFSET (0x0050) +#define IOMUXC_MUX_CTL_GPIO_IO17_OFFSET (0x0054) +#define IOMUXC_MUX_CTL_GPIO_IO18_OFFSET (0x0058) +#define IOMUXC_MUX_CTL_GPIO_IO19_OFFSET (0x005c) +#define IOMUXC_MUX_CTL_GPIO_IO20_OFFSET (0x0060) +#define IOMUXC_MUX_CTL_GPIO_IO21_OFFSET (0x0064) +#define IOMUXC_MUX_CTL_GPIO_IO22_OFFSET (0x0068) +#define IOMUXC_MUX_CTL_GPIO_IO23_OFFSET (0x006c) +#define IOMUXC_MUX_CTL_GPIO_IO24_OFFSET (0x0070) +#define IOMUXC_MUX_CTL_GPIO_IO25_OFFSET (0x0074) +#define IOMUXC_MUX_CTL_GPIO_IO26_OFFSET (0x0078) +#define IOMUXC_MUX_CTL_GPIO_IO27_OFFSET (0x007c) +#define IOMUXC_MUX_CTL_GPIO_IO28_OFFSET (0x0080) +#define IOMUXC_MUX_CTL_GPIO_IO29_OFFSET (0x0084) +#define IOMUXC_MUX_CTL_GPIO_IO30_OFFSET (0x0088) +#define IOMUXC_MUX_CTL_GPIO_IO31_OFFSET (0x008c) +#define IOMUXC_MUX_CTL_GPIO_IO32_OFFSET (0x0090) +#define IOMUXC_MUX_CTL_GPIO_IO33_OFFSET (0x0094) +#define IOMUXC_MUX_CTL_GPIO_IO34_OFFSET (0x0098) +#define IOMUXC_MUX_CTL_GPIO_IO35_OFFSET (0x009c) +#define IOMUXC_MUX_CTL_GPIO_IO36_OFFSET (0x00a0) +#define IOMUXC_MUX_CTL_GPIO_IO37_OFFSET (0x00a4) +#define IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET (0x00a8) +#define IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET (0x00ac) +#define IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET (0x00b0) +#define IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET (0x00b4) +#define IOMUXC_MUX_CTL_ENET1_MDC_OFFSET (0x00b8) +#define IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET (0x00bc) +#define IOMUXC_MUX_CTL_ENET1_TD3_OFFSET (0x00c0) +#define IOMUXC_MUX_CTL_ENET1_TD2_OFFSET (0x00c4) +#define IOMUXC_MUX_CTL_ENET1_TD1_OFFSET (0x00c8) +#define IOMUXC_MUX_CTL_ENET1_TD0_OFFSET (0x00cc) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET (0x00d0) +#define IOMUXC_MUX_CTL_ENET1_TXC_OFFSET (0x00d4) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET (0x00d8) +#define IOMUXC_MUX_CTL_ENET1_RXC_OFFSET (0x00dc) +#define IOMUXC_MUX_CTL_ENET1_RD0_OFFSET (0x00e0) +#define IOMUXC_MUX_CTL_ENET1_RD1_OFFSET (0x00e4) +#define IOMUXC_MUX_CTL_ENET1_RD2_OFFSET (0x00e8) +#define IOMUXC_MUX_CTL_ENET1_RD3_OFFSET (0x00ec) +#define IOMUXC_MUX_CTL_ENET2_MDC_OFFSET (0x00f0) +#define IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET (0x00f4) +#define IOMUXC_MUX_CTL_ENET2_TD3_OFFSET (0x00f8) +#define IOMUXC_MUX_CTL_ENET2_TD2_OFFSET (0x00fc) +#define IOMUXC_MUX_CTL_ENET2_TD1_OFFSET (0x0100) +#define IOMUXC_MUX_CTL_ENET2_TD0_OFFSET (0x0104) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET (0x0108) +#define IOMUXC_MUX_CTL_ENET2_TXC_OFFSET (0x010c) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET (0x0110) +#define IOMUXC_MUX_CTL_ENET2_RXC_OFFSET (0x0114) +#define IOMUXC_MUX_CTL_ENET2_RD0_OFFSET (0x0118) +#define IOMUXC_MUX_CTL_ENET2_RD1_OFFSET (0x011c) +#define IOMUXC_MUX_CTL_ENET2_RD2_OFFSET (0x0120) +#define IOMUXC_MUX_CTL_ENET2_RD3_OFFSET (0x0124) +#define IOMUXC_MUX_CTL_SD1_CLK_OFFSET (0x0128) +#define IOMUXC_MUX_CTL_SD1_CMD_OFFSET (0x012c) +#define IOMUXC_MUX_CTL_SD1_DATA0_OFFSET (0x0130) +#define IOMUXC_MUX_CTL_SD1_DATA1_OFFSET (0x0134) +#define IOMUXC_MUX_CTL_SD1_DATA2_OFFSET (0x0138) +#define IOMUXC_MUX_CTL_SD1_DATA3_OFFSET (0x013c) +#define IOMUXC_MUX_CTL_SD1_DATA4_OFFSET (0x0140) +#define IOMUXC_MUX_CTL_SD1_DATA5_OFFSET (0x0144) +#define IOMUXC_MUX_CTL_SD1_DATA6_OFFSET (0x0148) +#define IOMUXC_MUX_CTL_SD1_DATA7_OFFSET (0x014c) +#define IOMUXC_MUX_CTL_SD1_STROBE_OFFSET (0x0150) +#define IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET (0x0154) +#define IOMUXC_MUX_CTL_SD3_CLK_OFFSET (0x0158) +#define IOMUXC_MUX_CTL_SD3_CMD_OFFSET (0x015c) +#define IOMUXC_MUX_CTL_SD3_DATA0_OFFSET (0x0160) +#define IOMUXC_MUX_CTL_SD3_DATA1_OFFSET (0x0164) +#define IOMUXC_MUX_CTL_SD3_DATA2_OFFSET (0x0168) +#define IOMUXC_MUX_CTL_SD3_DATA3_OFFSET (0x016c) +#define IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET (0x0170) +#define IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET (0x0174) +#define IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET (0x0178) +#define IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET (0x017c) +#define IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET (0x0180) +#define IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET (0x0184) +#define IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET (0x0188) +#define IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET (0x018c) +#define IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET (0x0190) +#define IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET (0x0194) +#define IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET (0x0198) +#define IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET (0x019c) +#define IOMUXC_MUX_CTL_SD2_CD_B_OFFSET (0x01a0) +#define IOMUXC_MUX_CTL_SD2_CLK_OFFSET (0x01a4) +#define IOMUXC_MUX_CTL_SD2_CMD_OFFSET (0x01a8) +#define IOMUXC_MUX_CTL_SD2_DATA0_OFFSET (0x01ac) +#define IOMUXC_MUX_CTL_SD2_DATA1_OFFSET (0x01b0) +#define IOMUXC_MUX_CTL_SD2_DATA2_OFFSET (0x01b4) +#define IOMUXC_MUX_CTL_SD2_DATA3_OFFSET (0x01b8) +#define IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET (0x01bc) +#define IOMUXC_MUX_CTL_I2C1_SCL_OFFSET (0x01c0) +#define IOMUXC_MUX_CTL_I2C1_SDA_OFFSET (0x01c4) +#define IOMUXC_MUX_CTL_I2C2_SCL_OFFSET (0x01c8) +#define IOMUXC_MUX_CTL_I2C2_SDA_OFFSET (0x01cc) +#define IOMUXC_MUX_CTL_UART1_RXD_OFFSET (0x01d0) +#define IOMUXC_MUX_CTL_UART1_TXD_OFFSET (0x01d4) +#define IOMUXC_MUX_CTL_UART2_RXD_OFFSET (0x01d8) +#define IOMUXC_MUX_CTL_UART2_TXD_OFFSET (0x01dc) +#define IOMUXC_MUX_CTL_PDM_CLK_OFFSET (0x01e0) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET (0x01e4) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET (0x01e8) +#define IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET (0x01ec) +#define IOMUXC_MUX_CTL_SAI1_TXC_OFFSET (0x01f0) +#define IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET (0x01f4) +#define IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET (0x01f8) +#define IOMUXC_MUX_CTL_WDOG_ANY_OFFSET (0x01fc) + +#define IOMUXC_PAD_CTL_DAP_TDI_OFFSET (0x0204) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET (0x0208) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET (0x020c) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET (0x0210) +#define IOMUXC_PAD_CTL_GPIO_IO00_OFFSET (0x0214) +#define IOMUXC_PAD_CTL_GPIO_IO01_OFFSET (0x0218) +#define IOMUXC_PAD_CTL_GPIO_IO02_OFFSET (0x021c) +#define IOMUXC_PAD_CTL_GPIO_IO03_OFFSET (0x0220) +#define IOMUXC_PAD_CTL_GPIO_IO04_OFFSET (0x0224) +#define IOMUXC_PAD_CTL_GPIO_IO05_OFFSET (0x0228) +#define IOMUXC_PAD_CTL_GPIO_IO06_OFFSET (0x022c) +#define IOMUXC_PAD_CTL_GPIO_IO07_OFFSET (0x0230) +#define IOMUXC_PAD_CTL_GPIO_IO08_OFFSET (0x0234) +#define IOMUXC_PAD_CTL_GPIO_IO09_OFFSET (0x0238) +#define IOMUXC_PAD_CTL_GPIO_IO10_OFFSET (0x023c) +#define IOMUXC_PAD_CTL_GPIO_IO11_OFFSET (0x0240) +#define IOMUXC_PAD_CTL_GPIO_IO12_OFFSET (0x0244) +#define IOMUXC_PAD_CTL_GPIO_IO13_OFFSET (0x0248) +#define IOMUXC_PAD_CTL_GPIO_IO14_OFFSET (0x024c) +#define IOMUXC_PAD_CTL_GPIO_IO15_OFFSET (0x0250) +#define IOMUXC_PAD_CTL_GPIO_IO16_OFFSET (0x0254) +#define IOMUXC_PAD_CTL_GPIO_IO17_OFFSET (0x0258) +#define IOMUXC_PAD_CTL_GPIO_IO18_OFFSET (0x025c) +#define IOMUXC_PAD_CTL_GPIO_IO19_OFFSET (0x0260) +#define IOMUXC_PAD_CTL_GPIO_IO20_OFFSET (0x0264) +#define IOMUXC_PAD_CTL_GPIO_IO21_OFFSET (0x0268) +#define IOMUXC_PAD_CTL_GPIO_IO22_OFFSET (0x026c) +#define IOMUXC_PAD_CTL_GPIO_IO23_OFFSET (0x0270) +#define IOMUXC_PAD_CTL_GPIO_IO24_OFFSET (0x0274) +#define IOMUXC_PAD_CTL_GPIO_IO25_OFFSET (0x0278) +#define IOMUXC_PAD_CTL_GPIO_IO26_OFFSET (0x027c) +#define IOMUXC_PAD_CTL_GPIO_IO27_OFFSET (0x0280) +#define IOMUXC_PAD_CTL_GPIO_IO28_OFFSET (0x0284) +#define IOMUXC_PAD_CTL_GPIO_IO29_OFFSET (0x0288) +#define IOMUXC_PAD_CTL_GPIO_IO30_OFFSET (0x028c) +#define IOMUXC_PAD_CTL_GPIO_IO31_OFFSET (0x0290) +#define IOMUXC_PAD_CTL_GPIO_IO32_OFFSET (0x0294) +#define IOMUXC_PAD_CTL_GPIO_IO33_OFFSET (0x0298) +#define IOMUXC_PAD_CTL_GPIO_IO34_OFFSET (0x029c) +#define IOMUXC_PAD_CTL_GPIO_IO35_OFFSET (0x02a0) +#define IOMUXC_PAD_CTL_GPIO_IO36_OFFSET (0x02a4) +#define IOMUXC_PAD_CTL_GPIO_IO37_OFFSET (0x02a8) +#define IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET (0x02ac) +#define IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET (0x02b0) +#define IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET (0x02b4) +#define IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET (0x02b8) +#define IOMUXC_PAD_CTL_ENET1_MDC_OFFSET (0x02bc) +#define IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET (0x02c0) +#define IOMUXC_PAD_CTL_ENET1_TD3_OFFSET (0x02c4) +#define IOMUXC_PAD_CTL_ENET1_TD2_OFFSET (0x02c8) +#define IOMUXC_PAD_CTL_ENET1_TD1_OFFSET (0x02cc) +#define IOMUXC_PAD_CTL_ENET1_TD0_OFFSET (0x02d0) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET (0x02d4) +#define IOMUXC_PAD_CTL_ENET1_TXC_OFFSET (0x02d8) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET (0x02dc) +#define IOMUXC_PAD_CTL_ENET1_RXC_OFFSET (0x02e0) +#define IOMUXC_PAD_CTL_ENET1_RD0_OFFSET (0x02e4) +#define IOMUXC_PAD_CTL_ENET1_RD1_OFFSET (0x02e8) +#define IOMUXC_PAD_CTL_ENET1_RD2_OFFSET (0x02ec) +#define IOMUXC_PAD_CTL_ENET1_RD3_OFFSET (0x02f0) +#define IOMUXC_PAD_CTL_ENET2_MDC_OFFSET (0x02f4) +#define IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET (0x02f8) +#define IOMUXC_PAD_CTL_ENET2_TD3_OFFSET (0x02fc) +#define IOMUXC_PAD_CTL_ENET2_TD2_OFFSET (0x0300) +#define IOMUXC_PAD_CTL_ENET2_TD1_OFFSET (0x0304) +#define IOMUXC_PAD_CTL_ENET2_TD0_OFFSET (0x0308) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET (0x030c) +#define IOMUXC_PAD_CTL_ENET2_TXC_OFFSET (0x0310) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET (0x0314) +#define IOMUXC_PAD_CTL_ENET2_RXC_OFFSET (0x0318) +#define IOMUXC_PAD_CTL_ENET2_RD0_OFFSET (0x031c) +#define IOMUXC_PAD_CTL_ENET2_RD1_OFFSET (0x0320) +#define IOMUXC_PAD_CTL_ENET2_RD2_OFFSET (0x0324) +#define IOMUXC_PAD_CTL_ENET2_RD3_OFFSET (0x0328) +#define IOMUXC_PAD_CTL_SD1_CLK_OFFSET (0x032c) +#define IOMUXC_PAD_CTL_SD1_CMD_OFFSET (0x0330) +#define IOMUXC_PAD_CTL_SD1_DATA0_OFFSET (0x0334) +#define IOMUXC_PAD_CTL_SD1_DATA1_OFFSET (0x0338) +#define IOMUXC_PAD_CTL_SD1_DATA2_OFFSET (0x033c) +#define IOMUXC_PAD_CTL_SD1_DATA3_OFFSET (0x0340) +#define IOMUXC_PAD_CTL_SD1_DATA4_OFFSET (0x0344) +#define IOMUXC_PAD_CTL_SD1_DATA5_OFFSET (0x0348) +#define IOMUXC_PAD_CTL_SD1_DATA6_OFFSET (0x034c) +#define IOMUXC_PAD_CTL_SD1_DATA7_OFFSET (0x0350) +#define IOMUXC_PAD_CTL_SD1_STROBE_OFFSET (0x0354) +#define IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET (0x0358) +#define IOMUXC_PAD_CTL_SD3_CLK_OFFSET (0x035c) +#define IOMUXC_PAD_CTL_SD3_CMD_OFFSET (0x0360) +#define IOMUXC_PAD_CTL_SD3_DATA0_OFFSET (0x0364) +#define IOMUXC_PAD_CTL_SD3_DATA1_OFFSET (0x0368) +#define IOMUXC_PAD_CTL_SD3_DATA2_OFFSET (0x036c) +#define IOMUXC_PAD_CTL_SD3_DATA3_OFFSET (0x0370) +#define IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET (0x0374) +#define IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET (0x0378) +#define IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET (0x037c) +#define IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET (0x0380) +#define IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET (0x0384) +#define IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET (0x0388) +#define IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET (0x038c) +#define IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET (0x0390) +#define IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET (0x0394) +#define IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET (0x0398) +#define IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET (0x039c) +#define IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET (0x03a0) +#define IOMUXC_PAD_CTL_SD2_CD_B_OFFSET (0x03a4) +#define IOMUXC_PAD_CTL_SD2_CLK_OFFSET (0x03a8) +#define IOMUXC_PAD_CTL_SD2_CMD_OFFSET (0x03ac) +#define IOMUXC_PAD_CTL_SD2_DATA0_OFFSET (0x03b0) +#define IOMUXC_PAD_CTL_SD2_DATA1_OFFSET (0x03b4) +#define IOMUXC_PAD_CTL_SD2_DATA2_OFFSET (0x03b8) +#define IOMUXC_PAD_CTL_SD2_DATA3_OFFSET (0x03bc) +#define IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET (0x03c0) +#define IOMUXC_PAD_CTL_I2C1_SCL_OFFSET (0x03c4) +#define IOMUXC_PAD_CTL_I2C1_SDA_OFFSET (0x03c8) +#define IOMUXC_PAD_CTL_I2C2_SCL_OFFSET (0x03cc) +#define IOMUXC_PAD_CTL_I2C2_SDA_OFFSET (0x03d0) +#define IOMUXC_PAD_CTL_UART1_RXD_OFFSET (0x03d4) +#define IOMUXC_PAD_CTL_UART1_TXD_OFFSET (0x03d8) +#define IOMUXC_PAD_CTL_UART2_RXD_OFFSET (0x03dc) +#define IOMUXC_PAD_CTL_UART2_TXD_OFFSET (0x03e0) +#define IOMUXC_PAD_CTL_PDM_CLK_OFFSET (0x03e4) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET (0x03e8) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET (0x03ec) +#define IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET (0x03f0) +#define IOMUXC_PAD_CTL_SAI1_TXC_OFFSET (0x03f4) +#define IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET (0x03f8) +#define IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET (0x03fc) +#define IOMUXC_PAD_CTL_WDOG_ANY_OFFSET (0x0400) +#define IOMUXC_PAD_CTL_FCCU_ERR0_OFFSET (0x0404) + +#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0408) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET (0x040c) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET (0x0410) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET (0x0414) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET (0x0418) +#define IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET (0x041c) +#define IOMUXC_EXT1_CLK_SELECT_INPUT_OFFSET (0x0420) +#define IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET (0x0424) +#define IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET (0x0428) +#define IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET (0x042c) +#define IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET (0x0430) +#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET (0x0434) +#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET (0x0438) +#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET (0x043c) +#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET (0x0440) +#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0444) +#define IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0448) +#define IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x044c) +#define IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0450) +#define IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET (0x0454) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET (0x0458) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET (0x045c) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET (0x0460) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET (0x0464) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET (0x0468) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET (0x046c) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET (0x0470) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET (0x0474) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET (0x0478) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET (0x047c) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET (0x0480) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET (0x0484) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET (0x0488) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET (0x048c) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET (0x0490) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET (0x0494) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET (0x0498) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET (0x049c) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET (0x04a0) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET (0x04a4) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET (0x04a8) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET (0x04ac) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET (0x04b0) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET (0x04b4) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET (0x04b8) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET (0x04bc) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET (0x04c0) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET (0x04c4) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET (0x04c8) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET (0x04cc) +#define IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET (0x04d0) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET (0x04d4) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET (0x04d8) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET (0x04dc) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET (0x04e0) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET (0x04e4) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET (0x04e8) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET (0x04ec) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET (0x04f0) +#define IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET (0x04f4) +#define IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET (0x04f8) +#define IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET (0x04fc) +#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0500) +#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0504) +#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0508) +#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x050c) +#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0510) +#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0514) +#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0518) +#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x051c) +#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0520) +#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0524) +#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0528) +#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x052c) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET (0x0530) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET (0x0534) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET (0x0538) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET (0x053c) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET (0x0540) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET (0x0544) +#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET (0x0548) +#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET (0x054c) +#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET (0x0550) +#define IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x0554) +#define IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0558) +#define IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x055c) +#define IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x0560) +#define IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0564) +#define IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0568) +#define IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x056c) +#define IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0570) +#define IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0574) +#define IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET (0x0578) +#define IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x057c) +#define IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0580) +#define IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0584) +#define IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0588) +#define IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x058c) +#define IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x0590) +#define IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x0594) +#define IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET (0x0598) +#define IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x059c) +#define IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET (0x05a0) +#define IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET (0x05a4) +#define IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x05a8) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET (0x05ac) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET (0x05b0) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET (0x05b4) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET (0x05b8) +#define IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x05bc) +#define IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET (0x05c0) +#define IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET (0x05c4) +#define IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET (0x05c8) +#define IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET (0x05cc) +#define IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET (0x05d0) +#define IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET (0x05d4) +#define IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET (0x05d8) +#define IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET (0x05dc) +#define IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET (0x05e0) +#define IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET (0x05e4) +#define IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET (0x05e8) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET (0x05ec) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET (0x05f0) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET (0x05f4) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET (0x05f8) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET (0x05fc) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET (0x0600) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET (0x0604) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET (0x0608) +#define IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET (0x060c) +#define IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET (0x0610) +#define IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET (0x0614) + +#define IOMUXC_MUX_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDI_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO30 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO30_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO31 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO31_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO32 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO32_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO33 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO33_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO34 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO34_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO35 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO35_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO36 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO36_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO37 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO37_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_MUX_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_MUX_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_DQS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_SCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_SS0_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_MUX_CTL_XSPI1_SS1_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_MUX_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_TXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_TXD_OFFSET) +#define IOMUXC_MUX_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_CLK_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_MUX_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_WDOG_ANY_OFFSET) + +#define IOMUXC_PAD_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO30 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO30_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO31 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO31_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO32 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO32_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO33 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO33_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO34 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO34_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO35 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO35_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO36 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO36_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO37 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO37_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_DQS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_SCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_SS0_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_CTL_XSPI1_SS1_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) +#define IOMUXC_PAD_CTL_FCCU_ERR0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_FCCU_ERR0_OFFSET) + +#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET) +#define IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET) +#define IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET) +#define IOMUXC_EXT1_CLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_EXT1_CLK_SELECT_INPUT_OFFSET) +#define IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET) +#define IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET) +#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET) +#define IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET) +#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET) +#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET) +#define IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET) +#define IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET) +#define IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET) +#define IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET) +#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET) +#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET) +#define IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET) +#define IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET) +#define IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET) +#define IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET) +#define IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET) +#define IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET) +#define IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET) +#define IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET) +#define IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET) +#define IOMUXC_JTAG_MUX_TCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET) +#define IOMUXC_JTAG_MUX_TDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET) +#define IOMUXC_JTAG_MUX_TMS_SELECT_INPUT (IMX9_IOMUXC1_BASE + IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET) diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h b/arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h new file mode 100644 index 0000000000000..56d26b306a6c0 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h @@ -0,0 +1,765 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_ITCM_BASE (0x00000000) /* 512 KB ITCM (FlexRAM) */ +#define IMX9_FLEXSPI1_ALIAS_BASE (0x02000000) /* 32 MB FlexSPI1 (alias) */ +#define IMX9_DTCM_BASE (0x20000000) /* 512 KB DTCM (FlexRAM) */ +#define IMX9_OCRAM_BASE (0x20480000) /* 352 KB, OCRAM */ +#define IMX9_FLEXSPI1_BASE (0x28000000) /* 128 MB FlexSPI1 */ +#define IMX9_AIPS1_BASE (0x42000000) /* AIPS 8192KB */ +#define IMX9_AIPS2_BASE (0x42800000) /* AIPS 8192KB */ +#define IMX9_AIPS3_BASE (0x44000000) /* AIPS 8192KB */ +#define IMX9_AIPS4_BASE (0x49000000) /* AIPS 8192KB */ +#define IMX9_GPIO_MEM_BASE (0x43810000) /* GPIO 2-3-4-5 320KB region */ +#define IMX9_GPIO1_BASE (0x47400000) /* GPIO 1 64KB region */ +#define IMX9_DRAM_BASE (0x80000000) /* DRAM */ +#define IMX9_DRAM_XIP_BASE (0x90000800) /* DRAM XIP */ +#define IMX9_RPMSG_BASE (0x88000000) /* DRAM for VRING and RSC */ + +#define IMX9_ADC_BASE (0x44530000) +#define IMX9_ANALOG__AGDET_BASE (0x44487000) +#define IMX9_ANALOG__AUDIO_FRACT_PLL1_BASE (0x44481100) +#define IMX9_ANALOG__AUDIO_FRACT_PLL2_BASE (0x44481200) +#define IMX9_ANALOG__CMU0_BASE (0x44670000) +#define IMX9_ANALOG__FRO_BASE (0x44485000) +#define IMX9_ANALOG__OSC24M_BASE (0x44480000) +#define IMX9_ANALOG__PMRO_BASE (0x44484000) +#define IMX9_ANALOG__SFA_BASE (0x44483000) +#define IMX9_ANALOG__SYS_FRACT_PLL1_BASE (0x44481000) +#define IMX9_ANALOG__TCU_BASE (0x444C0000) +#define IMX9_ANALOG__TRGMUX_BASE (0x44531000) +#define IMX9_ANALOG__VDET_BASE (0x44486000) +#define IMX9_ANALOG__VIDEO_FRACT_PLL1_BASE (0x44481300) +#define IMX9_AON__AXBS_BASE (0x44510000) +#define IMX9_AON__BLK_CTRL_NS_AONMIX1_BASE (0x44210000) +#define IMX9_AON__BLK_CTRL_S_AONMIX2_BASE (0x444F0000) +#define IMX9_AON__CMUA1_BASE (0x44540000) +#define IMX9_AON__CMUA2_BASE (0x44650000) +#define IMX9_AON__CRCA_BASE (0x44660000) +#define IMX9_AON__CSTCU_BASE (0x44590000) +#define IMX9_AON__EDMA3_TCD1_BASE (0x44010000) +#define IMX9_AON__EIMA_BASE (0x44550000) +#define IMX9_AON__FCCU_BASE (0x44570000) +#define IMX9_AON__INTM_BASE (0x44580000) +#define IMX9_AON__IOMUXC0__IOMUXC_GPR_BASE (0x443D0000) +#define IMX9_AON__LSTCUA_BASE (0x445A0000) +#define IMX9_AON__M33_CACHE_CTRL_ECC0__CM33_CACHE_ECC_MCM_BASE (0x44401000) +#define IMX9_AON__M33_CACHE_CTRL_ECC0__CM33_TCM_MCM_BASE (0x44420000) +#define IMX9_AON__M33_PCF1_BASE (0x443E0000) +#define IMX9_AON__M33_PSF1_BASE (0x443F0000) +#define IMX9_AON__MCM_BASE (0xE0080000) +#define IMX9_AON__ROMCP1_BASE (0x44430000) +#define IMX9_AON__SYS_CTR1__SYS_CTR_COMPARE_BASE (0x442A0000) +#define IMX9_AON__SYS_CTR1__SYS_CTR_CONTROL_BASE (0x44290000) +#define IMX9_AON__SYS_CTR1__SYS_CTR_READ_BASE (0x442B0000) +#define IMX9_AON__TCU_BASE (0x444B0000) +#define IMX9_BBSM__BBNSM_BASE (0x44440000) +#define IMX9_BBSM__BLK_CTRL_BBSMMIX_BBSMMIX1_BASE (0x44410000) +#define IMX9_BBSM__TCU_BBSMMIX_BASE (0x444E0000) +#define IMX9_BLK_CTRL_CAMERAMIX_BASE (0x4AC10000) +#define IMX9_BLK_CTRL_NETCMIX_BASE (0x4C810000) +#define IMX9_CAMERA__DSI_CAMID_CSR_BASE (0x4ADE0000) +#define IMX9_CAMERA__DSI_CSI_COMBO_COMPLEX_CSI1__CSI_BASE (0x4AD40000) +#define IMX9_CAMERA__DSI_MASTER_CSR_BASE (0x4AD10000) +#define IMX9_CAMERA__DSI_OR_CSI_PHY_CSR_BASE (0x4AD20000) +#define IMX9_CAMERA__DSI_PIXEL_FORMATTING_BASE (0x4AC00000) +#define IMX9_CAMERA__DSI_STREAM_CSR_BASE (0x4AD00000) +#define IMX9_CAMERA__EDMA5_TCDC_BASE (0x4AE20000) +#define IMX9_CAMERA__GPV__ISI_RD_I_MAIN_QOSGENERATOR_BASE (0x4AFF0C00) +#define IMX9_CAMERA__GPV__ISI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1000) +#define IMX9_CAMERA__GPV__ISI_WR_U_I_MAIN_QOSGENERATOR_BASE (0x4AFF0C80) +#define IMX9_CAMERA__GPV__ISI_WR_U_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1080) +#define IMX9_CAMERA__GPV__ISI_WR_V_I_MAIN_QOSGENERATOR_BASE (0x4AFF0D00) +#define IMX9_CAMERA__GPV__ISI_WR_V_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1100) +#define IMX9_CAMERA__GPV__ISI_WR_Y_I_MAIN_QOSGENERATOR_BASE (0x4AFF0D80) +#define IMX9_CAMERA__GPV__ISI_WR_Y_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1180) +#define IMX9_CAMERA__GPV__ISP_RD_0_I_MAIN_QOSGENERATOR_BASE (0x4AFF0E00) +#define IMX9_CAMERA__GPV__ISP_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1200) +#define IMX9_CAMERA__GPV__ISP_RD_1_I_MAIN_QOSGENERATOR_BASE (0x4AFF0E80) +#define IMX9_CAMERA__GPV__ISP_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1280) +#define IMX9_CAMERA__GPV__ISP_WR_0_I_MAIN_QOSGENERATOR_BASE (0x4AFF0F00) +#define IMX9_CAMERA__GPV__ISP_WR_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1300) +#define IMX9_CAMERA__GPV__ISP_WR_1_I_MAIN_QOSGENERATOR_BASE (0x4AFF0F80) +#define IMX9_CAMERA__GPV__ISP_WR_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4AFF1380) +#define IMX9_CAMERA__GPV__PROBE_ISI_MAIN_PROBE_BASE (0x4AFF0000) +#define IMX9_CAMERA__GPV__PROBE_ISI_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4AFF1400) +#define IMX9_CAMERA__GPV__PROBE_ISP_MAIN_PROBE_BASE (0x4AFF0400) +#define IMX9_CAMERA__GPV__PROBE_ISP_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4AFF1480) +#define IMX9_CAMERA__GPV__PROBE_SSI_FWD_MAIN_PROBE_BASE (0x4AFF0800) +#define IMX9_CAMERA__ISI_BASE (0x4AD50000) +#define IMX9_CAMERA__ISP__ALIAS_BASE (0x4AE02000) +#define IMX9_CAMERA__ISP__AUTOFOCUS_BASE (0x4AE01700) +#define IMX9_CAMERA__ISP__BNR_BASE (0x4AE00800) +#define IMX9_CAMERA__ISP__CAS_BASE (0x4AE01500) +#define IMX9_CAMERA__ISP__CCONVMED_BASE (0x4AE014C0) +#define IMX9_CAMERA__ISP__COLOR_TEMP_BASE (0x4AE00400) +#define IMX9_CAMERA__ISP__DEMOSAIC_BASE (0x4AE01180) +#define IMX9_CAMERA__ISP__DF_BASE (0x4AE01440) +#define IMX9_CAMERA__ISP__DRC_BASE (0x4AE01300) +#define IMX9_CAMERA__ISP__EE_BASE (0x4AE01480) +#define IMX9_CAMERA__ISP__GCM_BASE (0x4AE01600) +#define IMX9_CAMERA__ISP__HC_BASE (0x4AE000C0) +#define IMX9_CAMERA__ISP__HDR_DECOMPRESS0_BASE (0x4AE00100) +#define IMX9_CAMERA__ISP__HDR_DECOMPRESS1_BASE (0x4AE00180) +#define IMX9_CAMERA__ISP__HDR_MERGE_BASE (0x4AE00300) +#define IMX9_CAMERA__ISP__IDBG1_BASE (0x4AE00FC0) +#define IMX9_CAMERA__ISP__IDBG2_BASE (0x4AE01FC0) +#define IMX9_CAMERA__ISP__IR_COMPRESS_BASE (0x4AE00780) +#define IMX9_CAMERA__ISP__NR_BASE (0x4AE01400) +#define IMX9_CAMERA__ISP__OB_WB0_BASE (0x4AE00200) +#define IMX9_CAMERA__ISP__OB_WB1_BASE (0x4AE00240) +#define IMX9_CAMERA__ISP__OB_WB2_BASE (0x4AE00280) +#define IMX9_CAMERA__ISP__PACKETIZER_BASE (0x4AE01580) +#define IMX9_CAMERA__ISP__PIPE_CONF_BASE (0x4AE00000) +#define IMX9_CAMERA__ISP__RGBIR_BASE (0x4AE00600) +#define IMX9_CAMERA__ISP__RGB_TO_YUV_BASE (0x4AE011C0) +#define IMX9_CAMERA__ISP__STAT_BASE (0x4AE00700) +#define IMX9_CAMERA__ISP__VIGNETTING_BASE (0x4AE00900) +#define IMX9_CAMERA__MUI_A1__MUA_BASE (0x4AC60000) +#define IMX9_CAMERA__MUI_A2__MUA_BASE (0x4AC70000) +#define IMX9_CAMERA__MUI_A3__MUA_BASE (0x4AC80000) +#define IMX9_CAMERA__MUI_A4__MUA_BASE (0x4AC90000) +#define IMX9_CAMERA__MUI_A5__MUA_BASE (0x4ACA0000) +#define IMX9_CAMERA__MUI_A6__MUA_BASE (0x4ACB0000) +#define IMX9_CAMERA__MUI_A7__MUA_BASE (0x4ACC0000) +#define IMX9_CAMERA__MUI_A8__MUA_BASE (0x4ACD0000) +#define IMX9_CAMERA__MUI_A9__MUA_BASE (0x4ACE0000) +#define IMX9_CAMERA__OCRAM_MECC_BASE (0x4ADD0000) +#define IMX9_CAMERA__TCU_BASE (0x4AC00000) +#define IMX9_CAN1_BASE (0x443A0000) +#define IMX9_CAN2_BASE (0x425B0000) +#define IMX9_CAN3_BASE (0x42600000) +#define IMX9_CAN4_BASE (0x427C0000) +#define IMX9_CAN5_BASE (0x427D0000) +#define IMX9_CCM_CTRL_BASE (0x44450000) +#define IMX9_CCMSRCGPC__GPC__GPC_GLOBAL_BASE (0x44474800) +#define IMX9_CCMSRCGPC__SRC__SRC_CENTRAL_REG_BASE (0x44460000) +#define IMX9_CCMSRCGPC__SRC__XSPR_ANAMIX_BASE (0x44460400) +#define IMX9_CCMSRCGPC__SRC__XSPR_AONMIX_BASE (0x44460800) +#define IMX9_CCMSRCGPC__SRC__XSPR_AONMIX_MEM_BASE (0x44460900) +#define IMX9_CCMSRCGPC__SRC__XSPR_BBSMMIX_BASE (0x44460C00) +#define IMX9_CCMSRCGPC__SRC__XSPR_CAMERAMIX_BASE (0x44461000) +#define IMX9_CCMSRCGPC__SRC__XSPR_CAMERAMIX_MEM_BASE (0x44461100) +#define IMX9_CCMSRCGPC__SRC__XSPR_CCMSRCGPCMIX_BASE (0x44461400) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_BASE (0x44461800) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE0_MEM_BASE (0x44461900) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_BASE (0x44461C00) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE1_MEM_BASE (0x44461D00) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_BASE (0x44462000) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE2_MEM_BASE (0x44462100) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_BASE (0x44462400) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE3_MEM_BASE (0x44462500) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_BASE (0x44462800) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE4_MEM_BASE (0x44462900) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_BASE (0x44462C00) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_CORE5_MEM_BASE (0x44462D00) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_BASE (0x44463000) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM0_BASE (0x44463100) +#define IMX9_CCMSRCGPC__SRC__XSPR_CORTEXMIX_PLATFORM_MEM1_BASE (0x44463120) +#define IMX9_CCMSRCGPC__SRC__XSPR_DDRMIX_BASE (0x44463400) +#define IMX9_CCMSRCGPC__SRC__XSPR_DDRMIX_MEM_BASE (0x44463500) +#define IMX9_CCMSRCGPC__SRC__XSPR_DISPLAYMIX_BASE (0x44463800) +#define IMX9_CCMSRCGPC__SRC__XSPR_DISPLAYMIX_MEM_BASE (0x44463900) +#define IMX9_CCMSRCGPC__SRC__XSPR_GPUMIX_BASE (0x44463C00) +#define IMX9_CCMSRCGPC__SRC__XSPR_GPUMIX_MEM_BASE (0x44463D00) +#define IMX9_CCMSRCGPC__SRC__XSPR_HSIOMIX_MEM_BASE (0x44464100) +#define IMX9_CCMSRCGPC__SRC__XSPR_HSIOMIX_TOP_BASE (0x44464000) +#define IMX9_CCMSRCGPC__SRC__XSPR_HSIOMIX_WAON_BASE (0x44464400) +#define IMX9_CCMSRCGPC__SRC__XSPR_M7MIX_BASE (0x44464800) +#define IMX9_CCMSRCGPC__SRC__XSPR_M7MIX_MEM_BASE (0x44464900) +#define IMX9_CCMSRCGPC__SRC__XSPR_NETCMIX_BASE (0x44464C00) +#define IMX9_CCMSRCGPC__SRC__XSPR_NETCMIX_MEM_BASE (0x44464D00) +#define IMX9_CCMSRCGPC__SRC__XSPR_NOCMIX_BASE (0x44465000) +#define IMX9_CCMSRCGPC__SRC__XSPR_NOCMIX_MEM0_BASE (0x44465100) +#define IMX9_CCMSRCGPC__SRC__XSPR_NOCMIX_MEM1_BASE (0x44465120) +#define IMX9_CCMSRCGPC__SRC__XSPR_NPUMIX_BASE (0x44465400) +#define IMX9_CCMSRCGPC__SRC__XSPR_NPUMIX_MEM_BASE (0x44465500) +#define IMX9_CCMSRCGPC__SRC__XSPR_VPUMIX_BASE (0x44465800) +#define IMX9_CCMSRCGPC__SRC__XSPR_VPUMIX_MEM_BASE (0x44465900) +#define IMX9_CCMSRCGPC__SRC__XSPR_WAKEUPMIX_BASE (0x44465C00) +#define IMX9_CCMSRCGPC__SRC__XSPR_WAKEUPMIX_MEM_BASE (0x44465D00) +#define IMX9_CCMSRCGPC__TCU_BASE (0x444D0000) +#define IMX9_CORTEXA__FRACT_PLL_ARMPLL_BASE (0x44481600) +#define IMX9_CORTEXA__TCU_BASE (0x4A400000) +#define IMX9_DDRC_BASE (0x4E080000) +#define IMX9_DDRC__BLK_CTRL_DDRMIX_BASE (0x4E010000) +#define IMX9_DDRC__CMU_1_BASE (0x4E060000) +#define IMX9_DDRC__CMU_2_BASE (0x4E070000) +#define IMX9_DDRC__FRACT_PLL_BASE (0x44481700) +#define IMX9_DDRC__LSTCU_BASE (0x4E050000) +#define IMX9_DDRC__TCU_BASE (0x4E000000) +#define IMX9_DISPLAY__BLK_CTRL_DISPLAYMIX_BASE (0x4B010000) +#define IMX9_DISPLAY__FRACT_PLL_BASE (0x44481900) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_QOSGENERATOR_BASE (0x4B7E0800) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0A00) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_QOSGENERATOR_BASE (0x4B7E0880) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0A80) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_QOSGENERATOR_BASE (0x4B7E0900) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0B00) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_QOSGENERATOR_BASE (0x4B7E0980) +#define IMX9_DISPLAY__GPV__I_SEERIS_2D_BLITTER_STORE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0B80) +#define IMX9_DISPLAY__GPV__I_SEERIS_CMD_SEQ_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0C00) +#define IMX9_DISPLAY__GPV__I_SEERIS_CMD_SEQ_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0C80) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_0_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0D00) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_1_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0D80) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_2_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0E00) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_3_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0E80) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_4_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0F00) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_5_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E0F80) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_6_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1000) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_7_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1080) +#define IMX9_DISPLAY__GPV__I_SEERIS_DISPLAY_CTRL_FU_RD_8_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4B7E1100) +#define IMX9_DISPLAY__GPV__PROBE1_MAIN_PROBE_BASE (0x4B7E0000) +#define IMX9_DISPLAY__GPV__PROBE1_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4B7E1180) +#define IMX9_DISPLAY__GPV__PROBE_MAIN_PROBE_BASE (0x4B7E0400) +#define IMX9_DISPLAY__OCRAM_MECC_BASE (0x4B0F0000) +#define IMX9_DISPLAY__PIXEL_INTERLEAVER1_BASE (0x4B0D0000) +#define IMX9_DISPLAY__PIXEL_MAPPER_BASE (0x4B000000) +#define IMX9_DISPLAY_SEERIS_BASE (0x4B400000) +#define IMX9_DISPLAY__SEERIS__BLITBLEND_BASE (0x4B470000) +#define IMX9_DISPLAY__SEERIS__CLUT_clut_1_BASE (0x4B450400) +#define IMX9_DISPLAY__SEERIS__CLUT_clut_BASE (0x4B450000) +#define IMX9_DISPLAY__SEERIS__CMDSEQ_cmdseq_1_BASE (0x4B410100) +#define IMX9_DISPLAY__SEERIS__CMDSEQ_cmdseq_2_BASE (0x4B410180) +#define IMX9_DISPLAY__SEERIS__CMDSEQ_cmdseq_BASE (0x4B410000) +#define IMX9_DISPLAY__SEERIS__CONSTFRAME_1_BASE (0x4B500000) +#define IMX9_DISPLAY__SEERIS__CONSTFRAME_2_BASE (0x4B530000) +#define IMX9_DISPLAY__SEERIS__CONSTFRAME_3_BASE (0x4B540000) +#define IMX9_DISPLAY__SEERIS__CONSTFRAME_BASE (0x4B4F0000) +#define IMX9_DISPLAY__SEERIS__DITHER_1_BASE (0x4B770000) +#define IMX9_DISPLAY__SEERIS__DITHER_BASE (0x4B710000) +#define IMX9_DISPLAY__SEERIS__DOMAINBLEND_1_BASE (0x4B720000) +#define IMX9_DISPLAY__SEERIS__DOMAINBLEND_BASE (0x4B6A0000) +#define IMX9_DISPLAY__SEERIS__EXTDST_1_BASE (0x4B520000) +#define IMX9_DISPLAY__SEERIS__EXTDST_2_BASE (0x4B550000) +#define IMX9_DISPLAY__SEERIS__EXTDST_3_BASE (0x4B560000) +#define IMX9_DISPLAY__SEERIS__EXTDST_BASE (0x4B510000) +#define IMX9_DISPLAY__SEERIS__FETCHDECODE_1_BASE (0x4B490028) +#define IMX9_DISPLAY__SEERIS__FETCHDECODE_2_BASE (0x4B490060) +#define IMX9_DISPLAY__SEERIS__FETCHDECODE_3_BASE (0x4B490088) +#define IMX9_DISPLAY__SEERIS__FETCHDECODE_4_BASE (0x4B490098) +#define IMX9_DISPLAY__SEERIS__FETCHDECODE_5_BASE (0x4B490400) +#define IMX9_DISPLAY__SEERIS__FETCHDECODE_BASE (0x4B490000) +#define IMX9_DISPLAY__SEERIS__FETCHECO_10_BASE (0x4B630000) +#define IMX9_DISPLAY__SEERIS__FETCHECO_11_BASE (0x4B630010) +#define IMX9_DISPLAY__SEERIS__FETCHECO_12_BASE (0x4B630048) +#define IMX9_DISPLAY__SEERIS__FETCHECO_13_BASE (0x4B630060) +#define IMX9_DISPLAY__SEERIS__FETCHECO_14_BASE (0x4B630068) +#define IMX9_DISPLAY__SEERIS__FETCHECO_15_BASE (0x4B650000) +#define IMX9_DISPLAY__SEERIS__FETCHECO_16_BASE (0x4B650010) +#define IMX9_DISPLAY__SEERIS__FETCHECO_17_BASE (0x4B650048) +#define IMX9_DISPLAY__SEERIS__FETCHECO_18_BASE (0x4B650060) +#define IMX9_DISPLAY__SEERIS__FETCHECO_19_BASE (0x4B650068) +#define IMX9_DISPLAY__SEERIS__FETCHECO_1_BASE (0x4B4A0010) +#define IMX9_DISPLAY__SEERIS__FETCHECO_2_BASE (0x4B4A0048) +#define IMX9_DISPLAY__SEERIS__FETCHECO_3_BASE (0x4B4A0060) +#define IMX9_DISPLAY__SEERIS__FETCHECO_4_BASE (0x4B4A0068) +#define IMX9_DISPLAY__SEERIS__FETCHECO_5_BASE (0x4B610000) +#define IMX9_DISPLAY__SEERIS__FETCHECO_6_BASE (0x4B610010) +#define IMX9_DISPLAY__SEERIS__FETCHECO_7_BASE (0x4B610048) +#define IMX9_DISPLAY__SEERIS__FETCHECO_8_BASE (0x4B610060) +#define IMX9_DISPLAY__SEERIS__FETCHECO_9_BASE (0x4B610068) +#define IMX9_DISPLAY__SEERIS__FETCHECO_BASE (0x4B4A0000) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_10_BASE (0x4B5D01F8) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_11_BASE (0x4B5D0200) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_12_BASE (0x4B5D0400) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_13_BASE (0x4B5E0000) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_14_BASE (0x4B5E0018) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_15_BASE (0x4B5E0050) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_16_BASE (0x4B5E0088) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_17_BASE (0x4B5E00C0) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_18_BASE (0x4B5E00F8) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_19_BASE (0x4B5E0130) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_1_BASE (0x4B5D0018) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_20_BASE (0x4B5E0168) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_21_BASE (0x4B5E01A0) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_22_BASE (0x4B5E01D8) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_23_BASE (0x4B5E01F8) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_24_BASE (0x4B5E0200) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_25_BASE (0x4B5E0400) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_2_BASE (0x4B5D0050) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_3_BASE (0x4B5D0088) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_4_BASE (0x4B5D00C0) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_5_BASE (0x4B5D00F8) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_6_BASE (0x4B5D0130) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_7_BASE (0x4B5D0168) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_8_BASE (0x4B5D01A0) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_9_BASE (0x4B5D01D8) +#define IMX9_DISPLAY__SEERIS__FETCHLAYER_BASE (0x4B5D0000) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_10_BASE (0x4B484000) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_1_BASE (0x4B480020) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_2_BASE (0x4B480058) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_3_BASE (0x4B4800A0) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_4_BASE (0x4B4800B0) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_5_BASE (0x4B480100) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_6_BASE (0x4B480200) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_7_BASE (0x4B480400) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_8_BASE (0x4B480600) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_9_BASE (0x4B482000) +#define IMX9_DISPLAY__SEERIS__FETCHROT_fetchrot_BASE (0x4B480000) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_10_BASE (0x4B620000) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_11_BASE (0x4B620028) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_12_BASE (0x4B620060) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_13_BASE (0x4B620078) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_14_BASE (0x4B620088) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_15_BASE (0x4B640000) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_16_BASE (0x4B640028) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_17_BASE (0x4B640060) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_18_BASE (0x4B640078) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_19_BASE (0x4B640088) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_1_BASE (0x4B5F0028) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_2_BASE (0x4B5F0060) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_3_BASE (0x4B5F0078) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_4_BASE (0x4B5F0088) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_5_BASE (0x4B600000) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_6_BASE (0x4B600028) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_7_BASE (0x4B600060) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_8_BASE (0x4B600078) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_9_BASE (0x4B600088) +#define IMX9_DISPLAY__SEERIS__FETCHYUV_BASE (0x4B5F0000) +#define IMX9_DISPLAY__SEERIS__FILTER_BASE (0x4B4D0000) +#define IMX9_DISPLAY__SEERIS__FRAMEGEN_1_BASE (0x4B730000) +#define IMX9_DISPLAY__SEERIS__FRAMEGEN_BASE (0x4B6B0000) +#define IMX9_DISPLAY__SEERIS__HSCALER_1_BASE (0x4B670000) +#define IMX9_DISPLAY__SEERIS__HSCALER_BASE (0x4B4B0000) +#define IMX9_DISPLAY__SEERIS__IDHASH_1_BASE (0x4B6C1000) +#define IMX9_DISPLAY__SEERIS__IDHASH_BASE (0x4B6C0000) +#define IMX9_DISPLAY__SEERIS__LAYERBLEND_1_BASE (0x4B580000) +#define IMX9_DISPLAY__SEERIS__LAYERBLEND_2_BASE (0x4B590000) +#define IMX9_DISPLAY__SEERIS__LAYERBLEND_3_BASE (0x4B5A0000) +#define IMX9_DISPLAY__SEERIS__LAYERBLEND_4_BASE (0x4B5B0000) +#define IMX9_DISPLAY__SEERIS__LAYERBLEND_5_BASE (0x4B5C0000) +#define IMX9_DISPLAY__SEERIS__LAYERBLEND_BASE (0x4B570000) +#define IMX9_DISPLAY__SEERIS__LUT3D_1_BASE (0x4B702000) +#define IMX9_DISPLAY__SEERIS__LUT3D_2_BASE (0x4B750000) +#define IMX9_DISPLAY__SEERIS__LUT3D_3_BASE (0x4B752000) +#define IMX9_DISPLAY__SEERIS__LUT3D_BASE (0x4B700000) +#define IMX9_DISPLAY__SEERIS__MATRIX_1_BASE (0x4B660000) +#define IMX9_DISPLAY__SEERIS__MATRIX_BASE (0x4B460000) +#define IMX9_DISPLAY__SEERIS__MATRIXL_1_BASE (0x4B6F0030) +#define IMX9_DISPLAY__SEERIS__MATRIXL_2_BASE (0x4B760000) +#define IMX9_DISPLAY__SEERIS__MATRIXL_3_BASE (0x4B760030) +#define IMX9_DISPLAY__SEERIS__MATRIXL_BASE (0x4B6F0000) +#define IMX9_DISPLAY__SEERIS__ROP_BASE (0x4B440000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_BLITBLEND9CFG_BASE (0x4B471000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CLUT9CFG_BASE (0x4B451000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CMDSEQMASK_BASE (0x4B403000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME0CFG_BASE (0x4B4F1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME1CFG_BASE (0x4B531000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME4CFG_BASE (0x4B501000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_CONSTFRAME5CFG_BASE (0x4B541000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_DITHER0CFG_BASE (0x4B711000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_DITHER1CFG_BASE (0x4B771020) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_DOMAINMASK_BASE (0x4B402000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST0CFG_BASE (0x4B511000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST1CFG_BASE (0x4B551000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST4CFG_BASE (0x4B521000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_EXTDST5CFG_BASE (0x4B561000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHDECODE9CFG_BASE (0x4B491000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO0CFG_BASE (0x4B611000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO1CFG_BASE (0x4B631000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO2CFG_BASE (0x4B651000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHECO9CFG_BASE (0x4B4A1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHLAYER0CFG_BASE (0x4B5D1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHLAYER1CFG_BASE (0x4B5E1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHROT9CFG_BASE (0x4B486000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV0CFG_BASE (0x4B601000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV1CFG_BASE (0x4B621000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV2CFG_BASE (0x4B641000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FETCHYUV3CFG_BASE (0x4B5F1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_FILTER9CFG_BASE (0x4B4D1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_GENERALPURPOSE_BASE (0x4B412000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_HSCALER4CFG_BASE (0x4B671000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_HSCALER9CFG_BASE (0x4B4B1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IDHASH0CFG_BASE (0x4B6C3000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_1_BASE (0x4B411000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_2_BASE (0x4B431000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_3_BASE (0x4B781000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_4_BASE (0x4B791000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_5_BASE (0x4B7A1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_6_BASE (0x4B7B1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_IRQ_BASE (0x4B401000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND1CFG_BASE (0x4B571000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND2CFG_BASE (0x4B581000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND3CFG_BASE (0x4B591000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND4CFG_BASE (0x4B5A1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND5CFG_BASE (0x4B5B1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_LAYERBLEND6CFG_BASE (0x4B5C1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_MATRIX4CFG_BASE (0x4B661000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_MATRIX9CFG_BASE (0x4B461000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_ROP9CFG_BASE (0x4B441000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_SIG0CFG_BASE (0x4B6D1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_SIG1CFG_BASE (0x4B741020) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_SIG2CFG_BASE (0x4B6E1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_STORE9CFG_BASE (0x4B4E1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_VSCALER4CFG_BASE (0x4B681000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_VSCALER9CFG_BASE (0x4B4C1000) +#define IMX9_DISPLAY__SEERIS__SEERIS_MDR5_XPC_BASE (0x4B420000) +#define IMX9_DISPLAY__SEERIS__SIG_1_BASE (0x4B6D0400) +#define IMX9_DISPLAY__SEERIS__SIG_2_BASE (0x4B6E0000) +#define IMX9_DISPLAY__SEERIS__SIG_3_BASE (0x4B6E0400) +#define IMX9_DISPLAY__SEERIS__SIG_4_BASE (0x4B740000) +#define IMX9_DISPLAY__SEERIS__SIG_5_BASE (0x4B740400) +#define IMX9_DISPLAY__SEERIS__SIG_BASE (0x4B6D0000) +#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_1_BASE (0x4B4E0038) +#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_2_BASE (0x4B4E0048) +#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_3_BASE (0x4B4E0070) +#define IMX9_DISPLAY__SEERIS__STORE_PLANAR_BASE (0x4B4E0000) +#define IMX9_DISPLAY__SEERIS__VSCALER_1_BASE (0x4B680000) +#define IMX9_DISPLAY__SEERIS__VSCALER_BASE (0x4B4C0000) +#define IMX9_DISPLAY__TCU_BASE (0x4B000000) +#define IMX9_DMA3_BASE (0x44000000) +#define IMX9_DPU_IRQSTEER_BASE (0x4B0B0000) +#define IMX9_EDMA5_2_BASE (0x42000000) +#define IMX9_EDMA5_3_BASE (0x42210000) +#define IMX9_EDMA5_4_BASE (0x4AE10000) +#define IMX9_EMDIO0_PCI_HDR_TYPE0_BASE (0x4CB00000) +#define IMX9_EMDIO_BASE_BASE (0x4CCE0000) +#define IMX9_EMDIO_GLOBAL_BASE (0x4CCF0000) +#define IMX9_ENETC0_BASE_BASE (0x4CC10000) +#define IMX9_ENETC0_COMMON_BASE (0x4CC11000) +#define IMX9_ENETC0_ETH_MAC_PORT_BASE (0x4CC15000) +#define IMX9_ENETC0_GLOBAL_BASE (0x4CC20000) +#define IMX9_ENETC0_PCI_HDR_TYPE0_BASE (0x4CA00000) +#define IMX9_ENETC0_PORT_BASE (0x4CC14000) +#define IMX9_ENETC0_PSI_BASE (0x4CC00000) +#define IMX9_ENETC1_BASE_BASE (0x4CC50000) +#define IMX9_ENETC1_COMMON_BASE (0x4CC51000) +#define IMX9_ENETC1_ETH_MAC_PORT_BASE (0x4CC55000) +#define IMX9_ENETC1_GLOBAL_BASE (0x4CC60000) +#define IMX9_ENETC1_PCI_HDR_TYPE0_BASE (0x4CA40000) +#define IMX9_ENETC1_PORT_BASE (0x4CC54000) +#define IMX9_ENETC1_PSI_BASE (0x4CC40000) +#define IMX9_ENETC2_BASE_BASE (0x4CC90000) +#define IMX9_ENETC2_COMMON_BASE (0x4CC91000) +#define IMX9_ENETC2_ETH_MAC_PORT_BASE (0x4CC95000) +#define IMX9_ENETC2_GLOBAL_BASE (0x4CCA0000) +#define IMX9_ENETC2_PCI_HDR_TYPE0_BASE (0x4CA80000) +#define IMX9_ENETC2_PORT_BASE (0x4CC94000) +#define IMX9_ENETC2_PSI_BASE (0x4CC80000) +#define IMX9_ENETC_VSI0_BASE (0x4CD20000) +#define IMX9_ENETC_VSI1_BASE (0x4CD30000) +#define IMX9_ENETC_VSI2_BASE (0x4CD40000) +#define IMX9_ENETC_VSI3_BASE (0x4CD50000) +#define IMX9_ENETC_VSI4_BASE (0x4CD60000) +#define IMX9_ENETC_VSI5_BASE (0x4CD70000) +#define IMX9_ENET_PHY_MAC_ADAPTER_BASE (0x3E0000) +#define IMX9_ENET_PHY_PMA_MMD_BASE (0x20000) +#define IMX9_ENET_PHY_VS_MII_MMD_BASE (0x3E0000) +#define IMX9_ENET_PHY_VS_MMD1_BASE (0x3C0000) +#define IMX9_ENET_PHY_XS_PCS_MMD_BASE (0x60000) +#define IMX9_FLEXIO1_BASE (0x425C0000) +#define IMX9_FLEXIO2_BASE (0x425D0000) +#define IMX9_FLEXSPI_BASE (0x425E0000) +#define IMX9_GPC_CTRL_CA55_0_BASE (0x44471000) +#define IMX9_GPC_CTRL_CA55_1_BASE (0x44471800) +#define IMX9_GPC_CTRL_CA55_2_BASE (0x44472000) +#define IMX9_GPC_CTRL_CA55_3_BASE (0x44472800) +#define IMX9_GPC_CTRL_CA55_4_BASE (0x44473000) +#define IMX9_GPC_CTRL_CA55_5_BASE (0x44473800) +#define IMX9_GPC_CTRL_CA55_CLUSTER_BASE (0x44474000) +#define IMX9_GPC_CTRL_CM33_BASE (0x44470000) +#define IMX9_GPC_CTRL_CM7_BASE (0x44470800) +#define IMX9_GPIO1_BASE (0x47400000) +#define IMX9_GPIO2_BASE (0x43810000) +#define IMX9_GPIO3_BASE (0x43820000) +#define IMX9_GPIO4_BASE (0x43840000) +#define IMX9_GPIO5_BASE (0x43850000) +#define IMX9_GPU__BLK_CTRL_GPUMIX_BASE (0x4D810000) +#define IMX9_GPU__REG__GPU_MALI_DOORBELLS_BASE (0x4D980000) +#define IMX9_GPU__REG__GPU_MALI_GPU_REGISTERS_BASE (0x4D900000) +#define IMX9_GPU__REG__GPU_MALI_IPA_CONTROL_BASE (0x4D940000) +#define IMX9_GPU__REG__GPU_MALI_USER_BASE (0x4D910000) +#define IMX9_GPU__TCU_BASE (0x4D800000) +#define IMX9_HSIO__BLK_CTRL_HSIOMIX_BASE (0x4C010000) +#define IMX9_HSIO__GHZ_LN_PLL_BASE (0x44481800) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_OBSERVER_SSI_MASTER_ERROR_MAIN_ERRORLOGGER_0_BASE (0x980C0000) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0480) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0400) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0380) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PCIE2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0300) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_PROBE_BASE (0x980C0800) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_PROBE_TRANSACTION_MAIN_TRANSACTIONSTATPROFILER_BASE (0x980C0280) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0200) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB1_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0180) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0100) +#define IMX9_HSIO__GPV__SSI_AXI_SLAVE_RD_USB2_AXI_SLAVE_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x980C0080) +#define IMX9_HSIO__PCIE1__PCIE_DMA_IATU_BASE (0x4C360000) +#define IMX9_HSIO__PCIE1__PCIE_EP_BASE (0x4C300000) +#define IMX9_HSIO__PCIE1__PCIE_RC_BASE (0x4C300000) +#define IMX9_HSIO__PCIE1__PCIE_SHADOW_EP_BASE (0x4C320000) +#define IMX9_HSIO__PCIE1__SERDES_SS_BASE (0x4C340000) +#define IMX9_HSIO__PCIE2__PCIE_DMA_IATU_BASE (0x4C3E0000) +#define IMX9_HSIO__PCIE2__PCIE_EP_BASE (0x4C380000) +#define IMX9_HSIO__PCIE2__PCIE_RC_BASE (0x4C380000) +#define IMX9_HSIO__PCIE2__PCIE_SHADOW_EP_BASE (0x4C3A0000) +#define IMX9_HSIO__PCIE2__SERDES_SS_BASE (0x4C3C0000) +#define IMX9_HSIO__TCU_BASE (0x4C000000) +#define IMX9_HSIO__USB_3_01__GLUE_BASE (0x4C1F0000) +#define IMX9_HSIO__USB_3_01__USB3_BASE (0x4C100000) +#define IMX9_HSIO__USB_3_0_PHY__TCA_BASE (0x4C1FC000) +#define IMX9_I3C1_BASE (0x44330000) +#define IMX9_I3C2_BASE (0x42520000) +#define IMX9_IOMUXC_BASE (0x443C0000) +#define IMX9_IRQSTEER_BASE (0x44680000) +#define IMX9_LPI2C1_BASE (0x44340000) +#define IMX9_LPI2C2_BASE (0x44350000) +#define IMX9_LPI2C3_BASE (0x42530000) +#define IMX9_LPI2C4_BASE (0x42540000) +#define IMX9_LPI2C5_BASE (0x426B0000) +#define IMX9_LPI2C6_BASE (0x426C0000) +#define IMX9_LPI2C7_BASE (0x426D0000) +#define IMX9_LPI2C8_BASE (0x426E0000) +#define IMX9_LPIT1_BASE (0x442F0000) +#define IMX9_LPIT2_BASE (0x424C0000) +#define IMX9_LPSPI1_BASE (0x44360000) +#define IMX9_LPSPI2_BASE (0x44370000) +#define IMX9_LPSPI3_BASE (0x42550000) +#define IMX9_LPSPI4_BASE (0x42560000) +#define IMX9_LPSPI5_BASE (0x426F0000) +#define IMX9_LPSPI6_BASE (0x42700000) +#define IMX9_LPSPI7_BASE (0x42710000) +#define IMX9_LPSPI8_BASE (0x42720000) +#define IMX9_LPTMR1_BASE (0x44300000) +#define IMX9_LPTMR2_BASE (0x424D0000) +#define IMX9_LPUART1_BASE (0x44380000) +#define IMX9_LPUART2_BASE (0x44390000) +#define IMX9_LPUART3_BASE (0x42570000) +#define IMX9_LPUART4_BASE (0x42580000) +#define IMX9_LPUART5_BASE (0x42590000) +#define IMX9_LPUART6_BASE (0x425A0000) +#define IMX9_LPUART7_BASE (0x42690000) +#define IMX9_LPUART8_BASE (0x426A0000) +#define IMX9_LVDS_BASE (0x4B0C0000) +#define IMX9_M33_CACHE_CTRLPC_BASE (0x44400000) +#define IMX9_M33_CACHE_CTRLPS_BASE (0x44400800) +#define IMX9_M7__A7_APB_MCM1_BASE (0x4A0A0000) +#define IMX9_M7__CMU_M0_BASE (0x4A080000) +#define IMX9_M7__CMU_M1_BASE (0x4A090000) +#define IMX9_M7__EIM_BASE (0x4A060000) +#define IMX9_M7__ERM_BASE (0x4A070000) +#define IMX9_M7__LSTCU_M7MIX_BASE (0x4A050000) +#define IMX9_M7__TCU_BASE (0x4A000000) +#define IMX9_MIPI_CSI2_BASE (0x4AD30000) +#define IMX9_MIPI_DSI_BASE (0x4ACF0000) +#define IMX9_MSGINTR1_BASE (0x44690000) +#define IMX9_MSGINTR2_BASE (0x446A0000) +#define IMX9_MU5_MUA_BASE (0x44610000) +#define IMX9_MU7_MUB_BASE (0x42440000) +#define IMX9_MU8_MUB_BASE (0x42740000) +#define IMX9_NETC__IEPRC_1__IEPRC_B0_EC_F0_PCI_HDR_TYPE0_BASE (0x4CA08000) +#define IMX9_NETC__IEPRC_1__IEPRC_B1_EC_F0_PCI_HDR_TYPE0_BASE (0x4CB08000) +#define IMX9_NETC__IEPRC_1__IEPRC_IERB_BASE (0x4C8A0000) +#define IMX9_NETC__IEPRC_1__IEPRC_PRB_BASE (0x4C8B0000) +#define IMX9_NETC_IERB_BASE (0x4CDE0000) +#define IMX9_NETC_PRIV_BASE (0x4CDF0000) +#define IMX9_NETC__TCU_BASE (0x4C800000) +#define IMX9_NETC_VF1_PCI_HDR_TYPE0_BASE (0x4CA10000) +#define IMX9_NETC_VF2_PCI_HDR_TYPE0_BASE (0x4CA20000) +#define IMX9_NETC_VF3_PCI_HDR_TYPE0_BASE (0x4CA50000) +#define IMX9_NETC_VF4_PCI_HDR_TYPE0_BASE (0x4CA60000) +#define IMX9_NETC_VF5_PCI_HDR_TYPE0_BASE (0x4CA90000) +#define IMX9_NETC_VF6_PCI_HDR_TYPE0_BASE (0x4CAA0000) +#define IMX9_NOC__BLK_CTRL_NOCMIX_BASE (0x49000000) +#define IMX9_NOC__CMU_N0_BASE (0x49070000) +#define IMX9_NOC__CMU_N1_BASE (0x49080000) +#define IMX9_NOC__EIMN_BASE (0x49270000) +#define IMX9_NOC__GIC__GICA_BASE (0x48010000) +#define IMX9_NOC__GIC__GICDA_BASE (0x48120000) +#define IMX9_NOC__GIC__GICD_BASE (0x48000000) +#define IMX9_NOC__GIC__GICP_BASE (0x48030000) +#define IMX9_NOC__GIC__GICRLPI0_BASE (0x48060000) +#define IMX9_NOC__GIC__GICRLPI1_BASE (0x48080000) +#define IMX9_NOC__GIC__GICRLPI2_BASE (0x480A0000) +#define IMX9_NOC__GIC__GICRLPI3_BASE (0x480C0000) +#define IMX9_NOC__GIC__GICRLPI4_BASE (0x480E0000) +#define IMX9_NOC__GIC__GICRLPI5_BASE (0x48100000) +#define IMX9_NOC__GIC__GICRSGI0_BASE (0x48070000) +#define IMX9_NOC__GIC__GICRSGI1_BASE (0x48090000) +#define IMX9_NOC__GIC__GICRSGI2_BASE (0x480B0000) +#define IMX9_NOC__GIC__GICRSGI3_BASE (0x480D0000) +#define IMX9_NOC__GIC__GICRSGI4_BASE (0x480F0000) +#define IMX9_NOC__GIC__GICRSGI5_BASE (0x48110000) +#define IMX9_NOC__GIC__GICT_BASE (0x48020000) +#define IMX9_NOC__GIC__GITS0_BASE (0x48040000) +#define IMX9_NOC__GIC__GITS0TRANSLATER_BASE (0x48050000) +#define IMX9_NOC__GPV__ALWAYS_ON_MAIN_RESILIENCEFAULTCONTROLLER_BASE (0x49063080) +#define IMX9_NOC__GPV__M_E_0_RD_I_MAIN_QOSGENERATOR_BASE (0x49062400) +#define IMX9_NOC__GPV__M_E_0_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063100) +#define IMX9_NOC__GPV__M_E_0_WR_I_MAIN_QOSGENERATOR_BASE (0x49062480) +#define IMX9_NOC__GPV__M_E_0_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063180) +#define IMX9_NOC__GPV__M_E_10_RD_I_MAIN_QOSGENERATOR_BASE (0x49062E80) +#define IMX9_NOC__GPV__M_E_10_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063780) +#define IMX9_NOC__GPV__M_E_10_WR_I_MAIN_QOSGENERATOR_BASE (0x49062F00) +#define IMX9_NOC__GPV__M_E_10_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063800) +#define IMX9_NOC__GPV__M_E_11_RD_I_MAIN_QOSGENERATOR_BASE (0x49062F80) +#define IMX9_NOC__GPV__M_E_11_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063880) +#define IMX9_NOC__GPV__M_E_11_WR_I_MAIN_QOSGENERATOR_BASE (0x49063000) +#define IMX9_NOC__GPV__M_E_11_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063900) +#define IMX9_NOC__GPV__M_E_1A_RD_I_MAIN_QOSGENERATOR_BASE (0x49062500) +#define IMX9_NOC__GPV__M_E_1A_WR_I_MAIN_QOSGENERATOR_BASE (0x49062580) +#define IMX9_NOC__GPV__M_E_1B_RD_I_MAIN_QOSGENERATOR_BASE (0x49062600) +#define IMX9_NOC__GPV__M_E_1B_WR_I_MAIN_QOSGENERATOR_BASE (0x49062680) +#define IMX9_NOC__GPV__M_E_3_RD_I_MAIN_QOSGENERATOR_BASE (0x49062800) +#define IMX9_NOC__GPV__M_E_3_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063200) +#define IMX9_NOC__GPV__M_E_3_WR_I_MAIN_QOSGENERATOR_BASE (0x49062880) +#define IMX9_NOC__GPV__M_E_3_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063280) +#define IMX9_NOC__GPV__M_E_4_RD_I_MAIN_QOSGENERATOR_BASE (0x49062900) +#define IMX9_NOC__GPV__M_E_4_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063300) +#define IMX9_NOC__GPV__M_E_4_WR_I_MAIN_QOSGENERATOR_BASE (0x49062980) +#define IMX9_NOC__GPV__M_E_4_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063380) +#define IMX9_NOC__GPV__M_E_5_RD_I_MAIN_QOSGENERATOR_BASE (0x49062A00) +#define IMX9_NOC__GPV__M_E_5_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063400) +#define IMX9_NOC__GPV__M_E_5_WR_I_MAIN_QOSGENERATOR_BASE (0x49062A80) +#define IMX9_NOC__GPV__M_E_5_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063480) +#define IMX9_NOC__GPV__M_E_6_RD_I_MAIN_QOSGENERATOR_BASE (0x49062B00) +#define IMX9_NOC__GPV__M_E_6_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063500) +#define IMX9_NOC__GPV__M_E_7_RD_I_MAIN_QOSGENERATOR_BASE (0x49062B80) +#define IMX9_NOC__GPV__M_E_7_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063580) +#define IMX9_NOC__GPV__M_E_7_WR_I_MAIN_QOSGENERATOR_BASE (0x49062C00) +#define IMX9_NOC__GPV__M_E_7_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063600) +#define IMX9_NOC__GPV__M_E_8_RD_I_MAIN_QOSGENERATOR_BASE (0x49062C80) +#define IMX9_NOC__GPV__M_E_8_WR_I_MAIN_QOSGENERATOR_BASE (0x49062D00) +#define IMX9_NOC__GPV__M_E_9_RD_I_MAIN_QOSGENERATOR_BASE (0x49062D80) +#define IMX9_NOC__GPV__M_E_9_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063680) +#define IMX9_NOC__GPV__M_E_9_WR_I_MAIN_QOSGENERATOR_BASE (0x49062E00) +#define IMX9_NOC__GPV__M_E_9_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x49063700) +#define IMX9_NOC__GPV__PROBE_M_E_0_MAIN_PROBE_BASE (0x49060000) +#define IMX9_NOC__GPV__PROBE_M_E_0_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063980) +#define IMX9_NOC__GPV__PROBE_M_E_10_MAIN_PROBE_BASE (0x49061C00) +#define IMX9_NOC__GPV__PROBE_M_E_10_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063D00) +#define IMX9_NOC__GPV__PROBE_M_E_11_MAIN_PROBE_BASE (0x49062000) +#define IMX9_NOC__GPV__PROBE_M_E_11_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063D80) +#define IMX9_NOC__GPV__PROBE_M_E_3_MAIN_PROBE_BASE (0x49060400) +#define IMX9_NOC__GPV__PROBE_M_E_3_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063A00) +#define IMX9_NOC__GPV__PROBE_M_E_4_MAIN_PROBE_BASE (0x49060800) +#define IMX9_NOC__GPV__PROBE_M_E_4_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063A80) +#define IMX9_NOC__GPV__PROBE_M_E_5_MAIN_PROBE_BASE (0x49060C00) +#define IMX9_NOC__GPV__PROBE_M_E_5_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063B00) +#define IMX9_NOC__GPV__PROBE_M_E_6_MAIN_PROBE_BASE (0x49061000) +#define IMX9_NOC__GPV__PROBE_M_E_6_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063B80) +#define IMX9_NOC__GPV__PROBE_M_E_7_MAIN_PROBE_BASE (0x49061400) +#define IMX9_NOC__GPV__PROBE_M_E_7_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063C00) +#define IMX9_NOC__GPV__PROBE_M_E_9_MAIN_PROBE_BASE (0x49061800) +#define IMX9_NOC__GPV__PROBE_M_E_9_MAIN_TRANSACTIONSTATPROFILER_BASE (0x49063C80) +#define IMX9_NOC__LSTCUN_BASE (0x490B0000) +#define IMX9_NOC__MMU_TBU_TCU__TBU0_BASE (0x49110000) +#define IMX9_NOC__MMU_TBU_TCU__TBU10_BASE (0x49230000) +#define IMX9_NOC__MMU_TBU_TCU__TBU11_BASE (0x49250000) +#define IMX9_NOC__MMU_TBU_TCU__TBU1_BASE (0x49130000) +#define IMX9_NOC__MMU_TBU_TCU__TBU2_BASE (0x49150000) +#define IMX9_NOC__MMU_TBU_TCU__TBU3_BASE (0x49170000) +#define IMX9_NOC__MMU_TBU_TCU__TBU4_BASE (0x49190000) +#define IMX9_NOC__MMU_TBU_TCU__TBU5_BASE (0x491B0000) +#define IMX9_NOC__MMU_TBU_TCU__TBU6_BASE (0x491D0000) +#define IMX9_NOC__MMU_TBU_TCU__TBU7_BASE (0x491F0000) +#define IMX9_NOC__MMU_TBU_TCU__TBU9_BASE (0x49210000) +#define IMX9_NOC__MMU_TBU_TCU__TCU_BASE (0x490D0000) +#define IMX9_NOC__SRAMCTL_BASE (0x490A0000) +#define IMX9_NOC__TCU_BASE (0x49040000) +#define IMX9_NPU__EIM_NPUMIX_BASE (0x4A860000) +#define IMX9_NPU__LSTCU_NPUMIX_BASE (0x4A850000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON0__NEUTRON_BASE (0x4ABC0000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON1__NEUTRON_BASE (0x4ABC1000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON2__NEUTRON_BASE (0x4ABC2000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON3__NEUTRON_BASE (0x4ABC3000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON_GANGED__NEUTRON_BASE (0x4ABC4000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON_S__MMR_SOC_BASE (0x4AB00000) +#define IMX9_NPU__NEUTRON_NPU__NEUTRON_S__MMR_ZV_BASE (0x4AB80000) +#define IMX9_NPU__TCU_BASE (0x4A800000) +#define IMX9_PDM_BASE (0x44520000) +#define IMX9_SAI1_BASE (0x443B0000) +#define IMX9_SAI2_BASE (0x4C880000) +#define IMX9_SAI3_BASE (0x42650000) +#define IMX9_SAI4_BASE (0x42660000) +#define IMX9_SAI5_BASE (0x42670000) +#define IMX9_SEMA42_1_BASE (0x44260000) +#define IMX9_SEMA42_2_BASE (0x42450000) +#define IMX9_TMPSNS1_BASE (0x44482000) +#define IMX9_TMPSNS2_BASE (0x4A440000) +#define IMX9_TMR0_BASE_BASE (0x4CCC0000) +#define IMX9_TMR0_GLOBAL_BASE (0x4CCD0000) +#define IMX9_TMR0_PCI_HDR_TYPE0_BASE (0x4CAC0000) +#define IMX9_TPM1_BASE (0x44310000) +#define IMX9_TPM2_BASE (0x44320000) +#define IMX9_TPM3_BASE (0x424E0000) +#define IMX9_TPM4_BASE (0x424F0000) +#define IMX9_TPM5_BASE (0x42500000) +#define IMX9_TPM6_BASE (0x42510000) +#define IMX9_TRDC1_BASE (0x44270000) +#define IMX9_TSTMR1_BASE (0x442C0000) +#define IMX9_TSTMR2_BASE (0x42480000) +#define IMX9_USBC_BASE (0x4C200000) +#define IMX9_USBNC_BASE (0x4C200200) +#define IMX9_VPU__BLK_CTRL_VPUMIX_BASE (0x4C410000) +#define IMX9_VPU__GPV__JPEG_DEC_PROBE_MAIN_PROBE_BASE (0x4C801000) +#define IMX9_VPU__GPV__JPEG_DEC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C801580) +#define IMX9_VPU__GPV__JPEG_DEC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C801480) +#define IMX9_VPU__GPV__JPEG_DEC_WR_I_MAIN_QOSGENERATOR_BASE (0x4C801400) +#define IMX9_VPU__GPV__JPEG_DEC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C801500) +#define IMX9_VPU__GPV__JPEG_ENC_PROBE_MAIN_PROBE_BASE (0x4C802000) +#define IMX9_VPU__GPV__JPEG_ENC_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C802580) +#define IMX9_VPU__GPV__JPEG_ENC_RD_I_MAIN_QOSGENERATOR_BASE (0x4C802400) +#define IMX9_VPU__GPV__JPEG_ENC_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C802480) +#define IMX9_VPU__GPV__JPEG_ENC_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C802500) +#define IMX9_VPU__GPV__SSI_PRI_PROBE_MAIN_PROBE_BASE (0x4C800000) +#define IMX9_VPU__GPV__VPU_PRI_PROBE_MAIN_PROBE_BASE (0x4C800400) +#define IMX9_VPU__GPV__VPU_PRI_PROBE_MAIN_TRANSACTIONSTATPROFILER_BASE (0x4C800A00) +#define IMX9_VPU__GPV__VPU_PRI_RD_I_MAIN_QOSGENERATOR_BASE (0x4C800800) +#define IMX9_VPU__GPV__VPU_PRI_RD_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C800900) +#define IMX9_VPU__GPV__VPU_PRI_WR_I_MAIN_QOSGENERATOR_BASE (0x4C800880) +#define IMX9_VPU__GPV__VPU_PRI_WR_I_MAIN_TRANSACTIONSTATFILTER_BASE (0x4C800980) +#define IMX9_VPU__JPEG_DEC_BASE (0x4C500100) +#define IMX9_VPU__JPEG_DEC_WRAP_BASE (0x4C500000) +#define IMX9_VPU__JPEG_ENC_BASE (0x4C550100) +#define IMX9_VPU__JPEG_ENC_WRAP_BASE (0x4C550000) +#define IMX9_VPU__TCU_BASE (0x4C400000) +#define IMX9_VPU__VPU__VPU_CODEC_BASE (0x4C480000) +#define IMX9_WAKEUP__AHBRM1_BASE (0x425E0000) +#define IMX9_WAKEUP__ATUA_BASE (0x42760000) +#define IMX9_WAKEUP__ATUM_BASE (0x42770000) +#define IMX9_WAKEUP__AUDIO_XCVR_BASE (0x42680000) +#define IMX9_WAKEUP__BLK_CTRL_WAKEUPMIX_BASE (0x42420000) +#define IMX9_WAKEUP__CMU1_BASE (0x42750000) +#define IMX9_WAKEUP__CMU2_BASE (0x427A0000) +#define IMX9_WAKEUP__DMA_CRC2_BASE (0x427B0000) +#define IMX9_WAKEUP__EDMA5_TCD2_BASE (0x42010000) +#define IMX9_WAKEUP__EDMA5_TCD3_BASE (0x42220000) +#define IMX9_WAKEUP__EIMW_BASE (0x42780000) +#define IMX9_WAKEUP__FLEXSPI_OTFAD_BASE (0x425E0000) +#define IMX9_WAKEUP__GPV_NOCM__POWER_MEGA_RESILIENCEFAULTCONTROLLER_BASE (0x42830000) +#define IMX9_WAKEUP__GPV_NOC__POWER_MAIN_RESILIENCEFAULTCONTROLLER_BASE (0x43900000) +#define IMX9_WAKEUP__ROMCP2_BASE (0x42640000) +#define IMX9_WAKEUP__USDHC1_BASE (0x42850000) +#define IMX9_WAKEUP__USDHC2_BASE (0x42860000) +#define IMX9_WAKEUP__USDHC3_BASE (0x428B0000) +#define IMX9_WAKEUP__XSPI_RESPONDER_BASE (0x428A0000) +#define IMX9_WDOG1_BASE (0x442D0000) +#define IMX9_WDOG2_BASE (0x442E0000) +#define IMX9_WDOG3_BASE (0x42490000) +#define IMX9_WDOG4_BASE (0x424A0000) +#define IMX9_WDOG5_BASE (0x424B0000) diff --git a/arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h b/arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h new file mode 100644 index 0000000000000..2bc9466a3d273 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h @@ -0,0 +1,748 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOMUXC_REGISTER_NOT_AVAILABLE 0x0000 + +#define IOMUXC_PAD_DAP_TDI_JTAG_MUX_TDI IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x0, IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TDI_MQS2_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TDI_NETC_TMR_1588_ALARM1 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TDI_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TDI_FLEXIO2_FLEXIO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TDI_GPIO3_IO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TDI_LPUART5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDI_OFFSET, 0x6, IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_DAP_TMS_SWDIO_JTAG_MUX_TMS IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x0, IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_DAP_TMS_SWDIO_CAN4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_DAP_TMS_SWDIO_FLEXIO2_FLEXIO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_DAP_TMS_SWDIO_GPIO3_IO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_DAP_TMS_SWDIO_LPUART5_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_JTAG_MUX_TCK IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x0, IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_CAN4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x2, IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_FLEXIO1_FLEXIO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_GPIO3_IO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_LPUART5_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET, 0x6, IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_JTAG_MUX_TDO IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_MQS2_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_NETC_TMR_1588_ALARM2 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x3, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_FLEXIO1_FLEXIO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_GPIO3_IO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_LPUART5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET, 0x6, IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_GPIO_IO00_GPIO2_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_GPIO_IO00_LPI2C3_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_GPIO_IO00_LPSPI6_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_GPIO_IO00_LPUART5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x5, IOMUXC_LPUART5_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_GPIO_IO00_LPI2C5_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_GPIO_IO00_FLEXIO1_FLEXIO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO00_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_GPIO_IO01_GPIO2_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_GPIO_IO01_LPI2C3_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_GPIO_IO01_LPSPI6_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_GPIO_IO01_LPUART5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x5, IOMUXC_LPUART5_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_GPIO_IO01_LPI2C5_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_GPIO_IO01_FLEXIO1_FLEXIO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO01_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_GPIO_IO02_GPIO2_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_GPIO_IO02_LPI2C4_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_GPIO_IO02_LPSPI6_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_GPIO_IO02_LPUART5_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x5, IOMUXC_LPUART5_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_GPIO_IO02_FLEXIO1_FLEXIO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO02_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_GPIO_IO03_GPIO2_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_GPIO_IO03_LPI2C4_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_GPIO_IO03_LPSPI6_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_GPIO_IO03_LPUART5_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_GPIO_IO03_FLEXIO1_FLEXIO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO03_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_GPIO2_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_TPM3_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_PDM_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_CAN4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_LPSPI7_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_LPUART6_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x5, IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_LPI2C6_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO04_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_GPIO2_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_TPM4_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_PDM_BIT_STREAM00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_CAN4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x3, IOMUXC_CAN4_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_LPSPI7_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_LPUART6_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x5, IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_LPI2C6_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x6, IOMUXC_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO05_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_GPIO2_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_TPM5_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_PDM_BIT_STREAM01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_LPSPI7_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_LPUART6_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x5, IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_LPI2C7_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO06_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_GPIO_IO07_GPIO2_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_GPIO_IO07_LPSPI3_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_GPIO_IO07_LPSPI7_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_GPIO_IO07_LPUART6_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_GPIO_IO07_LPI2C7_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO07_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_GPIO_IO08_GPIO2_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_GPIO_IO08_LPSPI3_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_GPIO_IO08_TPM6_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_GPIO_IO08_LPUART7_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x5, IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_GPIO_IO08_LPI2C7_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_GPIO_IO08_FLEXIO1_FLEXIO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO08_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_GPIO_IO09_GPIO2_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_GPIO_IO09_LPSPI3_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_GPIO_IO09_TPM3_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_GPIO_IO09_LPUART7_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x5, IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_GPIO_IO09_LPI2C7_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x6, IOMUXC_LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_GPIO_IO09_FLEXIO1_FLEXIO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO09_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_GPIO_IO10_GPIO2_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_GPIO_IO10_LPSPI3_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_GPIO_IO10_TPM4_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_GPIO_IO10_LPUART7_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_GPIO_IO10_LPI2C8_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_GPIO_IO10_FLEXIO1_FLEXIO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO10_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_GPIO_IO11_GPIO2_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_GPIO_IO11_LPSPI3_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_GPIO_IO11_TPM5_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_GPIO_IO11_LPUART7_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_GPIO_IO11_LPI2C8_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_GPIO_IO11_FLEXIO1_FLEXIO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO11_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_GPIO2_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_TPM3_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_PDM_BIT_STREAM02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_FLEXIO1_FLEXIO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_LPSPI8_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_LPUART8_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_LPI2C8_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO12_SAI3_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO12_OFFSET, 0x7, IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_GPIO2_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_TPM4_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_PDM_BIT_STREAM03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_LPSPI8_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_LPUART8_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_LPI2C8_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x6, IOMUXC_LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO13_FLEXIO1_FLEXIO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO13_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_GPIO_IO14_GPIO2_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_GPIO_IO14_LPUART3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_GPIO_IO14_LPSPI8_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_GPIO_IO14_LPUART8_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_GPIO_IO14_LPUART4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x6, IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_GPIO_IO14_FLEXIO1_FLEXIO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO14_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_GPIO_IO15_GPIO2_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_GPIO_IO15_LPUART3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_GPIO_IO15_LPSPI8_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_GPIO_IO15_LPUART8_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_GPIO_IO15_LPUART4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x6, IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_GPIO_IO15_FLEXIO1_FLEXIO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO15_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_GPIO2_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_SAI3_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_PDM_BIT_STREAM02 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_LPUART3_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x4, IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_LPSPI4_PCS2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_LPUART4_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x6, IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO16_FLEXIO1_FLEXIO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO16_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_GPIO_IO17_GPIO2_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_GPIO_IO17_SAI3_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_GPIO_IO17_LPUART3_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_GPIO_IO17_LPSPI4_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_GPIO_IO17_LPUART4_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_GPIO_IO17_FLEXIO1_FLEXIO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO17_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_GPIO_IO18_GPIO2_IO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_GPIO_IO18_SAI3_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x1, IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_GPIO_IO18_LPSPI5_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_GPIO_IO18_LPSPI4_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_GPIO_IO18_TPM5_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_GPIO_IO18_FLEXIO1_FLEXIO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO18_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_GPIO2_IO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_SAI3_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x1, IOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_PDM_BIT_STREAM03 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_FLEXIO1_FLEXIO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_LPSPI5_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_LPSPI4_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_TPM6_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO19_SAI3_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO19_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_GPIO2_IO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_SAI3_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_PDM_BIT_STREAM00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_LPSPI5_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_LPSPI4_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_TPM3_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO20_FLEXIO1_FLEXIO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO20_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_GPIO2_IO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_SAI3_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_PDM_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_FLEXIO1_FLEXIO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_LPSPI5_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_LPSPI4_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x5, IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_TPM4_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO21_SAI3_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO21_OFFSET, 0x7, IOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_GPIO2_IO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_USDHC3_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x1, IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_SPDIF_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x2, IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_CAN5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_TPM5_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_TPM6_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_LPI2C5_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO22_FLEXIO1_FLEXIO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO22_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_GPIO2_IO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_USDHC3_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x1, IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_SPDIF_OUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_CAN5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x3, IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_TPM6_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_LPI2C5_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x6, IOMUXC_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO23_FLEXIO1_FLEXIO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO23_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_GPIO_IO24_GPIO2_IO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_GPIO_IO24_USDHC3_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_GPIO_IO24_TPM3_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_GPIO_IO24_JTAG_MUX_TDO IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_GPIO_IO24_LPSPI6_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_GPIO_IO24_FLEXIO1_FLEXIO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO24_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_GPIO2_IO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_USDHC3_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_TPM4_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_JTAG_MUX_TCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x5, IOMUXC_JTAG_MUX_TCK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_LPSPI7_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO25_FLEXIO1_FLEXIO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO25_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_GPIO2_IO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_USDHC3_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_PDM_BIT_STREAM01 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x2, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_FLEXIO1_FLEXIO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x3, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_TPM5_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_JTAG_MUX_TDI IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x5, IOMUXC_JTAG_MUX_TDI_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_LPSPI8_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO26_SAI3_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO26_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_GPIO2_IO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_USDHC3_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x1, IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x2, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x2, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_TPM6_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_JTAG_MUX_TMS IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x5, IOMUXC_JTAG_MUX_TMS_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_LPSPI5_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO27_FLEXIO1_FLEXIO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO27_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_GPIO_IO28_GPIO2_IO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_GPIO_IO28_LPI2C3_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_GPIO_IO28_CAN3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_GPIO_IO28_FLEXIO1_FLEXIO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO28_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_GPIO_IO29_GPIO2_IO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_GPIO_IO29_LPI2C3_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x1, IOMUXC_LPI2C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_GPIO_IO29_CAN3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x2, IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_GPIO_IO29_FLEXIO1_FLEXIO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO29_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_GPIO_IO30_GPIO2_IO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET) +#define IOMUXC_PAD_GPIO_IO30_LPI2C4_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET) +#define IOMUXC_PAD_GPIO_IO30_CAN5_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET) +#define IOMUXC_PAD_GPIO_IO30_FLEXIO1_FLEXIO30 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO30_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_30_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO30_OFFSET) +#define IOMUXC_PAD_GPIO_IO31_GPIO2_IO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET) +#define IOMUXC_PAD_GPIO_IO31_LPI2C4_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x1, IOMUXC_LPI2C4_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET) +#define IOMUXC_PAD_GPIO_IO31_CAN5_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x2, IOMUXC_CAN5_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET) +#define IOMUXC_PAD_GPIO_IO31_FLEXIO1_FLEXIO31 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO31_OFFSET, 0x7, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_31_OFFSET, 0x1, IOMUXC_PAD_CTL_GPIO_IO31_OFFSET) +#define IOMUXC_PAD_GPIO_IO32_GPIO5_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET) +#define IOMUXC_PAD_GPIO_IO32_PCIE1_CLKREQ_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET) +#define IOMUXC_PAD_GPIO_IO32_LPUART6_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x2, IOMUXC_LPUART6_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET) +#define IOMUXC_PAD_GPIO_IO32_LPSPI4_PCS2 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO32_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO32_OFFSET) +#define IOMUXC_PAD_GPIO_IO33_GPIO5_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO33_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO33_OFFSET) +#define IOMUXC_PAD_GPIO_IO33_LPUART6_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO33_OFFSET, 0x2, IOMUXC_LPUART6_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO33_OFFSET) +#define IOMUXC_PAD_GPIO_IO33_LPSPI4_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO33_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO33_OFFSET) +#define IOMUXC_PAD_GPIO_IO34_GPIO5_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO34_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO34_OFFSET) +#define IOMUXC_PAD_GPIO_IO34_LPUART6_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO34_OFFSET, 0x2, IOMUXC_LPUART6_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO34_OFFSET) +#define IOMUXC_PAD_GPIO_IO34_LPSPI4_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO34_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_PCS_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO34_OFFSET) +#define IOMUXC_PAD_GPIO_IO35_GPIO5_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET) +#define IOMUXC_PAD_GPIO_IO35_PCIE2_CLKREQ_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET) +#define IOMUXC_PAD_GPIO_IO35_LPUART6_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET) +#define IOMUXC_PAD_GPIO_IO35_LPSPI4_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO35_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDI_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO35_OFFSET) +#define IOMUXC_PAD_GPIO_IO36_GPIO5_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO36_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO36_OFFSET) +#define IOMUXC_PAD_GPIO_IO36_LPUART7_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO36_OFFSET, 0x2, IOMUXC_LPUART7_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO36_OFFSET) +#define IOMUXC_PAD_GPIO_IO36_LPSPI4_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO36_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_SDO_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO36_OFFSET) +#define IOMUXC_PAD_GPIO_IO37_GPIO5_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO37_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_GPIO_IO37_OFFSET) +#define IOMUXC_PAD_GPIO_IO37_LPUART7_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO37_OFFSET, 0x2, IOMUXC_LPUART7_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO37_OFFSET) +#define IOMUXC_PAD_GPIO_IO37_LPSPI4_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_GPIO_IO37_OFFSET, 0x4, IOMUXC_LPSPI4_IPP_IND_LPSPI_SCK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_GPIO_IO37_OFFSET) +#define IOMUXC_PAD_CCM_CLKO1_CLKO_1 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CCM_CLKO1_NETC_TMR_1588_TRIG1 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CCM_CLKO1_FLEXIO1_FLEXIO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_26_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CCM_CLKO1_GPIO3_IO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CCM_CLKO2_CLKO_2 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CCM_CLKO2_NETC_TMR_1588_PP1 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CCM_CLKO2_FLEXIO1_FLEXIO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CCM_CLKO2_GPIO3_IO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CCM_CLKO3_CLKO_3 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CCM_CLKO3_NETC_TMR_1588_TRIG2 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CCM_CLKO3_CAN3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CCM_CLKO3_FLEXIO2_FLEXIO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CCM_CLKO3_GPIO4_IO28 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CCM_CLKO4_CLKO_4 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CCM_CLKO4_NETC_TMR_1588_PP2 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CCM_CLKO4_CAN3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x2, IOMUXC_CAN3_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CCM_CLKO4_FLEXIO2_FLEXIO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CCM_CLKO4_GPIO4_IO29 IOMUX_PADCFG(IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_ENET1_MDC_NETC_MDC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_ENET1_MDC_LPUART3_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_ENET1_MDC_I3C2_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x2, IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_ENET1_MDC_USB1_OTG_ID IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_ENET1_MDC_FLEXIO2_FLEXIO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_ENET1_MDC_GPIO4_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_ENET1_MDIO_NETC_MDIO IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_ENET1_MDIO_LPUART3_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_ENET1_MDIO_I3C2_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x2, IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_ENET1_MDIO_USB1_OTG_PWR IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_ENET1_MDIO_FLEXIO2_FLEXIO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_ENET1_MDIO_GPIO4_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_ENET1_TD3_ETH0_RGMII_TD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_ENET1_TD3_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_ENET1_TD3_USB2_OTG_ID IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_ENET1_TD3_FLEXIO2_FLEXIO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_ENET1_TD3_GPIO4_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_ENET1_TD2_ETH0_RGMII_TD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_ENET1_TD2_ETH0_RMII_REF50_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_ENET1_TD2_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x2, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_ENET1_TD2_USB2_OTG_OC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_ENET1_TD2_FLEXIO2_FLEXIO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_ENET1_TD2_GPIO4_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_ETH0_RGMII_TD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_LPUART3_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_USB1_OTG_OC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_FLEXIO2_FLEXIO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_GPIO4_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD1_ETH0_RMII_TXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD1_OFFSET, 0x7, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_ENET1_TD0_ETH0_RGMII_TD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_ENET1_TD0_LPUART3_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_ENET1_TD0_ETH0_RMII_TXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_ENET1_TD0_FLEXIO2_FLEXIO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_ENET1_TD0_GPIO4_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_ENET1_TX_CTL_ETH0_RGMII_TX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_TX_CTL_LPUART3_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_TX_CTL_ETH0_RMII_TX_EN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_TX_CTL_FLEXIO2_FLEXIO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_TX_CTL_GPIO4_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_TXC_ETH0_RGMII_TX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_ENET1_TXC_ENET_CLK_ROOT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_ENET1_TXC_FLEXIO2_FLEXIO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_ENET1_TXC_GPIO4_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_TXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_ENET1_RX_CTL_ETH0_RGMII_RX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_RX_CTL_LPUART3_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_RX_CTL_ETH0_RMII_CRS_DV IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_RX_CTL_USB2_OTG_PWR IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_RX_CTL_FLEXIO2_FLEXIO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_RX_CTL_GPIO4_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET1_RXC_ETH0_RGMII_RX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_ENET1_RXC_ETH0_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x1, IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_ENET1_RXC_FLEXIO2_FLEXIO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_ENET1_RXC_GPIO4_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_ENET1_RD0_ETH0_RGMII_RD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_ENET1_RD0_LPUART3_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_ENET1_RD0_ETH0_RMII_RXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_ENET1_RD0_FLEXIO2_FLEXIO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_ENET1_RD0_GPIO4_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_ENET1_RD1_ETH0_RGMII_RD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_ENET1_RD1_LPUART3_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x1, IOMUXC_LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_ENET1_RD1_ETH0_RMII_RXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_ENET1_RD1_LPTMR2_ALT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x3, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_ENET1_RD1_FLEXIO2_FLEXIO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_ENET1_RD1_GPIO4_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_ENET1_RD2_ETH0_RGMII_RD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_ENET1_RD2_ETH0_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x2, IOMUXC_NETC_CMPLX_ETH0_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_ENET1_RD2_LPTMR2_ALT2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x3, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_ENET1_RD2_FLEXIO2_FLEXIO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_ENET1_RD2_GPIO4_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_ENET1_RD3_ETH0_RGMII_RD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_ENET1_RD3_LPTMR2_ALT3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x3, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_ENET1_RD3_FLEXIO2_FLEXIO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_ENET1_RD3_GPIO4_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET1_RD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_ENET2_MDC_NETC_MDC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDC_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_ENET2_MDC_LPUART4_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_ENET2_MDC_SAI2_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_ENET2_MDC_FLEXIO2_FLEXIO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_ENET2_MDC_GPIO4_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_ENET2_MDIO_NETC_MDIO IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x0, IOMUXC_NETC_CMPLX_EMDIO_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_ENET2_MDIO_LPUART4_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_ENET2_MDIO_SAI2_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_ENET2_MDIO_FLEXIO2_FLEXIO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_ENET2_MDIO_GPIO4_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_ENET2_TD3_ETH1_RGMII_TD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_ENET2_TD3_SAI2_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_ENET2_TD3_FLEXIO2_FLEXIO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_ENET2_TD3_GPIO4_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_ENET2_TD2_ETH1_RGMII_TD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_ENET2_TD2_ETH1_RMII_REF50_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_ENET2_TD2_SAI2_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_ENET2_TD2_SAI4_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_ENET2_TD2_FLEXIO2_FLEXIO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_ENET2_TD2_GPIO4_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_ETH1_RGMII_TD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_LPUART4_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_SAI2_RX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_SAI4_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_FLEXIO2_FLEXIO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_GPIO4_IO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD1_ETH1_RMII_TXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD1_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_ETH1_RGMII_TD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_LPUART4_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x1, IOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_SAI2_RX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_SAI4_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_FLEXIO2_FLEXIO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_GPIO4_IO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TD0_ETH1_RMII_TXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TD0_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_ENET2_TX_CTL_ETH1_RGMII_TX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_TX_CTL_LPUART4_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_TX_CTL_SAI2_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_TX_CTL_ETH1_RMII_TX_EN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_TX_CTL_FLEXIO2_FLEXIO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_TX_CTL_GPIO4_IO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_TXC_ETH1_RGMII_TX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_ENET2_TXC_ENET_CLK_ROOT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_ENET2_TXC_SAI2_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_ENET2_TXC_FLEXIO2_FLEXIO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_ENET2_TXC_GPIO4_IO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_TXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_ENET2_RX_CTL_ETH1_RGMII_RX_CTL IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_RX_CTL_LPUART4_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_RX_CTL_SAI2_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_RX_CTL_FLEXIO2_FLEXIO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_RX_CTL_GPIO4_IO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_RX_CTL_ETH1_RMII_CRS_DV IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_ENET2_RXC_ETH1_RGMII_RX_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_ENET2_RXC_ETH1_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x1, IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_ENET2_RXC_SAI2_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_ENET2_RXC_SAI4_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_ENET2_RXC_FLEXIO2_FLEXIO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_ENET2_RXC_GPIO4_IO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_ETH1_RGMII_RD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_LPUART4_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x1, IOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_SAI2_TX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_SAI4_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_FLEXIO2_FLEXIO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_GPIO4_IO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD0_ETH1_RMII_RXD0 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD0_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_ETH1_RGMII_RD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_SPDIF_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x1, IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_SAI2_TX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_SAI4_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x3, IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_FLEXIO2_FLEXIO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_GPIO4_IO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD1_ETH1_RMII_RXD1 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD1_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_ETH1_RGMII_RD2 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_LPUART4_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x1, IOMUXC_LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_SAI2_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_MQS2_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_FLEXIO2_FLEXIO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_GPIO4_IO26 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD2_ETH1_RMII_RX_ER IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD2_OFFSET, 0x6, IOMUXC_NETC_CMPLX_ETH1_RMII_RX_ER_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_ENET2_RD3_ETH1_RGMII_RD3 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_OUT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x2, IOMUXC_EARC_PHY_SPDIF_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_ENET2_RD3_MQS2_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_ENET2_RD3_FLEXIO2_FLEXIO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_ENET2_RD3_GPIO4_IO27 IOMUX_PADCFG(IOMUXC_MUX_CTL_ENET2_RD3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_SD1_CLK_USDHC1_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CLK_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_SD1_CLK_FLEXIO1_FLEXIO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_SD1_CLK_GPIO3_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_SD1_CMD_USDHC1_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CMD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_SD1_CMD_FLEXIO1_FLEXIO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CMD_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_SD1_CMD_GPIO3_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_CMD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_SD1_DATA0_USDHC1_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_SD1_DATA0_FLEXIO1_FLEXIO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA0_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_SD1_DATA0_GPIO3_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_SD1_DATA1_USDHC1_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_SD1_DATA1_FLEXIO1_FLEXIO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_SD1_DATA1_GPIO3_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_SD1_DATA2_USDHC1_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_SD1_DATA2_FLEXIO1_FLEXIO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_12_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_SD1_DATA2_GPIO3_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_SD1_DATA3_USDHC1_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_SD1_DATA3_FLEXSPI1_A_SS1_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_SD1_DATA3_FLEXIO1_FLEXIO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_SD1_DATA3_GPIO3_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_SD1_DATA4_USDHC1_DATA4 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_SD1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_SD1_DATA4_FLEXIO1_FLEXIO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_SD1_DATA4_GPIO3_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_SD1_DATA4_XSPI_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA4_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_DATA5 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_SD1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_RESET_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_SD1_DATA5_FLEXIO1_FLEXIO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_SD1_DATA5_GPIO3_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_SD1_DATA5_XSPI_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA5_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_DATA6 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_SD1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_CD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_SD1_DATA6_FLEXIO1_FLEXIO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_SD1_DATA6_GPIO3_IO16 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_SD1_DATA6_XSPI_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA6_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_DATA7 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_SD1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_WP IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_SD1_DATA7_FLEXIO1_FLEXIO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_SD1_DATA7_GPIO3_IO17 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_SD1_DATA7_XSPI_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_DATA7_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_SD1_STROBE_USDHC1_STROBE IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_SD1_STROBE_FLEXSPI1_A_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_SD1_STROBE_FLEXIO1_FLEXIO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET, 0x1, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_SD1_STROBE_GPIO3_IO18 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_SD1_STROBE_XSPI_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_SD1_STROBE_OFFSET, 0x6, IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_VSELECT IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_WP IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_SD2_VSELECT_LPTMR2_ALT3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x2, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_SD2_VSELECT_FLEXIO1_FLEXIO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_19_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_SD2_VSELECT_GPIO3_IO19 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_SD3_CLK_USDHC3_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x0, IOMUXC_USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CLK_SAI5_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CLK_SAI5_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CLK_FLEXIO1_FLEXIO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CLK_GPIO3_IO20 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CLK_XSPI_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CLK_OFFSET, 0x6, IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_SD3_CMD_USDHC3_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x0, IOMUXC_USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_CMD_FLEXSPI1_A_SS0_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_CMD_SAI5_TX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_CMD_SAI5_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_CMD_FLEXIO1_FLEXIO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_21_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_CMD_GPIO3_IO21 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_CMD_XSPI_CS IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_CMD_OFFSET, 0x6, IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_USDHC3_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT0_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_SAI5_TX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_SAI5_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_FLEXIO1_FLEXIO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_GPIO3_IO22 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA0_XSPI_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA0_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_USDHC3_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_SAI5_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_SAI5_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_FLEXIO1_FLEXIO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_GPIO3_IO23 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA1_XSPI_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA1_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_USDHC3_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_SAI5_RX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_SAI5_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_FLEXIO1_FLEXIO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_GPIO3_IO24 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA2_XSPI_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA2_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_USDHC3_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x0, IOMUXC_USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x1, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_SAI5_RX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_SAI5_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x3, IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_FLEXIO1_FLEXIO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET, 0x1, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_GPIO3_IO25 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_SD3_DATA3_XSPI_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD3_DATA3_OFFSET, 0x6, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET, 0x0, IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA0_SAI2_TX_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA0_SAI4_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA0_SAI4_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA0_XSPI_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA0_GPIO5_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA0_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA1_SAI2_TX_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA1_SAI4_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA1_SAI4_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA1_XSPI_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA1_GPIO5_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA1_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA2_SAI2_TX_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA2_SAI4_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA2_XSPI_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA2_GPIO5_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA2_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA3_SAI2_TX_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA3_SAI4_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA3_XSPI_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA3_GPIO5_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA3_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_4_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA4_SAI5_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA4_SAI5_RX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA4_XSPI_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_4_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA4_GPIO5_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA4_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA4_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_5_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA5_SAI5_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_TXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA5_SAI5_RX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA5_SAI2_RX_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA5_XSPI_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_5_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA5_GPIO5_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA5_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA5_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA6_SAI5_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_TXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA6_SAI5_RX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x2, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA6_SAI2_RX_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA6_XSPI_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA6_GPIO5_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA6_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA6_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_IO_FA_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA7_SAI5_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA7_SAI5_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA7_XSPI_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x4, IOMUXC_XSPI_SLV_IPP_IND_IO_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_PAD_XSPI1_DATA7_GPIO5_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DATA7_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DATA7_OFFSET) +#define IOMUXC_PAD_XSPI1_DQS_FLEXSPI1_A_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_DQS_FA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_XSPI1_DQS_SAI5_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_XSPI1_DQS_SAI5_TX_DATA02 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_XSPI1_DQS_SAI2_RX_DATA06 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_XSPI1_DQS_XSPI_DQS IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x4, IOMUXC_XSPI_IPP_IND_DQS_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_XSPI1_DQS_GPIO5_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_DQS_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_DQS_OFFSET) +#define IOMUXC_PAD_XSPI1_SCLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x0, IOMUXC_FLEXSPI1_I_IPP_IND_SCK_FA_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_XSPI1_SCLK_SAI2_RX_DATA04 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_XSPI1_SCLK_SAI4_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_XSPI1_SCLK_EARC_DC_HPD_IN IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_XSPI1_SCLK_XSPI_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x4, IOMUXC_XSPI_IPP_IND_SCK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_XSPI1_SCLK_GPIO5_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SCLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SCLK_OFFSET) +#define IOMUXC_PAD_XSPI1_SS0_B_FLEXSPI1_A_SS0_B IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS0_B_SAI2_RX_DATA05 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS0_B_SAI4_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x2, IOMUXC_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS0_B_EARC_CEC_OUT IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS0_B_XSPI_CS IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x4, IOMUXC_XSPI_IPP_IND_CS_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS0_B_GPIO5_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS0_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS0_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS1_B_FLEXSPI1_A_SS1_B IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS1_B_SAI5_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x1, IOMUXC_SAI5_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS1_B_SAI5_TX_DATA03 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS1_B_SAI2_RX_DATA07 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x3, IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_PAD_XSPI1_SS1_B_GPIO5_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_XSPI1_SS1_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_XSPI1_SS1_B_OFFSET) +#define IOMUXC_PAD_SD2_CD_B_USDHC2_CD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_SD2_CD_B_NETC_TMR_1588_TRIG1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG1_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_SD2_CD_B_I3C2_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x2, IOMUXC_I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_SD2_CD_B_FLEXIO1_FLEXIO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_SD2_CD_B_GPIO3_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CD_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_SD2_CLK_USDHC2_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_SD2_CLK_NETC_TMR_1588_PP1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_SD2_CLK_I3C2_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x2, IOMUXC_I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_SD2_CLK_FLEXIO1_FLEXIO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_SD2_CLK_GPIO3_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_SD2_CMD_USDHC2_CMD IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_SD2_CMD_NETC_TMR_1588_TRIG2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x1, IOMUXC_NETC_CMPLX_TMR_1588_TRIG2_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_SD2_CMD_FLEXIO1_FLEXIO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_SD2_CMD_GPIO3_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_CMD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_SD2_DATA0_USDHC2_DATA0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_SD2_DATA0_NETC_TMR_1588_PP2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_SD2_DATA0_CAN2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_SD2_DATA0_FLEXIO1_FLEXIO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_SD2_DATA0_GPIO3_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_SD2_DATA1_NETC_TMR_1588_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_SD2_DATA1_CAN2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x2, IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x3, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_SD2_DATA1_FLEXIO1_FLEXIO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_SD2_DATA1_GPIO3_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_SD2_DATA2_USDHC2_DATA2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_SD2_DATA2_NETC_TMR_1588_PP3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_SD2_DATA2_MQS2_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_SD2_DATA2_FLEXIO1_FLEXIO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_SD2_DATA2_GPIO3_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA2_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_SD2_DATA3_LPTMR2_ALT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x1, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_0_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_SD2_DATA3_MQS2_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_SD2_DATA3_NETC_TMR_1588_ALARM1 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_SD2_DATA3_FLEXIO1_FLEXIO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_SD2_DATA3_GPIO3_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_DATA3_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_SD2_RESET_B_USDHC2_RESET_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_SD2_RESET_B_LPTMR2_ALT2 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x1, IOMUXC_LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_SD2_RESET_B_NETC_TMR_1588_GCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_SD2_RESET_B_FLEXIO1_FLEXIO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x4, IOMUXC_FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET, 0x1, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_SD2_RESET_B_GPIO3_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_I2C1_SCL_LPI2C1_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_I2C1_SCL_I3C1_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_I2C1_SCL_LPUART1_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_I2C1_SCL_TPM2_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_I2C1_SCL_UART_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_I2C1_SCL_GPIO1_IO00 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SCL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_I2C1_SDA_LPI2C1_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_I2C1_SDA_I3C1_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_I2C1_SDA_LPUART1_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_I2C1_SDA_TPM2_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_I2C1_SDA_UART_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_I2C1_SDA_GPIO1_IO01 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C1_SDA_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_LPI2C2_SCL IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_LPUART2_DCD_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_TPM2_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_SAI1_RX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_GPIO1_IO02 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SCL_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_I2C2_SDA_LPI2C2_SDA IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_I2C2_SDA_LPUART2_RIN_B IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_I2C2_SDA_TPM2_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_I2C2_SDA_SAI1_RX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_I2C2_SDA_GPIO1_IO03 IOMUX_PADCFG(IOMUXC_MUX_CTL_I2C2_SDA_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_UART1_RXD_LPUART1_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_UART1_RXD_ELE_UART_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_UART1_RXD_LPSPI2_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_UART1_RXD_TPM1_CH0 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_UART1_RXD_GPIO1_IO04 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_RXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_UART1_TXD_LPUART1_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_UART1_TXD_ELE_UART_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_UART1_TXD_LPSPI2_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_UART1_TXD_TPM1_CH1 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_UART1_TXD_GPIO1_IO05 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART1_TXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_UART2_RXD_LPUART2_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_UART2_RXD_LPUART1_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_UART2_RXD_LPSPI2_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_UART2_RXD_TPM1_CH2 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_UART2_RXD_SAI1_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x4, IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_UART2_RXD_GPIO1_IO06 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_RXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_UART2_TXD_LPUART2_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_UART2_TXD_LPUART1_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_UART2_TXD_LPSPI2_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_UART2_TXD_TPM1_CH3 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_UART2_TXD_GPIO1_IO07 IOMUX_PADCFG(IOMUXC_MUX_CTL_UART2_TXD_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_PDM_CLK_PDM_CLK IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_PDM_CLK_MQS1_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_PDM_CLK_LPTMR1_ALT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_PDM_CLK_GPIO1_IO08 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_PDM_CLK_CAN1_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_CLK_OFFSET, 0x6, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_PDM_BIT_STREAM00 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x0, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0_OFFSET, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_MQS1_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPSPI1_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_TPM1_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPTMR1_ALT2 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_GPIO1_IO09 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET, 0x6, IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM1_PDM_BIT_STREAM01 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x0, IOMUXC_PDM_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1_OFFSET, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM1_NMI_GLUE_NMI IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPSPI2_PCS1 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM1_TPM2_EXTCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPTMR1_ALT3 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_PDM_BIT_STREAM1_GPIO1_IO10 IOMUX_PADCFG(IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_SYNC IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_DATA01 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_SAI1_TXFS_LPSPI1_PCS0 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_SAI1_TXFS_LPUART2_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_SAI1_TXFS_MQS1_LEFT IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_SAI1_TXC_SAI1_TX_BCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_SAI1_TXC_LPUART2_CTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_SAI1_TXC_LPUART1_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_SAI1_TXC_CAN1_RX IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x4, IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_SAI1_TXC_GPIO1_IO12 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXC_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_SAI1_TXD0_SAI1_TX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_SAI1_TXD0_LPUART2_RTS_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_SAI1_TXD0_LPUART1_DTR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_SAI1_TXD0_CAN1_TX IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_SAI1_TXD0_GPIO1_IO13 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_RX_DATA00 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_MCLK IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x1, IOMUXC_SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET, 0x1, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x2, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_SAI1_RXD0_LPUART2_DSR_B IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x3, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_SAI1_RXD0_MQS1_RIGHT IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x4, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_SAI1_RXD0_GPIO1_IO14 IOMUX_PADCFG(IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_WDOG_ANY_WDOG_ANY IOMUX_PADCFG(IOMUXC_MUX_CTL_WDOG_ANY_OFFSET, 0x0, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) +#define IOMUXC_PAD_WDOG_ANY_FCCU_EOUT1 IOMUX_PADCFG(IOMUXC_MUX_CTL_WDOG_ANY_OFFSET, 0x1, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) +#define IOMUXC_PAD_WDOG_ANY_GPIO1_IO15 IOMUX_PADCFG(IOMUXC_MUX_CTL_WDOG_ANY_OFFSET, 0x5, IOMUXC_REGISTER_NOT_AVAILABLE, 0x0, IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) diff --git a/arch/arm/src/imx9/hardware/imx9_clock.h b/arch/arm/src/imx9/hardware/imx9_clock.h new file mode 100644 index 0000000000000..141cdb450718e --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_clock.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_clock.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/imx9_memorymap.h" + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_clock.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H_ */ diff --git a/arch/arm/src/imx9/hardware/imx9_dmamux.h b/arch/arm/src/imx9/hardware/imx9_dmamux.h new file mode 100644 index 0000000000000..0dac2d5f83051 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_dmamux.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_dmamux.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_dmamux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_edma.h b/arch/arm/src/imx9/hardware/imx9_edma.h new file mode 100644 index 0000000000000..b84dd5175c4f9 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_edma.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_edma.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_edma.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_flexcan.h b/arch/arm/src/imx9/hardware/imx9_flexcan.h new file mode 100644 index 0000000000000..b7c33f6f732da --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_flexcan.h @@ -0,0 +1,7703 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_flexcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_FLEXCAN_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_FLEXCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CAN Register Offsets *****************************************************/ +#define IMX9_CAN_MCR_OFFSET (0x0000) +#define IMX9_CAN_CTRL1_OFFSET (0x0004) +#define IMX9_CAN_TIMER_OFFSET (0x0008) +#define IMX9_CAN_RXMGMASK_OFFSET (0x0010) +#define IMX9_CAN_RX14MASK_OFFSET (0x0014) +#define IMX9_CAN_RX15MASK_OFFSET (0x0018) +#define IMX9_CAN_ECR_OFFSET (0x001c) +#define IMX9_CAN_ESR1_OFFSET (0x0020) +#define IMX9_CAN_IMASK2_OFFSET (0x0024) +#define IMX9_CAN_IMASK1_OFFSET (0x0028) +#define IMX9_CAN_IFLAG2_OFFSET (0x002c) +#define IMX9_CAN_IFLAG1_OFFSET (0x0030) +#define IMX9_CAN_CTRL2_OFFSET (0x0034) +#define IMX9_CAN_ESR2_OFFSET (0x0038) +#define IMX9_CAN_CRCR_OFFSET (0x0044) +#define IMX9_CAN_RXFGMASK_OFFSET (0x0048) +#define IMX9_CAN_RXFIR_OFFSET (0x004c) +#define IMX9_CAN_CBT_OFFSET (0x0050) +#define IMX9_CAN_IMASK3_OFFSET (0x006c) +#define IMX9_CAN_IFLAG3_OFFSET (0x0074) +#define IMX9_CAN_CS0_OFFSET (0x0080) +#define IMX9_CAN_WORD00_OFFSET (0x0088) +#define IMX9_CAN_WORD10_OFFSET (0x008c) +#define IMX9_CAN_CS1_OFFSET (0x0090) +#define IMX9_CAN_WORD01_OFFSET (0x0098) +#define IMX9_CAN_WORD11_OFFSET (0x009c) +#define IMX9_CAN_CS2_OFFSET (0x00a0) +#define IMX9_CAN_WORD02_OFFSET (0x00a8) +#define IMX9_CAN_WORD12_OFFSET (0x00ac) +#define IMX9_CAN_CS3_OFFSET (0x00b0) +#define IMX9_CAN_WORD03_OFFSET (0x00b8) +#define IMX9_CAN_WORD13_OFFSET (0x00bc) +#define IMX9_CAN_CS4_OFFSET (0x00c0) +#define IMX9_CAN_WORD04_OFFSET (0x00c8) +#define IMX9_CAN_WORD14_OFFSET (0x00cc) +#define IMX9_CAN_CS5_OFFSET (0x00d0) +#define IMX9_CAN_WORD05_OFFSET (0x00d8) +#define IMX9_CAN_WORD15_OFFSET (0x00dc) +#define IMX9_CAN_CS6_OFFSET (0x00e0) +#define IMX9_CAN_WORD06_OFFSET (0x00e8) +#define IMX9_CAN_WORD16_OFFSET (0x00ec) +#define IMX9_CAN_CS7_OFFSET (0x00f0) +#define IMX9_CAN_WORD07_OFFSET (0x00f8) +#define IMX9_CAN_WORD17_OFFSET (0x00fc) +#define IMX9_CAN_CS8_OFFSET (0x0100) +#define IMX9_CAN_WORD08_OFFSET (0x0108) +#define IMX9_CAN_WORD18_OFFSET (0x010c) +#define IMX9_CAN_CS9_OFFSET (0x0110) +#define IMX9_CAN_WORD09_OFFSET (0x0118) +#define IMX9_CAN_WORD19_OFFSET (0x011c) +#define IMX9_CAN_CS10_OFFSET (0x0120) +#define IMX9_CAN_WORD010_OFFSET (0x0128) +#define IMX9_CAN_WORD110_OFFSET (0x012c) +#define IMX9_CAN_CS11_OFFSET (0x0130) +#define IMX9_CAN_WORD011_OFFSET (0x0138) +#define IMX9_CAN_WORD111_OFFSET (0x013c) +#define IMX9_CAN_CS12_OFFSET (0x0140) +#define IMX9_CAN_WORD012_OFFSET (0x0148) +#define IMX9_CAN_WORD112_OFFSET (0x014c) +#define IMX9_CAN_CS13_OFFSET (0x0150) +#define IMX9_CAN_WORD013_OFFSET (0x0158) +#define IMX9_CAN_WORD113_OFFSET (0x015c) +#define IMX9_CAN_CS14_OFFSET (0x0160) +#define IMX9_CAN_WORD014_OFFSET (0x0168) +#define IMX9_CAN_WORD114_OFFSET (0x016c) +#define IMX9_CAN_CS15_OFFSET (0x0170) +#define IMX9_CAN_WORD015_OFFSET (0x0178) +#define IMX9_CAN_WORD115_OFFSET (0x017c) +#define IMX9_CAN_CS16_OFFSET (0x0180) +#define IMX9_CAN_WORD016_OFFSET (0x0188) +#define IMX9_CAN_WORD116_OFFSET (0x018c) +#define IMX9_CAN_CS17_OFFSET (0x0190) +#define IMX9_CAN_WORD017_OFFSET (0x0198) +#define IMX9_CAN_WORD117_OFFSET (0x019c) +#define IMX9_CAN_CS18_OFFSET (0x01a0) +#define IMX9_CAN_WORD018_OFFSET (0x01a8) +#define IMX9_CAN_WORD118_OFFSET (0x01ac) +#define IMX9_CAN_CS19_OFFSET (0x01b0) +#define IMX9_CAN_WORD019_OFFSET (0x01b8) +#define IMX9_CAN_WORD119_OFFSET (0x01bc) +#define IMX9_CAN_CS20_OFFSET (0x01c0) +#define IMX9_CAN_WORD020_OFFSET (0x01c8) +#define IMX9_CAN_WORD120_OFFSET (0x01cc) +#define IMX9_CAN_CS21_OFFSET (0x01d0) +#define IMX9_CAN_WORD021_OFFSET (0x01d8) +#define IMX9_CAN_WORD121_OFFSET (0x01dc) +#define IMX9_CAN_CS22_OFFSET (0x01e0) +#define IMX9_CAN_WORD022_OFFSET (0x01e8) +#define IMX9_CAN_WORD122_OFFSET (0x01ec) +#define IMX9_CAN_CS23_OFFSET (0x01f0) +#define IMX9_CAN_WORD023_OFFSET (0x01f8) +#define IMX9_CAN_WORD123_OFFSET (0x01fc) +#define IMX9_CAN_CS24_OFFSET (0x0200) +#define IMX9_CAN_WORD024_OFFSET (0x0208) +#define IMX9_CAN_WORD124_OFFSET (0x020c) +#define IMX9_CAN_CS25_OFFSET (0x0210) +#define IMX9_CAN_WORD025_OFFSET (0x0218) +#define IMX9_CAN_WORD125_OFFSET (0x021c) +#define IMX9_CAN_CS26_OFFSET (0x0220) +#define IMX9_CAN_WORD026_OFFSET (0x0228) +#define IMX9_CAN_WORD126_OFFSET (0x022c) +#define IMX9_CAN_CS27_OFFSET (0x0230) +#define IMX9_CAN_WORD027_OFFSET (0x0238) +#define IMX9_CAN_WORD127_OFFSET (0x023c) +#define IMX9_CAN_CS28_OFFSET (0x0240) +#define IMX9_CAN_WORD028_OFFSET (0x0248) +#define IMX9_CAN_WORD128_OFFSET (0x024c) +#define IMX9_CAN_CS29_OFFSET (0x0250) +#define IMX9_CAN_WORD029_OFFSET (0x0258) +#define IMX9_CAN_WORD129_OFFSET (0x025c) +#define IMX9_CAN_CS30_OFFSET (0x0260) +#define IMX9_CAN_WORD030_OFFSET (0x0268) +#define IMX9_CAN_WORD130_OFFSET (0x026c) +#define IMX9_CAN_CS31_OFFSET (0x0270) +#define IMX9_CAN_WORD031_OFFSET (0x0278) +#define IMX9_CAN_WORD131_OFFSET (0x027c) +#define IMX9_CAN_CS32_OFFSET (0x0280) +#define IMX9_CAN_WORD032_OFFSET (0x0288) +#define IMX9_CAN_WORD132_OFFSET (0x028c) +#define IMX9_CAN_CS33_OFFSET (0x0290) +#define IMX9_CAN_WORD033_OFFSET (0x0298) +#define IMX9_CAN_WORD133_OFFSET (0x029c) +#define IMX9_CAN_CS34_OFFSET (0x02a0) +#define IMX9_CAN_WORD034_OFFSET (0x02a8) +#define IMX9_CAN_WORD134_OFFSET (0x02ac) +#define IMX9_CAN_CS35_OFFSET (0x02b0) +#define IMX9_CAN_WORD035_OFFSET (0x02b8) +#define IMX9_CAN_WORD135_OFFSET (0x02bc) +#define IMX9_CAN_CS36_OFFSET (0x02c0) +#define IMX9_CAN_WORD036_OFFSET (0x02c8) +#define IMX9_CAN_WORD136_OFFSET (0x02cc) +#define IMX9_CAN_CS37_OFFSET (0x02d0) +#define IMX9_CAN_WORD037_OFFSET (0x02d8) +#define IMX9_CAN_WORD137_OFFSET (0x02dc) +#define IMX9_CAN_CS38_OFFSET (0x02e0) +#define IMX9_CAN_WORD038_OFFSET (0x02e8) +#define IMX9_CAN_WORD138_OFFSET (0x02ec) +#define IMX9_CAN_CS39_OFFSET (0x02f0) +#define IMX9_CAN_WORD039_OFFSET (0x02f8) +#define IMX9_CAN_WORD139_OFFSET (0x02fc) +#define IMX9_CAN_CS40_OFFSET (0x0300) +#define IMX9_CAN_WORD040_OFFSET (0x0308) +#define IMX9_CAN_WORD140_OFFSET (0x030c) +#define IMX9_CAN_CS41_OFFSET (0x0310) +#define IMX9_CAN_WORD041_OFFSET (0x0318) +#define IMX9_CAN_WORD141_OFFSET (0x031c) +#define IMX9_CAN_CS42_OFFSET (0x0320) +#define IMX9_CAN_WORD042_OFFSET (0x0328) +#define IMX9_CAN_WORD142_OFFSET (0x032c) +#define IMX9_CAN_CS43_OFFSET (0x0330) +#define IMX9_CAN_WORD043_OFFSET (0x0338) +#define IMX9_CAN_WORD143_OFFSET (0x033c) +#define IMX9_CAN_CS44_OFFSET (0x0340) +#define IMX9_CAN_WORD044_OFFSET (0x0348) +#define IMX9_CAN_WORD144_OFFSET (0x034c) +#define IMX9_CAN_CS45_OFFSET (0x0350) +#define IMX9_CAN_WORD045_OFFSET (0x0358) +#define IMX9_CAN_WORD145_OFFSET (0x035c) +#define IMX9_CAN_CS46_OFFSET (0x0360) +#define IMX9_CAN_WORD046_OFFSET (0x0368) +#define IMX9_CAN_WORD146_OFFSET (0x036c) +#define IMX9_CAN_CS47_OFFSET (0x0370) +#define IMX9_CAN_WORD047_OFFSET (0x0378) +#define IMX9_CAN_WORD147_OFFSET (0x037c) +#define IMX9_CAN_CS48_OFFSET (0x0380) +#define IMX9_CAN_WORD048_OFFSET (0x0388) +#define IMX9_CAN_WORD148_OFFSET (0x038c) +#define IMX9_CAN_CS49_OFFSET (0x0390) +#define IMX9_CAN_WORD049_OFFSET (0x0398) +#define IMX9_CAN_WORD149_OFFSET (0x039c) +#define IMX9_CAN_CS50_OFFSET (0x03a0) +#define IMX9_CAN_WORD050_OFFSET (0x03a8) +#define IMX9_CAN_WORD150_OFFSET (0x03ac) +#define IMX9_CAN_CS51_OFFSET (0x03b0) +#define IMX9_CAN_WORD051_OFFSET (0x03b8) +#define IMX9_CAN_WORD151_OFFSET (0x03bc) +#define IMX9_CAN_CS52_OFFSET (0x03c0) +#define IMX9_CAN_WORD052_OFFSET (0x03c8) +#define IMX9_CAN_WORD152_OFFSET (0x03cc) +#define IMX9_CAN_CS53_OFFSET (0x03d0) +#define IMX9_CAN_WORD053_OFFSET (0x03d8) +#define IMX9_CAN_WORD153_OFFSET (0x03dc) +#define IMX9_CAN_CS54_OFFSET (0x03e0) +#define IMX9_CAN_WORD054_OFFSET (0x03e8) +#define IMX9_CAN_WORD154_OFFSET (0x03ec) +#define IMX9_CAN_CS55_OFFSET (0x03f0) +#define IMX9_CAN_WORD055_OFFSET (0x03f8) +#define IMX9_CAN_WORD155_OFFSET (0x03fc) +#define IMX9_CAN_CS56_OFFSET (0x0400) +#define IMX9_CAN_WORD056_OFFSET (0x0408) +#define IMX9_CAN_WORD156_OFFSET (0x040c) +#define IMX9_CAN_CS57_OFFSET (0x0410) +#define IMX9_CAN_WORD057_OFFSET (0x0418) +#define IMX9_CAN_WORD157_OFFSET (0x041c) +#define IMX9_CAN_CS58_OFFSET (0x0420) +#define IMX9_CAN_WORD058_OFFSET (0x0428) +#define IMX9_CAN_WORD158_OFFSET (0x042c) +#define IMX9_CAN_CS59_OFFSET (0x0430) +#define IMX9_CAN_WORD059_OFFSET (0x0438) +#define IMX9_CAN_WORD159_OFFSET (0x043c) +#define IMX9_CAN_CS60_OFFSET (0x0440) +#define IMX9_CAN_WORD060_OFFSET (0x0448) +#define IMX9_CAN_WORD160_OFFSET (0x044c) +#define IMX9_CAN_CS61_OFFSET (0x0450) +#define IMX9_CAN_WORD061_OFFSET (0x0458) +#define IMX9_CAN_WORD161_OFFSET (0x045c) +#define IMX9_CAN_CS62_OFFSET (0x0460) +#define IMX9_CAN_WORD062_OFFSET (0x0468) +#define IMX9_CAN_WORD162_OFFSET (0x046c) +#define IMX9_CAN_CS63_OFFSET (0x0470) +#define IMX9_CAN_WORD063_OFFSET (0x0478) +#define IMX9_CAN_WORD163_OFFSET (0x047c) +#define IMX9_CAN_CS64_OFFSET (0x0480) +#define IMX9_CAN_WORD064_OFFSET (0x0488) +#define IMX9_CAN_WORD164_OFFSET (0x048c) +#define IMX9_CAN_CS65_OFFSET (0x0490) +#define IMX9_CAN_WORD065_OFFSET (0x0498) +#define IMX9_CAN_WORD165_OFFSET (0x049c) +#define IMX9_CAN_CS66_OFFSET (0x04a0) +#define IMX9_CAN_WORD066_OFFSET (0x04a8) +#define IMX9_CAN_WORD166_OFFSET (0x04ac) +#define IMX9_CAN_CS67_OFFSET (0x04b0) +#define IMX9_CAN_WORD067_OFFSET (0x04b8) +#define IMX9_CAN_WORD167_OFFSET (0x04bc) +#define IMX9_CAN_CS68_OFFSET (0x04c0) +#define IMX9_CAN_WORD068_OFFSET (0x04c8) +#define IMX9_CAN_WORD168_OFFSET (0x04cc) +#define IMX9_CAN_CS69_OFFSET (0x04d0) +#define IMX9_CAN_WORD069_OFFSET (0x04d8) +#define IMX9_CAN_WORD169_OFFSET (0x04dc) +#define IMX9_CAN_CS70_OFFSET (0x04e0) +#define IMX9_CAN_WORD070_OFFSET (0x04e8) +#define IMX9_CAN_WORD170_OFFSET (0x04ec) +#define IMX9_CAN_CS71_OFFSET (0x04f0) +#define IMX9_CAN_WORD071_OFFSET (0x04f8) +#define IMX9_CAN_WORD171_OFFSET (0x04fc) +#define IMX9_CAN_CS72_OFFSET (0x0500) +#define IMX9_CAN_WORD072_OFFSET (0x0508) +#define IMX9_CAN_WORD172_OFFSET (0x050c) +#define IMX9_CAN_CS73_OFFSET (0x0510) +#define IMX9_CAN_WORD073_OFFSET (0x0518) +#define IMX9_CAN_WORD173_OFFSET (0x051c) +#define IMX9_CAN_CS74_OFFSET (0x0520) +#define IMX9_CAN_WORD074_OFFSET (0x0528) +#define IMX9_CAN_WORD174_OFFSET (0x052c) +#define IMX9_CAN_CS75_OFFSET (0x0530) +#define IMX9_CAN_WORD075_OFFSET (0x0538) +#define IMX9_CAN_WORD175_OFFSET (0x053c) +#define IMX9_CAN_CS76_OFFSET (0x0540) +#define IMX9_CAN_WORD076_OFFSET (0x0548) +#define IMX9_CAN_WORD176_OFFSET (0x054c) +#define IMX9_CAN_CS77_OFFSET (0x0550) +#define IMX9_CAN_WORD077_OFFSET (0x0558) +#define IMX9_CAN_WORD177_OFFSET (0x055c) +#define IMX9_CAN_CS78_OFFSET (0x0560) +#define IMX9_CAN_WORD078_OFFSET (0x0568) +#define IMX9_CAN_WORD178_OFFSET (0x056c) +#define IMX9_CAN_CS79_OFFSET (0x0570) +#define IMX9_CAN_WORD079_OFFSET (0x0578) +#define IMX9_CAN_WORD179_OFFSET (0x057c) +#define IMX9_CAN_CS80_OFFSET (0x0580) +#define IMX9_CAN_WORD080_OFFSET (0x0588) +#define IMX9_CAN_WORD180_OFFSET (0x058c) +#define IMX9_CAN_CS81_OFFSET (0x0590) +#define IMX9_CAN_WORD081_OFFSET (0x0598) +#define IMX9_CAN_WORD181_OFFSET (0x059c) +#define IMX9_CAN_CS82_OFFSET (0x05a0) +#define IMX9_CAN_WORD082_OFFSET (0x05a8) +#define IMX9_CAN_WORD182_OFFSET (0x05ac) +#define IMX9_CAN_CS83_OFFSET (0x05b0) +#define IMX9_CAN_WORD083_OFFSET (0x05b8) +#define IMX9_CAN_WORD183_OFFSET (0x05bc) +#define IMX9_CAN_CS84_OFFSET (0x05c0) +#define IMX9_CAN_WORD084_OFFSET (0x05c8) +#define IMX9_CAN_WORD184_OFFSET (0x05cc) +#define IMX9_CAN_CS85_OFFSET (0x05d0) +#define IMX9_CAN_WORD085_OFFSET (0x05d8) +#define IMX9_CAN_WORD185_OFFSET (0x05dc) +#define IMX9_CAN_CS86_OFFSET (0x05e0) +#define IMX9_CAN_WORD086_OFFSET (0x05e8) +#define IMX9_CAN_WORD186_OFFSET (0x05ec) +#define IMX9_CAN_CS87_OFFSET (0x05f0) +#define IMX9_CAN_WORD087_OFFSET (0x05f8) +#define IMX9_CAN_WORD187_OFFSET (0x05fc) +#define IMX9_CAN_CS88_OFFSET (0x0600) +#define IMX9_CAN_WORD088_OFFSET (0x0608) +#define IMX9_CAN_WORD188_OFFSET (0x060c) +#define IMX9_CAN_CS89_OFFSET (0x0610) +#define IMX9_CAN_WORD089_OFFSET (0x0618) +#define IMX9_CAN_WORD189_OFFSET (0x061c) +#define IMX9_CAN_CS90_OFFSET (0x0620) +#define IMX9_CAN_WORD090_OFFSET (0x0628) +#define IMX9_CAN_WORD190_OFFSET (0x062c) +#define IMX9_CAN_CS91_OFFSET (0x0630) +#define IMX9_CAN_WORD091_OFFSET (0x0638) +#define IMX9_CAN_WORD191_OFFSET (0x063c) +#define IMX9_CAN_CS92_OFFSET (0x0640) +#define IMX9_CAN_WORD092_OFFSET (0x0648) +#define IMX9_CAN_WORD192_OFFSET (0x064c) +#define IMX9_CAN_CS93_OFFSET (0x0650) +#define IMX9_CAN_WORD093_OFFSET (0x0658) +#define IMX9_CAN_WORD193_OFFSET (0x065c) +#define IMX9_CAN_CS94_OFFSET (0x0660) +#define IMX9_CAN_WORD094_OFFSET (0x0668) +#define IMX9_CAN_WORD194_OFFSET (0x066c) +#define IMX9_CAN_CS95_OFFSET (0x0670) +#define IMX9_CAN_WORD095_OFFSET (0x0678) +#define IMX9_CAN_WORD195_OFFSET (0x067c) +#define IMX9_CAN_MECR_OFFSET (0x0ae0) +#define IMX9_CAN_ERRIAR_OFFSET (0x0ae4) +#define IMX9_CAN_ERRIDPR_OFFSET (0x0ae8) +#define IMX9_CAN_ERRIPPR_OFFSET (0x0aec) +#define IMX9_CAN_RERRAR_OFFSET (0x0af0) +#define IMX9_CAN_RERRDR_OFFSET (0x0af4) +#define IMX9_CAN_RERRSYNR_OFFSET (0x0af8) +#define IMX9_CAN_ERRSR_OFFSET (0x0afc) +#define IMX9_CAN_EPRS_OFFSET (0x0bf0) +#define IMX9_CAN_ENCBT_OFFSET (0x0bf4) +#define IMX9_CAN_EDCBT_OFFSET (0x0bf8) +#define IMX9_CAN_ETDC_OFFSET (0x0bfc) +#define IMX9_CAN_FDCTRL_OFFSET (0x0c00) +#define IMX9_CAN_FDCBT_OFFSET (0x0c04) +#define IMX9_CAN_FDCRC_OFFSET (0x0c08) +#define IMX9_CAN_ERFCR_OFFSET (0x0c0c) +#define IMX9_CAN_ERFIER_OFFSET (0x0c10) +#define IMX9_CAN_ERFSR_OFFSET (0x0c14) +#define IMX9_CAN_RXIMR_OFFSET(n) (0x0880+((n)<<2)) /* Rn Individual Mask Registers */ +#define IMX9_CAN_RXIMR0_OFFSET (0x0880) +#define IMX9_CAN_RXIMR1_OFFSET (0x0884) +#define IMX9_CAN_RXIMR2_OFFSET (0x0888) +#define IMX9_CAN_RXIMR3_OFFSET (0x088c) +#define IMX9_CAN_RXIMR4_OFFSET (0x0890) +#define IMX9_CAN_RXIMR5_OFFSET (0x0894) +#define IMX9_CAN_RXIMR6_OFFSET (0x0898) +#define IMX9_CAN_RXIMR7_OFFSET (0x089c) +#define IMX9_CAN_RXIMR8_OFFSET (0x08a0) +#define IMX9_CAN_RXIMR9_OFFSET (0x08a4) +#define IMX9_CAN_RXIMR10_OFFSET (0x08a8) +#define IMX9_CAN_RXIMR11_OFFSET (0x08ac) +#define IMX9_CAN_RXIMR12_OFFSET (0x08b0) +#define IMX9_CAN_RXIMR13_OFFSET (0x08b4) +#define IMX9_CAN_RXIMR14_OFFSET (0x08b8) +#define IMX9_CAN_RXIMR15_OFFSET (0x08bc) +#define IMX9_CAN_RXIMR16_OFFSET (0x08c0) +#define IMX9_CAN_RXIMR17_OFFSET (0x08c4) +#define IMX9_CAN_RXIMR18_OFFSET (0x08c8) +#define IMX9_CAN_RXIMR19_OFFSET (0x08cc) +#define IMX9_CAN_RXIMR20_OFFSET (0x08d0) +#define IMX9_CAN_RXIMR21_OFFSET (0x08d4) +#define IMX9_CAN_RXIMR22_OFFSET (0x08d8) +#define IMX9_CAN_RXIMR23_OFFSET (0x08dc) +#define IMX9_CAN_RXIMR24_OFFSET (0x08e0) +#define IMX9_CAN_RXIMR25_OFFSET (0x08e4) +#define IMX9_CAN_RXIMR26_OFFSET (0x08e8) +#define IMX9_CAN_RXIMR27_OFFSET (0x08ec) +#define IMX9_CAN_RXIMR28_OFFSET (0x08f0) +#define IMX9_CAN_RXIMR29_OFFSET (0x08f4) +#define IMX9_CAN_RXIMR30_OFFSET (0x08f8) +#define IMX9_CAN_RXIMR31_OFFSET (0x08fc) +#define IMX9_CAN_RXIMR32_OFFSET (0x0900) +#define IMX9_CAN_RXIMR33_OFFSET (0x0904) +#define IMX9_CAN_RXIMR34_OFFSET (0x0908) +#define IMX9_CAN_RXIMR35_OFFSET (0x090c) +#define IMX9_CAN_RXIMR36_OFFSET (0x0910) +#define IMX9_CAN_RXIMR37_OFFSET (0x0914) +#define IMX9_CAN_RXIMR38_OFFSET (0x0918) +#define IMX9_CAN_RXIMR39_OFFSET (0x091c) +#define IMX9_CAN_RXIMR40_OFFSET (0x0920) +#define IMX9_CAN_RXIMR41_OFFSET (0x0924) +#define IMX9_CAN_RXIMR42_OFFSET (0x0928) +#define IMX9_CAN_RXIMR43_OFFSET (0x092c) +#define IMX9_CAN_RXIMR44_OFFSET (0x0930) +#define IMX9_CAN_RXIMR45_OFFSET (0x0934) +#define IMX9_CAN_RXIMR46_OFFSET (0x0938) +#define IMX9_CAN_RXIMR47_OFFSET (0x093c) +#define IMX9_CAN_RXIMR48_OFFSET (0x0940) +#define IMX9_CAN_RXIMR49_OFFSET (0x0944) +#define IMX9_CAN_RXIMR50_OFFSET (0x0948) +#define IMX9_CAN_RXIMR51_OFFSET (0x094c) +#define IMX9_CAN_RXIMR52_OFFSET (0x0950) +#define IMX9_CAN_RXIMR53_OFFSET (0x0954) +#define IMX9_CAN_RXIMR54_OFFSET (0x0958) +#define IMX9_CAN_RXIMR55_OFFSET (0x095c) +#define IMX9_CAN_RXIMR56_OFFSET (0x0960) +#define IMX9_CAN_RXIMR57_OFFSET (0x0964) +#define IMX9_CAN_RXIMR58_OFFSET (0x0968) +#define IMX9_CAN_RXIMR59_OFFSET (0x096c) +#define IMX9_CAN_RXIMR60_OFFSET (0x0970) +#define IMX9_CAN_RXIMR61_OFFSET (0x0974) +#define IMX9_CAN_RXIMR62_OFFSET (0x0978) +#define IMX9_CAN_RXIMR63_OFFSET (0x097c) +#define IMX9_CAN_RXIMR64_OFFSET (0x0980) +#define IMX9_CAN_RXIMR65_OFFSET (0x0984) +#define IMX9_CAN_RXIMR66_OFFSET (0x0988) +#define IMX9_CAN_RXIMR67_OFFSET (0x098c) +#define IMX9_CAN_RXIMR68_OFFSET (0x0990) +#define IMX9_CAN_RXIMR69_OFFSET (0x0994) +#define IMX9_CAN_RXIMR70_OFFSET (0x0998) +#define IMX9_CAN_RXIMR71_OFFSET (0x099c) +#define IMX9_CAN_RXIMR72_OFFSET (0x09a0) +#define IMX9_CAN_RXIMR73_OFFSET (0x09a4) +#define IMX9_CAN_RXIMR74_OFFSET (0x09a8) +#define IMX9_CAN_RXIMR75_OFFSET (0x09ac) +#define IMX9_CAN_RXIMR76_OFFSET (0x09b0) +#define IMX9_CAN_RXIMR77_OFFSET (0x09b4) +#define IMX9_CAN_RXIMR78_OFFSET (0x09b8) +#define IMX9_CAN_RXIMR79_OFFSET (0x09bc) +#define IMX9_CAN_RXIMR80_OFFSET (0x09c0) +#define IMX9_CAN_RXIMR81_OFFSET (0x09c4) +#define IMX9_CAN_RXIMR82_OFFSET (0x09c8) +#define IMX9_CAN_RXIMR83_OFFSET (0x09cc) +#define IMX9_CAN_RXIMR84_OFFSET (0x09d0) +#define IMX9_CAN_RXIMR85_OFFSET (0x09d4) +#define IMX9_CAN_RXIMR86_OFFSET (0x09d8) +#define IMX9_CAN_RXIMR87_OFFSET (0x09dc) +#define IMX9_CAN_RXIMR88_OFFSET (0x09e0) +#define IMX9_CAN_RXIMR89_OFFSET (0x09e4) +#define IMX9_CAN_RXIMR90_OFFSET (0x09e8) +#define IMX9_CAN_RXIMR91_OFFSET (0x09ec) +#define IMX9_CAN_RXIMR92_OFFSET (0x09f0) +#define IMX9_CAN_RXIMR93_OFFSET (0x09f4) +#define IMX9_CAN_RXIMR94_OFFSET (0x09f8) +#define IMX9_CAN_RXIMR95_OFFSET (0x09fc) +#define IMX9_CAN_HR_TIME_STAMP0_OFFSET (0x0c30) +#define IMX9_CAN_HR_TIME_STAMP1_OFFSET (0x0c34) +#define IMX9_CAN_HR_TIME_STAMP2_OFFSET (0x0c38) +#define IMX9_CAN_HR_TIME_STAMP3_OFFSET (0x0c3c) +#define IMX9_CAN_HR_TIME_STAMP4_OFFSET (0x0c40) +#define IMX9_CAN_HR_TIME_STAMP5_OFFSET (0x0c44) +#define IMX9_CAN_HR_TIME_STAMP6_OFFSET (0x0c48) +#define IMX9_CAN_HR_TIME_STAMP7_OFFSET (0x0c4c) +#define IMX9_CAN_HR_TIME_STAMP8_OFFSET (0x0c50) +#define IMX9_CAN_HR_TIME_STAMP9_OFFSET (0x0c54) +#define IMX9_CAN_HR_TIME_STAMP10_OFFSET (0x0c58) +#define IMX9_CAN_HR_TIME_STAMP11_OFFSET (0x0c5c) +#define IMX9_CAN_HR_TIME_STAMP12_OFFSET (0x0c60) +#define IMX9_CAN_HR_TIME_STAMP13_OFFSET (0x0c64) +#define IMX9_CAN_HR_TIME_STAMP14_OFFSET (0x0c68) +#define IMX9_CAN_HR_TIME_STAMP15_OFFSET (0x0c6c) +#define IMX9_CAN_HR_TIME_STAMP16_OFFSET (0x0c70) +#define IMX9_CAN_HR_TIME_STAMP17_OFFSET (0x0c74) +#define IMX9_CAN_HR_TIME_STAMP18_OFFSET (0x0c78) +#define IMX9_CAN_HR_TIME_STAMP19_OFFSET (0x0c7c) +#define IMX9_CAN_HR_TIME_STAMP20_OFFSET (0x0c80) +#define IMX9_CAN_HR_TIME_STAMP21_OFFSET (0x0c84) +#define IMX9_CAN_HR_TIME_STAMP22_OFFSET (0x0c88) +#define IMX9_CAN_HR_TIME_STAMP23_OFFSET (0x0c8c) +#define IMX9_CAN_HR_TIME_STAMP24_OFFSET (0x0c90) +#define IMX9_CAN_HR_TIME_STAMP25_OFFSET (0x0c94) +#define IMX9_CAN_HR_TIME_STAMP26_OFFSET (0x0c98) +#define IMX9_CAN_HR_TIME_STAMP27_OFFSET (0x0c9c) +#define IMX9_CAN_HR_TIME_STAMP28_OFFSET (0x0ca0) +#define IMX9_CAN_HR_TIME_STAMP29_OFFSET (0x0ca4) +#define IMX9_CAN_HR_TIME_STAMP30_OFFSET (0x0ca8) +#define IMX9_CAN_HR_TIME_STAMP31_OFFSET (0x0cac) +#define IMX9_CAN_HR_TIME_STAMP32_OFFSET (0x0cb0) +#define IMX9_CAN_HR_TIME_STAMP33_OFFSET (0x0cb4) +#define IMX9_CAN_HR_TIME_STAMP34_OFFSET (0x0cb8) +#define IMX9_CAN_HR_TIME_STAMP35_OFFSET (0x0cbc) +#define IMX9_CAN_HR_TIME_STAMP36_OFFSET (0x0cc0) +#define IMX9_CAN_HR_TIME_STAMP37_OFFSET (0x0cc4) +#define IMX9_CAN_HR_TIME_STAMP38_OFFSET (0x0cc8) +#define IMX9_CAN_HR_TIME_STAMP39_OFFSET (0x0ccc) +#define IMX9_CAN_HR_TIME_STAMP40_OFFSET (0x0cd0) +#define IMX9_CAN_HR_TIME_STAMP41_OFFSET (0x0cd4) +#define IMX9_CAN_HR_TIME_STAMP42_OFFSET (0x0cd8) +#define IMX9_CAN_HR_TIME_STAMP43_OFFSET (0x0cdc) +#define IMX9_CAN_HR_TIME_STAMP44_OFFSET (0x0ce0) +#define IMX9_CAN_HR_TIME_STAMP45_OFFSET (0x0ce4) +#define IMX9_CAN_HR_TIME_STAMP46_OFFSET (0x0ce8) +#define IMX9_CAN_HR_TIME_STAMP47_OFFSET (0x0cec) +#define IMX9_CAN_HR_TIME_STAMP48_OFFSET (0x0cf0) +#define IMX9_CAN_HR_TIME_STAMP49_OFFSET (0x0cf4) +#define IMX9_CAN_HR_TIME_STAMP50_OFFSET (0x0cf8) +#define IMX9_CAN_HR_TIME_STAMP51_OFFSET (0x0cfc) +#define IMX9_CAN_HR_TIME_STAMP52_OFFSET (0x0d00) +#define IMX9_CAN_HR_TIME_STAMP53_OFFSET (0x0d04) +#define IMX9_CAN_HR_TIME_STAMP54_OFFSET (0x0d08) +#define IMX9_CAN_HR_TIME_STAMP55_OFFSET (0x0d0c) +#define IMX9_CAN_HR_TIME_STAMP56_OFFSET (0x0d10) +#define IMX9_CAN_HR_TIME_STAMP57_OFFSET (0x0d14) +#define IMX9_CAN_HR_TIME_STAMP58_OFFSET (0x0d18) +#define IMX9_CAN_HR_TIME_STAMP59_OFFSET (0x0d1c) +#define IMX9_CAN_HR_TIME_STAMP60_OFFSET (0x0d20) +#define IMX9_CAN_HR_TIME_STAMP61_OFFSET (0x0d24) +#define IMX9_CAN_HR_TIME_STAMP62_OFFSET (0x0d28) +#define IMX9_CAN_HR_TIME_STAMP63_OFFSET (0x0d2c) +#define IMX9_CAN_HR_TIME_STAMP64_OFFSET (0x0d30) +#define IMX9_CAN_HR_TIME_STAMP65_OFFSET (0x0d34) +#define IMX9_CAN_HR_TIME_STAMP66_OFFSET (0x0d38) +#define IMX9_CAN_HR_TIME_STAMP67_OFFSET (0x0d3c) +#define IMX9_CAN_HR_TIME_STAMP68_OFFSET (0x0d40) +#define IMX9_CAN_HR_TIME_STAMP69_OFFSET (0x0d44) +#define IMX9_CAN_HR_TIME_STAMP70_OFFSET (0x0d48) +#define IMX9_CAN_HR_TIME_STAMP71_OFFSET (0x0d4c) +#define IMX9_CAN_HR_TIME_STAMP72_OFFSET (0x0d50) +#define IMX9_CAN_HR_TIME_STAMP73_OFFSET (0x0d54) +#define IMX9_CAN_HR_TIME_STAMP74_OFFSET (0x0d58) +#define IMX9_CAN_HR_TIME_STAMP75_OFFSET (0x0d5c) +#define IMX9_CAN_HR_TIME_STAMP76_OFFSET (0x0d60) +#define IMX9_CAN_HR_TIME_STAMP77_OFFSET (0x0d64) +#define IMX9_CAN_HR_TIME_STAMP78_OFFSET (0x0d68) +#define IMX9_CAN_HR_TIME_STAMP79_OFFSET (0x0d6c) +#define IMX9_CAN_HR_TIME_STAMP80_OFFSET (0x0d70) +#define IMX9_CAN_HR_TIME_STAMP81_OFFSET (0x0d74) +#define IMX9_CAN_HR_TIME_STAMP82_OFFSET (0x0d78) +#define IMX9_CAN_HR_TIME_STAMP83_OFFSET (0x0d7c) +#define IMX9_CAN_HR_TIME_STAMP84_OFFSET (0x0d80) +#define IMX9_CAN_HR_TIME_STAMP85_OFFSET (0x0d84) +#define IMX9_CAN_HR_TIME_STAMP86_OFFSET (0x0d88) +#define IMX9_CAN_HR_TIME_STAMP87_OFFSET (0x0d8c) +#define IMX9_CAN_HR_TIME_STAMP88_OFFSET (0x0d90) +#define IMX9_CAN_HR_TIME_STAMP89_OFFSET (0x0d94) +#define IMX9_CAN_HR_TIME_STAMP90_OFFSET (0x0d98) +#define IMX9_CAN_HR_TIME_STAMP91_OFFSET (0x0d9c) +#define IMX9_CAN_HR_TIME_STAMP92_OFFSET (0x0da0) +#define IMX9_CAN_HR_TIME_STAMP93_OFFSET (0x0da4) +#define IMX9_CAN_HR_TIME_STAMP94_OFFSET (0x0da8) +#define IMX9_CAN_HR_TIME_STAMP95_OFFSET (0x0dac) +#define IMX9_CAN_ERFFEL0_OFFSET (0x3000) +#define IMX9_CAN_ERFFEL1_OFFSET (0x3004) +#define IMX9_CAN_ERFFEL2_OFFSET (0x3008) +#define IMX9_CAN_ERFFEL3_OFFSET (0x300c) +#define IMX9_CAN_ERFFEL4_OFFSET (0x3010) +#define IMX9_CAN_ERFFEL5_OFFSET (0x3014) +#define IMX9_CAN_ERFFEL6_OFFSET (0x3018) +#define IMX9_CAN_ERFFEL7_OFFSET (0x301c) +#define IMX9_CAN_ERFFEL8_OFFSET (0x3020) +#define IMX9_CAN_ERFFEL9_OFFSET (0x3024) +#define IMX9_CAN_ERFFEL10_OFFSET (0x3028) +#define IMX9_CAN_ERFFEL11_OFFSET (0x302c) +#define IMX9_CAN_ERFFEL12_OFFSET (0x3030) +#define IMX9_CAN_ERFFEL13_OFFSET (0x3034) +#define IMX9_CAN_ERFFEL14_OFFSET (0x3038) +#define IMX9_CAN_ERFFEL15_OFFSET (0x303c) +#define IMX9_CAN_ERFFEL16_OFFSET (0x3040) +#define IMX9_CAN_ERFFEL17_OFFSET (0x3044) +#define IMX9_CAN_ERFFEL18_OFFSET (0x3048) +#define IMX9_CAN_ERFFEL19_OFFSET (0x304c) +#define IMX9_CAN_ERFFEL20_OFFSET (0x3050) +#define IMX9_CAN_ERFFEL21_OFFSET (0x3054) +#define IMX9_CAN_ERFFEL22_OFFSET (0x3058) +#define IMX9_CAN_ERFFEL23_OFFSET (0x305c) +#define IMX9_CAN_ERFFEL24_OFFSET (0x3060) +#define IMX9_CAN_ERFFEL25_OFFSET (0x3064) +#define IMX9_CAN_ERFFEL26_OFFSET (0x3068) +#define IMX9_CAN_ERFFEL27_OFFSET (0x306c) +#define IMX9_CAN_ERFFEL28_OFFSET (0x3070) +#define IMX9_CAN_ERFFEL29_OFFSET (0x3074) +#define IMX9_CAN_ERFFEL30_OFFSET (0x3078) +#define IMX9_CAN_ERFFEL31_OFFSET (0x307c) +#define IMX9_CAN_ERFFEL32_OFFSET (0x3080) +#define IMX9_CAN_ERFFEL33_OFFSET (0x3084) +#define IMX9_CAN_ERFFEL34_OFFSET (0x3088) +#define IMX9_CAN_ERFFEL35_OFFSET (0x308c) +#define IMX9_CAN_ERFFEL36_OFFSET (0x3090) +#define IMX9_CAN_ERFFEL37_OFFSET (0x3094) +#define IMX9_CAN_ERFFEL38_OFFSET (0x3098) +#define IMX9_CAN_ERFFEL39_OFFSET (0x309c) +#define IMX9_CAN_ERFFEL40_OFFSET (0x30a0) +#define IMX9_CAN_ERFFEL41_OFFSET (0x30a4) +#define IMX9_CAN_ERFFEL42_OFFSET (0x30a8) +#define IMX9_CAN_ERFFEL43_OFFSET (0x30ac) +#define IMX9_CAN_ERFFEL44_OFFSET (0x30b0) +#define IMX9_CAN_ERFFEL45_OFFSET (0x30b4) +#define IMX9_CAN_ERFFEL46_OFFSET (0x30b8) +#define IMX9_CAN_ERFFEL47_OFFSET (0x30bc) +#define IMX9_CAN_ERFFEL48_OFFSET (0x30c0) +#define IMX9_CAN_ERFFEL49_OFFSET (0x30c4) +#define IMX9_CAN_ERFFEL50_OFFSET (0x30c8) +#define IMX9_CAN_ERFFEL51_OFFSET (0x30cc) +#define IMX9_CAN_ERFFEL52_OFFSET (0x30d0) +#define IMX9_CAN_ERFFEL53_OFFSET (0x30d4) +#define IMX9_CAN_ERFFEL54_OFFSET (0x30d8) +#define IMX9_CAN_ERFFEL55_OFFSET (0x30dc) +#define IMX9_CAN_ERFFEL56_OFFSET (0x30e0) +#define IMX9_CAN_ERFFEL57_OFFSET (0x30e4) +#define IMX9_CAN_ERFFEL58_OFFSET (0x30e8) +#define IMX9_CAN_ERFFEL59_OFFSET (0x30ec) +#define IMX9_CAN_ERFFEL60_OFFSET (0x30f0) +#define IMX9_CAN_ERFFEL61_OFFSET (0x30f4) +#define IMX9_CAN_ERFFEL62_OFFSET (0x30f8) +#define IMX9_CAN_ERFFEL63_OFFSET (0x30fc) +#define IMX9_CAN_ERFFEL64_OFFSET (0x3100) +#define IMX9_CAN_ERFFEL65_OFFSET (0x3104) +#define IMX9_CAN_ERFFEL66_OFFSET (0x3108) +#define IMX9_CAN_ERFFEL67_OFFSET (0x310c) +#define IMX9_CAN_ERFFEL68_OFFSET (0x3110) +#define IMX9_CAN_ERFFEL69_OFFSET (0x3114) +#define IMX9_CAN_ERFFEL70_OFFSET (0x3118) +#define IMX9_CAN_ERFFEL71_OFFSET (0x311c) +#define IMX9_CAN_ERFFEL72_OFFSET (0x3120) +#define IMX9_CAN_ERFFEL73_OFFSET (0x3124) +#define IMX9_CAN_ERFFEL74_OFFSET (0x3128) +#define IMX9_CAN_ERFFEL75_OFFSET (0x312c) +#define IMX9_CAN_ERFFEL76_OFFSET (0x3130) +#define IMX9_CAN_ERFFEL77_OFFSET (0x3134) +#define IMX9_CAN_ERFFEL78_OFFSET (0x3138) +#define IMX9_CAN_ERFFEL79_OFFSET (0x313c) +#define IMX9_CAN_ERFFEL80_OFFSET (0x3140) +#define IMX9_CAN_ERFFEL81_OFFSET (0x3144) +#define IMX9_CAN_ERFFEL82_OFFSET (0x3148) +#define IMX9_CAN_ERFFEL83_OFFSET (0x314c) +#define IMX9_CAN_ERFFEL84_OFFSET (0x3150) +#define IMX9_CAN_ERFFEL85_OFFSET (0x3154) +#define IMX9_CAN_ERFFEL86_OFFSET (0x3158) +#define IMX9_CAN_ERFFEL87_OFFSET (0x315c) +#define IMX9_CAN_ERFFEL88_OFFSET (0x3160) +#define IMX9_CAN_ERFFEL89_OFFSET (0x3164) +#define IMX9_CAN_ERFFEL90_OFFSET (0x3168) +#define IMX9_CAN_ERFFEL91_OFFSET (0x316c) +#define IMX9_CAN_ERFFEL92_OFFSET (0x3170) +#define IMX9_CAN_ERFFEL93_OFFSET (0x3174) +#define IMX9_CAN_ERFFEL94_OFFSET (0x3178) +#define IMX9_CAN_ERFFEL95_OFFSET (0x317c) +#define IMX9_CAN_ERFFEL96_OFFSET (0x3180) +#define IMX9_CAN_ERFFEL97_OFFSET (0x3184) +#define IMX9_CAN_ERFFEL98_OFFSET (0x3188) +#define IMX9_CAN_ERFFEL99_OFFSET (0x318c) +#define IMX9_CAN_ERFFEL100_OFFSET (0x3190) +#define IMX9_CAN_ERFFEL101_OFFSET (0x3194) +#define IMX9_CAN_ERFFEL102_OFFSET (0x3198) +#define IMX9_CAN_ERFFEL103_OFFSET (0x319c) +#define IMX9_CAN_ERFFEL104_OFFSET (0x31a0) +#define IMX9_CAN_ERFFEL105_OFFSET (0x31a4) +#define IMX9_CAN_ERFFEL106_OFFSET (0x31a8) +#define IMX9_CAN_ERFFEL107_OFFSET (0x31ac) +#define IMX9_CAN_ERFFEL108_OFFSET (0x31b0) +#define IMX9_CAN_ERFFEL109_OFFSET (0x31b4) +#define IMX9_CAN_ERFFEL110_OFFSET (0x31b8) +#define IMX9_CAN_ERFFEL111_OFFSET (0x31bc) +#define IMX9_CAN_ERFFEL112_OFFSET (0x31c0) +#define IMX9_CAN_ERFFEL113_OFFSET (0x31c4) +#define IMX9_CAN_ERFFEL114_OFFSET (0x31c8) +#define IMX9_CAN_ERFFEL115_OFFSET (0x31cc) +#define IMX9_CAN_ERFFEL116_OFFSET (0x31d0) +#define IMX9_CAN_ERFFEL117_OFFSET (0x31d4) +#define IMX9_CAN_ERFFEL118_OFFSET (0x31d8) +#define IMX9_CAN_ERFFEL119_OFFSET (0x31dc) +#define IMX9_CAN_ERFFEL120_OFFSET (0x31e0) +#define IMX9_CAN_ERFFEL121_OFFSET (0x31e4) +#define IMX9_CAN_ERFFEL122_OFFSET (0x31e8) +#define IMX9_CAN_ERFFEL123_OFFSET (0x31ec) +#define IMX9_CAN_ERFFEL124_OFFSET (0x31f0) +#define IMX9_CAN_ERFFEL125_OFFSET (0x31f4) +#define IMX9_CAN_ERFFEL126_OFFSET (0x31f8) +#define IMX9_CAN_ERFFEL127_OFFSET (0x31fc) + +#define IMX9_CAN_MB_OFFSET IMX9_CAN_CS0_OFFSET +#define IMX9_CAN_MB_END 0x0ADF + +#define IMX9_CAN_MB2_OFFSET 0x0C20 /* CAN MB2 register */ +#define IMX9_CAN_MB2_END 0x31FF + +/* CAN Register Addresses ***************************************************/ +#define IMX9_CAN_MCR (IMX9_CAN_BASE + IMX9_CAN_MCR_OFFSET) +#define IMX9_CAN_CTRL1 (IMX9_CAN_BASE + IMX9_CAN_CTRL1_OFFSET) +#define IMX9_CAN_TIMER (IMX9_CAN_BASE + IMX9_CAN_TIMER_OFFSET) +#define IMX9_CAN_RXMGMASK (IMX9_CAN_BASE + IMX9_CAN_RXMGMASK_OFFSET) +#define IMX9_CAN_RX14MASK (IMX9_CAN_BASE + IMX9_CAN_RX14MASK_OFFSET) +#define IMX9_CAN_RX15MASK (IMX9_CAN_BASE + IMX9_CAN_RX15MASK_OFFSET) +#define IMX9_CAN_ECR (IMX9_CAN_BASE + IMX9_CAN_ECR_OFFSET) +#define IMX9_CAN_ESR1 (IMX9_CAN_BASE + IMX9_CAN_ESR1_OFFSET) +#define IMX9_CAN_IMASK2 (IMX9_CAN_BASE + IMX9_CAN_IMASK2_OFFSET) +#define IMX9_CAN_IMASK1 (IMX9_CAN_BASE + IMX9_CAN_IMASK1_OFFSET) +#define IMX9_CAN_IFLAG2 (IMX9_CAN_BASE + IMX9_CAN_IFLAG2_OFFSET) +#define IMX9_CAN_IFLAG1 (IMX9_CAN_BASE + IMX9_CAN_IFLAG1_OFFSET) +#define IMX9_CAN_CTRL2 (IMX9_CAN_BASE + IMX9_CAN_CTRL2_OFFSET) +#define IMX9_CAN_ESR2 (IMX9_CAN_BASE + IMX9_CAN_ESR2_OFFSET) +#define IMX9_CAN_CRCR (IMX9_CAN_BASE + IMX9_CAN_CRCR_OFFSET) +#define IMX9_CAN_RXFGMASK (IMX9_CAN_BASE + IMX9_CAN_RXFGMASK_OFFSET) +#define IMX9_CAN_RXFIR (IMX9_CAN_BASE + IMX9_CAN_RXFIR_OFFSET) +#define IMX9_CAN_CBT (IMX9_CAN_BASE + IMX9_CAN_CBT_OFFSET) +#define IMX9_CAN_IMASK3 (IMX9_CAN_BASE + IMX9_CAN_IMASK3_OFFSET) +#define IMX9_CAN_IFLAG3 (IMX9_CAN_BASE + IMX9_CAN_IFLAG3_OFFSET) +#define IMX9_CAN_CS0 (IMX9_CAN_BASE + IMX9_CAN_CS0_OFFSET) +#define IMX9_CAN_WORD00 (IMX9_CAN_BASE + IMX9_CAN_WORD00_OFFSET) +#define IMX9_CAN_WORD10 (IMX9_CAN_BASE + IMX9_CAN_WORD10_OFFSET) +#define IMX9_CAN_CS1 (IMX9_CAN_BASE + IMX9_CAN_CS1_OFFSET) +#define IMX9_CAN_WORD01 (IMX9_CAN_BASE + IMX9_CAN_WORD01_OFFSET) +#define IMX9_CAN_WORD11 (IMX9_CAN_BASE + IMX9_CAN_WORD11_OFFSET) +#define IMX9_CAN_CS2 (IMX9_CAN_BASE + IMX9_CAN_CS2_OFFSET) +#define IMX9_CAN_WORD02 (IMX9_CAN_BASE + IMX9_CAN_WORD02_OFFSET) +#define IMX9_CAN_WORD12 (IMX9_CAN_BASE + IMX9_CAN_WORD12_OFFSET) +#define IMX9_CAN_CS3 (IMX9_CAN_BASE + IMX9_CAN_CS3_OFFSET) +#define IMX9_CAN_WORD03 (IMX9_CAN_BASE + IMX9_CAN_WORD03_OFFSET) +#define IMX9_CAN_WORD13 (IMX9_CAN_BASE + IMX9_CAN_WORD13_OFFSET) +#define IMX9_CAN_CS4 (IMX9_CAN_BASE + IMX9_CAN_CS4_OFFSET) +#define IMX9_CAN_WORD04 (IMX9_CAN_BASE + IMX9_CAN_WORD04_OFFSET) +#define IMX9_CAN_WORD14 (IMX9_CAN_BASE + IMX9_CAN_WORD14_OFFSET) +#define IMX9_CAN_CS5 (IMX9_CAN_BASE + IMX9_CAN_CS5_OFFSET) +#define IMX9_CAN_WORD05 (IMX9_CAN_BASE + IMX9_CAN_WORD05_OFFSET) +#define IMX9_CAN_WORD15 (IMX9_CAN_BASE + IMX9_CAN_WORD15_OFFSET) +#define IMX9_CAN_CS6 (IMX9_CAN_BASE + IMX9_CAN_CS6_OFFSET) +#define IMX9_CAN_WORD06 (IMX9_CAN_BASE + IMX9_CAN_WORD06_OFFSET) +#define IMX9_CAN_WORD16 (IMX9_CAN_BASE + IMX9_CAN_WORD16_OFFSET) +#define IMX9_CAN_CS7 (IMX9_CAN_BASE + IMX9_CAN_CS7_OFFSET) +#define IMX9_CAN_WORD07 (IMX9_CAN_BASE + IMX9_CAN_WORD07_OFFSET) +#define IMX9_CAN_WORD17 (IMX9_CAN_BASE + IMX9_CAN_WORD17_OFFSET) +#define IMX9_CAN_CS8 (IMX9_CAN_BASE + IMX9_CAN_CS8_OFFSET) +#define IMX9_CAN_WORD08 (IMX9_CAN_BASE + IMX9_CAN_WORD08_OFFSET) +#define IMX9_CAN_WORD18 (IMX9_CAN_BASE + IMX9_CAN_WORD18_OFFSET) +#define IMX9_CAN_CS9 (IMX9_CAN_BASE + IMX9_CAN_CS9_OFFSET) +#define IMX9_CAN_WORD09 (IMX9_CAN_BASE + IMX9_CAN_WORD09_OFFSET) +#define IMX9_CAN_WORD19 (IMX9_CAN_BASE + IMX9_CAN_WORD19_OFFSET) +#define IMX9_CAN_CS10 (IMX9_CAN_BASE + IMX9_CAN_CS10_OFFSET) +#define IMX9_CAN_WORD010 (IMX9_CAN_BASE + IMX9_CAN_WORD010_OFFSET) +#define IMX9_CAN_WORD110 (IMX9_CAN_BASE + IMX9_CAN_WORD110_OFFSET) +#define IMX9_CAN_CS11 (IMX9_CAN_BASE + IMX9_CAN_CS11_OFFSET) +#define IMX9_CAN_WORD011 (IMX9_CAN_BASE + IMX9_CAN_WORD011_OFFSET) +#define IMX9_CAN_WORD111 (IMX9_CAN_BASE + IMX9_CAN_WORD111_OFFSET) +#define IMX9_CAN_CS12 (IMX9_CAN_BASE + IMX9_CAN_CS12_OFFSET) +#define IMX9_CAN_WORD012 (IMX9_CAN_BASE + IMX9_CAN_WORD012_OFFSET) +#define IMX9_CAN_WORD112 (IMX9_CAN_BASE + IMX9_CAN_WORD112_OFFSET) +#define IMX9_CAN_CS13 (IMX9_CAN_BASE + IMX9_CAN_CS13_OFFSET) +#define IMX9_CAN_WORD013 (IMX9_CAN_BASE + IMX9_CAN_WORD013_OFFSET) +#define IMX9_CAN_WORD113 (IMX9_CAN_BASE + IMX9_CAN_WORD113_OFFSET) +#define IMX9_CAN_CS14 (IMX9_CAN_BASE + IMX9_CAN_CS14_OFFSET) +#define IMX9_CAN_WORD014 (IMX9_CAN_BASE + IMX9_CAN_WORD014_OFFSET) +#define IMX9_CAN_WORD114 (IMX9_CAN_BASE + IMX9_CAN_WORD114_OFFSET) +#define IMX9_CAN_CS15 (IMX9_CAN_BASE + IMX9_CAN_CS15_OFFSET) +#define IMX9_CAN_WORD015 (IMX9_CAN_BASE + IMX9_CAN_WORD015_OFFSET) +#define IMX9_CAN_WORD115 (IMX9_CAN_BASE + IMX9_CAN_WORD115_OFFSET) +#define IMX9_CAN_CS16 (IMX9_CAN_BASE + IMX9_CAN_CS16_OFFSET) +#define IMX9_CAN_WORD016 (IMX9_CAN_BASE + IMX9_CAN_WORD016_OFFSET) +#define IMX9_CAN_WORD116 (IMX9_CAN_BASE + IMX9_CAN_WORD116_OFFSET) +#define IMX9_CAN_CS17 (IMX9_CAN_BASE + IMX9_CAN_CS17_OFFSET) +#define IMX9_CAN_WORD017 (IMX9_CAN_BASE + IMX9_CAN_WORD017_OFFSET) +#define IMX9_CAN_WORD117 (IMX9_CAN_BASE + IMX9_CAN_WORD117_OFFSET) +#define IMX9_CAN_CS18 (IMX9_CAN_BASE + IMX9_CAN_CS18_OFFSET) +#define IMX9_CAN_WORD018 (IMX9_CAN_BASE + IMX9_CAN_WORD018_OFFSET) +#define IMX9_CAN_WORD118 (IMX9_CAN_BASE + IMX9_CAN_WORD118_OFFSET) +#define IMX9_CAN_CS19 (IMX9_CAN_BASE + IMX9_CAN_CS19_OFFSET) +#define IMX9_CAN_WORD019 (IMX9_CAN_BASE + IMX9_CAN_WORD019_OFFSET) +#define IMX9_CAN_WORD119 (IMX9_CAN_BASE + IMX9_CAN_WORD119_OFFSET) +#define IMX9_CAN_CS20 (IMX9_CAN_BASE + IMX9_CAN_CS20_OFFSET) +#define IMX9_CAN_WORD020 (IMX9_CAN_BASE + IMX9_CAN_WORD020_OFFSET) +#define IMX9_CAN_WORD120 (IMX9_CAN_BASE + IMX9_CAN_WORD120_OFFSET) +#define IMX9_CAN_CS21 (IMX9_CAN_BASE + IMX9_CAN_CS21_OFFSET) +#define IMX9_CAN_WORD021 (IMX9_CAN_BASE + IMX9_CAN_WORD021_OFFSET) +#define IMX9_CAN_WORD121 (IMX9_CAN_BASE + IMX9_CAN_WORD121_OFFSET) +#define IMX9_CAN_CS22 (IMX9_CAN_BASE + IMX9_CAN_CS22_OFFSET) +#define IMX9_CAN_WORD022 (IMX9_CAN_BASE + IMX9_CAN_WORD022_OFFSET) +#define IMX9_CAN_WORD122 (IMX9_CAN_BASE + IMX9_CAN_WORD122_OFFSET) +#define IMX9_CAN_CS23 (IMX9_CAN_BASE + IMX9_CAN_CS23_OFFSET) +#define IMX9_CAN_WORD023 (IMX9_CAN_BASE + IMX9_CAN_WORD023_OFFSET) +#define IMX9_CAN_WORD123 (IMX9_CAN_BASE + IMX9_CAN_WORD123_OFFSET) +#define IMX9_CAN_CS24 (IMX9_CAN_BASE + IMX9_CAN_CS24_OFFSET) +#define IMX9_CAN_WORD024 (IMX9_CAN_BASE + IMX9_CAN_WORD024_OFFSET) +#define IMX9_CAN_WORD124 (IMX9_CAN_BASE + IMX9_CAN_WORD124_OFFSET) +#define IMX9_CAN_CS25 (IMX9_CAN_BASE + IMX9_CAN_CS25_OFFSET) +#define IMX9_CAN_WORD025 (IMX9_CAN_BASE + IMX9_CAN_WORD025_OFFSET) +#define IMX9_CAN_WORD125 (IMX9_CAN_BASE + IMX9_CAN_WORD125_OFFSET) +#define IMX9_CAN_CS26 (IMX9_CAN_BASE + IMX9_CAN_CS26_OFFSET) +#define IMX9_CAN_WORD026 (IMX9_CAN_BASE + IMX9_CAN_WORD026_OFFSET) +#define IMX9_CAN_WORD126 (IMX9_CAN_BASE + IMX9_CAN_WORD126_OFFSET) +#define IMX9_CAN_CS27 (IMX9_CAN_BASE + IMX9_CAN_CS27_OFFSET) +#define IMX9_CAN_WORD027 (IMX9_CAN_BASE + IMX9_CAN_WORD027_OFFSET) +#define IMX9_CAN_WORD127 (IMX9_CAN_BASE + IMX9_CAN_WORD127_OFFSET) +#define IMX9_CAN_CS28 (IMX9_CAN_BASE + IMX9_CAN_CS28_OFFSET) +#define IMX9_CAN_WORD028 (IMX9_CAN_BASE + IMX9_CAN_WORD028_OFFSET) +#define IMX9_CAN_WORD128 (IMX9_CAN_BASE + IMX9_CAN_WORD128_OFFSET) +#define IMX9_CAN_CS29 (IMX9_CAN_BASE + IMX9_CAN_CS29_OFFSET) +#define IMX9_CAN_WORD029 (IMX9_CAN_BASE + IMX9_CAN_WORD029_OFFSET) +#define IMX9_CAN_WORD129 (IMX9_CAN_BASE + IMX9_CAN_WORD129_OFFSET) +#define IMX9_CAN_CS30 (IMX9_CAN_BASE + IMX9_CAN_CS30_OFFSET) +#define IMX9_CAN_WORD030 (IMX9_CAN_BASE + IMX9_CAN_WORD030_OFFSET) +#define IMX9_CAN_WORD130 (IMX9_CAN_BASE + IMX9_CAN_WORD130_OFFSET) +#define IMX9_CAN_CS31 (IMX9_CAN_BASE + IMX9_CAN_CS31_OFFSET) +#define IMX9_CAN_WORD031 (IMX9_CAN_BASE + IMX9_CAN_WORD031_OFFSET) +#define IMX9_CAN_WORD131 (IMX9_CAN_BASE + IMX9_CAN_WORD131_OFFSET) +#define IMX9_CAN_CS32 (IMX9_CAN_BASE + IMX9_CAN_CS32_OFFSET) +#define IMX9_CAN_WORD032 (IMX9_CAN_BASE + IMX9_CAN_WORD032_OFFSET) +#define IMX9_CAN_WORD132 (IMX9_CAN_BASE + IMX9_CAN_WORD132_OFFSET) +#define IMX9_CAN_CS33 (IMX9_CAN_BASE + IMX9_CAN_CS33_OFFSET) +#define IMX9_CAN_WORD033 (IMX9_CAN_BASE + IMX9_CAN_WORD033_OFFSET) +#define IMX9_CAN_WORD133 (IMX9_CAN_BASE + IMX9_CAN_WORD133_OFFSET) +#define IMX9_CAN_CS34 (IMX9_CAN_BASE + IMX9_CAN_CS34_OFFSET) +#define IMX9_CAN_WORD034 (IMX9_CAN_BASE + IMX9_CAN_WORD034_OFFSET) +#define IMX9_CAN_WORD134 (IMX9_CAN_BASE + IMX9_CAN_WORD134_OFFSET) +#define IMX9_CAN_CS35 (IMX9_CAN_BASE + IMX9_CAN_CS35_OFFSET) +#define IMX9_CAN_WORD035 (IMX9_CAN_BASE + IMX9_CAN_WORD035_OFFSET) +#define IMX9_CAN_WORD135 (IMX9_CAN_BASE + IMX9_CAN_WORD135_OFFSET) +#define IMX9_CAN_CS36 (IMX9_CAN_BASE + IMX9_CAN_CS36_OFFSET) +#define IMX9_CAN_WORD036 (IMX9_CAN_BASE + IMX9_CAN_WORD036_OFFSET) +#define IMX9_CAN_WORD136 (IMX9_CAN_BASE + IMX9_CAN_WORD136_OFFSET) +#define IMX9_CAN_CS37 (IMX9_CAN_BASE + IMX9_CAN_CS37_OFFSET) +#define IMX9_CAN_WORD037 (IMX9_CAN_BASE + IMX9_CAN_WORD037_OFFSET) +#define IMX9_CAN_WORD137 (IMX9_CAN_BASE + IMX9_CAN_WORD137_OFFSET) +#define IMX9_CAN_CS38 (IMX9_CAN_BASE + IMX9_CAN_CS38_OFFSET) +#define IMX9_CAN_WORD038 (IMX9_CAN_BASE + IMX9_CAN_WORD038_OFFSET) +#define IMX9_CAN_WORD138 (IMX9_CAN_BASE + IMX9_CAN_WORD138_OFFSET) +#define IMX9_CAN_CS39 (IMX9_CAN_BASE + IMX9_CAN_CS39_OFFSET) +#define IMX9_CAN_WORD039 (IMX9_CAN_BASE + IMX9_CAN_WORD039_OFFSET) +#define IMX9_CAN_WORD139 (IMX9_CAN_BASE + IMX9_CAN_WORD139_OFFSET) +#define IMX9_CAN_CS40 (IMX9_CAN_BASE + IMX9_CAN_CS40_OFFSET) +#define IMX9_CAN_WORD040 (IMX9_CAN_BASE + IMX9_CAN_WORD040_OFFSET) +#define IMX9_CAN_WORD140 (IMX9_CAN_BASE + IMX9_CAN_WORD140_OFFSET) +#define IMX9_CAN_CS41 (IMX9_CAN_BASE + IMX9_CAN_CS41_OFFSET) +#define IMX9_CAN_WORD041 (IMX9_CAN_BASE + IMX9_CAN_WORD041_OFFSET) +#define IMX9_CAN_WORD141 (IMX9_CAN_BASE + IMX9_CAN_WORD141_OFFSET) +#define IMX9_CAN_CS42 (IMX9_CAN_BASE + IMX9_CAN_CS42_OFFSET) +#define IMX9_CAN_WORD042 (IMX9_CAN_BASE + IMX9_CAN_WORD042_OFFSET) +#define IMX9_CAN_WORD142 (IMX9_CAN_BASE + IMX9_CAN_WORD142_OFFSET) +#define IMX9_CAN_CS43 (IMX9_CAN_BASE + IMX9_CAN_CS43_OFFSET) +#define IMX9_CAN_WORD043 (IMX9_CAN_BASE + IMX9_CAN_WORD043_OFFSET) +#define IMX9_CAN_WORD143 (IMX9_CAN_BASE + IMX9_CAN_WORD143_OFFSET) +#define IMX9_CAN_CS44 (IMX9_CAN_BASE + IMX9_CAN_CS44_OFFSET) +#define IMX9_CAN_WORD044 (IMX9_CAN_BASE + IMX9_CAN_WORD044_OFFSET) +#define IMX9_CAN_WORD144 (IMX9_CAN_BASE + IMX9_CAN_WORD144_OFFSET) +#define IMX9_CAN_CS45 (IMX9_CAN_BASE + IMX9_CAN_CS45_OFFSET) +#define IMX9_CAN_WORD045 (IMX9_CAN_BASE + IMX9_CAN_WORD045_OFFSET) +#define IMX9_CAN_WORD145 (IMX9_CAN_BASE + IMX9_CAN_WORD145_OFFSET) +#define IMX9_CAN_CS46 (IMX9_CAN_BASE + IMX9_CAN_CS46_OFFSET) +#define IMX9_CAN_WORD046 (IMX9_CAN_BASE + IMX9_CAN_WORD046_OFFSET) +#define IMX9_CAN_WORD146 (IMX9_CAN_BASE + IMX9_CAN_WORD146_OFFSET) +#define IMX9_CAN_CS47 (IMX9_CAN_BASE + IMX9_CAN_CS47_OFFSET) +#define IMX9_CAN_WORD047 (IMX9_CAN_BASE + IMX9_CAN_WORD047_OFFSET) +#define IMX9_CAN_WORD147 (IMX9_CAN_BASE + IMX9_CAN_WORD147_OFFSET) +#define IMX9_CAN_CS48 (IMX9_CAN_BASE + IMX9_CAN_CS48_OFFSET) +#define IMX9_CAN_WORD048 (IMX9_CAN_BASE + IMX9_CAN_WORD048_OFFSET) +#define IMX9_CAN_WORD148 (IMX9_CAN_BASE + IMX9_CAN_WORD148_OFFSET) +#define IMX9_CAN_CS49 (IMX9_CAN_BASE + IMX9_CAN_CS49_OFFSET) +#define IMX9_CAN_WORD049 (IMX9_CAN_BASE + IMX9_CAN_WORD049_OFFSET) +#define IMX9_CAN_WORD149 (IMX9_CAN_BASE + IMX9_CAN_WORD149_OFFSET) +#define IMX9_CAN_CS50 (IMX9_CAN_BASE + IMX9_CAN_CS50_OFFSET) +#define IMX9_CAN_WORD050 (IMX9_CAN_BASE + IMX9_CAN_WORD050_OFFSET) +#define IMX9_CAN_WORD150 (IMX9_CAN_BASE + IMX9_CAN_WORD150_OFFSET) +#define IMX9_CAN_CS51 (IMX9_CAN_BASE + IMX9_CAN_CS51_OFFSET) +#define IMX9_CAN_WORD051 (IMX9_CAN_BASE + IMX9_CAN_WORD051_OFFSET) +#define IMX9_CAN_WORD151 (IMX9_CAN_BASE + IMX9_CAN_WORD151_OFFSET) +#define IMX9_CAN_CS52 (IMX9_CAN_BASE + IMX9_CAN_CS52_OFFSET) +#define IMX9_CAN_WORD052 (IMX9_CAN_BASE + IMX9_CAN_WORD052_OFFSET) +#define IMX9_CAN_WORD152 (IMX9_CAN_BASE + IMX9_CAN_WORD152_OFFSET) +#define IMX9_CAN_CS53 (IMX9_CAN_BASE + IMX9_CAN_CS53_OFFSET) +#define IMX9_CAN_WORD053 (IMX9_CAN_BASE + IMX9_CAN_WORD053_OFFSET) +#define IMX9_CAN_WORD153 (IMX9_CAN_BASE + IMX9_CAN_WORD153_OFFSET) +#define IMX9_CAN_CS54 (IMX9_CAN_BASE + IMX9_CAN_CS54_OFFSET) +#define IMX9_CAN_WORD054 (IMX9_CAN_BASE + IMX9_CAN_WORD054_OFFSET) +#define IMX9_CAN_WORD154 (IMX9_CAN_BASE + IMX9_CAN_WORD154_OFFSET) +#define IMX9_CAN_CS55 (IMX9_CAN_BASE + IMX9_CAN_CS55_OFFSET) +#define IMX9_CAN_WORD055 (IMX9_CAN_BASE + IMX9_CAN_WORD055_OFFSET) +#define IMX9_CAN_WORD155 (IMX9_CAN_BASE + IMX9_CAN_WORD155_OFFSET) +#define IMX9_CAN_CS56 (IMX9_CAN_BASE + IMX9_CAN_CS56_OFFSET) +#define IMX9_CAN_WORD056 (IMX9_CAN_BASE + IMX9_CAN_WORD056_OFFSET) +#define IMX9_CAN_WORD156 (IMX9_CAN_BASE + IMX9_CAN_WORD156_OFFSET) +#define IMX9_CAN_CS57 (IMX9_CAN_BASE + IMX9_CAN_CS57_OFFSET) +#define IMX9_CAN_WORD057 (IMX9_CAN_BASE + IMX9_CAN_WORD057_OFFSET) +#define IMX9_CAN_WORD157 (IMX9_CAN_BASE + IMX9_CAN_WORD157_OFFSET) +#define IMX9_CAN_CS58 (IMX9_CAN_BASE + IMX9_CAN_CS58_OFFSET) +#define IMX9_CAN_WORD058 (IMX9_CAN_BASE + IMX9_CAN_WORD058_OFFSET) +#define IMX9_CAN_WORD158 (IMX9_CAN_BASE + IMX9_CAN_WORD158_OFFSET) +#define IMX9_CAN_CS59 (IMX9_CAN_BASE + IMX9_CAN_CS59_OFFSET) +#define IMX9_CAN_WORD059 (IMX9_CAN_BASE + IMX9_CAN_WORD059_OFFSET) +#define IMX9_CAN_WORD159 (IMX9_CAN_BASE + IMX9_CAN_WORD159_OFFSET) +#define IMX9_CAN_CS60 (IMX9_CAN_BASE + IMX9_CAN_CS60_OFFSET) +#define IMX9_CAN_WORD060 (IMX9_CAN_BASE + IMX9_CAN_WORD060_OFFSET) +#define IMX9_CAN_WORD160 (IMX9_CAN_BASE + IMX9_CAN_WORD160_OFFSET) +#define IMX9_CAN_CS61 (IMX9_CAN_BASE + IMX9_CAN_CS61_OFFSET) +#define IMX9_CAN_WORD061 (IMX9_CAN_BASE + IMX9_CAN_WORD061_OFFSET) +#define IMX9_CAN_WORD161 (IMX9_CAN_BASE + IMX9_CAN_WORD161_OFFSET) +#define IMX9_CAN_CS62 (IMX9_CAN_BASE + IMX9_CAN_CS62_OFFSET) +#define IMX9_CAN_WORD062 (IMX9_CAN_BASE + IMX9_CAN_WORD062_OFFSET) +#define IMX9_CAN_WORD162 (IMX9_CAN_BASE + IMX9_CAN_WORD162_OFFSET) +#define IMX9_CAN_CS63 (IMX9_CAN_BASE + IMX9_CAN_CS63_OFFSET) +#define IMX9_CAN_WORD063 (IMX9_CAN_BASE + IMX9_CAN_WORD063_OFFSET) +#define IMX9_CAN_WORD163 (IMX9_CAN_BASE + IMX9_CAN_WORD163_OFFSET) +#define IMX9_CAN_CS64 (IMX9_CAN_BASE + IMX9_CAN_CS64_OFFSET) +#define IMX9_CAN_WORD064 (IMX9_CAN_BASE + IMX9_CAN_WORD064_OFFSET) +#define IMX9_CAN_WORD164 (IMX9_CAN_BASE + IMX9_CAN_WORD164_OFFSET) +#define IMX9_CAN_CS65 (IMX9_CAN_BASE + IMX9_CAN_CS65_OFFSET) +#define IMX9_CAN_WORD065 (IMX9_CAN_BASE + IMX9_CAN_WORD065_OFFSET) +#define IMX9_CAN_WORD165 (IMX9_CAN_BASE + IMX9_CAN_WORD165_OFFSET) +#define IMX9_CAN_CS66 (IMX9_CAN_BASE + IMX9_CAN_CS66_OFFSET) +#define IMX9_CAN_WORD066 (IMX9_CAN_BASE + IMX9_CAN_WORD066_OFFSET) +#define IMX9_CAN_WORD166 (IMX9_CAN_BASE + IMX9_CAN_WORD166_OFFSET) +#define IMX9_CAN_CS67 (IMX9_CAN_BASE + IMX9_CAN_CS67_OFFSET) +#define IMX9_CAN_WORD067 (IMX9_CAN_BASE + IMX9_CAN_WORD067_OFFSET) +#define IMX9_CAN_WORD167 (IMX9_CAN_BASE + IMX9_CAN_WORD167_OFFSET) +#define IMX9_CAN_CS68 (IMX9_CAN_BASE + IMX9_CAN_CS68_OFFSET) +#define IMX9_CAN_WORD068 (IMX9_CAN_BASE + IMX9_CAN_WORD068_OFFSET) +#define IMX9_CAN_WORD168 (IMX9_CAN_BASE + IMX9_CAN_WORD168_OFFSET) +#define IMX9_CAN_CS69 (IMX9_CAN_BASE + IMX9_CAN_CS69_OFFSET) +#define IMX9_CAN_WORD069 (IMX9_CAN_BASE + IMX9_CAN_WORD069_OFFSET) +#define IMX9_CAN_WORD169 (IMX9_CAN_BASE + IMX9_CAN_WORD169_OFFSET) +#define IMX9_CAN_CS70 (IMX9_CAN_BASE + IMX9_CAN_CS70_OFFSET) +#define IMX9_CAN_WORD070 (IMX9_CAN_BASE + IMX9_CAN_WORD070_OFFSET) +#define IMX9_CAN_WORD170 (IMX9_CAN_BASE + IMX9_CAN_WORD170_OFFSET) +#define IMX9_CAN_CS71 (IMX9_CAN_BASE + IMX9_CAN_CS71_OFFSET) +#define IMX9_CAN_WORD071 (IMX9_CAN_BASE + IMX9_CAN_WORD071_OFFSET) +#define IMX9_CAN_WORD171 (IMX9_CAN_BASE + IMX9_CAN_WORD171_OFFSET) +#define IMX9_CAN_CS72 (IMX9_CAN_BASE + IMX9_CAN_CS72_OFFSET) +#define IMX9_CAN_WORD072 (IMX9_CAN_BASE + IMX9_CAN_WORD072_OFFSET) +#define IMX9_CAN_WORD172 (IMX9_CAN_BASE + IMX9_CAN_WORD172_OFFSET) +#define IMX9_CAN_CS73 (IMX9_CAN_BASE + IMX9_CAN_CS73_OFFSET) +#define IMX9_CAN_WORD073 (IMX9_CAN_BASE + IMX9_CAN_WORD073_OFFSET) +#define IMX9_CAN_WORD173 (IMX9_CAN_BASE + IMX9_CAN_WORD173_OFFSET) +#define IMX9_CAN_CS74 (IMX9_CAN_BASE + IMX9_CAN_CS74_OFFSET) +#define IMX9_CAN_WORD074 (IMX9_CAN_BASE + IMX9_CAN_WORD074_OFFSET) +#define IMX9_CAN_WORD174 (IMX9_CAN_BASE + IMX9_CAN_WORD174_OFFSET) +#define IMX9_CAN_CS75 (IMX9_CAN_BASE + IMX9_CAN_CS75_OFFSET) +#define IMX9_CAN_WORD075 (IMX9_CAN_BASE + IMX9_CAN_WORD075_OFFSET) +#define IMX9_CAN_WORD175 (IMX9_CAN_BASE + IMX9_CAN_WORD175_OFFSET) +#define IMX9_CAN_CS76 (IMX9_CAN_BASE + IMX9_CAN_CS76_OFFSET) +#define IMX9_CAN_WORD076 (IMX9_CAN_BASE + IMX9_CAN_WORD076_OFFSET) +#define IMX9_CAN_WORD176 (IMX9_CAN_BASE + IMX9_CAN_WORD176_OFFSET) +#define IMX9_CAN_CS77 (IMX9_CAN_BASE + IMX9_CAN_CS77_OFFSET) +#define IMX9_CAN_WORD077 (IMX9_CAN_BASE + IMX9_CAN_WORD077_OFFSET) +#define IMX9_CAN_WORD177 (IMX9_CAN_BASE + IMX9_CAN_WORD177_OFFSET) +#define IMX9_CAN_CS78 (IMX9_CAN_BASE + IMX9_CAN_CS78_OFFSET) +#define IMX9_CAN_WORD078 (IMX9_CAN_BASE + IMX9_CAN_WORD078_OFFSET) +#define IMX9_CAN_WORD178 (IMX9_CAN_BASE + IMX9_CAN_WORD178_OFFSET) +#define IMX9_CAN_CS79 (IMX9_CAN_BASE + IMX9_CAN_CS79_OFFSET) +#define IMX9_CAN_WORD079 (IMX9_CAN_BASE + IMX9_CAN_WORD079_OFFSET) +#define IMX9_CAN_WORD179 (IMX9_CAN_BASE + IMX9_CAN_WORD179_OFFSET) +#define IMX9_CAN_CS80 (IMX9_CAN_BASE + IMX9_CAN_CS80_OFFSET) +#define IMX9_CAN_WORD080 (IMX9_CAN_BASE + IMX9_CAN_WORD080_OFFSET) +#define IMX9_CAN_WORD180 (IMX9_CAN_BASE + IMX9_CAN_WORD180_OFFSET) +#define IMX9_CAN_CS81 (IMX9_CAN_BASE + IMX9_CAN_CS81_OFFSET) +#define IMX9_CAN_WORD081 (IMX9_CAN_BASE + IMX9_CAN_WORD081_OFFSET) +#define IMX9_CAN_WORD181 (IMX9_CAN_BASE + IMX9_CAN_WORD181_OFFSET) +#define IMX9_CAN_CS82 (IMX9_CAN_BASE + IMX9_CAN_CS82_OFFSET) +#define IMX9_CAN_WORD082 (IMX9_CAN_BASE + IMX9_CAN_WORD082_OFFSET) +#define IMX9_CAN_WORD182 (IMX9_CAN_BASE + IMX9_CAN_WORD182_OFFSET) +#define IMX9_CAN_CS83 (IMX9_CAN_BASE + IMX9_CAN_CS83_OFFSET) +#define IMX9_CAN_WORD083 (IMX9_CAN_BASE + IMX9_CAN_WORD083_OFFSET) +#define IMX9_CAN_WORD183 (IMX9_CAN_BASE + IMX9_CAN_WORD183_OFFSET) +#define IMX9_CAN_CS84 (IMX9_CAN_BASE + IMX9_CAN_CS84_OFFSET) +#define IMX9_CAN_WORD084 (IMX9_CAN_BASE + IMX9_CAN_WORD084_OFFSET) +#define IMX9_CAN_WORD184 (IMX9_CAN_BASE + IMX9_CAN_WORD184_OFFSET) +#define IMX9_CAN_CS85 (IMX9_CAN_BASE + IMX9_CAN_CS85_OFFSET) +#define IMX9_CAN_WORD085 (IMX9_CAN_BASE + IMX9_CAN_WORD085_OFFSET) +#define IMX9_CAN_WORD185 (IMX9_CAN_BASE + IMX9_CAN_WORD185_OFFSET) +#define IMX9_CAN_CS86 (IMX9_CAN_BASE + IMX9_CAN_CS86_OFFSET) +#define IMX9_CAN_WORD086 (IMX9_CAN_BASE + IMX9_CAN_WORD086_OFFSET) +#define IMX9_CAN_WORD186 (IMX9_CAN_BASE + IMX9_CAN_WORD186_OFFSET) +#define IMX9_CAN_CS87 (IMX9_CAN_BASE + IMX9_CAN_CS87_OFFSET) +#define IMX9_CAN_WORD087 (IMX9_CAN_BASE + IMX9_CAN_WORD087_OFFSET) +#define IMX9_CAN_WORD187 (IMX9_CAN_BASE + IMX9_CAN_WORD187_OFFSET) +#define IMX9_CAN_CS88 (IMX9_CAN_BASE + IMX9_CAN_CS88_OFFSET) +#define IMX9_CAN_WORD088 (IMX9_CAN_BASE + IMX9_CAN_WORD088_OFFSET) +#define IMX9_CAN_WORD188 (IMX9_CAN_BASE + IMX9_CAN_WORD188_OFFSET) +#define IMX9_CAN_CS89 (IMX9_CAN_BASE + IMX9_CAN_CS89_OFFSET) +#define IMX9_CAN_WORD089 (IMX9_CAN_BASE + IMX9_CAN_WORD089_OFFSET) +#define IMX9_CAN_WORD189 (IMX9_CAN_BASE + IMX9_CAN_WORD189_OFFSET) +#define IMX9_CAN_CS90 (IMX9_CAN_BASE + IMX9_CAN_CS90_OFFSET) +#define IMX9_CAN_WORD090 (IMX9_CAN_BASE + IMX9_CAN_WORD090_OFFSET) +#define IMX9_CAN_WORD190 (IMX9_CAN_BASE + IMX9_CAN_WORD190_OFFSET) +#define IMX9_CAN_CS91 (IMX9_CAN_BASE + IMX9_CAN_CS91_OFFSET) +#define IMX9_CAN_WORD091 (IMX9_CAN_BASE + IMX9_CAN_WORD091_OFFSET) +#define IMX9_CAN_WORD191 (IMX9_CAN_BASE + IMX9_CAN_WORD191_OFFSET) +#define IMX9_CAN_CS92 (IMX9_CAN_BASE + IMX9_CAN_CS92_OFFSET) +#define IMX9_CAN_WORD092 (IMX9_CAN_BASE + IMX9_CAN_WORD092_OFFSET) +#define IMX9_CAN_WORD192 (IMX9_CAN_BASE + IMX9_CAN_WORD192_OFFSET) +#define IMX9_CAN_CS93 (IMX9_CAN_BASE + IMX9_CAN_CS93_OFFSET) +#define IMX9_CAN_WORD093 (IMX9_CAN_BASE + IMX9_CAN_WORD093_OFFSET) +#define IMX9_CAN_WORD193 (IMX9_CAN_BASE + IMX9_CAN_WORD193_OFFSET) +#define IMX9_CAN_CS94 (IMX9_CAN_BASE + IMX9_CAN_CS94_OFFSET) +#define IMX9_CAN_WORD094 (IMX9_CAN_BASE + IMX9_CAN_WORD094_OFFSET) +#define IMX9_CAN_WORD194 (IMX9_CAN_BASE + IMX9_CAN_WORD194_OFFSET) +#define IMX9_CAN_CS95 (IMX9_CAN_BASE + IMX9_CAN_CS95_OFFSET) +#define IMX9_CAN_WORD095 (IMX9_CAN_BASE + IMX9_CAN_WORD095_OFFSET) +#define IMX9_CAN_WORD195 (IMX9_CAN_BASE + IMX9_CAN_WORD195_OFFSET) +#define IMX9_CAN_MECR (IMX9_CAN_BASE + IMX9_CAN_MECR_OFFSET) +#define IMX9_CAN_ERRIAR (IMX9_CAN_BASE + IMX9_CAN_ERRIAR_OFFSET) +#define IMX9_CAN_ERRIDPR (IMX9_CAN_BASE + IMX9_CAN_ERRIDPR_OFFSET) +#define IMX9_CAN_ERRIPPR (IMX9_CAN_BASE + IMX9_CAN_ERRIPPR_OFFSET) +#define IMX9_CAN_RERRAR (IMX9_CAN_BASE + IMX9_CAN_RERRAR_OFFSET) +#define IMX9_CAN_RERRDR (IMX9_CAN_BASE + IMX9_CAN_RERRDR_OFFSET) +#define IMX9_CAN_RERRSYNR (IMX9_CAN_BASE + IMX9_CAN_RERRSYNR_OFFSET) +#define IMX9_CAN_ERRSR (IMX9_CAN_BASE + IMX9_CAN_ERRSR_OFFSET) +#define IMX9_CAN_EPRS (IMX9_CAN_BASE + IMX9_CAN_EPRS_OFFSET) +#define IMX9_CAN_ENCBT (IMX9_CAN_BASE + IMX9_CAN_ENCBT_OFFSET) +#define IMX9_CAN_EDCBT (IMX9_CAN_BASE + IMX9_CAN_EDCBT_OFFSET) +#define IMX9_CAN_ETDC (IMX9_CAN_BASE + IMX9_CAN_ETDC_OFFSET) +#define IMX9_CAN_FDCTRL (IMX9_CAN_BASE + IMX9_CAN_FDCTRL_OFFSET) +#define IMX9_CAN_FDCBT (IMX9_CAN_BASE + IMX9_CAN_FDCBT_OFFSET) +#define IMX9_CAN_FDCRC (IMX9_CAN_BASE + IMX9_CAN_FDCRC_OFFSET) +#define IMX9_CAN_ERFCR (IMX9_CAN_BASE + IMX9_CAN_ERFCR_OFFSET) +#define IMX9_CAN_ERFIER (IMX9_CAN_BASE + IMX9_CAN_ERFIER_OFFSET) +#define IMX9_CAN_ERFSR (IMX9_CAN_BASE + IMX9_CAN_ERFSR_OFFSET) +#define IMX9_CAN_RXIMR0 (IMX9_CAN_BASE + IMX9_CAN_RXIMR0_OFFSET) +#define IMX9_CAN_RXIMR1 (IMX9_CAN_BASE + IMX9_CAN_RXIMR1_OFFSET) +#define IMX9_CAN_RXIMR2 (IMX9_CAN_BASE + IMX9_CAN_RXIMR2_OFFSET) +#define IMX9_CAN_RXIMR3 (IMX9_CAN_BASE + IMX9_CAN_RXIMR3_OFFSET) +#define IMX9_CAN_RXIMR4 (IMX9_CAN_BASE + IMX9_CAN_RXIMR4_OFFSET) +#define IMX9_CAN_RXIMR5 (IMX9_CAN_BASE + IMX9_CAN_RXIMR5_OFFSET) +#define IMX9_CAN_RXIMR6 (IMX9_CAN_BASE + IMX9_CAN_RXIMR6_OFFSET) +#define IMX9_CAN_RXIMR7 (IMX9_CAN_BASE + IMX9_CAN_RXIMR7_OFFSET) +#define IMX9_CAN_RXIMR8 (IMX9_CAN_BASE + IMX9_CAN_RXIMR8_OFFSET) +#define IMX9_CAN_RXIMR9 (IMX9_CAN_BASE + IMX9_CAN_RXIMR9_OFFSET) +#define IMX9_CAN_RXIMR10 (IMX9_CAN_BASE + IMX9_CAN_RXIMR10_OFFSET) +#define IMX9_CAN_RXIMR11 (IMX9_CAN_BASE + IMX9_CAN_RXIMR11_OFFSET) +#define IMX9_CAN_RXIMR12 (IMX9_CAN_BASE + IMX9_CAN_RXIMR12_OFFSET) +#define IMX9_CAN_RXIMR13 (IMX9_CAN_BASE + IMX9_CAN_RXIMR13_OFFSET) +#define IMX9_CAN_RXIMR14 (IMX9_CAN_BASE + IMX9_CAN_RXIMR14_OFFSET) +#define IMX9_CAN_RXIMR15 (IMX9_CAN_BASE + IMX9_CAN_RXIMR15_OFFSET) +#define IMX9_CAN_RXIMR16 (IMX9_CAN_BASE + IMX9_CAN_RXIMR16_OFFSET) +#define IMX9_CAN_RXIMR17 (IMX9_CAN_BASE + IMX9_CAN_RXIMR17_OFFSET) +#define IMX9_CAN_RXIMR18 (IMX9_CAN_BASE + IMX9_CAN_RXIMR18_OFFSET) +#define IMX9_CAN_RXIMR19 (IMX9_CAN_BASE + IMX9_CAN_RXIMR19_OFFSET) +#define IMX9_CAN_RXIMR20 (IMX9_CAN_BASE + IMX9_CAN_RXIMR20_OFFSET) +#define IMX9_CAN_RXIMR21 (IMX9_CAN_BASE + IMX9_CAN_RXIMR21_OFFSET) +#define IMX9_CAN_RXIMR22 (IMX9_CAN_BASE + IMX9_CAN_RXIMR22_OFFSET) +#define IMX9_CAN_RXIMR23 (IMX9_CAN_BASE + IMX9_CAN_RXIMR23_OFFSET) +#define IMX9_CAN_RXIMR24 (IMX9_CAN_BASE + IMX9_CAN_RXIMR24_OFFSET) +#define IMX9_CAN_RXIMR25 (IMX9_CAN_BASE + IMX9_CAN_RXIMR25_OFFSET) +#define IMX9_CAN_RXIMR26 (IMX9_CAN_BASE + IMX9_CAN_RXIMR26_OFFSET) +#define IMX9_CAN_RXIMR27 (IMX9_CAN_BASE + IMX9_CAN_RXIMR27_OFFSET) +#define IMX9_CAN_RXIMR28 (IMX9_CAN_BASE + IMX9_CAN_RXIMR28_OFFSET) +#define IMX9_CAN_RXIMR29 (IMX9_CAN_BASE + IMX9_CAN_RXIMR29_OFFSET) +#define IMX9_CAN_RXIMR30 (IMX9_CAN_BASE + IMX9_CAN_RXIMR30_OFFSET) +#define IMX9_CAN_RXIMR31 (IMX9_CAN_BASE + IMX9_CAN_RXIMR31_OFFSET) +#define IMX9_CAN_RXIMR32 (IMX9_CAN_BASE + IMX9_CAN_RXIMR32_OFFSET) +#define IMX9_CAN_RXIMR33 (IMX9_CAN_BASE + IMX9_CAN_RXIMR33_OFFSET) +#define IMX9_CAN_RXIMR34 (IMX9_CAN_BASE + IMX9_CAN_RXIMR34_OFFSET) +#define IMX9_CAN_RXIMR35 (IMX9_CAN_BASE + IMX9_CAN_RXIMR35_OFFSET) +#define IMX9_CAN_RXIMR36 (IMX9_CAN_BASE + IMX9_CAN_RXIMR36_OFFSET) +#define IMX9_CAN_RXIMR37 (IMX9_CAN_BASE + IMX9_CAN_RXIMR37_OFFSET) +#define IMX9_CAN_RXIMR38 (IMX9_CAN_BASE + IMX9_CAN_RXIMR38_OFFSET) +#define IMX9_CAN_RXIMR39 (IMX9_CAN_BASE + IMX9_CAN_RXIMR39_OFFSET) +#define IMX9_CAN_RXIMR40 (IMX9_CAN_BASE + IMX9_CAN_RXIMR40_OFFSET) +#define IMX9_CAN_RXIMR41 (IMX9_CAN_BASE + IMX9_CAN_RXIMR41_OFFSET) +#define IMX9_CAN_RXIMR42 (IMX9_CAN_BASE + IMX9_CAN_RXIMR42_OFFSET) +#define IMX9_CAN_RXIMR43 (IMX9_CAN_BASE + IMX9_CAN_RXIMR43_OFFSET) +#define IMX9_CAN_RXIMR44 (IMX9_CAN_BASE + IMX9_CAN_RXIMR44_OFFSET) +#define IMX9_CAN_RXIMR45 (IMX9_CAN_BASE + IMX9_CAN_RXIMR45_OFFSET) +#define IMX9_CAN_RXIMR46 (IMX9_CAN_BASE + IMX9_CAN_RXIMR46_OFFSET) +#define IMX9_CAN_RXIMR47 (IMX9_CAN_BASE + IMX9_CAN_RXIMR47_OFFSET) +#define IMX9_CAN_RXIMR48 (IMX9_CAN_BASE + IMX9_CAN_RXIMR48_OFFSET) +#define IMX9_CAN_RXIMR49 (IMX9_CAN_BASE + IMX9_CAN_RXIMR49_OFFSET) +#define IMX9_CAN_RXIMR50 (IMX9_CAN_BASE + IMX9_CAN_RXIMR50_OFFSET) +#define IMX9_CAN_RXIMR51 (IMX9_CAN_BASE + IMX9_CAN_RXIMR51_OFFSET) +#define IMX9_CAN_RXIMR52 (IMX9_CAN_BASE + IMX9_CAN_RXIMR52_OFFSET) +#define IMX9_CAN_RXIMR53 (IMX9_CAN_BASE + IMX9_CAN_RXIMR53_OFFSET) +#define IMX9_CAN_RXIMR54 (IMX9_CAN_BASE + IMX9_CAN_RXIMR54_OFFSET) +#define IMX9_CAN_RXIMR55 (IMX9_CAN_BASE + IMX9_CAN_RXIMR55_OFFSET) +#define IMX9_CAN_RXIMR56 (IMX9_CAN_BASE + IMX9_CAN_RXIMR56_OFFSET) +#define IMX9_CAN_RXIMR57 (IMX9_CAN_BASE + IMX9_CAN_RXIMR57_OFFSET) +#define IMX9_CAN_RXIMR58 (IMX9_CAN_BASE + IMX9_CAN_RXIMR58_OFFSET) +#define IMX9_CAN_RXIMR59 (IMX9_CAN_BASE + IMX9_CAN_RXIMR59_OFFSET) +#define IMX9_CAN_RXIMR60 (IMX9_CAN_BASE + IMX9_CAN_RXIMR60_OFFSET) +#define IMX9_CAN_RXIMR61 (IMX9_CAN_BASE + IMX9_CAN_RXIMR61_OFFSET) +#define IMX9_CAN_RXIMR62 (IMX9_CAN_BASE + IMX9_CAN_RXIMR62_OFFSET) +#define IMX9_CAN_RXIMR63 (IMX9_CAN_BASE + IMX9_CAN_RXIMR63_OFFSET) +#define IMX9_CAN_RXIMR64 (IMX9_CAN_BASE + IMX9_CAN_RXIMR64_OFFSET) +#define IMX9_CAN_RXIMR65 (IMX9_CAN_BASE + IMX9_CAN_RXIMR65_OFFSET) +#define IMX9_CAN_RXIMR66 (IMX9_CAN_BASE + IMX9_CAN_RXIMR66_OFFSET) +#define IMX9_CAN_RXIMR67 (IMX9_CAN_BASE + IMX9_CAN_RXIMR67_OFFSET) +#define IMX9_CAN_RXIMR68 (IMX9_CAN_BASE + IMX9_CAN_RXIMR68_OFFSET) +#define IMX9_CAN_RXIMR69 (IMX9_CAN_BASE + IMX9_CAN_RXIMR69_OFFSET) +#define IMX9_CAN_RXIMR70 (IMX9_CAN_BASE + IMX9_CAN_RXIMR70_OFFSET) +#define IMX9_CAN_RXIMR71 (IMX9_CAN_BASE + IMX9_CAN_RXIMR71_OFFSET) +#define IMX9_CAN_RXIMR72 (IMX9_CAN_BASE + IMX9_CAN_RXIMR72_OFFSET) +#define IMX9_CAN_RXIMR73 (IMX9_CAN_BASE + IMX9_CAN_RXIMR73_OFFSET) +#define IMX9_CAN_RXIMR74 (IMX9_CAN_BASE + IMX9_CAN_RXIMR74_OFFSET) +#define IMX9_CAN_RXIMR75 (IMX9_CAN_BASE + IMX9_CAN_RXIMR75_OFFSET) +#define IMX9_CAN_RXIMR76 (IMX9_CAN_BASE + IMX9_CAN_RXIMR76_OFFSET) +#define IMX9_CAN_RXIMR77 (IMX9_CAN_BASE + IMX9_CAN_RXIMR77_OFFSET) +#define IMX9_CAN_RXIMR78 (IMX9_CAN_BASE + IMX9_CAN_RXIMR78_OFFSET) +#define IMX9_CAN_RXIMR79 (IMX9_CAN_BASE + IMX9_CAN_RXIMR79_OFFSET) +#define IMX9_CAN_RXIMR80 (IMX9_CAN_BASE + IMX9_CAN_RXIMR80_OFFSET) +#define IMX9_CAN_RXIMR81 (IMX9_CAN_BASE + IMX9_CAN_RXIMR81_OFFSET) +#define IMX9_CAN_RXIMR82 (IMX9_CAN_BASE + IMX9_CAN_RXIMR82_OFFSET) +#define IMX9_CAN_RXIMR83 (IMX9_CAN_BASE + IMX9_CAN_RXIMR83_OFFSET) +#define IMX9_CAN_RXIMR84 (IMX9_CAN_BASE + IMX9_CAN_RXIMR84_OFFSET) +#define IMX9_CAN_RXIMR85 (IMX9_CAN_BASE + IMX9_CAN_RXIMR85_OFFSET) +#define IMX9_CAN_RXIMR86 (IMX9_CAN_BASE + IMX9_CAN_RXIMR86_OFFSET) +#define IMX9_CAN_RXIMR87 (IMX9_CAN_BASE + IMX9_CAN_RXIMR87_OFFSET) +#define IMX9_CAN_RXIMR88 (IMX9_CAN_BASE + IMX9_CAN_RXIMR88_OFFSET) +#define IMX9_CAN_RXIMR89 (IMX9_CAN_BASE + IMX9_CAN_RXIMR89_OFFSET) +#define IMX9_CAN_RXIMR90 (IMX9_CAN_BASE + IMX9_CAN_RXIMR90_OFFSET) +#define IMX9_CAN_RXIMR91 (IMX9_CAN_BASE + IMX9_CAN_RXIMR91_OFFSET) +#define IMX9_CAN_RXIMR92 (IMX9_CAN_BASE + IMX9_CAN_RXIMR92_OFFSET) +#define IMX9_CAN_RXIMR93 (IMX9_CAN_BASE + IMX9_CAN_RXIMR93_OFFSET) +#define IMX9_CAN_RXIMR94 (IMX9_CAN_BASE + IMX9_CAN_RXIMR94_OFFSET) +#define IMX9_CAN_RXIMR95 (IMX9_CAN_BASE + IMX9_CAN_RXIMR95_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP0 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP0_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP1 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP1_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP2 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP2_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP3 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP3_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP4 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP4_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP5 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP5_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP6 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP6_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP7 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP7_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP8 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP8_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP9 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP9_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP10 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP10_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP11 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP11_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP12 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP12_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP13 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP13_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP14 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP14_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP15 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP15_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP16 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP16_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP17 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP17_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP18 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP18_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP19 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP19_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP20 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP20_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP21 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP21_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP22 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP22_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP23 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP23_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP24 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP24_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP25 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP25_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP26 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP26_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP27 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP27_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP28 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP28_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP29 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP29_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP30 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP30_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP31 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP31_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP32 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP32_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP33 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP33_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP34 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP34_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP35 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP35_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP36 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP36_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP37 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP37_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP38 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP38_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP39 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP39_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP40 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP40_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP41 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP41_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP42 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP42_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP43 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP43_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP44 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP44_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP45 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP45_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP46 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP46_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP47 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP47_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP48 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP48_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP49 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP49_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP50 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP50_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP51 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP51_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP52 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP52_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP53 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP53_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP54 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP54_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP55 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP55_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP56 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP56_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP57 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP57_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP58 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP58_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP59 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP59_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP60 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP60_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP61 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP61_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP62 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP62_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP63 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP63_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP64 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP64_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP65 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP65_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP66 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP66_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP67 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP67_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP68 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP68_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP69 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP69_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP70 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP70_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP71 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP71_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP72 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP72_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP73 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP73_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP74 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP74_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP75 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP75_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP76 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP76_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP77 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP77_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP78 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP78_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP79 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP79_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP80 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP80_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP81 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP81_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP82 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP82_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP83 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP83_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP84 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP84_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP85 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP85_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP86 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP86_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP87 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP87_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP88 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP88_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP89 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP89_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP90 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP90_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP91 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP91_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP92 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP92_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP93 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP93_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP94 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP94_OFFSET) +#define IMX9_CAN_HR_TIME_STAMP95 (IMX9_CAN_BASE + IMX9_CAN_HR_TIME_STAMP95_OFFSET) +#define IMX9_CAN_ERFFEL0 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL0_OFFSET) +#define IMX9_CAN_ERFFEL1 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL1_OFFSET) +#define IMX9_CAN_ERFFEL2 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL2_OFFSET) +#define IMX9_CAN_ERFFEL3 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL3_OFFSET) +#define IMX9_CAN_ERFFEL4 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL4_OFFSET) +#define IMX9_CAN_ERFFEL5 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL5_OFFSET) +#define IMX9_CAN_ERFFEL6 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL6_OFFSET) +#define IMX9_CAN_ERFFEL7 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL7_OFFSET) +#define IMX9_CAN_ERFFEL8 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL8_OFFSET) +#define IMX9_CAN_ERFFEL9 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL9_OFFSET) +#define IMX9_CAN_ERFFEL10 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL10_OFFSET) +#define IMX9_CAN_ERFFEL11 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL11_OFFSET) +#define IMX9_CAN_ERFFEL12 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL12_OFFSET) +#define IMX9_CAN_ERFFEL13 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL13_OFFSET) +#define IMX9_CAN_ERFFEL14 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL14_OFFSET) +#define IMX9_CAN_ERFFEL15 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL15_OFFSET) +#define IMX9_CAN_ERFFEL16 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL16_OFFSET) +#define IMX9_CAN_ERFFEL17 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL17_OFFSET) +#define IMX9_CAN_ERFFEL18 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL18_OFFSET) +#define IMX9_CAN_ERFFEL19 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL19_OFFSET) +#define IMX9_CAN_ERFFEL20 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL20_OFFSET) +#define IMX9_CAN_ERFFEL21 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL21_OFFSET) +#define IMX9_CAN_ERFFEL22 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL22_OFFSET) +#define IMX9_CAN_ERFFEL23 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL23_OFFSET) +#define IMX9_CAN_ERFFEL24 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL24_OFFSET) +#define IMX9_CAN_ERFFEL25 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL25_OFFSET) +#define IMX9_CAN_ERFFEL26 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL26_OFFSET) +#define IMX9_CAN_ERFFEL27 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL27_OFFSET) +#define IMX9_CAN_ERFFEL28 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL28_OFFSET) +#define IMX9_CAN_ERFFEL29 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL29_OFFSET) +#define IMX9_CAN_ERFFEL30 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL30_OFFSET) +#define IMX9_CAN_ERFFEL31 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL31_OFFSET) +#define IMX9_CAN_ERFFEL32 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL32_OFFSET) +#define IMX9_CAN_ERFFEL33 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL33_OFFSET) +#define IMX9_CAN_ERFFEL34 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL34_OFFSET) +#define IMX9_CAN_ERFFEL35 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL35_OFFSET) +#define IMX9_CAN_ERFFEL36 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL36_OFFSET) +#define IMX9_CAN_ERFFEL37 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL37_OFFSET) +#define IMX9_CAN_ERFFEL38 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL38_OFFSET) +#define IMX9_CAN_ERFFEL39 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL39_OFFSET) +#define IMX9_CAN_ERFFEL40 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL40_OFFSET) +#define IMX9_CAN_ERFFEL41 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL41_OFFSET) +#define IMX9_CAN_ERFFEL42 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL42_OFFSET) +#define IMX9_CAN_ERFFEL43 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL43_OFFSET) +#define IMX9_CAN_ERFFEL44 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL44_OFFSET) +#define IMX9_CAN_ERFFEL45 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL45_OFFSET) +#define IMX9_CAN_ERFFEL46 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL46_OFFSET) +#define IMX9_CAN_ERFFEL47 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL47_OFFSET) +#define IMX9_CAN_ERFFEL48 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL48_OFFSET) +#define IMX9_CAN_ERFFEL49 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL49_OFFSET) +#define IMX9_CAN_ERFFEL50 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL50_OFFSET) +#define IMX9_CAN_ERFFEL51 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL51_OFFSET) +#define IMX9_CAN_ERFFEL52 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL52_OFFSET) +#define IMX9_CAN_ERFFEL53 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL53_OFFSET) +#define IMX9_CAN_ERFFEL54 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL54_OFFSET) +#define IMX9_CAN_ERFFEL55 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL55_OFFSET) +#define IMX9_CAN_ERFFEL56 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL56_OFFSET) +#define IMX9_CAN_ERFFEL57 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL57_OFFSET) +#define IMX9_CAN_ERFFEL58 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL58_OFFSET) +#define IMX9_CAN_ERFFEL59 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL59_OFFSET) +#define IMX9_CAN_ERFFEL60 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL60_OFFSET) +#define IMX9_CAN_ERFFEL61 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL61_OFFSET) +#define IMX9_CAN_ERFFEL62 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL62_OFFSET) +#define IMX9_CAN_ERFFEL63 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL63_OFFSET) +#define IMX9_CAN_ERFFEL64 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL64_OFFSET) +#define IMX9_CAN_ERFFEL65 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL65_OFFSET) +#define IMX9_CAN_ERFFEL66 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL66_OFFSET) +#define IMX9_CAN_ERFFEL67 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL67_OFFSET) +#define IMX9_CAN_ERFFEL68 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL68_OFFSET) +#define IMX9_CAN_ERFFEL69 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL69_OFFSET) +#define IMX9_CAN_ERFFEL70 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL70_OFFSET) +#define IMX9_CAN_ERFFEL71 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL71_OFFSET) +#define IMX9_CAN_ERFFEL72 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL72_OFFSET) +#define IMX9_CAN_ERFFEL73 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL73_OFFSET) +#define IMX9_CAN_ERFFEL74 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL74_OFFSET) +#define IMX9_CAN_ERFFEL75 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL75_OFFSET) +#define IMX9_CAN_ERFFEL76 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL76_OFFSET) +#define IMX9_CAN_ERFFEL77 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL77_OFFSET) +#define IMX9_CAN_ERFFEL78 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL78_OFFSET) +#define IMX9_CAN_ERFFEL79 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL79_OFFSET) +#define IMX9_CAN_ERFFEL80 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL80_OFFSET) +#define IMX9_CAN_ERFFEL81 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL81_OFFSET) +#define IMX9_CAN_ERFFEL82 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL82_OFFSET) +#define IMX9_CAN_ERFFEL83 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL83_OFFSET) +#define IMX9_CAN_ERFFEL84 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL84_OFFSET) +#define IMX9_CAN_ERFFEL85 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL85_OFFSET) +#define IMX9_CAN_ERFFEL86 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL86_OFFSET) +#define IMX9_CAN_ERFFEL87 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL87_OFFSET) +#define IMX9_CAN_ERFFEL88 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL88_OFFSET) +#define IMX9_CAN_ERFFEL89 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL89_OFFSET) +#define IMX9_CAN_ERFFEL90 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL90_OFFSET) +#define IMX9_CAN_ERFFEL91 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL91_OFFSET) +#define IMX9_CAN_ERFFEL92 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL92_OFFSET) +#define IMX9_CAN_ERFFEL93 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL93_OFFSET) +#define IMX9_CAN_ERFFEL94 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL94_OFFSET) +#define IMX9_CAN_ERFFEL95 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL95_OFFSET) +#define IMX9_CAN_ERFFEL96 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL96_OFFSET) +#define IMX9_CAN_ERFFEL97 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL97_OFFSET) +#define IMX9_CAN_ERFFEL98 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL98_OFFSET) +#define IMX9_CAN_ERFFEL99 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL99_OFFSET) +#define IMX9_CAN_ERFFEL100 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL100_OFFSET) +#define IMX9_CAN_ERFFEL101 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL101_OFFSET) +#define IMX9_CAN_ERFFEL102 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL102_OFFSET) +#define IMX9_CAN_ERFFEL103 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL103_OFFSET) +#define IMX9_CAN_ERFFEL104 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL104_OFFSET) +#define IMX9_CAN_ERFFEL105 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL105_OFFSET) +#define IMX9_CAN_ERFFEL106 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL106_OFFSET) +#define IMX9_CAN_ERFFEL107 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL107_OFFSET) +#define IMX9_CAN_ERFFEL108 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL108_OFFSET) +#define IMX9_CAN_ERFFEL109 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL109_OFFSET) +#define IMX9_CAN_ERFFEL110 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL110_OFFSET) +#define IMX9_CAN_ERFFEL111 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL111_OFFSET) +#define IMX9_CAN_ERFFEL112 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL112_OFFSET) +#define IMX9_CAN_ERFFEL113 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL113_OFFSET) +#define IMX9_CAN_ERFFEL114 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL114_OFFSET) +#define IMX9_CAN_ERFFEL115 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL115_OFFSET) +#define IMX9_CAN_ERFFEL116 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL116_OFFSET) +#define IMX9_CAN_ERFFEL117 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL117_OFFSET) +#define IMX9_CAN_ERFFEL118 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL118_OFFSET) +#define IMX9_CAN_ERFFEL119 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL119_OFFSET) +#define IMX9_CAN_ERFFEL120 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL120_OFFSET) +#define IMX9_CAN_ERFFEL121 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL121_OFFSET) +#define IMX9_CAN_ERFFEL122 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL122_OFFSET) +#define IMX9_CAN_ERFFEL123 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL123_OFFSET) +#define IMX9_CAN_ERFFEL124 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL124_OFFSET) +#define IMX9_CAN_ERFFEL125 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL125_OFFSET) +#define IMX9_CAN_ERFFEL126 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL126_OFFSET) +#define IMX9_CAN_ERFFEL127 (IMX9_CAN_BASE + IMX9_CAN_ERFFEL127_OFFSET) + +/* Module Configuration (MCR) */ +#define CAN_MCR_MAXMB_SHIFT (0) /* Bits 0-7: Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB_MASK (0x7F << CAN_MCR_MAXMB_SHIFT) +#define CAN_MCR_MAXMB(n) (((n) << CAN_MCR_MAXMB_SHIFT) & CAN_MCR_MAXMB_MASK) +#define CAN_MCR_IDAM_SHIFT (8) /* Bits 8-10: ID Acceptance Mode */ +#define CAN_MCR_IDAM_MASK (0x3 << CAN_MCR_IDAM_SHIFT) +#define CAN_MCR_IDAM(n) (((n) << CAN_MCR_IDAM_SHIFT) & CAN_MCR_IDAM_MASK) +#define CAN_MCR_FDEN (1 << 11) /* Bit 11: CAN FD Operation Enable */ +#define CAN_MCR_AEN (1 << 12) /* Bit 12: Abort Enable */ +#define CAN_MCR_LPRIOEN (1 << 13) /* Bit 13: Local Priority Enable */ +#define CAN_MCR_DMA (1 << 15) /* Bit 15: DMA Enable */ +#define CAN_MCR_IRMQ (1 << 16) /* Bit 16: Individual RX Masking and Queue Enable */ +#define CAN_MCR_SRXDIS (1 << 17) /* Bit 17: Self-Reception Disable */ +#define CAN_MCR_DOZE (1 << 18) /* Bit 18: Doze Mode Enable */ +#define CAN_MCR_WAKSRC (1 << 19) /* Bit 19: Wake-Up Source */ +#define CAN_MCR_LPMACK (1 << 20) /* Bit 20: Low-Power Mode Acknowledge */ +#define CAN_MCR_WRNEN (1 << 21) /* Bit 21: Warning Interrupt Enable */ +#define CAN_MCR_SLFWAK (1 << 22) /* Bit 22: Self Wake-up */ +#define CAN_MCR_SUPV (1 << 23) /* Bit 23: Supervisor Mode */ +#define CAN_MCR_FRZACK (1 << 24) /* Bit 24: Freeze Mode Acknowledge */ +#define CAN_MCR_SOFTRST (1 << 25) /* Bit 25: Soft Reset */ +#define CAN_MCR_WAKMSK (1 << 26) /* Bit 26: Wake-up Interrupt Mask */ +#define CAN_MCR_NOTRDY (1 << 27) /* Bit 27: FlexCAN Not Ready */ +#define CAN_MCR_HALT (1 << 28) /* Bit 28: Halt FlexCAN */ +#define CAN_MCR_RFEN (1 << 29) /* Bit 29: Legacy RX FIFO Enable */ +#define CAN_MCR_FRZ (1 << 30) /* Bit 30: Freeze Enable */ +#define CAN_MCR_MDIS (1 << 31) /* Bit 31: Module Disable */ + +/* Control 1 (CTRL1) */ +#define CAN_CTRL1_PROPSEG_SHIFT (0) /* Bits 0-3: Propagation Segment */ +#define CAN_CTRL1_PROPSEG_MASK (0x7 << CAN_CTRL1_PROPSEG_SHIFT) +#define CAN_CTRL1_PROPSEG(n) (((n) << CAN_CTRL1_PROPSEG_SHIFT) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM (1 << 3) /* Bit 3: Listen-Only Mode */ +#define CAN_CTRL1_LBUF (1 << 4) /* Bit 4: Lowest Buffer Transmitted First */ +#define CAN_CTRL1_TSYN (1 << 5) /* Bit 5: Timer Sync */ +#define CAN_CTRL1_BOFFREC (1 << 6) /* Bit 6: Bus Off Recovery */ +#define CAN_CTRL1_SMP (1 << 7) /* Bit 7: CAN Bit Sampling */ +#define CAN_CTRL1_RWRNMSK (1 << 10) /* Bit 10: RX Warning Interrupt Mask */ +#define CAN_CTRL1_TWRNMSK (1 << 11) /* Bit 11: TX Warning Interrupt Mask */ +#define CAN_CTRL1_LPB (1 << 12) /* Bit 12: Loopback Mode */ +#define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */ +#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Interrupt Mask */ +#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Interrupt Mask */ +#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-19: Phase Segment 2 */ +#define CAN_CTRL1_PSEG2_MASK (0x7 << CAN_CTRL1_PSEG2_SHIFT) +#define CAN_CTRL1_PSEG2(n) (((n) << CAN_CTRL1_PSEG2_SHIFT) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_SHIFT (19) /* Bits 19-22: Phase Segment 1 */ +#define CAN_CTRL1_PSEG1_MASK (0x7 << CAN_CTRL1_PSEG1_SHIFT) +#define CAN_CTRL1_PSEG1(n) (((n) << CAN_CTRL1_PSEG1_SHIFT) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_SHIFT (22) /* Bits 22-24: Resync Jump Width */ +#define CAN_CTRL1_RJW_MASK (0x3 << CAN_CTRL1_RJW_SHIFT) +#define CAN_CTRL1_RJW(n) (((n) << CAN_CTRL1_RJW_SHIFT) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_SHIFT (24) /* Bits 24-32: Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV_MASK (0xFF << CAN_CTRL1_PRESDIV_SHIFT) +#define CAN_CTRL1_PRESDIV(n) (((n) << CAN_CTRL1_PRESDIV_SHIFT) & CAN_CTRL1_PRESDIV_MASK) + +/* Free-Running Timer (TIMER) */ +#define CAN_TIMER_TIMER_SHIFT (0) /* Bits 0-16: Timer Value */ +#define CAN_TIMER_TIMER_MASK (0xFFFF << CAN_TIMER_TIMER_SHIFT) +#define CAN_TIMER_TIMER(n) (((n) << CAN_TIMER_TIMER_SHIFT) & CAN_TIMER_TIMER_MASK) + +/* RX Message Buffers Global Mask (RXMGMASK) */ +#define CAN_RXMGMASK_MG_SHIFT (0) /* Bits 0-32: Global Mask for RX Message Buffers */ +#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFF << CAN_RXMGMASK_MG_SHIFT) +#define CAN_RXMGMASK_MG(n) (((n) << CAN_RXMGMASK_MG_SHIFT) & CAN_RXMGMASK_MG_MASK) + +/* Receive 14 Mask (RX14MASK) */ +#define CAN_RX14MASK_RX14M_SHIFT (0) /* Bits 0-32: RX Buffer 14 Mask Bits */ +#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFF << CAN_RX14MASK_RX14M_SHIFT) +#define CAN_RX14MASK_RX14M(n) (((n) << CAN_RX14MASK_RX14M_SHIFT) & CAN_RX14MASK_RX14M_MASK) + +/* Receive 15 Mask (RX15MASK) */ +#define CAN_RX15MASK_RX15M_SHIFT (0) /* Bits 0-32: RX Buffer 15 Mask Bits */ +#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFF << CAN_RX15MASK_RX15M_SHIFT) +#define CAN_RX15MASK_RX15M(n) (((n) << CAN_RX15MASK_RX15M_SHIFT) & CAN_RX15MASK_RX15M_MASK) + +/* Error Counter (ECR) */ +#define CAN_ECR_TXERRCNT_SHIFT (0) /* Bits 0-8: Transmit Error Counter */ +#define CAN_ECR_TXERRCNT_MASK (0xFF << CAN_ECR_TXERRCNT_SHIFT) +#define CAN_ECR_TXERRCNT(n) (((n) << CAN_ECR_TXERRCNT_SHIFT) & CAN_ECR_TXERRCNT_MASK) +#define CAN_ECR_RXERRCNT_SHIFT (8) /* Bits 8-16: Receive Error Counter */ +#define CAN_ECR_RXERRCNT_MASK (0xFF << CAN_ECR_RXERRCNT_SHIFT) +#define CAN_ECR_RXERRCNT(n) (((n) << CAN_ECR_RXERRCNT_SHIFT) & CAN_ECR_RXERRCNT_MASK) +#define CAN_ECR_TXERRCNT_FAST_SHIFT (16) /* Bits 16-24: Transmit Error Counter for Fast Bits */ +#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF << CAN_ECR_TXERRCNT_FAST_SHIFT) +#define CAN_ECR_TXERRCNT_FAST(n) (((n) << CAN_ECR_TXERRCNT_FAST_SHIFT) & CAN_ECR_TXERRCNT_FAST_MASK) +#define CAN_ECR_RXERRCNT_FAST_SHIFT (24) /* Bits 24-32: Receive Error Counter for Fast Bits */ +#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF << CAN_ECR_RXERRCNT_FAST_SHIFT) +#define CAN_ECR_RXERRCNT_FAST(n) (((n) << CAN_ECR_RXERRCNT_FAST_SHIFT) & CAN_ECR_RXERRCNT_FAST_MASK) + +/* Error and Status 1 (ESR1) */ +#define CAN_ESR1_WAKINT (1 << 0) /* Bit 0: Wake-up Interrupt Flag */ +#define CAN_ESR1_ERRINT (1 << 1) /* Bit 1: Error Interrupt Flag */ +#define CAN_ESR1_BOFFINT (1 << 2) /* Bit 2: Bus Off Interrupt Flag */ +#define CAN_ESR1_RX (1 << 3) /* Bit 3: FlexCAN in Reception Flag */ +#define CAN_ESR1_FLTCONF_SHIFT (4) /* Bits 4-6: Fault Confinement State */ +#define CAN_ESR1_FLTCONF_MASK (0x3 << CAN_ESR1_FLTCONF_SHIFT) +#define CAN_ESR1_FLTCONF(n) (((n) << CAN_ESR1_FLTCONF_SHIFT) & CAN_ESR1_FLTCONF_MASK) +#define CAN_ESR1_TX (1 << 6) /* Bit 6: FlexCAN In Transmission */ +#define CAN_ESR1_IDLE (1 << 7) /* Bit 7: Idle */ +#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: RX Error Warning Flag */ +#define CAN_ESR1_TXWRN (1 << 9) /* Bit 9: TX Error Warning Flag */ +#define CAN_ESR1_STFERR (1 << 10) /* Bit 10: Stuffing Error Flag */ +#define CAN_ESR1_FRMERR (1 << 11) /* Bit 11: Form Error Flag */ +#define CAN_ESR1_CRCERR (1 << 12) /* Bit 12: Cyclic Redundancy Check Error Flag */ +#define CAN_ESR1_ACKERR (1 << 13) /* Bit 13: Acknowledge Error Flag */ +#define CAN_ESR1_BIT0ERR (1 << 14) /* Bit 14: Bit0 Error Flag */ +#define CAN_ESR1_BIT1ERR (1 << 15) /* Bit 15: Bit1 Error Flag */ +#define CAN_ESR1_RWRNINT (1 << 16) /* Bit 16: RX Warning Interrupt Flag */ +#define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: TX Warning Interrupt Flag */ +#define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status Flag */ +#define CAN_ESR1_BOFFDONEINT (1 << 19) /* Bit 19: Bus Off Done Interrupt Flag */ +#define CAN_ESR1_ERRINT_FAST (1 << 20) /* Bit 20: Fast Error Interrupt Flag */ +#define CAN_ESR1_ERROVR (1 << 21) /* Bit 21: Error Overrun Flag */ +#define CAN_ESR1_STFERR_FAST (1 << 26) /* Bit 26: Fast Stuffing Error Flag */ +#define CAN_ESR1_FRMERR_FAST (1 << 27) /* Bit 27: Fast Form Error Flag */ +#define CAN_ESR1_CRCERR_FAST (1 << 28) /* Bit 28: Fast Cyclic Redundancy Check Error Flag */ +#define CAN_ESR1_BIT0ERR_FAST (1 << 30) /* Bit 30: Fast Bit0 Error Flag */ +#define CAN_ESR1_BIT1ERR_FAST (1 << 31) /* Bit 31: Fast Bit1 Error Flag */ + +/* Interrupt Masks 2 (IMASK2) */ +#define CAN_IMASK2_BUF63TO32M_SHIFT (0) /* Bits 0-32: Buffer MBi Mask */ +#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFF << CAN_IMASK2_BUF63TO32M_SHIFT) +#define CAN_IMASK2_BUF63TO32M(n) (((n) << CAN_IMASK2_BUF63TO32M_SHIFT) & CAN_IMASK2_BUF63TO32M_MASK) + +/* Interrupt Masks 1 (IMASK1) */ +#define CAN_IMASK1_BUF31TO0M_SHIFT (0) /* Bits 0-32: Buffer MBi Mask */ +#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFF << CAN_IMASK1_BUF31TO0M_SHIFT) +#define CAN_IMASK1_BUF31TO0M(n) (((n) << CAN_IMASK1_BUF31TO0M_SHIFT) & CAN_IMASK1_BUF31TO0M_MASK) + +/* Interrupt Flags 2 (IFLAG2) */ +#define CAN_IFLAG2_BUF63TO32I_SHIFT (0) /* Bits 0-32: Buffer MBi Interrupt */ +#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFF << CAN_IFLAG2_BUF63TO32I_SHIFT) +#define CAN_IFLAG2_BUF63TO32I(n) (((n) << CAN_IFLAG2_BUF63TO32I_SHIFT) & CAN_IFLAG2_BUF63TO32I_MASK) + +/* Interrupt Flags 1 (IFLAG1) */ +#define CAN_IFLAG1_BUF0I (1 << 0) /* Bit 0: Buffer MB0 Interrupt or Clear Legacy FIFO bit */ +#define CAN_IFLAG1_BUF4TO1I_SHIFT (1) /* Bits 1-5: Buffer MBi Interrupt or Reserved */ +#define CAN_IFLAG1_BUF4TO1I_MASK (0xF << CAN_IFLAG1_BUF4TO1I_SHIFT) +#define CAN_IFLAG1_BUF4TO1I(n) (((n) << CAN_IFLAG1_BUF4TO1I_SHIFT) & CAN_IFLAG1_BUF4TO1I_MASK) +#define CAN_IFLAG1_BUF5I (1 << 5) /* Bit 5: Buffer MB5 Interrupt or Frames available in Legacy RX FIFO */ +#define CAN_IFLAG1_BUF6I (1 << 6) /* Bit 6: Buffer MB6 Interrupt or Legacy RX FIFO Warning */ +#define CAN_IFLAG1_BUF7I (1 << 7) /* Bit 7: Buffer MB7 Interrupt or Legacy RX FIFO Overflow */ +#define CAN_IFLAG1_BUF31TO8I_SHIFT (8) /* Bits 8-32: Buffer MBi Interrupt */ +#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF << CAN_IFLAG1_BUF31TO8I_SHIFT) +#define CAN_IFLAG1_BUF31TO8I(n) (((n) << CAN_IFLAG1_BUF31TO8I_SHIFT) & CAN_IFLAG1_BUF31TO8I_MASK) + +/* Control 2 (CTRL2) */ +#define CAN_CTRL2_TSTAMPCAP_SHIFT (6) /* Bits 6-8: Timestamp Capture Point */ +#define CAN_CTRL2_TSTAMPCAP_MASK (0x3 << CAN_CTRL2_TSTAMPCAP_SHIFT) +#define CAN_CTRL2_TSTAMPCAP(n) (((n) << CAN_CTRL2_TSTAMPCAP_SHIFT) & CAN_CTRL2_TSTAMPCAP_MASK) +#define CAN_CTRL2_MBTSBASE_SHIFT (8) /* Bits 8-10: Message Buffer Timestamp Base */ +#define CAN_CTRL2_MBTSBASE_MASK (0x3 << CAN_CTRL2_MBTSBASE_SHIFT) +#define CAN_CTRL2_MBTSBASE(n) (((n) << CAN_CTRL2_MBTSBASE_SHIFT) & CAN_CTRL2_MBTSBASE_MASK) +#define CAN_CTRL2_EDFLTDIS (1 << 11) /* Bit 11: Edge Filter Disable */ +#define CAN_CTRL2_ISOCANFDEN (1 << 12) /* Bit 12: ISO CAN FD Enable */ +#define CAN_CTRL2_BTE (1 << 13) /* Bit 13: Bit Timing Expansion Enable */ +#define CAN_CTRL2_PREXCEN (1 << 14) /* Bit 14: Protocol Exception Enable */ +#define CAN_CTRL2_TIMER_SRC (1 << 15) /* Bit 15: Timer Source */ +#define CAN_CTRL2_EACEN (1 << 16) /* Bit 16: Entire Frame Arbitration Field Comparison Enable for RX Message Buffers */ +#define CAN_CTRL2_RRS (1 << 17) /* Bit 17: Remote Request Storing */ +#define CAN_CTRL2_MRP (1 << 18) /* Bit 18: Message Buffers Reception Priority */ +#define CAN_CTRL2_TASD_SHIFT (19) /* Bits 19-24: Transmission Arbitration Start Delay */ +#define CAN_CTRL2_TASD_MASK (0x1F << CAN_CTRL2_TASD_SHIFT) +#define CAN_CTRL2_TASD(n) (((n) << CAN_CTRL2_TASD_SHIFT) & CAN_CTRL2_TASD_MASK) +#define CAN_CTRL2_RFFN_SHIFT (24) /* Bits 24-28: Number of Legacy Receive FIFO Filters */ +#define CAN_CTRL2_RFFN_MASK (0xF << CAN_CTRL2_RFFN_SHIFT) +#define CAN_CTRL2_RFFN(n) (((n) << CAN_CTRL2_RFFN_SHIFT) & CAN_CTRL2_RFFN_MASK) +#define CAN_CTRL2_WRMFRZ (1 << 28) /* Bit 28: Write Access to Memory in Freeze Mode */ +#define CAN_CTRL2_ECRWRE (1 << 29) /* Bit 29: Error Correction Configuration Register Write Enable */ +#define CAN_CTRL2_BOFFDONEMSK (1 << 30) /* Bit 30: Bus Off Done Interrupt Mask */ +#define CAN_CTRL2_ERRMSK_FAST (1 << 31) /* Bit 31: Error Interrupt Mask for Errors Detected in the Data Phase of Fast CAN FD Frames */ + +/* Error and Status 2 (ESR2) */ +#define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Message Buffer */ +#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */ +#define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-23: Lowest Priority TX Message Buffer */ +#define CAN_ESR2_LPTM_MASK (0x7F << CAN_ESR2_LPTM_SHIFT) +#define CAN_ESR2_LPTM(n) (((n) << CAN_ESR2_LPTM_SHIFT) & CAN_ESR2_LPTM_MASK) + +/* Cyclic Redundancy Check (CRCR) */ +#define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-15: Transmitted CRC value */ +#define CAN_CRCR_TXCRC_MASK (0x7FFF << CAN_CRCR_TXCRC_SHIFT) +#define CAN_CRCR_TXCRC(n) (((n) << CAN_CRCR_TXCRC_SHIFT) & CAN_CRCR_TXCRC_MASK) +#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-23: CRC Message Buffer */ +#define CAN_CRCR_MBCRC_MASK (0x7F << CAN_CRCR_MBCRC_SHIFT) +#define CAN_CRCR_MBCRC(n) (((n) << CAN_CRCR_MBCRC_SHIFT) & CAN_CRCR_MBCRC_MASK) + +/* Legacy RX FIFO Global Mask (RXFGMASK) */ +#define CAN_RXFGMASK_FGM_SHIFT (0) /* Bits 0-32: Legacy RX FIFO Global Mask Bits */ +#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFF << CAN_RXFGMASK_FGM_SHIFT) +#define CAN_RXFGMASK_FGM(n) (((n) << CAN_RXFGMASK_FGM_SHIFT) & CAN_RXFGMASK_FGM_MASK) + +/* Legacy RX FIFO Information (RXFIR) */ +#define CAN_RXFIR_IDHIT_SHIFT (0) /* Bits 0-9: Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT_MASK (0x1FF << CAN_RXFIR_IDHIT_SHIFT) +#define CAN_RXFIR_IDHIT(n) (((n) << CAN_RXFIR_IDHIT_SHIFT) & CAN_RXFIR_IDHIT_MASK) + +/* CAN Bit Timing (CBT) */ +#define CAN_CBT_EPSEG2_SHIFT (0) /* Bits 0-5: Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2_MASK (0x1F << CAN_CBT_EPSEG2_SHIFT) +#define CAN_CBT_EPSEG2(n) (((n) << CAN_CBT_EPSEG2_SHIFT) & CAN_CBT_EPSEG2_MASK) +#define CAN_CBT_EPSEG1_SHIFT (5) /* Bits 5-10: Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1_MASK (0x1F << CAN_CBT_EPSEG1_SHIFT) +#define CAN_CBT_EPSEG1(n) (((n) << CAN_CBT_EPSEG1_SHIFT) & CAN_CBT_EPSEG1_MASK) +#define CAN_CBT_EPROPSEG_SHIFT (10) /* Bits 10-16: Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG_MASK (0x3F << CAN_CBT_EPROPSEG_SHIFT) +#define CAN_CBT_EPROPSEG(n) (((n) << CAN_CBT_EPROPSEG_SHIFT) & CAN_CBT_EPROPSEG_MASK) +#define CAN_CBT_ERJW_SHIFT (16) /* Bits 16-21: Extended Resync Jump Width */ +#define CAN_CBT_ERJW_MASK (0x1F << CAN_CBT_ERJW_SHIFT) +#define CAN_CBT_ERJW(n) (((n) << CAN_CBT_ERJW_SHIFT) & CAN_CBT_ERJW_MASK) +#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-31: Extended Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV_MASK (0x3FF << CAN_CBT_EPRESDIV_SHIFT) +#define CAN_CBT_EPRESDIV(n) (((n) << CAN_CBT_EPRESDIV_SHIFT) & CAN_CBT_EPRESDIV_MASK) +#define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */ + +/* Interrupt Masks 3 (IMASK3) */ +#define CAN_IMASK3_BUF95TO64M_SHIFT (0) /* Bits 0-32: Buffer MBi Mask */ +#define CAN_IMASK3_BUF95TO64M_MASK (0xFFFFFFFF << CAN_IMASK3_BUF95TO64M_SHIFT) +#define CAN_IMASK3_BUF95TO64M(n) (((n) << CAN_IMASK3_BUF95TO64M_SHIFT) & CAN_IMASK3_BUF95TO64M_MASK) + +/* Interrupt Flags 3 (IFLAG3) */ +#define CAN_IFLAG3_BUF95TO64_SHIFT (0) /* Bits 0-32: Buffer MBi Interrupt */ +#define CAN_IFLAG3_BUF95TO64_MASK (0xFFFFFFFF << CAN_IFLAG3_BUF95TO64_SHIFT) +#define CAN_IFLAG3_BUF95TO64(n) (((n) << CAN_IFLAG3_BUF95TO64_SHIFT) & CAN_IFLAG3_BUF95TO64_MASK) + +/* Message Buffer 0 CS Register (CS0) */ +#define CAN_CS0_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS0_TIME_STAMP_MASK (0xFFFF << CAN_CS0_TIME_STAMP_SHIFT) +#define CAN_CS0_TIME_STAMP(n) (((n) << CAN_CS0_TIME_STAMP_SHIFT) & CAN_CS0_TIME_STAMP_MASK) +#define CAN_CS0_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS0_DLC_MASK (0xF << CAN_CS0_DLC_SHIFT) +#define CAN_CS0_DLC(n) (((n) << CAN_CS0_DLC_SHIFT) & CAN_CS0_DLC_MASK) +#define CAN_CS0_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS0_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS0_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS0_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS0_CODE_MASK (0xF << CAN_CS0_CODE_SHIFT) +#define CAN_CS0_CODE(n) (((n) << CAN_CS0_CODE_SHIFT) & CAN_CS0_CODE_MASK) +#define CAN_CS0_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS0_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS0_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 0 WORD0 Register (WORD00) */ +#define CAN_WORD00_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD00_DATA_BYTE_3_MASK (0xFF << CAN_WORD00_DATA_BYTE_3_SHIFT) +#define CAN_WORD00_DATA_BYTE_3(n) (((n) << CAN_WORD00_DATA_BYTE_3_SHIFT) & CAN_WORD00_DATA_BYTE_3_MASK) +#define CAN_WORD00_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD00_DATA_BYTE_2_MASK (0xFF << CAN_WORD00_DATA_BYTE_2_SHIFT) +#define CAN_WORD00_DATA_BYTE_2(n) (((n) << CAN_WORD00_DATA_BYTE_2_SHIFT) & CAN_WORD00_DATA_BYTE_2_MASK) +#define CAN_WORD00_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD00_DATA_BYTE_1_MASK (0xFF << CAN_WORD00_DATA_BYTE_1_SHIFT) +#define CAN_WORD00_DATA_BYTE_1(n) (((n) << CAN_WORD00_DATA_BYTE_1_SHIFT) & CAN_WORD00_DATA_BYTE_1_MASK) +#define CAN_WORD00_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD00_DATA_BYTE_0_MASK (0xFF << CAN_WORD00_DATA_BYTE_0_SHIFT) +#define CAN_WORD00_DATA_BYTE_0(n) (((n) << CAN_WORD00_DATA_BYTE_0_SHIFT) & CAN_WORD00_DATA_BYTE_0_MASK) + +/* Message Buffer 0 WORD1 Register (WORD10) */ +#define CAN_WORD10_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD10_DATA_BYTE_7_MASK (0xFF << CAN_WORD10_DATA_BYTE_7_SHIFT) +#define CAN_WORD10_DATA_BYTE_7(n) (((n) << CAN_WORD10_DATA_BYTE_7_SHIFT) & CAN_WORD10_DATA_BYTE_7_MASK) +#define CAN_WORD10_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD10_DATA_BYTE_6_MASK (0xFF << CAN_WORD10_DATA_BYTE_6_SHIFT) +#define CAN_WORD10_DATA_BYTE_6(n) (((n) << CAN_WORD10_DATA_BYTE_6_SHIFT) & CAN_WORD10_DATA_BYTE_6_MASK) +#define CAN_WORD10_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD10_DATA_BYTE_5_MASK (0xFF << CAN_WORD10_DATA_BYTE_5_SHIFT) +#define CAN_WORD10_DATA_BYTE_5(n) (((n) << CAN_WORD10_DATA_BYTE_5_SHIFT) & CAN_WORD10_DATA_BYTE_5_MASK) +#define CAN_WORD10_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD10_DATA_BYTE_4_MASK (0xFF << CAN_WORD10_DATA_BYTE_4_SHIFT) +#define CAN_WORD10_DATA_BYTE_4(n) (((n) << CAN_WORD10_DATA_BYTE_4_SHIFT) & CAN_WORD10_DATA_BYTE_4_MASK) + +/* Message Buffer 1 CS Register (CS1) */ +#define CAN_CS1_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS1_TIME_STAMP_MASK (0xFFFF << CAN_CS1_TIME_STAMP_SHIFT) +#define CAN_CS1_TIME_STAMP(n) (((n) << CAN_CS1_TIME_STAMP_SHIFT) & CAN_CS1_TIME_STAMP_MASK) +#define CAN_CS1_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS1_DLC_MASK (0xF << CAN_CS1_DLC_SHIFT) +#define CAN_CS1_DLC(n) (((n) << CAN_CS1_DLC_SHIFT) & CAN_CS1_DLC_MASK) +#define CAN_CS1_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS1_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS1_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS1_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS1_CODE_MASK (0xF << CAN_CS1_CODE_SHIFT) +#define CAN_CS1_CODE(n) (((n) << CAN_CS1_CODE_SHIFT) & CAN_CS1_CODE_MASK) +#define CAN_CS1_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS1_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS1_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 1 WORD0 Register (WORD01) */ +#define CAN_WORD01_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD01_DATA_BYTE_3_MASK (0xFF << CAN_WORD01_DATA_BYTE_3_SHIFT) +#define CAN_WORD01_DATA_BYTE_3(n) (((n) << CAN_WORD01_DATA_BYTE_3_SHIFT) & CAN_WORD01_DATA_BYTE_3_MASK) +#define CAN_WORD01_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD01_DATA_BYTE_2_MASK (0xFF << CAN_WORD01_DATA_BYTE_2_SHIFT) +#define CAN_WORD01_DATA_BYTE_2(n) (((n) << CAN_WORD01_DATA_BYTE_2_SHIFT) & CAN_WORD01_DATA_BYTE_2_MASK) +#define CAN_WORD01_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD01_DATA_BYTE_1_MASK (0xFF << CAN_WORD01_DATA_BYTE_1_SHIFT) +#define CAN_WORD01_DATA_BYTE_1(n) (((n) << CAN_WORD01_DATA_BYTE_1_SHIFT) & CAN_WORD01_DATA_BYTE_1_MASK) +#define CAN_WORD01_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD01_DATA_BYTE_0_MASK (0xFF << CAN_WORD01_DATA_BYTE_0_SHIFT) +#define CAN_WORD01_DATA_BYTE_0(n) (((n) << CAN_WORD01_DATA_BYTE_0_SHIFT) & CAN_WORD01_DATA_BYTE_0_MASK) + +/* Message Buffer 1 WORD1 Register (WORD11) */ +#define CAN_WORD11_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD11_DATA_BYTE_7_MASK (0xFF << CAN_WORD11_DATA_BYTE_7_SHIFT) +#define CAN_WORD11_DATA_BYTE_7(n) (((n) << CAN_WORD11_DATA_BYTE_7_SHIFT) & CAN_WORD11_DATA_BYTE_7_MASK) +#define CAN_WORD11_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD11_DATA_BYTE_6_MASK (0xFF << CAN_WORD11_DATA_BYTE_6_SHIFT) +#define CAN_WORD11_DATA_BYTE_6(n) (((n) << CAN_WORD11_DATA_BYTE_6_SHIFT) & CAN_WORD11_DATA_BYTE_6_MASK) +#define CAN_WORD11_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD11_DATA_BYTE_5_MASK (0xFF << CAN_WORD11_DATA_BYTE_5_SHIFT) +#define CAN_WORD11_DATA_BYTE_5(n) (((n) << CAN_WORD11_DATA_BYTE_5_SHIFT) & CAN_WORD11_DATA_BYTE_5_MASK) +#define CAN_WORD11_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD11_DATA_BYTE_4_MASK (0xFF << CAN_WORD11_DATA_BYTE_4_SHIFT) +#define CAN_WORD11_DATA_BYTE_4(n) (((n) << CAN_WORD11_DATA_BYTE_4_SHIFT) & CAN_WORD11_DATA_BYTE_4_MASK) + +/* Message Buffer 2 CS Register (CS2) */ +#define CAN_CS2_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS2_TIME_STAMP_MASK (0xFFFF << CAN_CS2_TIME_STAMP_SHIFT) +#define CAN_CS2_TIME_STAMP(n) (((n) << CAN_CS2_TIME_STAMP_SHIFT) & CAN_CS2_TIME_STAMP_MASK) +#define CAN_CS2_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS2_DLC_MASK (0xF << CAN_CS2_DLC_SHIFT) +#define CAN_CS2_DLC(n) (((n) << CAN_CS2_DLC_SHIFT) & CAN_CS2_DLC_MASK) +#define CAN_CS2_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS2_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS2_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS2_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS2_CODE_MASK (0xF << CAN_CS2_CODE_SHIFT) +#define CAN_CS2_CODE(n) (((n) << CAN_CS2_CODE_SHIFT) & CAN_CS2_CODE_MASK) +#define CAN_CS2_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS2_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS2_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 2 WORD0 Register (WORD02) */ +#define CAN_WORD02_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD02_DATA_BYTE_3_MASK (0xFF << CAN_WORD02_DATA_BYTE_3_SHIFT) +#define CAN_WORD02_DATA_BYTE_3(n) (((n) << CAN_WORD02_DATA_BYTE_3_SHIFT) & CAN_WORD02_DATA_BYTE_3_MASK) +#define CAN_WORD02_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD02_DATA_BYTE_2_MASK (0xFF << CAN_WORD02_DATA_BYTE_2_SHIFT) +#define CAN_WORD02_DATA_BYTE_2(n) (((n) << CAN_WORD02_DATA_BYTE_2_SHIFT) & CAN_WORD02_DATA_BYTE_2_MASK) +#define CAN_WORD02_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD02_DATA_BYTE_1_MASK (0xFF << CAN_WORD02_DATA_BYTE_1_SHIFT) +#define CAN_WORD02_DATA_BYTE_1(n) (((n) << CAN_WORD02_DATA_BYTE_1_SHIFT) & CAN_WORD02_DATA_BYTE_1_MASK) +#define CAN_WORD02_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD02_DATA_BYTE_0_MASK (0xFF << CAN_WORD02_DATA_BYTE_0_SHIFT) +#define CAN_WORD02_DATA_BYTE_0(n) (((n) << CAN_WORD02_DATA_BYTE_0_SHIFT) & CAN_WORD02_DATA_BYTE_0_MASK) + +/* Message Buffer 2 WORD1 Register (WORD12) */ +#define CAN_WORD12_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD12_DATA_BYTE_7_MASK (0xFF << CAN_WORD12_DATA_BYTE_7_SHIFT) +#define CAN_WORD12_DATA_BYTE_7(n) (((n) << CAN_WORD12_DATA_BYTE_7_SHIFT) & CAN_WORD12_DATA_BYTE_7_MASK) +#define CAN_WORD12_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD12_DATA_BYTE_6_MASK (0xFF << CAN_WORD12_DATA_BYTE_6_SHIFT) +#define CAN_WORD12_DATA_BYTE_6(n) (((n) << CAN_WORD12_DATA_BYTE_6_SHIFT) & CAN_WORD12_DATA_BYTE_6_MASK) +#define CAN_WORD12_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD12_DATA_BYTE_5_MASK (0xFF << CAN_WORD12_DATA_BYTE_5_SHIFT) +#define CAN_WORD12_DATA_BYTE_5(n) (((n) << CAN_WORD12_DATA_BYTE_5_SHIFT) & CAN_WORD12_DATA_BYTE_5_MASK) +#define CAN_WORD12_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD12_DATA_BYTE_4_MASK (0xFF << CAN_WORD12_DATA_BYTE_4_SHIFT) +#define CAN_WORD12_DATA_BYTE_4(n) (((n) << CAN_WORD12_DATA_BYTE_4_SHIFT) & CAN_WORD12_DATA_BYTE_4_MASK) + +/* Message Buffer 3 CS Register (CS3) */ +#define CAN_CS3_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS3_TIME_STAMP_MASK (0xFFFF << CAN_CS3_TIME_STAMP_SHIFT) +#define CAN_CS3_TIME_STAMP(n) (((n) << CAN_CS3_TIME_STAMP_SHIFT) & CAN_CS3_TIME_STAMP_MASK) +#define CAN_CS3_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS3_DLC_MASK (0xF << CAN_CS3_DLC_SHIFT) +#define CAN_CS3_DLC(n) (((n) << CAN_CS3_DLC_SHIFT) & CAN_CS3_DLC_MASK) +#define CAN_CS3_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS3_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS3_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS3_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS3_CODE_MASK (0xF << CAN_CS3_CODE_SHIFT) +#define CAN_CS3_CODE(n) (((n) << CAN_CS3_CODE_SHIFT) & CAN_CS3_CODE_MASK) +#define CAN_CS3_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS3_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS3_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 3 WORD0 Register (WORD03) */ +#define CAN_WORD03_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD03_DATA_BYTE_3_MASK (0xFF << CAN_WORD03_DATA_BYTE_3_SHIFT) +#define CAN_WORD03_DATA_BYTE_3(n) (((n) << CAN_WORD03_DATA_BYTE_3_SHIFT) & CAN_WORD03_DATA_BYTE_3_MASK) +#define CAN_WORD03_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD03_DATA_BYTE_2_MASK (0xFF << CAN_WORD03_DATA_BYTE_2_SHIFT) +#define CAN_WORD03_DATA_BYTE_2(n) (((n) << CAN_WORD03_DATA_BYTE_2_SHIFT) & CAN_WORD03_DATA_BYTE_2_MASK) +#define CAN_WORD03_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD03_DATA_BYTE_1_MASK (0xFF << CAN_WORD03_DATA_BYTE_1_SHIFT) +#define CAN_WORD03_DATA_BYTE_1(n) (((n) << CAN_WORD03_DATA_BYTE_1_SHIFT) & CAN_WORD03_DATA_BYTE_1_MASK) +#define CAN_WORD03_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD03_DATA_BYTE_0_MASK (0xFF << CAN_WORD03_DATA_BYTE_0_SHIFT) +#define CAN_WORD03_DATA_BYTE_0(n) (((n) << CAN_WORD03_DATA_BYTE_0_SHIFT) & CAN_WORD03_DATA_BYTE_0_MASK) + +/* Message Buffer 3 WORD1 Register (WORD13) */ +#define CAN_WORD13_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD13_DATA_BYTE_7_MASK (0xFF << CAN_WORD13_DATA_BYTE_7_SHIFT) +#define CAN_WORD13_DATA_BYTE_7(n) (((n) << CAN_WORD13_DATA_BYTE_7_SHIFT) & CAN_WORD13_DATA_BYTE_7_MASK) +#define CAN_WORD13_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD13_DATA_BYTE_6_MASK (0xFF << CAN_WORD13_DATA_BYTE_6_SHIFT) +#define CAN_WORD13_DATA_BYTE_6(n) (((n) << CAN_WORD13_DATA_BYTE_6_SHIFT) & CAN_WORD13_DATA_BYTE_6_MASK) +#define CAN_WORD13_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD13_DATA_BYTE_5_MASK (0xFF << CAN_WORD13_DATA_BYTE_5_SHIFT) +#define CAN_WORD13_DATA_BYTE_5(n) (((n) << CAN_WORD13_DATA_BYTE_5_SHIFT) & CAN_WORD13_DATA_BYTE_5_MASK) +#define CAN_WORD13_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD13_DATA_BYTE_4_MASK (0xFF << CAN_WORD13_DATA_BYTE_4_SHIFT) +#define CAN_WORD13_DATA_BYTE_4(n) (((n) << CAN_WORD13_DATA_BYTE_4_SHIFT) & CAN_WORD13_DATA_BYTE_4_MASK) + +/* Message Buffer 4 CS Register (CS4) */ +#define CAN_CS4_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS4_TIME_STAMP_MASK (0xFFFF << CAN_CS4_TIME_STAMP_SHIFT) +#define CAN_CS4_TIME_STAMP(n) (((n) << CAN_CS4_TIME_STAMP_SHIFT) & CAN_CS4_TIME_STAMP_MASK) +#define CAN_CS4_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS4_DLC_MASK (0xF << CAN_CS4_DLC_SHIFT) +#define CAN_CS4_DLC(n) (((n) << CAN_CS4_DLC_SHIFT) & CAN_CS4_DLC_MASK) +#define CAN_CS4_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS4_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS4_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS4_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS4_CODE_MASK (0xF << CAN_CS4_CODE_SHIFT) +#define CAN_CS4_CODE(n) (((n) << CAN_CS4_CODE_SHIFT) & CAN_CS4_CODE_MASK) +#define CAN_CS4_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS4_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS4_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 4 WORD0 Register (WORD04) */ +#define CAN_WORD04_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD04_DATA_BYTE_3_MASK (0xFF << CAN_WORD04_DATA_BYTE_3_SHIFT) +#define CAN_WORD04_DATA_BYTE_3(n) (((n) << CAN_WORD04_DATA_BYTE_3_SHIFT) & CAN_WORD04_DATA_BYTE_3_MASK) +#define CAN_WORD04_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD04_DATA_BYTE_2_MASK (0xFF << CAN_WORD04_DATA_BYTE_2_SHIFT) +#define CAN_WORD04_DATA_BYTE_2(n) (((n) << CAN_WORD04_DATA_BYTE_2_SHIFT) & CAN_WORD04_DATA_BYTE_2_MASK) +#define CAN_WORD04_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD04_DATA_BYTE_1_MASK (0xFF << CAN_WORD04_DATA_BYTE_1_SHIFT) +#define CAN_WORD04_DATA_BYTE_1(n) (((n) << CAN_WORD04_DATA_BYTE_1_SHIFT) & CAN_WORD04_DATA_BYTE_1_MASK) +#define CAN_WORD04_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD04_DATA_BYTE_0_MASK (0xFF << CAN_WORD04_DATA_BYTE_0_SHIFT) +#define CAN_WORD04_DATA_BYTE_0(n) (((n) << CAN_WORD04_DATA_BYTE_0_SHIFT) & CAN_WORD04_DATA_BYTE_0_MASK) + +/* Message Buffer 4 WORD1 Register (WORD14) */ +#define CAN_WORD14_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD14_DATA_BYTE_7_MASK (0xFF << CAN_WORD14_DATA_BYTE_7_SHIFT) +#define CAN_WORD14_DATA_BYTE_7(n) (((n) << CAN_WORD14_DATA_BYTE_7_SHIFT) & CAN_WORD14_DATA_BYTE_7_MASK) +#define CAN_WORD14_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD14_DATA_BYTE_6_MASK (0xFF << CAN_WORD14_DATA_BYTE_6_SHIFT) +#define CAN_WORD14_DATA_BYTE_6(n) (((n) << CAN_WORD14_DATA_BYTE_6_SHIFT) & CAN_WORD14_DATA_BYTE_6_MASK) +#define CAN_WORD14_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD14_DATA_BYTE_5_MASK (0xFF << CAN_WORD14_DATA_BYTE_5_SHIFT) +#define CAN_WORD14_DATA_BYTE_5(n) (((n) << CAN_WORD14_DATA_BYTE_5_SHIFT) & CAN_WORD14_DATA_BYTE_5_MASK) +#define CAN_WORD14_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD14_DATA_BYTE_4_MASK (0xFF << CAN_WORD14_DATA_BYTE_4_SHIFT) +#define CAN_WORD14_DATA_BYTE_4(n) (((n) << CAN_WORD14_DATA_BYTE_4_SHIFT) & CAN_WORD14_DATA_BYTE_4_MASK) + +/* Message Buffer 5 CS Register (CS5) */ +#define CAN_CS5_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS5_TIME_STAMP_MASK (0xFFFF << CAN_CS5_TIME_STAMP_SHIFT) +#define CAN_CS5_TIME_STAMP(n) (((n) << CAN_CS5_TIME_STAMP_SHIFT) & CAN_CS5_TIME_STAMP_MASK) +#define CAN_CS5_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS5_DLC_MASK (0xF << CAN_CS5_DLC_SHIFT) +#define CAN_CS5_DLC(n) (((n) << CAN_CS5_DLC_SHIFT) & CAN_CS5_DLC_MASK) +#define CAN_CS5_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS5_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS5_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS5_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS5_CODE_MASK (0xF << CAN_CS5_CODE_SHIFT) +#define CAN_CS5_CODE(n) (((n) << CAN_CS5_CODE_SHIFT) & CAN_CS5_CODE_MASK) +#define CAN_CS5_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS5_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS5_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 5 WORD0 Register (WORD05) */ +#define CAN_WORD05_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD05_DATA_BYTE_3_MASK (0xFF << CAN_WORD05_DATA_BYTE_3_SHIFT) +#define CAN_WORD05_DATA_BYTE_3(n) (((n) << CAN_WORD05_DATA_BYTE_3_SHIFT) & CAN_WORD05_DATA_BYTE_3_MASK) +#define CAN_WORD05_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD05_DATA_BYTE_2_MASK (0xFF << CAN_WORD05_DATA_BYTE_2_SHIFT) +#define CAN_WORD05_DATA_BYTE_2(n) (((n) << CAN_WORD05_DATA_BYTE_2_SHIFT) & CAN_WORD05_DATA_BYTE_2_MASK) +#define CAN_WORD05_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD05_DATA_BYTE_1_MASK (0xFF << CAN_WORD05_DATA_BYTE_1_SHIFT) +#define CAN_WORD05_DATA_BYTE_1(n) (((n) << CAN_WORD05_DATA_BYTE_1_SHIFT) & CAN_WORD05_DATA_BYTE_1_MASK) +#define CAN_WORD05_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD05_DATA_BYTE_0_MASK (0xFF << CAN_WORD05_DATA_BYTE_0_SHIFT) +#define CAN_WORD05_DATA_BYTE_0(n) (((n) << CAN_WORD05_DATA_BYTE_0_SHIFT) & CAN_WORD05_DATA_BYTE_0_MASK) + +/* Message Buffer 5 WORD1 Register (WORD15) */ +#define CAN_WORD15_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD15_DATA_BYTE_7_MASK (0xFF << CAN_WORD15_DATA_BYTE_7_SHIFT) +#define CAN_WORD15_DATA_BYTE_7(n) (((n) << CAN_WORD15_DATA_BYTE_7_SHIFT) & CAN_WORD15_DATA_BYTE_7_MASK) +#define CAN_WORD15_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD15_DATA_BYTE_6_MASK (0xFF << CAN_WORD15_DATA_BYTE_6_SHIFT) +#define CAN_WORD15_DATA_BYTE_6(n) (((n) << CAN_WORD15_DATA_BYTE_6_SHIFT) & CAN_WORD15_DATA_BYTE_6_MASK) +#define CAN_WORD15_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD15_DATA_BYTE_5_MASK (0xFF << CAN_WORD15_DATA_BYTE_5_SHIFT) +#define CAN_WORD15_DATA_BYTE_5(n) (((n) << CAN_WORD15_DATA_BYTE_5_SHIFT) & CAN_WORD15_DATA_BYTE_5_MASK) +#define CAN_WORD15_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD15_DATA_BYTE_4_MASK (0xFF << CAN_WORD15_DATA_BYTE_4_SHIFT) +#define CAN_WORD15_DATA_BYTE_4(n) (((n) << CAN_WORD15_DATA_BYTE_4_SHIFT) & CAN_WORD15_DATA_BYTE_4_MASK) + +/* Message Buffer 6 CS Register (CS6) */ +#define CAN_CS6_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS6_TIME_STAMP_MASK (0xFFFF << CAN_CS6_TIME_STAMP_SHIFT) +#define CAN_CS6_TIME_STAMP(n) (((n) << CAN_CS6_TIME_STAMP_SHIFT) & CAN_CS6_TIME_STAMP_MASK) +#define CAN_CS6_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS6_DLC_MASK (0xF << CAN_CS6_DLC_SHIFT) +#define CAN_CS6_DLC(n) (((n) << CAN_CS6_DLC_SHIFT) & CAN_CS6_DLC_MASK) +#define CAN_CS6_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS6_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS6_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS6_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS6_CODE_MASK (0xF << CAN_CS6_CODE_SHIFT) +#define CAN_CS6_CODE(n) (((n) << CAN_CS6_CODE_SHIFT) & CAN_CS6_CODE_MASK) +#define CAN_CS6_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS6_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS6_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 6 WORD0 Register (WORD06) */ +#define CAN_WORD06_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD06_DATA_BYTE_3_MASK (0xFF << CAN_WORD06_DATA_BYTE_3_SHIFT) +#define CAN_WORD06_DATA_BYTE_3(n) (((n) << CAN_WORD06_DATA_BYTE_3_SHIFT) & CAN_WORD06_DATA_BYTE_3_MASK) +#define CAN_WORD06_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD06_DATA_BYTE_2_MASK (0xFF << CAN_WORD06_DATA_BYTE_2_SHIFT) +#define CAN_WORD06_DATA_BYTE_2(n) (((n) << CAN_WORD06_DATA_BYTE_2_SHIFT) & CAN_WORD06_DATA_BYTE_2_MASK) +#define CAN_WORD06_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD06_DATA_BYTE_1_MASK (0xFF << CAN_WORD06_DATA_BYTE_1_SHIFT) +#define CAN_WORD06_DATA_BYTE_1(n) (((n) << CAN_WORD06_DATA_BYTE_1_SHIFT) & CAN_WORD06_DATA_BYTE_1_MASK) +#define CAN_WORD06_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD06_DATA_BYTE_0_MASK (0xFF << CAN_WORD06_DATA_BYTE_0_SHIFT) +#define CAN_WORD06_DATA_BYTE_0(n) (((n) << CAN_WORD06_DATA_BYTE_0_SHIFT) & CAN_WORD06_DATA_BYTE_0_MASK) + +/* Message Buffer 6 WORD1 Register (WORD16) */ +#define CAN_WORD16_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD16_DATA_BYTE_7_MASK (0xFF << CAN_WORD16_DATA_BYTE_7_SHIFT) +#define CAN_WORD16_DATA_BYTE_7(n) (((n) << CAN_WORD16_DATA_BYTE_7_SHIFT) & CAN_WORD16_DATA_BYTE_7_MASK) +#define CAN_WORD16_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD16_DATA_BYTE_6_MASK (0xFF << CAN_WORD16_DATA_BYTE_6_SHIFT) +#define CAN_WORD16_DATA_BYTE_6(n) (((n) << CAN_WORD16_DATA_BYTE_6_SHIFT) & CAN_WORD16_DATA_BYTE_6_MASK) +#define CAN_WORD16_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD16_DATA_BYTE_5_MASK (0xFF << CAN_WORD16_DATA_BYTE_5_SHIFT) +#define CAN_WORD16_DATA_BYTE_5(n) (((n) << CAN_WORD16_DATA_BYTE_5_SHIFT) & CAN_WORD16_DATA_BYTE_5_MASK) +#define CAN_WORD16_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD16_DATA_BYTE_4_MASK (0xFF << CAN_WORD16_DATA_BYTE_4_SHIFT) +#define CAN_WORD16_DATA_BYTE_4(n) (((n) << CAN_WORD16_DATA_BYTE_4_SHIFT) & CAN_WORD16_DATA_BYTE_4_MASK) + +/* Message Buffer 7 CS Register (CS7) */ +#define CAN_CS7_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS7_TIME_STAMP_MASK (0xFFFF << CAN_CS7_TIME_STAMP_SHIFT) +#define CAN_CS7_TIME_STAMP(n) (((n) << CAN_CS7_TIME_STAMP_SHIFT) & CAN_CS7_TIME_STAMP_MASK) +#define CAN_CS7_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS7_DLC_MASK (0xF << CAN_CS7_DLC_SHIFT) +#define CAN_CS7_DLC(n) (((n) << CAN_CS7_DLC_SHIFT) & CAN_CS7_DLC_MASK) +#define CAN_CS7_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS7_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS7_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS7_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS7_CODE_MASK (0xF << CAN_CS7_CODE_SHIFT) +#define CAN_CS7_CODE(n) (((n) << CAN_CS7_CODE_SHIFT) & CAN_CS7_CODE_MASK) +#define CAN_CS7_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS7_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS7_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 7 WORD0 Register (WORD07) */ +#define CAN_WORD07_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD07_DATA_BYTE_3_MASK (0xFF << CAN_WORD07_DATA_BYTE_3_SHIFT) +#define CAN_WORD07_DATA_BYTE_3(n) (((n) << CAN_WORD07_DATA_BYTE_3_SHIFT) & CAN_WORD07_DATA_BYTE_3_MASK) +#define CAN_WORD07_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD07_DATA_BYTE_2_MASK (0xFF << CAN_WORD07_DATA_BYTE_2_SHIFT) +#define CAN_WORD07_DATA_BYTE_2(n) (((n) << CAN_WORD07_DATA_BYTE_2_SHIFT) & CAN_WORD07_DATA_BYTE_2_MASK) +#define CAN_WORD07_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD07_DATA_BYTE_1_MASK (0xFF << CAN_WORD07_DATA_BYTE_1_SHIFT) +#define CAN_WORD07_DATA_BYTE_1(n) (((n) << CAN_WORD07_DATA_BYTE_1_SHIFT) & CAN_WORD07_DATA_BYTE_1_MASK) +#define CAN_WORD07_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD07_DATA_BYTE_0_MASK (0xFF << CAN_WORD07_DATA_BYTE_0_SHIFT) +#define CAN_WORD07_DATA_BYTE_0(n) (((n) << CAN_WORD07_DATA_BYTE_0_SHIFT) & CAN_WORD07_DATA_BYTE_0_MASK) + +/* Message Buffer 7 WORD1 Register (WORD17) */ +#define CAN_WORD17_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD17_DATA_BYTE_7_MASK (0xFF << CAN_WORD17_DATA_BYTE_7_SHIFT) +#define CAN_WORD17_DATA_BYTE_7(n) (((n) << CAN_WORD17_DATA_BYTE_7_SHIFT) & CAN_WORD17_DATA_BYTE_7_MASK) +#define CAN_WORD17_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD17_DATA_BYTE_6_MASK (0xFF << CAN_WORD17_DATA_BYTE_6_SHIFT) +#define CAN_WORD17_DATA_BYTE_6(n) (((n) << CAN_WORD17_DATA_BYTE_6_SHIFT) & CAN_WORD17_DATA_BYTE_6_MASK) +#define CAN_WORD17_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD17_DATA_BYTE_5_MASK (0xFF << CAN_WORD17_DATA_BYTE_5_SHIFT) +#define CAN_WORD17_DATA_BYTE_5(n) (((n) << CAN_WORD17_DATA_BYTE_5_SHIFT) & CAN_WORD17_DATA_BYTE_5_MASK) +#define CAN_WORD17_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD17_DATA_BYTE_4_MASK (0xFF << CAN_WORD17_DATA_BYTE_4_SHIFT) +#define CAN_WORD17_DATA_BYTE_4(n) (((n) << CAN_WORD17_DATA_BYTE_4_SHIFT) & CAN_WORD17_DATA_BYTE_4_MASK) + +/* Message Buffer 8 CS Register (CS8) */ +#define CAN_CS8_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS8_TIME_STAMP_MASK (0xFFFF << CAN_CS8_TIME_STAMP_SHIFT) +#define CAN_CS8_TIME_STAMP(n) (((n) << CAN_CS8_TIME_STAMP_SHIFT) & CAN_CS8_TIME_STAMP_MASK) +#define CAN_CS8_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS8_DLC_MASK (0xF << CAN_CS8_DLC_SHIFT) +#define CAN_CS8_DLC(n) (((n) << CAN_CS8_DLC_SHIFT) & CAN_CS8_DLC_MASK) +#define CAN_CS8_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS8_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS8_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS8_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS8_CODE_MASK (0xF << CAN_CS8_CODE_SHIFT) +#define CAN_CS8_CODE(n) (((n) << CAN_CS8_CODE_SHIFT) & CAN_CS8_CODE_MASK) +#define CAN_CS8_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS8_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS8_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 8 WORD0 Register (WORD08) */ +#define CAN_WORD08_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD08_DATA_BYTE_3_MASK (0xFF << CAN_WORD08_DATA_BYTE_3_SHIFT) +#define CAN_WORD08_DATA_BYTE_3(n) (((n) << CAN_WORD08_DATA_BYTE_3_SHIFT) & CAN_WORD08_DATA_BYTE_3_MASK) +#define CAN_WORD08_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD08_DATA_BYTE_2_MASK (0xFF << CAN_WORD08_DATA_BYTE_2_SHIFT) +#define CAN_WORD08_DATA_BYTE_2(n) (((n) << CAN_WORD08_DATA_BYTE_2_SHIFT) & CAN_WORD08_DATA_BYTE_2_MASK) +#define CAN_WORD08_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD08_DATA_BYTE_1_MASK (0xFF << CAN_WORD08_DATA_BYTE_1_SHIFT) +#define CAN_WORD08_DATA_BYTE_1(n) (((n) << CAN_WORD08_DATA_BYTE_1_SHIFT) & CAN_WORD08_DATA_BYTE_1_MASK) +#define CAN_WORD08_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD08_DATA_BYTE_0_MASK (0xFF << CAN_WORD08_DATA_BYTE_0_SHIFT) +#define CAN_WORD08_DATA_BYTE_0(n) (((n) << CAN_WORD08_DATA_BYTE_0_SHIFT) & CAN_WORD08_DATA_BYTE_0_MASK) + +/* Message Buffer 8 WORD1 Register (WORD18) */ +#define CAN_WORD18_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD18_DATA_BYTE_7_MASK (0xFF << CAN_WORD18_DATA_BYTE_7_SHIFT) +#define CAN_WORD18_DATA_BYTE_7(n) (((n) << CAN_WORD18_DATA_BYTE_7_SHIFT) & CAN_WORD18_DATA_BYTE_7_MASK) +#define CAN_WORD18_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD18_DATA_BYTE_6_MASK (0xFF << CAN_WORD18_DATA_BYTE_6_SHIFT) +#define CAN_WORD18_DATA_BYTE_6(n) (((n) << CAN_WORD18_DATA_BYTE_6_SHIFT) & CAN_WORD18_DATA_BYTE_6_MASK) +#define CAN_WORD18_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD18_DATA_BYTE_5_MASK (0xFF << CAN_WORD18_DATA_BYTE_5_SHIFT) +#define CAN_WORD18_DATA_BYTE_5(n) (((n) << CAN_WORD18_DATA_BYTE_5_SHIFT) & CAN_WORD18_DATA_BYTE_5_MASK) +#define CAN_WORD18_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD18_DATA_BYTE_4_MASK (0xFF << CAN_WORD18_DATA_BYTE_4_SHIFT) +#define CAN_WORD18_DATA_BYTE_4(n) (((n) << CAN_WORD18_DATA_BYTE_4_SHIFT) & CAN_WORD18_DATA_BYTE_4_MASK) + +/* Message Buffer 9 CS Register (CS9) */ +#define CAN_CS9_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS9_TIME_STAMP_MASK (0xFFFF << CAN_CS9_TIME_STAMP_SHIFT) +#define CAN_CS9_TIME_STAMP(n) (((n) << CAN_CS9_TIME_STAMP_SHIFT) & CAN_CS9_TIME_STAMP_MASK) +#define CAN_CS9_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS9_DLC_MASK (0xF << CAN_CS9_DLC_SHIFT) +#define CAN_CS9_DLC(n) (((n) << CAN_CS9_DLC_SHIFT) & CAN_CS9_DLC_MASK) +#define CAN_CS9_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS9_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS9_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS9_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS9_CODE_MASK (0xF << CAN_CS9_CODE_SHIFT) +#define CAN_CS9_CODE(n) (((n) << CAN_CS9_CODE_SHIFT) & CAN_CS9_CODE_MASK) +#define CAN_CS9_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS9_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS9_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 9 WORD0 Register (WORD09) */ +#define CAN_WORD09_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD09_DATA_BYTE_3_MASK (0xFF << CAN_WORD09_DATA_BYTE_3_SHIFT) +#define CAN_WORD09_DATA_BYTE_3(n) (((n) << CAN_WORD09_DATA_BYTE_3_SHIFT) & CAN_WORD09_DATA_BYTE_3_MASK) +#define CAN_WORD09_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD09_DATA_BYTE_2_MASK (0xFF << CAN_WORD09_DATA_BYTE_2_SHIFT) +#define CAN_WORD09_DATA_BYTE_2(n) (((n) << CAN_WORD09_DATA_BYTE_2_SHIFT) & CAN_WORD09_DATA_BYTE_2_MASK) +#define CAN_WORD09_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD09_DATA_BYTE_1_MASK (0xFF << CAN_WORD09_DATA_BYTE_1_SHIFT) +#define CAN_WORD09_DATA_BYTE_1(n) (((n) << CAN_WORD09_DATA_BYTE_1_SHIFT) & CAN_WORD09_DATA_BYTE_1_MASK) +#define CAN_WORD09_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD09_DATA_BYTE_0_MASK (0xFF << CAN_WORD09_DATA_BYTE_0_SHIFT) +#define CAN_WORD09_DATA_BYTE_0(n) (((n) << CAN_WORD09_DATA_BYTE_0_SHIFT) & CAN_WORD09_DATA_BYTE_0_MASK) + +/* Message Buffer 9 WORD1 Register (WORD19) */ +#define CAN_WORD19_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD19_DATA_BYTE_7_MASK (0xFF << CAN_WORD19_DATA_BYTE_7_SHIFT) +#define CAN_WORD19_DATA_BYTE_7(n) (((n) << CAN_WORD19_DATA_BYTE_7_SHIFT) & CAN_WORD19_DATA_BYTE_7_MASK) +#define CAN_WORD19_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD19_DATA_BYTE_6_MASK (0xFF << CAN_WORD19_DATA_BYTE_6_SHIFT) +#define CAN_WORD19_DATA_BYTE_6(n) (((n) << CAN_WORD19_DATA_BYTE_6_SHIFT) & CAN_WORD19_DATA_BYTE_6_MASK) +#define CAN_WORD19_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD19_DATA_BYTE_5_MASK (0xFF << CAN_WORD19_DATA_BYTE_5_SHIFT) +#define CAN_WORD19_DATA_BYTE_5(n) (((n) << CAN_WORD19_DATA_BYTE_5_SHIFT) & CAN_WORD19_DATA_BYTE_5_MASK) +#define CAN_WORD19_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD19_DATA_BYTE_4_MASK (0xFF << CAN_WORD19_DATA_BYTE_4_SHIFT) +#define CAN_WORD19_DATA_BYTE_4(n) (((n) << CAN_WORD19_DATA_BYTE_4_SHIFT) & CAN_WORD19_DATA_BYTE_4_MASK) + +/* Message Buffer 10 CS Register (CS10) */ +#define CAN_CS10_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS10_TIME_STAMP_MASK (0xFFFF << CAN_CS10_TIME_STAMP_SHIFT) +#define CAN_CS10_TIME_STAMP(n) (((n) << CAN_CS10_TIME_STAMP_SHIFT) & CAN_CS10_TIME_STAMP_MASK) +#define CAN_CS10_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS10_DLC_MASK (0xF << CAN_CS10_DLC_SHIFT) +#define CAN_CS10_DLC(n) (((n) << CAN_CS10_DLC_SHIFT) & CAN_CS10_DLC_MASK) +#define CAN_CS10_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS10_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS10_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS10_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS10_CODE_MASK (0xF << CAN_CS10_CODE_SHIFT) +#define CAN_CS10_CODE(n) (((n) << CAN_CS10_CODE_SHIFT) & CAN_CS10_CODE_MASK) +#define CAN_CS10_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS10_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS10_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 10 WORD0 Register (WORD010) */ +#define CAN_WORD010_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD010_DATA_BYTE_3_MASK (0xFF << CAN_WORD010_DATA_BYTE_3_SHIFT) +#define CAN_WORD010_DATA_BYTE_3(n) (((n) << CAN_WORD010_DATA_BYTE_3_SHIFT) & CAN_WORD010_DATA_BYTE_3_MASK) +#define CAN_WORD010_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD010_DATA_BYTE_2_MASK (0xFF << CAN_WORD010_DATA_BYTE_2_SHIFT) +#define CAN_WORD010_DATA_BYTE_2(n) (((n) << CAN_WORD010_DATA_BYTE_2_SHIFT) & CAN_WORD010_DATA_BYTE_2_MASK) +#define CAN_WORD010_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD010_DATA_BYTE_1_MASK (0xFF << CAN_WORD010_DATA_BYTE_1_SHIFT) +#define CAN_WORD010_DATA_BYTE_1(n) (((n) << CAN_WORD010_DATA_BYTE_1_SHIFT) & CAN_WORD010_DATA_BYTE_1_MASK) +#define CAN_WORD010_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD010_DATA_BYTE_0_MASK (0xFF << CAN_WORD010_DATA_BYTE_0_SHIFT) +#define CAN_WORD010_DATA_BYTE_0(n) (((n) << CAN_WORD010_DATA_BYTE_0_SHIFT) & CAN_WORD010_DATA_BYTE_0_MASK) + +/* Message Buffer 10 WORD1 Register (WORD110) */ +#define CAN_WORD110_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD110_DATA_BYTE_7_MASK (0xFF << CAN_WORD110_DATA_BYTE_7_SHIFT) +#define CAN_WORD110_DATA_BYTE_7(n) (((n) << CAN_WORD110_DATA_BYTE_7_SHIFT) & CAN_WORD110_DATA_BYTE_7_MASK) +#define CAN_WORD110_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD110_DATA_BYTE_6_MASK (0xFF << CAN_WORD110_DATA_BYTE_6_SHIFT) +#define CAN_WORD110_DATA_BYTE_6(n) (((n) << CAN_WORD110_DATA_BYTE_6_SHIFT) & CAN_WORD110_DATA_BYTE_6_MASK) +#define CAN_WORD110_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD110_DATA_BYTE_5_MASK (0xFF << CAN_WORD110_DATA_BYTE_5_SHIFT) +#define CAN_WORD110_DATA_BYTE_5(n) (((n) << CAN_WORD110_DATA_BYTE_5_SHIFT) & CAN_WORD110_DATA_BYTE_5_MASK) +#define CAN_WORD110_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD110_DATA_BYTE_4_MASK (0xFF << CAN_WORD110_DATA_BYTE_4_SHIFT) +#define CAN_WORD110_DATA_BYTE_4(n) (((n) << CAN_WORD110_DATA_BYTE_4_SHIFT) & CAN_WORD110_DATA_BYTE_4_MASK) + +/* Message Buffer 11 CS Register (CS11) */ +#define CAN_CS11_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS11_TIME_STAMP_MASK (0xFFFF << CAN_CS11_TIME_STAMP_SHIFT) +#define CAN_CS11_TIME_STAMP(n) (((n) << CAN_CS11_TIME_STAMP_SHIFT) & CAN_CS11_TIME_STAMP_MASK) +#define CAN_CS11_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS11_DLC_MASK (0xF << CAN_CS11_DLC_SHIFT) +#define CAN_CS11_DLC(n) (((n) << CAN_CS11_DLC_SHIFT) & CAN_CS11_DLC_MASK) +#define CAN_CS11_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS11_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS11_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS11_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS11_CODE_MASK (0xF << CAN_CS11_CODE_SHIFT) +#define CAN_CS11_CODE(n) (((n) << CAN_CS11_CODE_SHIFT) & CAN_CS11_CODE_MASK) +#define CAN_CS11_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS11_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS11_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 11 WORD0 Register (WORD011) */ +#define CAN_WORD011_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD011_DATA_BYTE_3_MASK (0xFF << CAN_WORD011_DATA_BYTE_3_SHIFT) +#define CAN_WORD011_DATA_BYTE_3(n) (((n) << CAN_WORD011_DATA_BYTE_3_SHIFT) & CAN_WORD011_DATA_BYTE_3_MASK) +#define CAN_WORD011_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD011_DATA_BYTE_2_MASK (0xFF << CAN_WORD011_DATA_BYTE_2_SHIFT) +#define CAN_WORD011_DATA_BYTE_2(n) (((n) << CAN_WORD011_DATA_BYTE_2_SHIFT) & CAN_WORD011_DATA_BYTE_2_MASK) +#define CAN_WORD011_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD011_DATA_BYTE_1_MASK (0xFF << CAN_WORD011_DATA_BYTE_1_SHIFT) +#define CAN_WORD011_DATA_BYTE_1(n) (((n) << CAN_WORD011_DATA_BYTE_1_SHIFT) & CAN_WORD011_DATA_BYTE_1_MASK) +#define CAN_WORD011_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD011_DATA_BYTE_0_MASK (0xFF << CAN_WORD011_DATA_BYTE_0_SHIFT) +#define CAN_WORD011_DATA_BYTE_0(n) (((n) << CAN_WORD011_DATA_BYTE_0_SHIFT) & CAN_WORD011_DATA_BYTE_0_MASK) + +/* Message Buffer 11 WORD1 Register (WORD111) */ +#define CAN_WORD111_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD111_DATA_BYTE_7_MASK (0xFF << CAN_WORD111_DATA_BYTE_7_SHIFT) +#define CAN_WORD111_DATA_BYTE_7(n) (((n) << CAN_WORD111_DATA_BYTE_7_SHIFT) & CAN_WORD111_DATA_BYTE_7_MASK) +#define CAN_WORD111_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD111_DATA_BYTE_6_MASK (0xFF << CAN_WORD111_DATA_BYTE_6_SHIFT) +#define CAN_WORD111_DATA_BYTE_6(n) (((n) << CAN_WORD111_DATA_BYTE_6_SHIFT) & CAN_WORD111_DATA_BYTE_6_MASK) +#define CAN_WORD111_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD111_DATA_BYTE_5_MASK (0xFF << CAN_WORD111_DATA_BYTE_5_SHIFT) +#define CAN_WORD111_DATA_BYTE_5(n) (((n) << CAN_WORD111_DATA_BYTE_5_SHIFT) & CAN_WORD111_DATA_BYTE_5_MASK) +#define CAN_WORD111_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD111_DATA_BYTE_4_MASK (0xFF << CAN_WORD111_DATA_BYTE_4_SHIFT) +#define CAN_WORD111_DATA_BYTE_4(n) (((n) << CAN_WORD111_DATA_BYTE_4_SHIFT) & CAN_WORD111_DATA_BYTE_4_MASK) + +/* Message Buffer 12 CS Register (CS12) */ +#define CAN_CS12_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS12_TIME_STAMP_MASK (0xFFFF << CAN_CS12_TIME_STAMP_SHIFT) +#define CAN_CS12_TIME_STAMP(n) (((n) << CAN_CS12_TIME_STAMP_SHIFT) & CAN_CS12_TIME_STAMP_MASK) +#define CAN_CS12_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS12_DLC_MASK (0xF << CAN_CS12_DLC_SHIFT) +#define CAN_CS12_DLC(n) (((n) << CAN_CS12_DLC_SHIFT) & CAN_CS12_DLC_MASK) +#define CAN_CS12_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS12_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS12_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS12_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS12_CODE_MASK (0xF << CAN_CS12_CODE_SHIFT) +#define CAN_CS12_CODE(n) (((n) << CAN_CS12_CODE_SHIFT) & CAN_CS12_CODE_MASK) +#define CAN_CS12_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS12_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS12_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 12 WORD0 Register (WORD012) */ +#define CAN_WORD012_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD012_DATA_BYTE_3_MASK (0xFF << CAN_WORD012_DATA_BYTE_3_SHIFT) +#define CAN_WORD012_DATA_BYTE_3(n) (((n) << CAN_WORD012_DATA_BYTE_3_SHIFT) & CAN_WORD012_DATA_BYTE_3_MASK) +#define CAN_WORD012_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD012_DATA_BYTE_2_MASK (0xFF << CAN_WORD012_DATA_BYTE_2_SHIFT) +#define CAN_WORD012_DATA_BYTE_2(n) (((n) << CAN_WORD012_DATA_BYTE_2_SHIFT) & CAN_WORD012_DATA_BYTE_2_MASK) +#define CAN_WORD012_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD012_DATA_BYTE_1_MASK (0xFF << CAN_WORD012_DATA_BYTE_1_SHIFT) +#define CAN_WORD012_DATA_BYTE_1(n) (((n) << CAN_WORD012_DATA_BYTE_1_SHIFT) & CAN_WORD012_DATA_BYTE_1_MASK) +#define CAN_WORD012_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD012_DATA_BYTE_0_MASK (0xFF << CAN_WORD012_DATA_BYTE_0_SHIFT) +#define CAN_WORD012_DATA_BYTE_0(n) (((n) << CAN_WORD012_DATA_BYTE_0_SHIFT) & CAN_WORD012_DATA_BYTE_0_MASK) + +/* Message Buffer 12 WORD1 Register (WORD112) */ +#define CAN_WORD112_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD112_DATA_BYTE_7_MASK (0xFF << CAN_WORD112_DATA_BYTE_7_SHIFT) +#define CAN_WORD112_DATA_BYTE_7(n) (((n) << CAN_WORD112_DATA_BYTE_7_SHIFT) & CAN_WORD112_DATA_BYTE_7_MASK) +#define CAN_WORD112_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD112_DATA_BYTE_6_MASK (0xFF << CAN_WORD112_DATA_BYTE_6_SHIFT) +#define CAN_WORD112_DATA_BYTE_6(n) (((n) << CAN_WORD112_DATA_BYTE_6_SHIFT) & CAN_WORD112_DATA_BYTE_6_MASK) +#define CAN_WORD112_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD112_DATA_BYTE_5_MASK (0xFF << CAN_WORD112_DATA_BYTE_5_SHIFT) +#define CAN_WORD112_DATA_BYTE_5(n) (((n) << CAN_WORD112_DATA_BYTE_5_SHIFT) & CAN_WORD112_DATA_BYTE_5_MASK) +#define CAN_WORD112_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD112_DATA_BYTE_4_MASK (0xFF << CAN_WORD112_DATA_BYTE_4_SHIFT) +#define CAN_WORD112_DATA_BYTE_4(n) (((n) << CAN_WORD112_DATA_BYTE_4_SHIFT) & CAN_WORD112_DATA_BYTE_4_MASK) + +/* Message Buffer 13 CS Register (CS13) */ +#define CAN_CS13_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS13_TIME_STAMP_MASK (0xFFFF << CAN_CS13_TIME_STAMP_SHIFT) +#define CAN_CS13_TIME_STAMP(n) (((n) << CAN_CS13_TIME_STAMP_SHIFT) & CAN_CS13_TIME_STAMP_MASK) +#define CAN_CS13_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS13_DLC_MASK (0xF << CAN_CS13_DLC_SHIFT) +#define CAN_CS13_DLC(n) (((n) << CAN_CS13_DLC_SHIFT) & CAN_CS13_DLC_MASK) +#define CAN_CS13_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS13_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS13_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS13_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS13_CODE_MASK (0xF << CAN_CS13_CODE_SHIFT) +#define CAN_CS13_CODE(n) (((n) << CAN_CS13_CODE_SHIFT) & CAN_CS13_CODE_MASK) +#define CAN_CS13_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS13_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS13_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 13 WORD0 Register (WORD013) */ +#define CAN_WORD013_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD013_DATA_BYTE_3_MASK (0xFF << CAN_WORD013_DATA_BYTE_3_SHIFT) +#define CAN_WORD013_DATA_BYTE_3(n) (((n) << CAN_WORD013_DATA_BYTE_3_SHIFT) & CAN_WORD013_DATA_BYTE_3_MASK) +#define CAN_WORD013_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD013_DATA_BYTE_2_MASK (0xFF << CAN_WORD013_DATA_BYTE_2_SHIFT) +#define CAN_WORD013_DATA_BYTE_2(n) (((n) << CAN_WORD013_DATA_BYTE_2_SHIFT) & CAN_WORD013_DATA_BYTE_2_MASK) +#define CAN_WORD013_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD013_DATA_BYTE_1_MASK (0xFF << CAN_WORD013_DATA_BYTE_1_SHIFT) +#define CAN_WORD013_DATA_BYTE_1(n) (((n) << CAN_WORD013_DATA_BYTE_1_SHIFT) & CAN_WORD013_DATA_BYTE_1_MASK) +#define CAN_WORD013_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD013_DATA_BYTE_0_MASK (0xFF << CAN_WORD013_DATA_BYTE_0_SHIFT) +#define CAN_WORD013_DATA_BYTE_0(n) (((n) << CAN_WORD013_DATA_BYTE_0_SHIFT) & CAN_WORD013_DATA_BYTE_0_MASK) + +/* Message Buffer 13 WORD1 Register (WORD113) */ +#define CAN_WORD113_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD113_DATA_BYTE_7_MASK (0xFF << CAN_WORD113_DATA_BYTE_7_SHIFT) +#define CAN_WORD113_DATA_BYTE_7(n) (((n) << CAN_WORD113_DATA_BYTE_7_SHIFT) & CAN_WORD113_DATA_BYTE_7_MASK) +#define CAN_WORD113_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD113_DATA_BYTE_6_MASK (0xFF << CAN_WORD113_DATA_BYTE_6_SHIFT) +#define CAN_WORD113_DATA_BYTE_6(n) (((n) << CAN_WORD113_DATA_BYTE_6_SHIFT) & CAN_WORD113_DATA_BYTE_6_MASK) +#define CAN_WORD113_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD113_DATA_BYTE_5_MASK (0xFF << CAN_WORD113_DATA_BYTE_5_SHIFT) +#define CAN_WORD113_DATA_BYTE_5(n) (((n) << CAN_WORD113_DATA_BYTE_5_SHIFT) & CAN_WORD113_DATA_BYTE_5_MASK) +#define CAN_WORD113_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD113_DATA_BYTE_4_MASK (0xFF << CAN_WORD113_DATA_BYTE_4_SHIFT) +#define CAN_WORD113_DATA_BYTE_4(n) (((n) << CAN_WORD113_DATA_BYTE_4_SHIFT) & CAN_WORD113_DATA_BYTE_4_MASK) + +/* Message Buffer 14 CS Register (CS14) */ +#define CAN_CS14_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS14_TIME_STAMP_MASK (0xFFFF << CAN_CS14_TIME_STAMP_SHIFT) +#define CAN_CS14_TIME_STAMP(n) (((n) << CAN_CS14_TIME_STAMP_SHIFT) & CAN_CS14_TIME_STAMP_MASK) +#define CAN_CS14_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS14_DLC_MASK (0xF << CAN_CS14_DLC_SHIFT) +#define CAN_CS14_DLC(n) (((n) << CAN_CS14_DLC_SHIFT) & CAN_CS14_DLC_MASK) +#define CAN_CS14_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS14_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS14_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS14_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS14_CODE_MASK (0xF << CAN_CS14_CODE_SHIFT) +#define CAN_CS14_CODE(n) (((n) << CAN_CS14_CODE_SHIFT) & CAN_CS14_CODE_MASK) +#define CAN_CS14_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS14_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS14_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 14 WORD0 Register (WORD014) */ +#define CAN_WORD014_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD014_DATA_BYTE_3_MASK (0xFF << CAN_WORD014_DATA_BYTE_3_SHIFT) +#define CAN_WORD014_DATA_BYTE_3(n) (((n) << CAN_WORD014_DATA_BYTE_3_SHIFT) & CAN_WORD014_DATA_BYTE_3_MASK) +#define CAN_WORD014_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD014_DATA_BYTE_2_MASK (0xFF << CAN_WORD014_DATA_BYTE_2_SHIFT) +#define CAN_WORD014_DATA_BYTE_2(n) (((n) << CAN_WORD014_DATA_BYTE_2_SHIFT) & CAN_WORD014_DATA_BYTE_2_MASK) +#define CAN_WORD014_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD014_DATA_BYTE_1_MASK (0xFF << CAN_WORD014_DATA_BYTE_1_SHIFT) +#define CAN_WORD014_DATA_BYTE_1(n) (((n) << CAN_WORD014_DATA_BYTE_1_SHIFT) & CAN_WORD014_DATA_BYTE_1_MASK) +#define CAN_WORD014_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD014_DATA_BYTE_0_MASK (0xFF << CAN_WORD014_DATA_BYTE_0_SHIFT) +#define CAN_WORD014_DATA_BYTE_0(n) (((n) << CAN_WORD014_DATA_BYTE_0_SHIFT) & CAN_WORD014_DATA_BYTE_0_MASK) + +/* Message Buffer 14 WORD1 Register (WORD114) */ +#define CAN_WORD114_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD114_DATA_BYTE_7_MASK (0xFF << CAN_WORD114_DATA_BYTE_7_SHIFT) +#define CAN_WORD114_DATA_BYTE_7(n) (((n) << CAN_WORD114_DATA_BYTE_7_SHIFT) & CAN_WORD114_DATA_BYTE_7_MASK) +#define CAN_WORD114_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD114_DATA_BYTE_6_MASK (0xFF << CAN_WORD114_DATA_BYTE_6_SHIFT) +#define CAN_WORD114_DATA_BYTE_6(n) (((n) << CAN_WORD114_DATA_BYTE_6_SHIFT) & CAN_WORD114_DATA_BYTE_6_MASK) +#define CAN_WORD114_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD114_DATA_BYTE_5_MASK (0xFF << CAN_WORD114_DATA_BYTE_5_SHIFT) +#define CAN_WORD114_DATA_BYTE_5(n) (((n) << CAN_WORD114_DATA_BYTE_5_SHIFT) & CAN_WORD114_DATA_BYTE_5_MASK) +#define CAN_WORD114_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD114_DATA_BYTE_4_MASK (0xFF << CAN_WORD114_DATA_BYTE_4_SHIFT) +#define CAN_WORD114_DATA_BYTE_4(n) (((n) << CAN_WORD114_DATA_BYTE_4_SHIFT) & CAN_WORD114_DATA_BYTE_4_MASK) + +/* Message Buffer 15 CS Register (CS15) */ +#define CAN_CS15_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS15_TIME_STAMP_MASK (0xFFFF << CAN_CS15_TIME_STAMP_SHIFT) +#define CAN_CS15_TIME_STAMP(n) (((n) << CAN_CS15_TIME_STAMP_SHIFT) & CAN_CS15_TIME_STAMP_MASK) +#define CAN_CS15_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS15_DLC_MASK (0xF << CAN_CS15_DLC_SHIFT) +#define CAN_CS15_DLC(n) (((n) << CAN_CS15_DLC_SHIFT) & CAN_CS15_DLC_MASK) +#define CAN_CS15_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS15_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS15_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS15_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS15_CODE_MASK (0xF << CAN_CS15_CODE_SHIFT) +#define CAN_CS15_CODE(n) (((n) << CAN_CS15_CODE_SHIFT) & CAN_CS15_CODE_MASK) +#define CAN_CS15_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS15_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS15_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 15 WORD0 Register (WORD015) */ +#define CAN_WORD015_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD015_DATA_BYTE_3_MASK (0xFF << CAN_WORD015_DATA_BYTE_3_SHIFT) +#define CAN_WORD015_DATA_BYTE_3(n) (((n) << CAN_WORD015_DATA_BYTE_3_SHIFT) & CAN_WORD015_DATA_BYTE_3_MASK) +#define CAN_WORD015_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD015_DATA_BYTE_2_MASK (0xFF << CAN_WORD015_DATA_BYTE_2_SHIFT) +#define CAN_WORD015_DATA_BYTE_2(n) (((n) << CAN_WORD015_DATA_BYTE_2_SHIFT) & CAN_WORD015_DATA_BYTE_2_MASK) +#define CAN_WORD015_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD015_DATA_BYTE_1_MASK (0xFF << CAN_WORD015_DATA_BYTE_1_SHIFT) +#define CAN_WORD015_DATA_BYTE_1(n) (((n) << CAN_WORD015_DATA_BYTE_1_SHIFT) & CAN_WORD015_DATA_BYTE_1_MASK) +#define CAN_WORD015_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD015_DATA_BYTE_0_MASK (0xFF << CAN_WORD015_DATA_BYTE_0_SHIFT) +#define CAN_WORD015_DATA_BYTE_0(n) (((n) << CAN_WORD015_DATA_BYTE_0_SHIFT) & CAN_WORD015_DATA_BYTE_0_MASK) + +/* Message Buffer 15 WORD1 Register (WORD115) */ +#define CAN_WORD115_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD115_DATA_BYTE_7_MASK (0xFF << CAN_WORD115_DATA_BYTE_7_SHIFT) +#define CAN_WORD115_DATA_BYTE_7(n) (((n) << CAN_WORD115_DATA_BYTE_7_SHIFT) & CAN_WORD115_DATA_BYTE_7_MASK) +#define CAN_WORD115_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD115_DATA_BYTE_6_MASK (0xFF << CAN_WORD115_DATA_BYTE_6_SHIFT) +#define CAN_WORD115_DATA_BYTE_6(n) (((n) << CAN_WORD115_DATA_BYTE_6_SHIFT) & CAN_WORD115_DATA_BYTE_6_MASK) +#define CAN_WORD115_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD115_DATA_BYTE_5_MASK (0xFF << CAN_WORD115_DATA_BYTE_5_SHIFT) +#define CAN_WORD115_DATA_BYTE_5(n) (((n) << CAN_WORD115_DATA_BYTE_5_SHIFT) & CAN_WORD115_DATA_BYTE_5_MASK) +#define CAN_WORD115_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD115_DATA_BYTE_4_MASK (0xFF << CAN_WORD115_DATA_BYTE_4_SHIFT) +#define CAN_WORD115_DATA_BYTE_4(n) (((n) << CAN_WORD115_DATA_BYTE_4_SHIFT) & CAN_WORD115_DATA_BYTE_4_MASK) + +/* Message Buffer 16 CS Register (CS16) */ +#define CAN_CS16_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS16_TIME_STAMP_MASK (0xFFFF << CAN_CS16_TIME_STAMP_SHIFT) +#define CAN_CS16_TIME_STAMP(n) (((n) << CAN_CS16_TIME_STAMP_SHIFT) & CAN_CS16_TIME_STAMP_MASK) +#define CAN_CS16_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS16_DLC_MASK (0xF << CAN_CS16_DLC_SHIFT) +#define CAN_CS16_DLC(n) (((n) << CAN_CS16_DLC_SHIFT) & CAN_CS16_DLC_MASK) +#define CAN_CS16_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS16_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS16_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS16_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS16_CODE_MASK (0xF << CAN_CS16_CODE_SHIFT) +#define CAN_CS16_CODE(n) (((n) << CAN_CS16_CODE_SHIFT) & CAN_CS16_CODE_MASK) +#define CAN_CS16_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS16_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS16_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 16 WORD0 Register (WORD016) */ +#define CAN_WORD016_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD016_DATA_BYTE_3_MASK (0xFF << CAN_WORD016_DATA_BYTE_3_SHIFT) +#define CAN_WORD016_DATA_BYTE_3(n) (((n) << CAN_WORD016_DATA_BYTE_3_SHIFT) & CAN_WORD016_DATA_BYTE_3_MASK) +#define CAN_WORD016_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD016_DATA_BYTE_2_MASK (0xFF << CAN_WORD016_DATA_BYTE_2_SHIFT) +#define CAN_WORD016_DATA_BYTE_2(n) (((n) << CAN_WORD016_DATA_BYTE_2_SHIFT) & CAN_WORD016_DATA_BYTE_2_MASK) +#define CAN_WORD016_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD016_DATA_BYTE_1_MASK (0xFF << CAN_WORD016_DATA_BYTE_1_SHIFT) +#define CAN_WORD016_DATA_BYTE_1(n) (((n) << CAN_WORD016_DATA_BYTE_1_SHIFT) & CAN_WORD016_DATA_BYTE_1_MASK) +#define CAN_WORD016_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD016_DATA_BYTE_0_MASK (0xFF << CAN_WORD016_DATA_BYTE_0_SHIFT) +#define CAN_WORD016_DATA_BYTE_0(n) (((n) << CAN_WORD016_DATA_BYTE_0_SHIFT) & CAN_WORD016_DATA_BYTE_0_MASK) + +/* Message Buffer 16 WORD1 Register (WORD116) */ +#define CAN_WORD116_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD116_DATA_BYTE_7_MASK (0xFF << CAN_WORD116_DATA_BYTE_7_SHIFT) +#define CAN_WORD116_DATA_BYTE_7(n) (((n) << CAN_WORD116_DATA_BYTE_7_SHIFT) & CAN_WORD116_DATA_BYTE_7_MASK) +#define CAN_WORD116_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD116_DATA_BYTE_6_MASK (0xFF << CAN_WORD116_DATA_BYTE_6_SHIFT) +#define CAN_WORD116_DATA_BYTE_6(n) (((n) << CAN_WORD116_DATA_BYTE_6_SHIFT) & CAN_WORD116_DATA_BYTE_6_MASK) +#define CAN_WORD116_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD116_DATA_BYTE_5_MASK (0xFF << CAN_WORD116_DATA_BYTE_5_SHIFT) +#define CAN_WORD116_DATA_BYTE_5(n) (((n) << CAN_WORD116_DATA_BYTE_5_SHIFT) & CAN_WORD116_DATA_BYTE_5_MASK) +#define CAN_WORD116_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD116_DATA_BYTE_4_MASK (0xFF << CAN_WORD116_DATA_BYTE_4_SHIFT) +#define CAN_WORD116_DATA_BYTE_4(n) (((n) << CAN_WORD116_DATA_BYTE_4_SHIFT) & CAN_WORD116_DATA_BYTE_4_MASK) + +/* Message Buffer 17 CS Register (CS17) */ +#define CAN_CS17_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS17_TIME_STAMP_MASK (0xFFFF << CAN_CS17_TIME_STAMP_SHIFT) +#define CAN_CS17_TIME_STAMP(n) (((n) << CAN_CS17_TIME_STAMP_SHIFT) & CAN_CS17_TIME_STAMP_MASK) +#define CAN_CS17_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS17_DLC_MASK (0xF << CAN_CS17_DLC_SHIFT) +#define CAN_CS17_DLC(n) (((n) << CAN_CS17_DLC_SHIFT) & CAN_CS17_DLC_MASK) +#define CAN_CS17_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS17_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS17_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS17_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS17_CODE_MASK (0xF << CAN_CS17_CODE_SHIFT) +#define CAN_CS17_CODE(n) (((n) << CAN_CS17_CODE_SHIFT) & CAN_CS17_CODE_MASK) +#define CAN_CS17_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS17_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS17_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 17 WORD0 Register (WORD017) */ +#define CAN_WORD017_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD017_DATA_BYTE_3_MASK (0xFF << CAN_WORD017_DATA_BYTE_3_SHIFT) +#define CAN_WORD017_DATA_BYTE_3(n) (((n) << CAN_WORD017_DATA_BYTE_3_SHIFT) & CAN_WORD017_DATA_BYTE_3_MASK) +#define CAN_WORD017_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD017_DATA_BYTE_2_MASK (0xFF << CAN_WORD017_DATA_BYTE_2_SHIFT) +#define CAN_WORD017_DATA_BYTE_2(n) (((n) << CAN_WORD017_DATA_BYTE_2_SHIFT) & CAN_WORD017_DATA_BYTE_2_MASK) +#define CAN_WORD017_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD017_DATA_BYTE_1_MASK (0xFF << CAN_WORD017_DATA_BYTE_1_SHIFT) +#define CAN_WORD017_DATA_BYTE_1(n) (((n) << CAN_WORD017_DATA_BYTE_1_SHIFT) & CAN_WORD017_DATA_BYTE_1_MASK) +#define CAN_WORD017_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD017_DATA_BYTE_0_MASK (0xFF << CAN_WORD017_DATA_BYTE_0_SHIFT) +#define CAN_WORD017_DATA_BYTE_0(n) (((n) << CAN_WORD017_DATA_BYTE_0_SHIFT) & CAN_WORD017_DATA_BYTE_0_MASK) + +/* Message Buffer 17 WORD1 Register (WORD117) */ +#define CAN_WORD117_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD117_DATA_BYTE_7_MASK (0xFF << CAN_WORD117_DATA_BYTE_7_SHIFT) +#define CAN_WORD117_DATA_BYTE_7(n) (((n) << CAN_WORD117_DATA_BYTE_7_SHIFT) & CAN_WORD117_DATA_BYTE_7_MASK) +#define CAN_WORD117_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD117_DATA_BYTE_6_MASK (0xFF << CAN_WORD117_DATA_BYTE_6_SHIFT) +#define CAN_WORD117_DATA_BYTE_6(n) (((n) << CAN_WORD117_DATA_BYTE_6_SHIFT) & CAN_WORD117_DATA_BYTE_6_MASK) +#define CAN_WORD117_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD117_DATA_BYTE_5_MASK (0xFF << CAN_WORD117_DATA_BYTE_5_SHIFT) +#define CAN_WORD117_DATA_BYTE_5(n) (((n) << CAN_WORD117_DATA_BYTE_5_SHIFT) & CAN_WORD117_DATA_BYTE_5_MASK) +#define CAN_WORD117_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD117_DATA_BYTE_4_MASK (0xFF << CAN_WORD117_DATA_BYTE_4_SHIFT) +#define CAN_WORD117_DATA_BYTE_4(n) (((n) << CAN_WORD117_DATA_BYTE_4_SHIFT) & CAN_WORD117_DATA_BYTE_4_MASK) + +/* Message Buffer 18 CS Register (CS18) */ +#define CAN_CS18_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS18_TIME_STAMP_MASK (0xFFFF << CAN_CS18_TIME_STAMP_SHIFT) +#define CAN_CS18_TIME_STAMP(n) (((n) << CAN_CS18_TIME_STAMP_SHIFT) & CAN_CS18_TIME_STAMP_MASK) +#define CAN_CS18_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS18_DLC_MASK (0xF << CAN_CS18_DLC_SHIFT) +#define CAN_CS18_DLC(n) (((n) << CAN_CS18_DLC_SHIFT) & CAN_CS18_DLC_MASK) +#define CAN_CS18_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS18_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS18_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS18_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS18_CODE_MASK (0xF << CAN_CS18_CODE_SHIFT) +#define CAN_CS18_CODE(n) (((n) << CAN_CS18_CODE_SHIFT) & CAN_CS18_CODE_MASK) +#define CAN_CS18_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS18_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS18_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 18 WORD0 Register (WORD018) */ +#define CAN_WORD018_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD018_DATA_BYTE_3_MASK (0xFF << CAN_WORD018_DATA_BYTE_3_SHIFT) +#define CAN_WORD018_DATA_BYTE_3(n) (((n) << CAN_WORD018_DATA_BYTE_3_SHIFT) & CAN_WORD018_DATA_BYTE_3_MASK) +#define CAN_WORD018_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD018_DATA_BYTE_2_MASK (0xFF << CAN_WORD018_DATA_BYTE_2_SHIFT) +#define CAN_WORD018_DATA_BYTE_2(n) (((n) << CAN_WORD018_DATA_BYTE_2_SHIFT) & CAN_WORD018_DATA_BYTE_2_MASK) +#define CAN_WORD018_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD018_DATA_BYTE_1_MASK (0xFF << CAN_WORD018_DATA_BYTE_1_SHIFT) +#define CAN_WORD018_DATA_BYTE_1(n) (((n) << CAN_WORD018_DATA_BYTE_1_SHIFT) & CAN_WORD018_DATA_BYTE_1_MASK) +#define CAN_WORD018_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD018_DATA_BYTE_0_MASK (0xFF << CAN_WORD018_DATA_BYTE_0_SHIFT) +#define CAN_WORD018_DATA_BYTE_0(n) (((n) << CAN_WORD018_DATA_BYTE_0_SHIFT) & CAN_WORD018_DATA_BYTE_0_MASK) + +/* Message Buffer 18 WORD1 Register (WORD118) */ +#define CAN_WORD118_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD118_DATA_BYTE_7_MASK (0xFF << CAN_WORD118_DATA_BYTE_7_SHIFT) +#define CAN_WORD118_DATA_BYTE_7(n) (((n) << CAN_WORD118_DATA_BYTE_7_SHIFT) & CAN_WORD118_DATA_BYTE_7_MASK) +#define CAN_WORD118_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD118_DATA_BYTE_6_MASK (0xFF << CAN_WORD118_DATA_BYTE_6_SHIFT) +#define CAN_WORD118_DATA_BYTE_6(n) (((n) << CAN_WORD118_DATA_BYTE_6_SHIFT) & CAN_WORD118_DATA_BYTE_6_MASK) +#define CAN_WORD118_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD118_DATA_BYTE_5_MASK (0xFF << CAN_WORD118_DATA_BYTE_5_SHIFT) +#define CAN_WORD118_DATA_BYTE_5(n) (((n) << CAN_WORD118_DATA_BYTE_5_SHIFT) & CAN_WORD118_DATA_BYTE_5_MASK) +#define CAN_WORD118_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD118_DATA_BYTE_4_MASK (0xFF << CAN_WORD118_DATA_BYTE_4_SHIFT) +#define CAN_WORD118_DATA_BYTE_4(n) (((n) << CAN_WORD118_DATA_BYTE_4_SHIFT) & CAN_WORD118_DATA_BYTE_4_MASK) + +/* Message Buffer 19 CS Register (CS19) */ +#define CAN_CS19_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS19_TIME_STAMP_MASK (0xFFFF << CAN_CS19_TIME_STAMP_SHIFT) +#define CAN_CS19_TIME_STAMP(n) (((n) << CAN_CS19_TIME_STAMP_SHIFT) & CAN_CS19_TIME_STAMP_MASK) +#define CAN_CS19_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS19_DLC_MASK (0xF << CAN_CS19_DLC_SHIFT) +#define CAN_CS19_DLC(n) (((n) << CAN_CS19_DLC_SHIFT) & CAN_CS19_DLC_MASK) +#define CAN_CS19_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS19_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS19_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS19_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS19_CODE_MASK (0xF << CAN_CS19_CODE_SHIFT) +#define CAN_CS19_CODE(n) (((n) << CAN_CS19_CODE_SHIFT) & CAN_CS19_CODE_MASK) +#define CAN_CS19_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS19_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS19_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 19 WORD0 Register (WORD019) */ +#define CAN_WORD019_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD019_DATA_BYTE_3_MASK (0xFF << CAN_WORD019_DATA_BYTE_3_SHIFT) +#define CAN_WORD019_DATA_BYTE_3(n) (((n) << CAN_WORD019_DATA_BYTE_3_SHIFT) & CAN_WORD019_DATA_BYTE_3_MASK) +#define CAN_WORD019_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD019_DATA_BYTE_2_MASK (0xFF << CAN_WORD019_DATA_BYTE_2_SHIFT) +#define CAN_WORD019_DATA_BYTE_2(n) (((n) << CAN_WORD019_DATA_BYTE_2_SHIFT) & CAN_WORD019_DATA_BYTE_2_MASK) +#define CAN_WORD019_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD019_DATA_BYTE_1_MASK (0xFF << CAN_WORD019_DATA_BYTE_1_SHIFT) +#define CAN_WORD019_DATA_BYTE_1(n) (((n) << CAN_WORD019_DATA_BYTE_1_SHIFT) & CAN_WORD019_DATA_BYTE_1_MASK) +#define CAN_WORD019_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD019_DATA_BYTE_0_MASK (0xFF << CAN_WORD019_DATA_BYTE_0_SHIFT) +#define CAN_WORD019_DATA_BYTE_0(n) (((n) << CAN_WORD019_DATA_BYTE_0_SHIFT) & CAN_WORD019_DATA_BYTE_0_MASK) + +/* Message Buffer 19 WORD1 Register (WORD119) */ +#define CAN_WORD119_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD119_DATA_BYTE_7_MASK (0xFF << CAN_WORD119_DATA_BYTE_7_SHIFT) +#define CAN_WORD119_DATA_BYTE_7(n) (((n) << CAN_WORD119_DATA_BYTE_7_SHIFT) & CAN_WORD119_DATA_BYTE_7_MASK) +#define CAN_WORD119_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD119_DATA_BYTE_6_MASK (0xFF << CAN_WORD119_DATA_BYTE_6_SHIFT) +#define CAN_WORD119_DATA_BYTE_6(n) (((n) << CAN_WORD119_DATA_BYTE_6_SHIFT) & CAN_WORD119_DATA_BYTE_6_MASK) +#define CAN_WORD119_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD119_DATA_BYTE_5_MASK (0xFF << CAN_WORD119_DATA_BYTE_5_SHIFT) +#define CAN_WORD119_DATA_BYTE_5(n) (((n) << CAN_WORD119_DATA_BYTE_5_SHIFT) & CAN_WORD119_DATA_BYTE_5_MASK) +#define CAN_WORD119_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD119_DATA_BYTE_4_MASK (0xFF << CAN_WORD119_DATA_BYTE_4_SHIFT) +#define CAN_WORD119_DATA_BYTE_4(n) (((n) << CAN_WORD119_DATA_BYTE_4_SHIFT) & CAN_WORD119_DATA_BYTE_4_MASK) + +/* Message Buffer 20 CS Register (CS20) */ +#define CAN_CS20_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS20_TIME_STAMP_MASK (0xFFFF << CAN_CS20_TIME_STAMP_SHIFT) +#define CAN_CS20_TIME_STAMP(n) (((n) << CAN_CS20_TIME_STAMP_SHIFT) & CAN_CS20_TIME_STAMP_MASK) +#define CAN_CS20_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS20_DLC_MASK (0xF << CAN_CS20_DLC_SHIFT) +#define CAN_CS20_DLC(n) (((n) << CAN_CS20_DLC_SHIFT) & CAN_CS20_DLC_MASK) +#define CAN_CS20_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS20_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS20_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS20_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS20_CODE_MASK (0xF << CAN_CS20_CODE_SHIFT) +#define CAN_CS20_CODE(n) (((n) << CAN_CS20_CODE_SHIFT) & CAN_CS20_CODE_MASK) +#define CAN_CS20_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS20_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS20_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 20 WORD0 Register (WORD020) */ +#define CAN_WORD020_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD020_DATA_BYTE_3_MASK (0xFF << CAN_WORD020_DATA_BYTE_3_SHIFT) +#define CAN_WORD020_DATA_BYTE_3(n) (((n) << CAN_WORD020_DATA_BYTE_3_SHIFT) & CAN_WORD020_DATA_BYTE_3_MASK) +#define CAN_WORD020_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD020_DATA_BYTE_2_MASK (0xFF << CAN_WORD020_DATA_BYTE_2_SHIFT) +#define CAN_WORD020_DATA_BYTE_2(n) (((n) << CAN_WORD020_DATA_BYTE_2_SHIFT) & CAN_WORD020_DATA_BYTE_2_MASK) +#define CAN_WORD020_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD020_DATA_BYTE_1_MASK (0xFF << CAN_WORD020_DATA_BYTE_1_SHIFT) +#define CAN_WORD020_DATA_BYTE_1(n) (((n) << CAN_WORD020_DATA_BYTE_1_SHIFT) & CAN_WORD020_DATA_BYTE_1_MASK) +#define CAN_WORD020_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD020_DATA_BYTE_0_MASK (0xFF << CAN_WORD020_DATA_BYTE_0_SHIFT) +#define CAN_WORD020_DATA_BYTE_0(n) (((n) << CAN_WORD020_DATA_BYTE_0_SHIFT) & CAN_WORD020_DATA_BYTE_0_MASK) + +/* Message Buffer 20 WORD1 Register (WORD120) */ +#define CAN_WORD120_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD120_DATA_BYTE_7_MASK (0xFF << CAN_WORD120_DATA_BYTE_7_SHIFT) +#define CAN_WORD120_DATA_BYTE_7(n) (((n) << CAN_WORD120_DATA_BYTE_7_SHIFT) & CAN_WORD120_DATA_BYTE_7_MASK) +#define CAN_WORD120_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD120_DATA_BYTE_6_MASK (0xFF << CAN_WORD120_DATA_BYTE_6_SHIFT) +#define CAN_WORD120_DATA_BYTE_6(n) (((n) << CAN_WORD120_DATA_BYTE_6_SHIFT) & CAN_WORD120_DATA_BYTE_6_MASK) +#define CAN_WORD120_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD120_DATA_BYTE_5_MASK (0xFF << CAN_WORD120_DATA_BYTE_5_SHIFT) +#define CAN_WORD120_DATA_BYTE_5(n) (((n) << CAN_WORD120_DATA_BYTE_5_SHIFT) & CAN_WORD120_DATA_BYTE_5_MASK) +#define CAN_WORD120_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD120_DATA_BYTE_4_MASK (0xFF << CAN_WORD120_DATA_BYTE_4_SHIFT) +#define CAN_WORD120_DATA_BYTE_4(n) (((n) << CAN_WORD120_DATA_BYTE_4_SHIFT) & CAN_WORD120_DATA_BYTE_4_MASK) + +/* Message Buffer 21 CS Register (CS21) */ +#define CAN_CS21_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS21_TIME_STAMP_MASK (0xFFFF << CAN_CS21_TIME_STAMP_SHIFT) +#define CAN_CS21_TIME_STAMP(n) (((n) << CAN_CS21_TIME_STAMP_SHIFT) & CAN_CS21_TIME_STAMP_MASK) +#define CAN_CS21_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS21_DLC_MASK (0xF << CAN_CS21_DLC_SHIFT) +#define CAN_CS21_DLC(n) (((n) << CAN_CS21_DLC_SHIFT) & CAN_CS21_DLC_MASK) +#define CAN_CS21_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS21_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS21_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS21_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS21_CODE_MASK (0xF << CAN_CS21_CODE_SHIFT) +#define CAN_CS21_CODE(n) (((n) << CAN_CS21_CODE_SHIFT) & CAN_CS21_CODE_MASK) +#define CAN_CS21_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS21_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS21_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 21 WORD0 Register (WORD021) */ +#define CAN_WORD021_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD021_DATA_BYTE_3_MASK (0xFF << CAN_WORD021_DATA_BYTE_3_SHIFT) +#define CAN_WORD021_DATA_BYTE_3(n) (((n) << CAN_WORD021_DATA_BYTE_3_SHIFT) & CAN_WORD021_DATA_BYTE_3_MASK) +#define CAN_WORD021_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD021_DATA_BYTE_2_MASK (0xFF << CAN_WORD021_DATA_BYTE_2_SHIFT) +#define CAN_WORD021_DATA_BYTE_2(n) (((n) << CAN_WORD021_DATA_BYTE_2_SHIFT) & CAN_WORD021_DATA_BYTE_2_MASK) +#define CAN_WORD021_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD021_DATA_BYTE_1_MASK (0xFF << CAN_WORD021_DATA_BYTE_1_SHIFT) +#define CAN_WORD021_DATA_BYTE_1(n) (((n) << CAN_WORD021_DATA_BYTE_1_SHIFT) & CAN_WORD021_DATA_BYTE_1_MASK) +#define CAN_WORD021_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD021_DATA_BYTE_0_MASK (0xFF << CAN_WORD021_DATA_BYTE_0_SHIFT) +#define CAN_WORD021_DATA_BYTE_0(n) (((n) << CAN_WORD021_DATA_BYTE_0_SHIFT) & CAN_WORD021_DATA_BYTE_0_MASK) + +/* Message Buffer 21 WORD1 Register (WORD121) */ +#define CAN_WORD121_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD121_DATA_BYTE_7_MASK (0xFF << CAN_WORD121_DATA_BYTE_7_SHIFT) +#define CAN_WORD121_DATA_BYTE_7(n) (((n) << CAN_WORD121_DATA_BYTE_7_SHIFT) & CAN_WORD121_DATA_BYTE_7_MASK) +#define CAN_WORD121_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD121_DATA_BYTE_6_MASK (0xFF << CAN_WORD121_DATA_BYTE_6_SHIFT) +#define CAN_WORD121_DATA_BYTE_6(n) (((n) << CAN_WORD121_DATA_BYTE_6_SHIFT) & CAN_WORD121_DATA_BYTE_6_MASK) +#define CAN_WORD121_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD121_DATA_BYTE_5_MASK (0xFF << CAN_WORD121_DATA_BYTE_5_SHIFT) +#define CAN_WORD121_DATA_BYTE_5(n) (((n) << CAN_WORD121_DATA_BYTE_5_SHIFT) & CAN_WORD121_DATA_BYTE_5_MASK) +#define CAN_WORD121_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD121_DATA_BYTE_4_MASK (0xFF << CAN_WORD121_DATA_BYTE_4_SHIFT) +#define CAN_WORD121_DATA_BYTE_4(n) (((n) << CAN_WORD121_DATA_BYTE_4_SHIFT) & CAN_WORD121_DATA_BYTE_4_MASK) + +/* Message Buffer 22 CS Register (CS22) */ +#define CAN_CS22_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS22_TIME_STAMP_MASK (0xFFFF << CAN_CS22_TIME_STAMP_SHIFT) +#define CAN_CS22_TIME_STAMP(n) (((n) << CAN_CS22_TIME_STAMP_SHIFT) & CAN_CS22_TIME_STAMP_MASK) +#define CAN_CS22_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS22_DLC_MASK (0xF << CAN_CS22_DLC_SHIFT) +#define CAN_CS22_DLC(n) (((n) << CAN_CS22_DLC_SHIFT) & CAN_CS22_DLC_MASK) +#define CAN_CS22_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS22_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS22_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS22_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS22_CODE_MASK (0xF << CAN_CS22_CODE_SHIFT) +#define CAN_CS22_CODE(n) (((n) << CAN_CS22_CODE_SHIFT) & CAN_CS22_CODE_MASK) +#define CAN_CS22_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS22_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS22_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 22 WORD0 Register (WORD022) */ +#define CAN_WORD022_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD022_DATA_BYTE_3_MASK (0xFF << CAN_WORD022_DATA_BYTE_3_SHIFT) +#define CAN_WORD022_DATA_BYTE_3(n) (((n) << CAN_WORD022_DATA_BYTE_3_SHIFT) & CAN_WORD022_DATA_BYTE_3_MASK) +#define CAN_WORD022_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD022_DATA_BYTE_2_MASK (0xFF << CAN_WORD022_DATA_BYTE_2_SHIFT) +#define CAN_WORD022_DATA_BYTE_2(n) (((n) << CAN_WORD022_DATA_BYTE_2_SHIFT) & CAN_WORD022_DATA_BYTE_2_MASK) +#define CAN_WORD022_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD022_DATA_BYTE_1_MASK (0xFF << CAN_WORD022_DATA_BYTE_1_SHIFT) +#define CAN_WORD022_DATA_BYTE_1(n) (((n) << CAN_WORD022_DATA_BYTE_1_SHIFT) & CAN_WORD022_DATA_BYTE_1_MASK) +#define CAN_WORD022_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD022_DATA_BYTE_0_MASK (0xFF << CAN_WORD022_DATA_BYTE_0_SHIFT) +#define CAN_WORD022_DATA_BYTE_0(n) (((n) << CAN_WORD022_DATA_BYTE_0_SHIFT) & CAN_WORD022_DATA_BYTE_0_MASK) + +/* Message Buffer 22 WORD1 Register (WORD122) */ +#define CAN_WORD122_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD122_DATA_BYTE_7_MASK (0xFF << CAN_WORD122_DATA_BYTE_7_SHIFT) +#define CAN_WORD122_DATA_BYTE_7(n) (((n) << CAN_WORD122_DATA_BYTE_7_SHIFT) & CAN_WORD122_DATA_BYTE_7_MASK) +#define CAN_WORD122_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD122_DATA_BYTE_6_MASK (0xFF << CAN_WORD122_DATA_BYTE_6_SHIFT) +#define CAN_WORD122_DATA_BYTE_6(n) (((n) << CAN_WORD122_DATA_BYTE_6_SHIFT) & CAN_WORD122_DATA_BYTE_6_MASK) +#define CAN_WORD122_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD122_DATA_BYTE_5_MASK (0xFF << CAN_WORD122_DATA_BYTE_5_SHIFT) +#define CAN_WORD122_DATA_BYTE_5(n) (((n) << CAN_WORD122_DATA_BYTE_5_SHIFT) & CAN_WORD122_DATA_BYTE_5_MASK) +#define CAN_WORD122_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD122_DATA_BYTE_4_MASK (0xFF << CAN_WORD122_DATA_BYTE_4_SHIFT) +#define CAN_WORD122_DATA_BYTE_4(n) (((n) << CAN_WORD122_DATA_BYTE_4_SHIFT) & CAN_WORD122_DATA_BYTE_4_MASK) + +/* Message Buffer 23 CS Register (CS23) */ +#define CAN_CS23_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS23_TIME_STAMP_MASK (0xFFFF << CAN_CS23_TIME_STAMP_SHIFT) +#define CAN_CS23_TIME_STAMP(n) (((n) << CAN_CS23_TIME_STAMP_SHIFT) & CAN_CS23_TIME_STAMP_MASK) +#define CAN_CS23_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS23_DLC_MASK (0xF << CAN_CS23_DLC_SHIFT) +#define CAN_CS23_DLC(n) (((n) << CAN_CS23_DLC_SHIFT) & CAN_CS23_DLC_MASK) +#define CAN_CS23_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS23_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS23_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS23_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS23_CODE_MASK (0xF << CAN_CS23_CODE_SHIFT) +#define CAN_CS23_CODE(n) (((n) << CAN_CS23_CODE_SHIFT) & CAN_CS23_CODE_MASK) +#define CAN_CS23_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS23_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS23_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 23 WORD0 Register (WORD023) */ +#define CAN_WORD023_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD023_DATA_BYTE_3_MASK (0xFF << CAN_WORD023_DATA_BYTE_3_SHIFT) +#define CAN_WORD023_DATA_BYTE_3(n) (((n) << CAN_WORD023_DATA_BYTE_3_SHIFT) & CAN_WORD023_DATA_BYTE_3_MASK) +#define CAN_WORD023_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD023_DATA_BYTE_2_MASK (0xFF << CAN_WORD023_DATA_BYTE_2_SHIFT) +#define CAN_WORD023_DATA_BYTE_2(n) (((n) << CAN_WORD023_DATA_BYTE_2_SHIFT) & CAN_WORD023_DATA_BYTE_2_MASK) +#define CAN_WORD023_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD023_DATA_BYTE_1_MASK (0xFF << CAN_WORD023_DATA_BYTE_1_SHIFT) +#define CAN_WORD023_DATA_BYTE_1(n) (((n) << CAN_WORD023_DATA_BYTE_1_SHIFT) & CAN_WORD023_DATA_BYTE_1_MASK) +#define CAN_WORD023_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD023_DATA_BYTE_0_MASK (0xFF << CAN_WORD023_DATA_BYTE_0_SHIFT) +#define CAN_WORD023_DATA_BYTE_0(n) (((n) << CAN_WORD023_DATA_BYTE_0_SHIFT) & CAN_WORD023_DATA_BYTE_0_MASK) + +/* Message Buffer 23 WORD1 Register (WORD123) */ +#define CAN_WORD123_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD123_DATA_BYTE_7_MASK (0xFF << CAN_WORD123_DATA_BYTE_7_SHIFT) +#define CAN_WORD123_DATA_BYTE_7(n) (((n) << CAN_WORD123_DATA_BYTE_7_SHIFT) & CAN_WORD123_DATA_BYTE_7_MASK) +#define CAN_WORD123_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD123_DATA_BYTE_6_MASK (0xFF << CAN_WORD123_DATA_BYTE_6_SHIFT) +#define CAN_WORD123_DATA_BYTE_6(n) (((n) << CAN_WORD123_DATA_BYTE_6_SHIFT) & CAN_WORD123_DATA_BYTE_6_MASK) +#define CAN_WORD123_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD123_DATA_BYTE_5_MASK (0xFF << CAN_WORD123_DATA_BYTE_5_SHIFT) +#define CAN_WORD123_DATA_BYTE_5(n) (((n) << CAN_WORD123_DATA_BYTE_5_SHIFT) & CAN_WORD123_DATA_BYTE_5_MASK) +#define CAN_WORD123_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD123_DATA_BYTE_4_MASK (0xFF << CAN_WORD123_DATA_BYTE_4_SHIFT) +#define CAN_WORD123_DATA_BYTE_4(n) (((n) << CAN_WORD123_DATA_BYTE_4_SHIFT) & CAN_WORD123_DATA_BYTE_4_MASK) + +/* Message Buffer 24 CS Register (CS24) */ +#define CAN_CS24_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS24_TIME_STAMP_MASK (0xFFFF << CAN_CS24_TIME_STAMP_SHIFT) +#define CAN_CS24_TIME_STAMP(n) (((n) << CAN_CS24_TIME_STAMP_SHIFT) & CAN_CS24_TIME_STAMP_MASK) +#define CAN_CS24_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS24_DLC_MASK (0xF << CAN_CS24_DLC_SHIFT) +#define CAN_CS24_DLC(n) (((n) << CAN_CS24_DLC_SHIFT) & CAN_CS24_DLC_MASK) +#define CAN_CS24_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS24_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS24_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS24_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS24_CODE_MASK (0xF << CAN_CS24_CODE_SHIFT) +#define CAN_CS24_CODE(n) (((n) << CAN_CS24_CODE_SHIFT) & CAN_CS24_CODE_MASK) +#define CAN_CS24_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS24_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS24_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 24 WORD0 Register (WORD024) */ +#define CAN_WORD024_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD024_DATA_BYTE_3_MASK (0xFF << CAN_WORD024_DATA_BYTE_3_SHIFT) +#define CAN_WORD024_DATA_BYTE_3(n) (((n) << CAN_WORD024_DATA_BYTE_3_SHIFT) & CAN_WORD024_DATA_BYTE_3_MASK) +#define CAN_WORD024_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD024_DATA_BYTE_2_MASK (0xFF << CAN_WORD024_DATA_BYTE_2_SHIFT) +#define CAN_WORD024_DATA_BYTE_2(n) (((n) << CAN_WORD024_DATA_BYTE_2_SHIFT) & CAN_WORD024_DATA_BYTE_2_MASK) +#define CAN_WORD024_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD024_DATA_BYTE_1_MASK (0xFF << CAN_WORD024_DATA_BYTE_1_SHIFT) +#define CAN_WORD024_DATA_BYTE_1(n) (((n) << CAN_WORD024_DATA_BYTE_1_SHIFT) & CAN_WORD024_DATA_BYTE_1_MASK) +#define CAN_WORD024_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD024_DATA_BYTE_0_MASK (0xFF << CAN_WORD024_DATA_BYTE_0_SHIFT) +#define CAN_WORD024_DATA_BYTE_0(n) (((n) << CAN_WORD024_DATA_BYTE_0_SHIFT) & CAN_WORD024_DATA_BYTE_0_MASK) + +/* Message Buffer 24 WORD1 Register (WORD124) */ +#define CAN_WORD124_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD124_DATA_BYTE_7_MASK (0xFF << CAN_WORD124_DATA_BYTE_7_SHIFT) +#define CAN_WORD124_DATA_BYTE_7(n) (((n) << CAN_WORD124_DATA_BYTE_7_SHIFT) & CAN_WORD124_DATA_BYTE_7_MASK) +#define CAN_WORD124_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD124_DATA_BYTE_6_MASK (0xFF << CAN_WORD124_DATA_BYTE_6_SHIFT) +#define CAN_WORD124_DATA_BYTE_6(n) (((n) << CAN_WORD124_DATA_BYTE_6_SHIFT) & CAN_WORD124_DATA_BYTE_6_MASK) +#define CAN_WORD124_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD124_DATA_BYTE_5_MASK (0xFF << CAN_WORD124_DATA_BYTE_5_SHIFT) +#define CAN_WORD124_DATA_BYTE_5(n) (((n) << CAN_WORD124_DATA_BYTE_5_SHIFT) & CAN_WORD124_DATA_BYTE_5_MASK) +#define CAN_WORD124_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD124_DATA_BYTE_4_MASK (0xFF << CAN_WORD124_DATA_BYTE_4_SHIFT) +#define CAN_WORD124_DATA_BYTE_4(n) (((n) << CAN_WORD124_DATA_BYTE_4_SHIFT) & CAN_WORD124_DATA_BYTE_4_MASK) + +/* Message Buffer 25 CS Register (CS25) */ +#define CAN_CS25_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS25_TIME_STAMP_MASK (0xFFFF << CAN_CS25_TIME_STAMP_SHIFT) +#define CAN_CS25_TIME_STAMP(n) (((n) << CAN_CS25_TIME_STAMP_SHIFT) & CAN_CS25_TIME_STAMP_MASK) +#define CAN_CS25_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS25_DLC_MASK (0xF << CAN_CS25_DLC_SHIFT) +#define CAN_CS25_DLC(n) (((n) << CAN_CS25_DLC_SHIFT) & CAN_CS25_DLC_MASK) +#define CAN_CS25_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS25_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS25_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS25_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS25_CODE_MASK (0xF << CAN_CS25_CODE_SHIFT) +#define CAN_CS25_CODE(n) (((n) << CAN_CS25_CODE_SHIFT) & CAN_CS25_CODE_MASK) +#define CAN_CS25_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS25_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS25_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 25 WORD0 Register (WORD025) */ +#define CAN_WORD025_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD025_DATA_BYTE_3_MASK (0xFF << CAN_WORD025_DATA_BYTE_3_SHIFT) +#define CAN_WORD025_DATA_BYTE_3(n) (((n) << CAN_WORD025_DATA_BYTE_3_SHIFT) & CAN_WORD025_DATA_BYTE_3_MASK) +#define CAN_WORD025_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD025_DATA_BYTE_2_MASK (0xFF << CAN_WORD025_DATA_BYTE_2_SHIFT) +#define CAN_WORD025_DATA_BYTE_2(n) (((n) << CAN_WORD025_DATA_BYTE_2_SHIFT) & CAN_WORD025_DATA_BYTE_2_MASK) +#define CAN_WORD025_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD025_DATA_BYTE_1_MASK (0xFF << CAN_WORD025_DATA_BYTE_1_SHIFT) +#define CAN_WORD025_DATA_BYTE_1(n) (((n) << CAN_WORD025_DATA_BYTE_1_SHIFT) & CAN_WORD025_DATA_BYTE_1_MASK) +#define CAN_WORD025_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD025_DATA_BYTE_0_MASK (0xFF << CAN_WORD025_DATA_BYTE_0_SHIFT) +#define CAN_WORD025_DATA_BYTE_0(n) (((n) << CAN_WORD025_DATA_BYTE_0_SHIFT) & CAN_WORD025_DATA_BYTE_0_MASK) + +/* Message Buffer 25 WORD1 Register (WORD125) */ +#define CAN_WORD125_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD125_DATA_BYTE_7_MASK (0xFF << CAN_WORD125_DATA_BYTE_7_SHIFT) +#define CAN_WORD125_DATA_BYTE_7(n) (((n) << CAN_WORD125_DATA_BYTE_7_SHIFT) & CAN_WORD125_DATA_BYTE_7_MASK) +#define CAN_WORD125_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD125_DATA_BYTE_6_MASK (0xFF << CAN_WORD125_DATA_BYTE_6_SHIFT) +#define CAN_WORD125_DATA_BYTE_6(n) (((n) << CAN_WORD125_DATA_BYTE_6_SHIFT) & CAN_WORD125_DATA_BYTE_6_MASK) +#define CAN_WORD125_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD125_DATA_BYTE_5_MASK (0xFF << CAN_WORD125_DATA_BYTE_5_SHIFT) +#define CAN_WORD125_DATA_BYTE_5(n) (((n) << CAN_WORD125_DATA_BYTE_5_SHIFT) & CAN_WORD125_DATA_BYTE_5_MASK) +#define CAN_WORD125_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD125_DATA_BYTE_4_MASK (0xFF << CAN_WORD125_DATA_BYTE_4_SHIFT) +#define CAN_WORD125_DATA_BYTE_4(n) (((n) << CAN_WORD125_DATA_BYTE_4_SHIFT) & CAN_WORD125_DATA_BYTE_4_MASK) + +/* Message Buffer 26 CS Register (CS26) */ +#define CAN_CS26_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS26_TIME_STAMP_MASK (0xFFFF << CAN_CS26_TIME_STAMP_SHIFT) +#define CAN_CS26_TIME_STAMP(n) (((n) << CAN_CS26_TIME_STAMP_SHIFT) & CAN_CS26_TIME_STAMP_MASK) +#define CAN_CS26_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS26_DLC_MASK (0xF << CAN_CS26_DLC_SHIFT) +#define CAN_CS26_DLC(n) (((n) << CAN_CS26_DLC_SHIFT) & CAN_CS26_DLC_MASK) +#define CAN_CS26_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS26_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS26_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS26_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS26_CODE_MASK (0xF << CAN_CS26_CODE_SHIFT) +#define CAN_CS26_CODE(n) (((n) << CAN_CS26_CODE_SHIFT) & CAN_CS26_CODE_MASK) +#define CAN_CS26_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS26_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS26_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 26 WORD0 Register (WORD026) */ +#define CAN_WORD026_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD026_DATA_BYTE_3_MASK (0xFF << CAN_WORD026_DATA_BYTE_3_SHIFT) +#define CAN_WORD026_DATA_BYTE_3(n) (((n) << CAN_WORD026_DATA_BYTE_3_SHIFT) & CAN_WORD026_DATA_BYTE_3_MASK) +#define CAN_WORD026_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD026_DATA_BYTE_2_MASK (0xFF << CAN_WORD026_DATA_BYTE_2_SHIFT) +#define CAN_WORD026_DATA_BYTE_2(n) (((n) << CAN_WORD026_DATA_BYTE_2_SHIFT) & CAN_WORD026_DATA_BYTE_2_MASK) +#define CAN_WORD026_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD026_DATA_BYTE_1_MASK (0xFF << CAN_WORD026_DATA_BYTE_1_SHIFT) +#define CAN_WORD026_DATA_BYTE_1(n) (((n) << CAN_WORD026_DATA_BYTE_1_SHIFT) & CAN_WORD026_DATA_BYTE_1_MASK) +#define CAN_WORD026_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD026_DATA_BYTE_0_MASK (0xFF << CAN_WORD026_DATA_BYTE_0_SHIFT) +#define CAN_WORD026_DATA_BYTE_0(n) (((n) << CAN_WORD026_DATA_BYTE_0_SHIFT) & CAN_WORD026_DATA_BYTE_0_MASK) + +/* Message Buffer 26 WORD1 Register (WORD126) */ +#define CAN_WORD126_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD126_DATA_BYTE_7_MASK (0xFF << CAN_WORD126_DATA_BYTE_7_SHIFT) +#define CAN_WORD126_DATA_BYTE_7(n) (((n) << CAN_WORD126_DATA_BYTE_7_SHIFT) & CAN_WORD126_DATA_BYTE_7_MASK) +#define CAN_WORD126_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD126_DATA_BYTE_6_MASK (0xFF << CAN_WORD126_DATA_BYTE_6_SHIFT) +#define CAN_WORD126_DATA_BYTE_6(n) (((n) << CAN_WORD126_DATA_BYTE_6_SHIFT) & CAN_WORD126_DATA_BYTE_6_MASK) +#define CAN_WORD126_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD126_DATA_BYTE_5_MASK (0xFF << CAN_WORD126_DATA_BYTE_5_SHIFT) +#define CAN_WORD126_DATA_BYTE_5(n) (((n) << CAN_WORD126_DATA_BYTE_5_SHIFT) & CAN_WORD126_DATA_BYTE_5_MASK) +#define CAN_WORD126_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD126_DATA_BYTE_4_MASK (0xFF << CAN_WORD126_DATA_BYTE_4_SHIFT) +#define CAN_WORD126_DATA_BYTE_4(n) (((n) << CAN_WORD126_DATA_BYTE_4_SHIFT) & CAN_WORD126_DATA_BYTE_4_MASK) + +/* Message Buffer 27 CS Register (CS27) */ +#define CAN_CS27_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS27_TIME_STAMP_MASK (0xFFFF << CAN_CS27_TIME_STAMP_SHIFT) +#define CAN_CS27_TIME_STAMP(n) (((n) << CAN_CS27_TIME_STAMP_SHIFT) & CAN_CS27_TIME_STAMP_MASK) +#define CAN_CS27_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS27_DLC_MASK (0xF << CAN_CS27_DLC_SHIFT) +#define CAN_CS27_DLC(n) (((n) << CAN_CS27_DLC_SHIFT) & CAN_CS27_DLC_MASK) +#define CAN_CS27_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS27_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS27_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS27_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS27_CODE_MASK (0xF << CAN_CS27_CODE_SHIFT) +#define CAN_CS27_CODE(n) (((n) << CAN_CS27_CODE_SHIFT) & CAN_CS27_CODE_MASK) +#define CAN_CS27_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS27_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS27_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 27 WORD0 Register (WORD027) */ +#define CAN_WORD027_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD027_DATA_BYTE_3_MASK (0xFF << CAN_WORD027_DATA_BYTE_3_SHIFT) +#define CAN_WORD027_DATA_BYTE_3(n) (((n) << CAN_WORD027_DATA_BYTE_3_SHIFT) & CAN_WORD027_DATA_BYTE_3_MASK) +#define CAN_WORD027_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD027_DATA_BYTE_2_MASK (0xFF << CAN_WORD027_DATA_BYTE_2_SHIFT) +#define CAN_WORD027_DATA_BYTE_2(n) (((n) << CAN_WORD027_DATA_BYTE_2_SHIFT) & CAN_WORD027_DATA_BYTE_2_MASK) +#define CAN_WORD027_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD027_DATA_BYTE_1_MASK (0xFF << CAN_WORD027_DATA_BYTE_1_SHIFT) +#define CAN_WORD027_DATA_BYTE_1(n) (((n) << CAN_WORD027_DATA_BYTE_1_SHIFT) & CAN_WORD027_DATA_BYTE_1_MASK) +#define CAN_WORD027_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD027_DATA_BYTE_0_MASK (0xFF << CAN_WORD027_DATA_BYTE_0_SHIFT) +#define CAN_WORD027_DATA_BYTE_0(n) (((n) << CAN_WORD027_DATA_BYTE_0_SHIFT) & CAN_WORD027_DATA_BYTE_0_MASK) + +/* Message Buffer 27 WORD1 Register (WORD127) */ +#define CAN_WORD127_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD127_DATA_BYTE_7_MASK (0xFF << CAN_WORD127_DATA_BYTE_7_SHIFT) +#define CAN_WORD127_DATA_BYTE_7(n) (((n) << CAN_WORD127_DATA_BYTE_7_SHIFT) & CAN_WORD127_DATA_BYTE_7_MASK) +#define CAN_WORD127_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD127_DATA_BYTE_6_MASK (0xFF << CAN_WORD127_DATA_BYTE_6_SHIFT) +#define CAN_WORD127_DATA_BYTE_6(n) (((n) << CAN_WORD127_DATA_BYTE_6_SHIFT) & CAN_WORD127_DATA_BYTE_6_MASK) +#define CAN_WORD127_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD127_DATA_BYTE_5_MASK (0xFF << CAN_WORD127_DATA_BYTE_5_SHIFT) +#define CAN_WORD127_DATA_BYTE_5(n) (((n) << CAN_WORD127_DATA_BYTE_5_SHIFT) & CAN_WORD127_DATA_BYTE_5_MASK) +#define CAN_WORD127_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD127_DATA_BYTE_4_MASK (0xFF << CAN_WORD127_DATA_BYTE_4_SHIFT) +#define CAN_WORD127_DATA_BYTE_4(n) (((n) << CAN_WORD127_DATA_BYTE_4_SHIFT) & CAN_WORD127_DATA_BYTE_4_MASK) + +/* Message Buffer 28 CS Register (CS28) */ +#define CAN_CS28_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS28_TIME_STAMP_MASK (0xFFFF << CAN_CS28_TIME_STAMP_SHIFT) +#define CAN_CS28_TIME_STAMP(n) (((n) << CAN_CS28_TIME_STAMP_SHIFT) & CAN_CS28_TIME_STAMP_MASK) +#define CAN_CS28_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS28_DLC_MASK (0xF << CAN_CS28_DLC_SHIFT) +#define CAN_CS28_DLC(n) (((n) << CAN_CS28_DLC_SHIFT) & CAN_CS28_DLC_MASK) +#define CAN_CS28_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS28_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS28_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS28_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS28_CODE_MASK (0xF << CAN_CS28_CODE_SHIFT) +#define CAN_CS28_CODE(n) (((n) << CAN_CS28_CODE_SHIFT) & CAN_CS28_CODE_MASK) +#define CAN_CS28_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS28_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS28_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 28 WORD0 Register (WORD028) */ +#define CAN_WORD028_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD028_DATA_BYTE_3_MASK (0xFF << CAN_WORD028_DATA_BYTE_3_SHIFT) +#define CAN_WORD028_DATA_BYTE_3(n) (((n) << CAN_WORD028_DATA_BYTE_3_SHIFT) & CAN_WORD028_DATA_BYTE_3_MASK) +#define CAN_WORD028_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD028_DATA_BYTE_2_MASK (0xFF << CAN_WORD028_DATA_BYTE_2_SHIFT) +#define CAN_WORD028_DATA_BYTE_2(n) (((n) << CAN_WORD028_DATA_BYTE_2_SHIFT) & CAN_WORD028_DATA_BYTE_2_MASK) +#define CAN_WORD028_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD028_DATA_BYTE_1_MASK (0xFF << CAN_WORD028_DATA_BYTE_1_SHIFT) +#define CAN_WORD028_DATA_BYTE_1(n) (((n) << CAN_WORD028_DATA_BYTE_1_SHIFT) & CAN_WORD028_DATA_BYTE_1_MASK) +#define CAN_WORD028_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD028_DATA_BYTE_0_MASK (0xFF << CAN_WORD028_DATA_BYTE_0_SHIFT) +#define CAN_WORD028_DATA_BYTE_0(n) (((n) << CAN_WORD028_DATA_BYTE_0_SHIFT) & CAN_WORD028_DATA_BYTE_0_MASK) + +/* Message Buffer 28 WORD1 Register (WORD128) */ +#define CAN_WORD128_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD128_DATA_BYTE_7_MASK (0xFF << CAN_WORD128_DATA_BYTE_7_SHIFT) +#define CAN_WORD128_DATA_BYTE_7(n) (((n) << CAN_WORD128_DATA_BYTE_7_SHIFT) & CAN_WORD128_DATA_BYTE_7_MASK) +#define CAN_WORD128_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD128_DATA_BYTE_6_MASK (0xFF << CAN_WORD128_DATA_BYTE_6_SHIFT) +#define CAN_WORD128_DATA_BYTE_6(n) (((n) << CAN_WORD128_DATA_BYTE_6_SHIFT) & CAN_WORD128_DATA_BYTE_6_MASK) +#define CAN_WORD128_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD128_DATA_BYTE_5_MASK (0xFF << CAN_WORD128_DATA_BYTE_5_SHIFT) +#define CAN_WORD128_DATA_BYTE_5(n) (((n) << CAN_WORD128_DATA_BYTE_5_SHIFT) & CAN_WORD128_DATA_BYTE_5_MASK) +#define CAN_WORD128_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD128_DATA_BYTE_4_MASK (0xFF << CAN_WORD128_DATA_BYTE_4_SHIFT) +#define CAN_WORD128_DATA_BYTE_4(n) (((n) << CAN_WORD128_DATA_BYTE_4_SHIFT) & CAN_WORD128_DATA_BYTE_4_MASK) + +/* Message Buffer 29 CS Register (CS29) */ +#define CAN_CS29_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS29_TIME_STAMP_MASK (0xFFFF << CAN_CS29_TIME_STAMP_SHIFT) +#define CAN_CS29_TIME_STAMP(n) (((n) << CAN_CS29_TIME_STAMP_SHIFT) & CAN_CS29_TIME_STAMP_MASK) +#define CAN_CS29_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS29_DLC_MASK (0xF << CAN_CS29_DLC_SHIFT) +#define CAN_CS29_DLC(n) (((n) << CAN_CS29_DLC_SHIFT) & CAN_CS29_DLC_MASK) +#define CAN_CS29_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS29_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS29_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS29_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS29_CODE_MASK (0xF << CAN_CS29_CODE_SHIFT) +#define CAN_CS29_CODE(n) (((n) << CAN_CS29_CODE_SHIFT) & CAN_CS29_CODE_MASK) +#define CAN_CS29_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS29_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS29_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 29 WORD0 Register (WORD029) */ +#define CAN_WORD029_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD029_DATA_BYTE_3_MASK (0xFF << CAN_WORD029_DATA_BYTE_3_SHIFT) +#define CAN_WORD029_DATA_BYTE_3(n) (((n) << CAN_WORD029_DATA_BYTE_3_SHIFT) & CAN_WORD029_DATA_BYTE_3_MASK) +#define CAN_WORD029_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD029_DATA_BYTE_2_MASK (0xFF << CAN_WORD029_DATA_BYTE_2_SHIFT) +#define CAN_WORD029_DATA_BYTE_2(n) (((n) << CAN_WORD029_DATA_BYTE_2_SHIFT) & CAN_WORD029_DATA_BYTE_2_MASK) +#define CAN_WORD029_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD029_DATA_BYTE_1_MASK (0xFF << CAN_WORD029_DATA_BYTE_1_SHIFT) +#define CAN_WORD029_DATA_BYTE_1(n) (((n) << CAN_WORD029_DATA_BYTE_1_SHIFT) & CAN_WORD029_DATA_BYTE_1_MASK) +#define CAN_WORD029_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD029_DATA_BYTE_0_MASK (0xFF << CAN_WORD029_DATA_BYTE_0_SHIFT) +#define CAN_WORD029_DATA_BYTE_0(n) (((n) << CAN_WORD029_DATA_BYTE_0_SHIFT) & CAN_WORD029_DATA_BYTE_0_MASK) + +/* Message Buffer 29 WORD1 Register (WORD129) */ +#define CAN_WORD129_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD129_DATA_BYTE_7_MASK (0xFF << CAN_WORD129_DATA_BYTE_7_SHIFT) +#define CAN_WORD129_DATA_BYTE_7(n) (((n) << CAN_WORD129_DATA_BYTE_7_SHIFT) & CAN_WORD129_DATA_BYTE_7_MASK) +#define CAN_WORD129_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD129_DATA_BYTE_6_MASK (0xFF << CAN_WORD129_DATA_BYTE_6_SHIFT) +#define CAN_WORD129_DATA_BYTE_6(n) (((n) << CAN_WORD129_DATA_BYTE_6_SHIFT) & CAN_WORD129_DATA_BYTE_6_MASK) +#define CAN_WORD129_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD129_DATA_BYTE_5_MASK (0xFF << CAN_WORD129_DATA_BYTE_5_SHIFT) +#define CAN_WORD129_DATA_BYTE_5(n) (((n) << CAN_WORD129_DATA_BYTE_5_SHIFT) & CAN_WORD129_DATA_BYTE_5_MASK) +#define CAN_WORD129_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD129_DATA_BYTE_4_MASK (0xFF << CAN_WORD129_DATA_BYTE_4_SHIFT) +#define CAN_WORD129_DATA_BYTE_4(n) (((n) << CAN_WORD129_DATA_BYTE_4_SHIFT) & CAN_WORD129_DATA_BYTE_4_MASK) + +/* Message Buffer 30 CS Register (CS30) */ +#define CAN_CS30_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS30_TIME_STAMP_MASK (0xFFFF << CAN_CS30_TIME_STAMP_SHIFT) +#define CAN_CS30_TIME_STAMP(n) (((n) << CAN_CS30_TIME_STAMP_SHIFT) & CAN_CS30_TIME_STAMP_MASK) +#define CAN_CS30_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS30_DLC_MASK (0xF << CAN_CS30_DLC_SHIFT) +#define CAN_CS30_DLC(n) (((n) << CAN_CS30_DLC_SHIFT) & CAN_CS30_DLC_MASK) +#define CAN_CS30_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS30_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS30_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS30_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS30_CODE_MASK (0xF << CAN_CS30_CODE_SHIFT) +#define CAN_CS30_CODE(n) (((n) << CAN_CS30_CODE_SHIFT) & CAN_CS30_CODE_MASK) +#define CAN_CS30_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS30_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS30_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 30 WORD0 Register (WORD030) */ +#define CAN_WORD030_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD030_DATA_BYTE_3_MASK (0xFF << CAN_WORD030_DATA_BYTE_3_SHIFT) +#define CAN_WORD030_DATA_BYTE_3(n) (((n) << CAN_WORD030_DATA_BYTE_3_SHIFT) & CAN_WORD030_DATA_BYTE_3_MASK) +#define CAN_WORD030_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD030_DATA_BYTE_2_MASK (0xFF << CAN_WORD030_DATA_BYTE_2_SHIFT) +#define CAN_WORD030_DATA_BYTE_2(n) (((n) << CAN_WORD030_DATA_BYTE_2_SHIFT) & CAN_WORD030_DATA_BYTE_2_MASK) +#define CAN_WORD030_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD030_DATA_BYTE_1_MASK (0xFF << CAN_WORD030_DATA_BYTE_1_SHIFT) +#define CAN_WORD030_DATA_BYTE_1(n) (((n) << CAN_WORD030_DATA_BYTE_1_SHIFT) & CAN_WORD030_DATA_BYTE_1_MASK) +#define CAN_WORD030_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD030_DATA_BYTE_0_MASK (0xFF << CAN_WORD030_DATA_BYTE_0_SHIFT) +#define CAN_WORD030_DATA_BYTE_0(n) (((n) << CAN_WORD030_DATA_BYTE_0_SHIFT) & CAN_WORD030_DATA_BYTE_0_MASK) + +/* Message Buffer 30 WORD1 Register (WORD130) */ +#define CAN_WORD130_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD130_DATA_BYTE_7_MASK (0xFF << CAN_WORD130_DATA_BYTE_7_SHIFT) +#define CAN_WORD130_DATA_BYTE_7(n) (((n) << CAN_WORD130_DATA_BYTE_7_SHIFT) & CAN_WORD130_DATA_BYTE_7_MASK) +#define CAN_WORD130_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD130_DATA_BYTE_6_MASK (0xFF << CAN_WORD130_DATA_BYTE_6_SHIFT) +#define CAN_WORD130_DATA_BYTE_6(n) (((n) << CAN_WORD130_DATA_BYTE_6_SHIFT) & CAN_WORD130_DATA_BYTE_6_MASK) +#define CAN_WORD130_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD130_DATA_BYTE_5_MASK (0xFF << CAN_WORD130_DATA_BYTE_5_SHIFT) +#define CAN_WORD130_DATA_BYTE_5(n) (((n) << CAN_WORD130_DATA_BYTE_5_SHIFT) & CAN_WORD130_DATA_BYTE_5_MASK) +#define CAN_WORD130_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD130_DATA_BYTE_4_MASK (0xFF << CAN_WORD130_DATA_BYTE_4_SHIFT) +#define CAN_WORD130_DATA_BYTE_4(n) (((n) << CAN_WORD130_DATA_BYTE_4_SHIFT) & CAN_WORD130_DATA_BYTE_4_MASK) + +/* Message Buffer 31 CS Register (CS31) */ +#define CAN_CS31_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS31_TIME_STAMP_MASK (0xFFFF << CAN_CS31_TIME_STAMP_SHIFT) +#define CAN_CS31_TIME_STAMP(n) (((n) << CAN_CS31_TIME_STAMP_SHIFT) & CAN_CS31_TIME_STAMP_MASK) +#define CAN_CS31_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS31_DLC_MASK (0xF << CAN_CS31_DLC_SHIFT) +#define CAN_CS31_DLC(n) (((n) << CAN_CS31_DLC_SHIFT) & CAN_CS31_DLC_MASK) +#define CAN_CS31_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS31_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS31_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS31_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS31_CODE_MASK (0xF << CAN_CS31_CODE_SHIFT) +#define CAN_CS31_CODE(n) (((n) << CAN_CS31_CODE_SHIFT) & CAN_CS31_CODE_MASK) +#define CAN_CS31_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS31_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS31_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 31 WORD0 Register (WORD031) */ +#define CAN_WORD031_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD031_DATA_BYTE_3_MASK (0xFF << CAN_WORD031_DATA_BYTE_3_SHIFT) +#define CAN_WORD031_DATA_BYTE_3(n) (((n) << CAN_WORD031_DATA_BYTE_3_SHIFT) & CAN_WORD031_DATA_BYTE_3_MASK) +#define CAN_WORD031_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD031_DATA_BYTE_2_MASK (0xFF << CAN_WORD031_DATA_BYTE_2_SHIFT) +#define CAN_WORD031_DATA_BYTE_2(n) (((n) << CAN_WORD031_DATA_BYTE_2_SHIFT) & CAN_WORD031_DATA_BYTE_2_MASK) +#define CAN_WORD031_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD031_DATA_BYTE_1_MASK (0xFF << CAN_WORD031_DATA_BYTE_1_SHIFT) +#define CAN_WORD031_DATA_BYTE_1(n) (((n) << CAN_WORD031_DATA_BYTE_1_SHIFT) & CAN_WORD031_DATA_BYTE_1_MASK) +#define CAN_WORD031_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD031_DATA_BYTE_0_MASK (0xFF << CAN_WORD031_DATA_BYTE_0_SHIFT) +#define CAN_WORD031_DATA_BYTE_0(n) (((n) << CAN_WORD031_DATA_BYTE_0_SHIFT) & CAN_WORD031_DATA_BYTE_0_MASK) + +/* Message Buffer 31 WORD1 Register (WORD131) */ +#define CAN_WORD131_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD131_DATA_BYTE_7_MASK (0xFF << CAN_WORD131_DATA_BYTE_7_SHIFT) +#define CAN_WORD131_DATA_BYTE_7(n) (((n) << CAN_WORD131_DATA_BYTE_7_SHIFT) & CAN_WORD131_DATA_BYTE_7_MASK) +#define CAN_WORD131_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD131_DATA_BYTE_6_MASK (0xFF << CAN_WORD131_DATA_BYTE_6_SHIFT) +#define CAN_WORD131_DATA_BYTE_6(n) (((n) << CAN_WORD131_DATA_BYTE_6_SHIFT) & CAN_WORD131_DATA_BYTE_6_MASK) +#define CAN_WORD131_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD131_DATA_BYTE_5_MASK (0xFF << CAN_WORD131_DATA_BYTE_5_SHIFT) +#define CAN_WORD131_DATA_BYTE_5(n) (((n) << CAN_WORD131_DATA_BYTE_5_SHIFT) & CAN_WORD131_DATA_BYTE_5_MASK) +#define CAN_WORD131_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD131_DATA_BYTE_4_MASK (0xFF << CAN_WORD131_DATA_BYTE_4_SHIFT) +#define CAN_WORD131_DATA_BYTE_4(n) (((n) << CAN_WORD131_DATA_BYTE_4_SHIFT) & CAN_WORD131_DATA_BYTE_4_MASK) + +/* Message Buffer 32 CS Register (CS32) */ +#define CAN_CS32_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS32_TIME_STAMP_MASK (0xFFFF << CAN_CS32_TIME_STAMP_SHIFT) +#define CAN_CS32_TIME_STAMP(n) (((n) << CAN_CS32_TIME_STAMP_SHIFT) & CAN_CS32_TIME_STAMP_MASK) +#define CAN_CS32_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS32_DLC_MASK (0xF << CAN_CS32_DLC_SHIFT) +#define CAN_CS32_DLC(n) (((n) << CAN_CS32_DLC_SHIFT) & CAN_CS32_DLC_MASK) +#define CAN_CS32_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS32_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS32_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS32_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS32_CODE_MASK (0xF << CAN_CS32_CODE_SHIFT) +#define CAN_CS32_CODE(n) (((n) << CAN_CS32_CODE_SHIFT) & CAN_CS32_CODE_MASK) +#define CAN_CS32_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS32_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS32_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 32 WORD0 Register (WORD032) */ +#define CAN_WORD032_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD032_DATA_BYTE_3_MASK (0xFF << CAN_WORD032_DATA_BYTE_3_SHIFT) +#define CAN_WORD032_DATA_BYTE_3(n) (((n) << CAN_WORD032_DATA_BYTE_3_SHIFT) & CAN_WORD032_DATA_BYTE_3_MASK) +#define CAN_WORD032_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD032_DATA_BYTE_2_MASK (0xFF << CAN_WORD032_DATA_BYTE_2_SHIFT) +#define CAN_WORD032_DATA_BYTE_2(n) (((n) << CAN_WORD032_DATA_BYTE_2_SHIFT) & CAN_WORD032_DATA_BYTE_2_MASK) +#define CAN_WORD032_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD032_DATA_BYTE_1_MASK (0xFF << CAN_WORD032_DATA_BYTE_1_SHIFT) +#define CAN_WORD032_DATA_BYTE_1(n) (((n) << CAN_WORD032_DATA_BYTE_1_SHIFT) & CAN_WORD032_DATA_BYTE_1_MASK) +#define CAN_WORD032_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD032_DATA_BYTE_0_MASK (0xFF << CAN_WORD032_DATA_BYTE_0_SHIFT) +#define CAN_WORD032_DATA_BYTE_0(n) (((n) << CAN_WORD032_DATA_BYTE_0_SHIFT) & CAN_WORD032_DATA_BYTE_0_MASK) + +/* Message Buffer 32 WORD1 Register (WORD132) */ +#define CAN_WORD132_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD132_DATA_BYTE_7_MASK (0xFF << CAN_WORD132_DATA_BYTE_7_SHIFT) +#define CAN_WORD132_DATA_BYTE_7(n) (((n) << CAN_WORD132_DATA_BYTE_7_SHIFT) & CAN_WORD132_DATA_BYTE_7_MASK) +#define CAN_WORD132_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD132_DATA_BYTE_6_MASK (0xFF << CAN_WORD132_DATA_BYTE_6_SHIFT) +#define CAN_WORD132_DATA_BYTE_6(n) (((n) << CAN_WORD132_DATA_BYTE_6_SHIFT) & CAN_WORD132_DATA_BYTE_6_MASK) +#define CAN_WORD132_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD132_DATA_BYTE_5_MASK (0xFF << CAN_WORD132_DATA_BYTE_5_SHIFT) +#define CAN_WORD132_DATA_BYTE_5(n) (((n) << CAN_WORD132_DATA_BYTE_5_SHIFT) & CAN_WORD132_DATA_BYTE_5_MASK) +#define CAN_WORD132_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD132_DATA_BYTE_4_MASK (0xFF << CAN_WORD132_DATA_BYTE_4_SHIFT) +#define CAN_WORD132_DATA_BYTE_4(n) (((n) << CAN_WORD132_DATA_BYTE_4_SHIFT) & CAN_WORD132_DATA_BYTE_4_MASK) + +/* Message Buffer 33 CS Register (CS33) */ +#define CAN_CS33_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS33_TIME_STAMP_MASK (0xFFFF << CAN_CS33_TIME_STAMP_SHIFT) +#define CAN_CS33_TIME_STAMP(n) (((n) << CAN_CS33_TIME_STAMP_SHIFT) & CAN_CS33_TIME_STAMP_MASK) +#define CAN_CS33_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS33_DLC_MASK (0xF << CAN_CS33_DLC_SHIFT) +#define CAN_CS33_DLC(n) (((n) << CAN_CS33_DLC_SHIFT) & CAN_CS33_DLC_MASK) +#define CAN_CS33_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS33_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS33_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS33_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS33_CODE_MASK (0xF << CAN_CS33_CODE_SHIFT) +#define CAN_CS33_CODE(n) (((n) << CAN_CS33_CODE_SHIFT) & CAN_CS33_CODE_MASK) +#define CAN_CS33_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS33_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS33_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 33 WORD0 Register (WORD033) */ +#define CAN_WORD033_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD033_DATA_BYTE_3_MASK (0xFF << CAN_WORD033_DATA_BYTE_3_SHIFT) +#define CAN_WORD033_DATA_BYTE_3(n) (((n) << CAN_WORD033_DATA_BYTE_3_SHIFT) & CAN_WORD033_DATA_BYTE_3_MASK) +#define CAN_WORD033_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD033_DATA_BYTE_2_MASK (0xFF << CAN_WORD033_DATA_BYTE_2_SHIFT) +#define CAN_WORD033_DATA_BYTE_2(n) (((n) << CAN_WORD033_DATA_BYTE_2_SHIFT) & CAN_WORD033_DATA_BYTE_2_MASK) +#define CAN_WORD033_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD033_DATA_BYTE_1_MASK (0xFF << CAN_WORD033_DATA_BYTE_1_SHIFT) +#define CAN_WORD033_DATA_BYTE_1(n) (((n) << CAN_WORD033_DATA_BYTE_1_SHIFT) & CAN_WORD033_DATA_BYTE_1_MASK) +#define CAN_WORD033_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD033_DATA_BYTE_0_MASK (0xFF << CAN_WORD033_DATA_BYTE_0_SHIFT) +#define CAN_WORD033_DATA_BYTE_0(n) (((n) << CAN_WORD033_DATA_BYTE_0_SHIFT) & CAN_WORD033_DATA_BYTE_0_MASK) + +/* Message Buffer 33 WORD1 Register (WORD133) */ +#define CAN_WORD133_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD133_DATA_BYTE_7_MASK (0xFF << CAN_WORD133_DATA_BYTE_7_SHIFT) +#define CAN_WORD133_DATA_BYTE_7(n) (((n) << CAN_WORD133_DATA_BYTE_7_SHIFT) & CAN_WORD133_DATA_BYTE_7_MASK) +#define CAN_WORD133_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD133_DATA_BYTE_6_MASK (0xFF << CAN_WORD133_DATA_BYTE_6_SHIFT) +#define CAN_WORD133_DATA_BYTE_6(n) (((n) << CAN_WORD133_DATA_BYTE_6_SHIFT) & CAN_WORD133_DATA_BYTE_6_MASK) +#define CAN_WORD133_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD133_DATA_BYTE_5_MASK (0xFF << CAN_WORD133_DATA_BYTE_5_SHIFT) +#define CAN_WORD133_DATA_BYTE_5(n) (((n) << CAN_WORD133_DATA_BYTE_5_SHIFT) & CAN_WORD133_DATA_BYTE_5_MASK) +#define CAN_WORD133_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD133_DATA_BYTE_4_MASK (0xFF << CAN_WORD133_DATA_BYTE_4_SHIFT) +#define CAN_WORD133_DATA_BYTE_4(n) (((n) << CAN_WORD133_DATA_BYTE_4_SHIFT) & CAN_WORD133_DATA_BYTE_4_MASK) + +/* Message Buffer 34 CS Register (CS34) */ +#define CAN_CS34_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS34_TIME_STAMP_MASK (0xFFFF << CAN_CS34_TIME_STAMP_SHIFT) +#define CAN_CS34_TIME_STAMP(n) (((n) << CAN_CS34_TIME_STAMP_SHIFT) & CAN_CS34_TIME_STAMP_MASK) +#define CAN_CS34_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS34_DLC_MASK (0xF << CAN_CS34_DLC_SHIFT) +#define CAN_CS34_DLC(n) (((n) << CAN_CS34_DLC_SHIFT) & CAN_CS34_DLC_MASK) +#define CAN_CS34_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS34_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS34_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS34_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS34_CODE_MASK (0xF << CAN_CS34_CODE_SHIFT) +#define CAN_CS34_CODE(n) (((n) << CAN_CS34_CODE_SHIFT) & CAN_CS34_CODE_MASK) +#define CAN_CS34_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS34_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS34_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 34 WORD0 Register (WORD034) */ +#define CAN_WORD034_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD034_DATA_BYTE_3_MASK (0xFF << CAN_WORD034_DATA_BYTE_3_SHIFT) +#define CAN_WORD034_DATA_BYTE_3(n) (((n) << CAN_WORD034_DATA_BYTE_3_SHIFT) & CAN_WORD034_DATA_BYTE_3_MASK) +#define CAN_WORD034_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD034_DATA_BYTE_2_MASK (0xFF << CAN_WORD034_DATA_BYTE_2_SHIFT) +#define CAN_WORD034_DATA_BYTE_2(n) (((n) << CAN_WORD034_DATA_BYTE_2_SHIFT) & CAN_WORD034_DATA_BYTE_2_MASK) +#define CAN_WORD034_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD034_DATA_BYTE_1_MASK (0xFF << CAN_WORD034_DATA_BYTE_1_SHIFT) +#define CAN_WORD034_DATA_BYTE_1(n) (((n) << CAN_WORD034_DATA_BYTE_1_SHIFT) & CAN_WORD034_DATA_BYTE_1_MASK) +#define CAN_WORD034_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD034_DATA_BYTE_0_MASK (0xFF << CAN_WORD034_DATA_BYTE_0_SHIFT) +#define CAN_WORD034_DATA_BYTE_0(n) (((n) << CAN_WORD034_DATA_BYTE_0_SHIFT) & CAN_WORD034_DATA_BYTE_0_MASK) + +/* Message Buffer 34 WORD1 Register (WORD134) */ +#define CAN_WORD134_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD134_DATA_BYTE_7_MASK (0xFF << CAN_WORD134_DATA_BYTE_7_SHIFT) +#define CAN_WORD134_DATA_BYTE_7(n) (((n) << CAN_WORD134_DATA_BYTE_7_SHIFT) & CAN_WORD134_DATA_BYTE_7_MASK) +#define CAN_WORD134_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD134_DATA_BYTE_6_MASK (0xFF << CAN_WORD134_DATA_BYTE_6_SHIFT) +#define CAN_WORD134_DATA_BYTE_6(n) (((n) << CAN_WORD134_DATA_BYTE_6_SHIFT) & CAN_WORD134_DATA_BYTE_6_MASK) +#define CAN_WORD134_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD134_DATA_BYTE_5_MASK (0xFF << CAN_WORD134_DATA_BYTE_5_SHIFT) +#define CAN_WORD134_DATA_BYTE_5(n) (((n) << CAN_WORD134_DATA_BYTE_5_SHIFT) & CAN_WORD134_DATA_BYTE_5_MASK) +#define CAN_WORD134_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD134_DATA_BYTE_4_MASK (0xFF << CAN_WORD134_DATA_BYTE_4_SHIFT) +#define CAN_WORD134_DATA_BYTE_4(n) (((n) << CAN_WORD134_DATA_BYTE_4_SHIFT) & CAN_WORD134_DATA_BYTE_4_MASK) + +/* Message Buffer 35 CS Register (CS35) */ +#define CAN_CS35_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS35_TIME_STAMP_MASK (0xFFFF << CAN_CS35_TIME_STAMP_SHIFT) +#define CAN_CS35_TIME_STAMP(n) (((n) << CAN_CS35_TIME_STAMP_SHIFT) & CAN_CS35_TIME_STAMP_MASK) +#define CAN_CS35_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS35_DLC_MASK (0xF << CAN_CS35_DLC_SHIFT) +#define CAN_CS35_DLC(n) (((n) << CAN_CS35_DLC_SHIFT) & CAN_CS35_DLC_MASK) +#define CAN_CS35_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS35_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS35_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS35_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS35_CODE_MASK (0xF << CAN_CS35_CODE_SHIFT) +#define CAN_CS35_CODE(n) (((n) << CAN_CS35_CODE_SHIFT) & CAN_CS35_CODE_MASK) +#define CAN_CS35_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS35_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS35_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 35 WORD0 Register (WORD035) */ +#define CAN_WORD035_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD035_DATA_BYTE_3_MASK (0xFF << CAN_WORD035_DATA_BYTE_3_SHIFT) +#define CAN_WORD035_DATA_BYTE_3(n) (((n) << CAN_WORD035_DATA_BYTE_3_SHIFT) & CAN_WORD035_DATA_BYTE_3_MASK) +#define CAN_WORD035_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD035_DATA_BYTE_2_MASK (0xFF << CAN_WORD035_DATA_BYTE_2_SHIFT) +#define CAN_WORD035_DATA_BYTE_2(n) (((n) << CAN_WORD035_DATA_BYTE_2_SHIFT) & CAN_WORD035_DATA_BYTE_2_MASK) +#define CAN_WORD035_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD035_DATA_BYTE_1_MASK (0xFF << CAN_WORD035_DATA_BYTE_1_SHIFT) +#define CAN_WORD035_DATA_BYTE_1(n) (((n) << CAN_WORD035_DATA_BYTE_1_SHIFT) & CAN_WORD035_DATA_BYTE_1_MASK) +#define CAN_WORD035_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD035_DATA_BYTE_0_MASK (0xFF << CAN_WORD035_DATA_BYTE_0_SHIFT) +#define CAN_WORD035_DATA_BYTE_0(n) (((n) << CAN_WORD035_DATA_BYTE_0_SHIFT) & CAN_WORD035_DATA_BYTE_0_MASK) + +/* Message Buffer 35 WORD1 Register (WORD135) */ +#define CAN_WORD135_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD135_DATA_BYTE_7_MASK (0xFF << CAN_WORD135_DATA_BYTE_7_SHIFT) +#define CAN_WORD135_DATA_BYTE_7(n) (((n) << CAN_WORD135_DATA_BYTE_7_SHIFT) & CAN_WORD135_DATA_BYTE_7_MASK) +#define CAN_WORD135_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD135_DATA_BYTE_6_MASK (0xFF << CAN_WORD135_DATA_BYTE_6_SHIFT) +#define CAN_WORD135_DATA_BYTE_6(n) (((n) << CAN_WORD135_DATA_BYTE_6_SHIFT) & CAN_WORD135_DATA_BYTE_6_MASK) +#define CAN_WORD135_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD135_DATA_BYTE_5_MASK (0xFF << CAN_WORD135_DATA_BYTE_5_SHIFT) +#define CAN_WORD135_DATA_BYTE_5(n) (((n) << CAN_WORD135_DATA_BYTE_5_SHIFT) & CAN_WORD135_DATA_BYTE_5_MASK) +#define CAN_WORD135_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD135_DATA_BYTE_4_MASK (0xFF << CAN_WORD135_DATA_BYTE_4_SHIFT) +#define CAN_WORD135_DATA_BYTE_4(n) (((n) << CAN_WORD135_DATA_BYTE_4_SHIFT) & CAN_WORD135_DATA_BYTE_4_MASK) + +/* Message Buffer 36 CS Register (CS36) */ +#define CAN_CS36_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS36_TIME_STAMP_MASK (0xFFFF << CAN_CS36_TIME_STAMP_SHIFT) +#define CAN_CS36_TIME_STAMP(n) (((n) << CAN_CS36_TIME_STAMP_SHIFT) & CAN_CS36_TIME_STAMP_MASK) +#define CAN_CS36_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS36_DLC_MASK (0xF << CAN_CS36_DLC_SHIFT) +#define CAN_CS36_DLC(n) (((n) << CAN_CS36_DLC_SHIFT) & CAN_CS36_DLC_MASK) +#define CAN_CS36_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS36_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS36_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS36_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS36_CODE_MASK (0xF << CAN_CS36_CODE_SHIFT) +#define CAN_CS36_CODE(n) (((n) << CAN_CS36_CODE_SHIFT) & CAN_CS36_CODE_MASK) +#define CAN_CS36_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS36_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS36_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 36 WORD0 Register (WORD036) */ +#define CAN_WORD036_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD036_DATA_BYTE_3_MASK (0xFF << CAN_WORD036_DATA_BYTE_3_SHIFT) +#define CAN_WORD036_DATA_BYTE_3(n) (((n) << CAN_WORD036_DATA_BYTE_3_SHIFT) & CAN_WORD036_DATA_BYTE_3_MASK) +#define CAN_WORD036_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD036_DATA_BYTE_2_MASK (0xFF << CAN_WORD036_DATA_BYTE_2_SHIFT) +#define CAN_WORD036_DATA_BYTE_2(n) (((n) << CAN_WORD036_DATA_BYTE_2_SHIFT) & CAN_WORD036_DATA_BYTE_2_MASK) +#define CAN_WORD036_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD036_DATA_BYTE_1_MASK (0xFF << CAN_WORD036_DATA_BYTE_1_SHIFT) +#define CAN_WORD036_DATA_BYTE_1(n) (((n) << CAN_WORD036_DATA_BYTE_1_SHIFT) & CAN_WORD036_DATA_BYTE_1_MASK) +#define CAN_WORD036_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD036_DATA_BYTE_0_MASK (0xFF << CAN_WORD036_DATA_BYTE_0_SHIFT) +#define CAN_WORD036_DATA_BYTE_0(n) (((n) << CAN_WORD036_DATA_BYTE_0_SHIFT) & CAN_WORD036_DATA_BYTE_0_MASK) + +/* Message Buffer 36 WORD1 Register (WORD136) */ +#define CAN_WORD136_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD136_DATA_BYTE_7_MASK (0xFF << CAN_WORD136_DATA_BYTE_7_SHIFT) +#define CAN_WORD136_DATA_BYTE_7(n) (((n) << CAN_WORD136_DATA_BYTE_7_SHIFT) & CAN_WORD136_DATA_BYTE_7_MASK) +#define CAN_WORD136_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD136_DATA_BYTE_6_MASK (0xFF << CAN_WORD136_DATA_BYTE_6_SHIFT) +#define CAN_WORD136_DATA_BYTE_6(n) (((n) << CAN_WORD136_DATA_BYTE_6_SHIFT) & CAN_WORD136_DATA_BYTE_6_MASK) +#define CAN_WORD136_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD136_DATA_BYTE_5_MASK (0xFF << CAN_WORD136_DATA_BYTE_5_SHIFT) +#define CAN_WORD136_DATA_BYTE_5(n) (((n) << CAN_WORD136_DATA_BYTE_5_SHIFT) & CAN_WORD136_DATA_BYTE_5_MASK) +#define CAN_WORD136_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD136_DATA_BYTE_4_MASK (0xFF << CAN_WORD136_DATA_BYTE_4_SHIFT) +#define CAN_WORD136_DATA_BYTE_4(n) (((n) << CAN_WORD136_DATA_BYTE_4_SHIFT) & CAN_WORD136_DATA_BYTE_4_MASK) + +/* Message Buffer 37 CS Register (CS37) */ +#define CAN_CS37_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS37_TIME_STAMP_MASK (0xFFFF << CAN_CS37_TIME_STAMP_SHIFT) +#define CAN_CS37_TIME_STAMP(n) (((n) << CAN_CS37_TIME_STAMP_SHIFT) & CAN_CS37_TIME_STAMP_MASK) +#define CAN_CS37_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS37_DLC_MASK (0xF << CAN_CS37_DLC_SHIFT) +#define CAN_CS37_DLC(n) (((n) << CAN_CS37_DLC_SHIFT) & CAN_CS37_DLC_MASK) +#define CAN_CS37_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS37_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS37_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS37_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS37_CODE_MASK (0xF << CAN_CS37_CODE_SHIFT) +#define CAN_CS37_CODE(n) (((n) << CAN_CS37_CODE_SHIFT) & CAN_CS37_CODE_MASK) +#define CAN_CS37_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS37_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS37_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 37 WORD0 Register (WORD037) */ +#define CAN_WORD037_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD037_DATA_BYTE_3_MASK (0xFF << CAN_WORD037_DATA_BYTE_3_SHIFT) +#define CAN_WORD037_DATA_BYTE_3(n) (((n) << CAN_WORD037_DATA_BYTE_3_SHIFT) & CAN_WORD037_DATA_BYTE_3_MASK) +#define CAN_WORD037_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD037_DATA_BYTE_2_MASK (0xFF << CAN_WORD037_DATA_BYTE_2_SHIFT) +#define CAN_WORD037_DATA_BYTE_2(n) (((n) << CAN_WORD037_DATA_BYTE_2_SHIFT) & CAN_WORD037_DATA_BYTE_2_MASK) +#define CAN_WORD037_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD037_DATA_BYTE_1_MASK (0xFF << CAN_WORD037_DATA_BYTE_1_SHIFT) +#define CAN_WORD037_DATA_BYTE_1(n) (((n) << CAN_WORD037_DATA_BYTE_1_SHIFT) & CAN_WORD037_DATA_BYTE_1_MASK) +#define CAN_WORD037_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD037_DATA_BYTE_0_MASK (0xFF << CAN_WORD037_DATA_BYTE_0_SHIFT) +#define CAN_WORD037_DATA_BYTE_0(n) (((n) << CAN_WORD037_DATA_BYTE_0_SHIFT) & CAN_WORD037_DATA_BYTE_0_MASK) + +/* Message Buffer 37 WORD1 Register (WORD137) */ +#define CAN_WORD137_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD137_DATA_BYTE_7_MASK (0xFF << CAN_WORD137_DATA_BYTE_7_SHIFT) +#define CAN_WORD137_DATA_BYTE_7(n) (((n) << CAN_WORD137_DATA_BYTE_7_SHIFT) & CAN_WORD137_DATA_BYTE_7_MASK) +#define CAN_WORD137_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD137_DATA_BYTE_6_MASK (0xFF << CAN_WORD137_DATA_BYTE_6_SHIFT) +#define CAN_WORD137_DATA_BYTE_6(n) (((n) << CAN_WORD137_DATA_BYTE_6_SHIFT) & CAN_WORD137_DATA_BYTE_6_MASK) +#define CAN_WORD137_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD137_DATA_BYTE_5_MASK (0xFF << CAN_WORD137_DATA_BYTE_5_SHIFT) +#define CAN_WORD137_DATA_BYTE_5(n) (((n) << CAN_WORD137_DATA_BYTE_5_SHIFT) & CAN_WORD137_DATA_BYTE_5_MASK) +#define CAN_WORD137_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD137_DATA_BYTE_4_MASK (0xFF << CAN_WORD137_DATA_BYTE_4_SHIFT) +#define CAN_WORD137_DATA_BYTE_4(n) (((n) << CAN_WORD137_DATA_BYTE_4_SHIFT) & CAN_WORD137_DATA_BYTE_4_MASK) + +/* Message Buffer 38 CS Register (CS38) */ +#define CAN_CS38_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS38_TIME_STAMP_MASK (0xFFFF << CAN_CS38_TIME_STAMP_SHIFT) +#define CAN_CS38_TIME_STAMP(n) (((n) << CAN_CS38_TIME_STAMP_SHIFT) & CAN_CS38_TIME_STAMP_MASK) +#define CAN_CS38_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS38_DLC_MASK (0xF << CAN_CS38_DLC_SHIFT) +#define CAN_CS38_DLC(n) (((n) << CAN_CS38_DLC_SHIFT) & CAN_CS38_DLC_MASK) +#define CAN_CS38_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS38_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS38_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS38_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS38_CODE_MASK (0xF << CAN_CS38_CODE_SHIFT) +#define CAN_CS38_CODE(n) (((n) << CAN_CS38_CODE_SHIFT) & CAN_CS38_CODE_MASK) +#define CAN_CS38_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS38_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS38_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 38 WORD0 Register (WORD038) */ +#define CAN_WORD038_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD038_DATA_BYTE_3_MASK (0xFF << CAN_WORD038_DATA_BYTE_3_SHIFT) +#define CAN_WORD038_DATA_BYTE_3(n) (((n) << CAN_WORD038_DATA_BYTE_3_SHIFT) & CAN_WORD038_DATA_BYTE_3_MASK) +#define CAN_WORD038_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD038_DATA_BYTE_2_MASK (0xFF << CAN_WORD038_DATA_BYTE_2_SHIFT) +#define CAN_WORD038_DATA_BYTE_2(n) (((n) << CAN_WORD038_DATA_BYTE_2_SHIFT) & CAN_WORD038_DATA_BYTE_2_MASK) +#define CAN_WORD038_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD038_DATA_BYTE_1_MASK (0xFF << CAN_WORD038_DATA_BYTE_1_SHIFT) +#define CAN_WORD038_DATA_BYTE_1(n) (((n) << CAN_WORD038_DATA_BYTE_1_SHIFT) & CAN_WORD038_DATA_BYTE_1_MASK) +#define CAN_WORD038_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD038_DATA_BYTE_0_MASK (0xFF << CAN_WORD038_DATA_BYTE_0_SHIFT) +#define CAN_WORD038_DATA_BYTE_0(n) (((n) << CAN_WORD038_DATA_BYTE_0_SHIFT) & CAN_WORD038_DATA_BYTE_0_MASK) + +/* Message Buffer 38 WORD1 Register (WORD138) */ +#define CAN_WORD138_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD138_DATA_BYTE_7_MASK (0xFF << CAN_WORD138_DATA_BYTE_7_SHIFT) +#define CAN_WORD138_DATA_BYTE_7(n) (((n) << CAN_WORD138_DATA_BYTE_7_SHIFT) & CAN_WORD138_DATA_BYTE_7_MASK) +#define CAN_WORD138_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD138_DATA_BYTE_6_MASK (0xFF << CAN_WORD138_DATA_BYTE_6_SHIFT) +#define CAN_WORD138_DATA_BYTE_6(n) (((n) << CAN_WORD138_DATA_BYTE_6_SHIFT) & CAN_WORD138_DATA_BYTE_6_MASK) +#define CAN_WORD138_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD138_DATA_BYTE_5_MASK (0xFF << CAN_WORD138_DATA_BYTE_5_SHIFT) +#define CAN_WORD138_DATA_BYTE_5(n) (((n) << CAN_WORD138_DATA_BYTE_5_SHIFT) & CAN_WORD138_DATA_BYTE_5_MASK) +#define CAN_WORD138_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD138_DATA_BYTE_4_MASK (0xFF << CAN_WORD138_DATA_BYTE_4_SHIFT) +#define CAN_WORD138_DATA_BYTE_4(n) (((n) << CAN_WORD138_DATA_BYTE_4_SHIFT) & CAN_WORD138_DATA_BYTE_4_MASK) + +/* Message Buffer 39 CS Register (CS39) */ +#define CAN_CS39_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS39_TIME_STAMP_MASK (0xFFFF << CAN_CS39_TIME_STAMP_SHIFT) +#define CAN_CS39_TIME_STAMP(n) (((n) << CAN_CS39_TIME_STAMP_SHIFT) & CAN_CS39_TIME_STAMP_MASK) +#define CAN_CS39_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS39_DLC_MASK (0xF << CAN_CS39_DLC_SHIFT) +#define CAN_CS39_DLC(n) (((n) << CAN_CS39_DLC_SHIFT) & CAN_CS39_DLC_MASK) +#define CAN_CS39_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS39_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS39_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS39_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS39_CODE_MASK (0xF << CAN_CS39_CODE_SHIFT) +#define CAN_CS39_CODE(n) (((n) << CAN_CS39_CODE_SHIFT) & CAN_CS39_CODE_MASK) +#define CAN_CS39_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS39_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS39_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 39 WORD0 Register (WORD039) */ +#define CAN_WORD039_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD039_DATA_BYTE_3_MASK (0xFF << CAN_WORD039_DATA_BYTE_3_SHIFT) +#define CAN_WORD039_DATA_BYTE_3(n) (((n) << CAN_WORD039_DATA_BYTE_3_SHIFT) & CAN_WORD039_DATA_BYTE_3_MASK) +#define CAN_WORD039_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD039_DATA_BYTE_2_MASK (0xFF << CAN_WORD039_DATA_BYTE_2_SHIFT) +#define CAN_WORD039_DATA_BYTE_2(n) (((n) << CAN_WORD039_DATA_BYTE_2_SHIFT) & CAN_WORD039_DATA_BYTE_2_MASK) +#define CAN_WORD039_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD039_DATA_BYTE_1_MASK (0xFF << CAN_WORD039_DATA_BYTE_1_SHIFT) +#define CAN_WORD039_DATA_BYTE_1(n) (((n) << CAN_WORD039_DATA_BYTE_1_SHIFT) & CAN_WORD039_DATA_BYTE_1_MASK) +#define CAN_WORD039_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD039_DATA_BYTE_0_MASK (0xFF << CAN_WORD039_DATA_BYTE_0_SHIFT) +#define CAN_WORD039_DATA_BYTE_0(n) (((n) << CAN_WORD039_DATA_BYTE_0_SHIFT) & CAN_WORD039_DATA_BYTE_0_MASK) + +/* Message Buffer 39 WORD1 Register (WORD139) */ +#define CAN_WORD139_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD139_DATA_BYTE_7_MASK (0xFF << CAN_WORD139_DATA_BYTE_7_SHIFT) +#define CAN_WORD139_DATA_BYTE_7(n) (((n) << CAN_WORD139_DATA_BYTE_7_SHIFT) & CAN_WORD139_DATA_BYTE_7_MASK) +#define CAN_WORD139_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD139_DATA_BYTE_6_MASK (0xFF << CAN_WORD139_DATA_BYTE_6_SHIFT) +#define CAN_WORD139_DATA_BYTE_6(n) (((n) << CAN_WORD139_DATA_BYTE_6_SHIFT) & CAN_WORD139_DATA_BYTE_6_MASK) +#define CAN_WORD139_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD139_DATA_BYTE_5_MASK (0xFF << CAN_WORD139_DATA_BYTE_5_SHIFT) +#define CAN_WORD139_DATA_BYTE_5(n) (((n) << CAN_WORD139_DATA_BYTE_5_SHIFT) & CAN_WORD139_DATA_BYTE_5_MASK) +#define CAN_WORD139_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD139_DATA_BYTE_4_MASK (0xFF << CAN_WORD139_DATA_BYTE_4_SHIFT) +#define CAN_WORD139_DATA_BYTE_4(n) (((n) << CAN_WORD139_DATA_BYTE_4_SHIFT) & CAN_WORD139_DATA_BYTE_4_MASK) + +/* Message Buffer 40 CS Register (CS40) */ +#define CAN_CS40_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS40_TIME_STAMP_MASK (0xFFFF << CAN_CS40_TIME_STAMP_SHIFT) +#define CAN_CS40_TIME_STAMP(n) (((n) << CAN_CS40_TIME_STAMP_SHIFT) & CAN_CS40_TIME_STAMP_MASK) +#define CAN_CS40_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS40_DLC_MASK (0xF << CAN_CS40_DLC_SHIFT) +#define CAN_CS40_DLC(n) (((n) << CAN_CS40_DLC_SHIFT) & CAN_CS40_DLC_MASK) +#define CAN_CS40_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS40_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS40_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS40_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS40_CODE_MASK (0xF << CAN_CS40_CODE_SHIFT) +#define CAN_CS40_CODE(n) (((n) << CAN_CS40_CODE_SHIFT) & CAN_CS40_CODE_MASK) +#define CAN_CS40_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS40_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS40_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 40 WORD0 Register (WORD040) */ +#define CAN_WORD040_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD040_DATA_BYTE_3_MASK (0xFF << CAN_WORD040_DATA_BYTE_3_SHIFT) +#define CAN_WORD040_DATA_BYTE_3(n) (((n) << CAN_WORD040_DATA_BYTE_3_SHIFT) & CAN_WORD040_DATA_BYTE_3_MASK) +#define CAN_WORD040_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD040_DATA_BYTE_2_MASK (0xFF << CAN_WORD040_DATA_BYTE_2_SHIFT) +#define CAN_WORD040_DATA_BYTE_2(n) (((n) << CAN_WORD040_DATA_BYTE_2_SHIFT) & CAN_WORD040_DATA_BYTE_2_MASK) +#define CAN_WORD040_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD040_DATA_BYTE_1_MASK (0xFF << CAN_WORD040_DATA_BYTE_1_SHIFT) +#define CAN_WORD040_DATA_BYTE_1(n) (((n) << CAN_WORD040_DATA_BYTE_1_SHIFT) & CAN_WORD040_DATA_BYTE_1_MASK) +#define CAN_WORD040_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD040_DATA_BYTE_0_MASK (0xFF << CAN_WORD040_DATA_BYTE_0_SHIFT) +#define CAN_WORD040_DATA_BYTE_0(n) (((n) << CAN_WORD040_DATA_BYTE_0_SHIFT) & CAN_WORD040_DATA_BYTE_0_MASK) + +/* Message Buffer 40 WORD1 Register (WORD140) */ +#define CAN_WORD140_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD140_DATA_BYTE_7_MASK (0xFF << CAN_WORD140_DATA_BYTE_7_SHIFT) +#define CAN_WORD140_DATA_BYTE_7(n) (((n) << CAN_WORD140_DATA_BYTE_7_SHIFT) & CAN_WORD140_DATA_BYTE_7_MASK) +#define CAN_WORD140_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD140_DATA_BYTE_6_MASK (0xFF << CAN_WORD140_DATA_BYTE_6_SHIFT) +#define CAN_WORD140_DATA_BYTE_6(n) (((n) << CAN_WORD140_DATA_BYTE_6_SHIFT) & CAN_WORD140_DATA_BYTE_6_MASK) +#define CAN_WORD140_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD140_DATA_BYTE_5_MASK (0xFF << CAN_WORD140_DATA_BYTE_5_SHIFT) +#define CAN_WORD140_DATA_BYTE_5(n) (((n) << CAN_WORD140_DATA_BYTE_5_SHIFT) & CAN_WORD140_DATA_BYTE_5_MASK) +#define CAN_WORD140_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD140_DATA_BYTE_4_MASK (0xFF << CAN_WORD140_DATA_BYTE_4_SHIFT) +#define CAN_WORD140_DATA_BYTE_4(n) (((n) << CAN_WORD140_DATA_BYTE_4_SHIFT) & CAN_WORD140_DATA_BYTE_4_MASK) + +/* Message Buffer 41 CS Register (CS41) */ +#define CAN_CS41_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS41_TIME_STAMP_MASK (0xFFFF << CAN_CS41_TIME_STAMP_SHIFT) +#define CAN_CS41_TIME_STAMP(n) (((n) << CAN_CS41_TIME_STAMP_SHIFT) & CAN_CS41_TIME_STAMP_MASK) +#define CAN_CS41_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS41_DLC_MASK (0xF << CAN_CS41_DLC_SHIFT) +#define CAN_CS41_DLC(n) (((n) << CAN_CS41_DLC_SHIFT) & CAN_CS41_DLC_MASK) +#define CAN_CS41_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS41_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS41_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS41_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS41_CODE_MASK (0xF << CAN_CS41_CODE_SHIFT) +#define CAN_CS41_CODE(n) (((n) << CAN_CS41_CODE_SHIFT) & CAN_CS41_CODE_MASK) +#define CAN_CS41_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS41_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS41_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 41 WORD0 Register (WORD041) */ +#define CAN_WORD041_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD041_DATA_BYTE_3_MASK (0xFF << CAN_WORD041_DATA_BYTE_3_SHIFT) +#define CAN_WORD041_DATA_BYTE_3(n) (((n) << CAN_WORD041_DATA_BYTE_3_SHIFT) & CAN_WORD041_DATA_BYTE_3_MASK) +#define CAN_WORD041_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD041_DATA_BYTE_2_MASK (0xFF << CAN_WORD041_DATA_BYTE_2_SHIFT) +#define CAN_WORD041_DATA_BYTE_2(n) (((n) << CAN_WORD041_DATA_BYTE_2_SHIFT) & CAN_WORD041_DATA_BYTE_2_MASK) +#define CAN_WORD041_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD041_DATA_BYTE_1_MASK (0xFF << CAN_WORD041_DATA_BYTE_1_SHIFT) +#define CAN_WORD041_DATA_BYTE_1(n) (((n) << CAN_WORD041_DATA_BYTE_1_SHIFT) & CAN_WORD041_DATA_BYTE_1_MASK) +#define CAN_WORD041_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD041_DATA_BYTE_0_MASK (0xFF << CAN_WORD041_DATA_BYTE_0_SHIFT) +#define CAN_WORD041_DATA_BYTE_0(n) (((n) << CAN_WORD041_DATA_BYTE_0_SHIFT) & CAN_WORD041_DATA_BYTE_0_MASK) + +/* Message Buffer 41 WORD1 Register (WORD141) */ +#define CAN_WORD141_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD141_DATA_BYTE_7_MASK (0xFF << CAN_WORD141_DATA_BYTE_7_SHIFT) +#define CAN_WORD141_DATA_BYTE_7(n) (((n) << CAN_WORD141_DATA_BYTE_7_SHIFT) & CAN_WORD141_DATA_BYTE_7_MASK) +#define CAN_WORD141_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD141_DATA_BYTE_6_MASK (0xFF << CAN_WORD141_DATA_BYTE_6_SHIFT) +#define CAN_WORD141_DATA_BYTE_6(n) (((n) << CAN_WORD141_DATA_BYTE_6_SHIFT) & CAN_WORD141_DATA_BYTE_6_MASK) +#define CAN_WORD141_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD141_DATA_BYTE_5_MASK (0xFF << CAN_WORD141_DATA_BYTE_5_SHIFT) +#define CAN_WORD141_DATA_BYTE_5(n) (((n) << CAN_WORD141_DATA_BYTE_5_SHIFT) & CAN_WORD141_DATA_BYTE_5_MASK) +#define CAN_WORD141_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD141_DATA_BYTE_4_MASK (0xFF << CAN_WORD141_DATA_BYTE_4_SHIFT) +#define CAN_WORD141_DATA_BYTE_4(n) (((n) << CAN_WORD141_DATA_BYTE_4_SHIFT) & CAN_WORD141_DATA_BYTE_4_MASK) + +/* Message Buffer 42 CS Register (CS42) */ +#define CAN_CS42_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS42_TIME_STAMP_MASK (0xFFFF << CAN_CS42_TIME_STAMP_SHIFT) +#define CAN_CS42_TIME_STAMP(n) (((n) << CAN_CS42_TIME_STAMP_SHIFT) & CAN_CS42_TIME_STAMP_MASK) +#define CAN_CS42_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS42_DLC_MASK (0xF << CAN_CS42_DLC_SHIFT) +#define CAN_CS42_DLC(n) (((n) << CAN_CS42_DLC_SHIFT) & CAN_CS42_DLC_MASK) +#define CAN_CS42_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS42_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS42_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS42_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS42_CODE_MASK (0xF << CAN_CS42_CODE_SHIFT) +#define CAN_CS42_CODE(n) (((n) << CAN_CS42_CODE_SHIFT) & CAN_CS42_CODE_MASK) +#define CAN_CS42_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS42_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS42_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 42 WORD0 Register (WORD042) */ +#define CAN_WORD042_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD042_DATA_BYTE_3_MASK (0xFF << CAN_WORD042_DATA_BYTE_3_SHIFT) +#define CAN_WORD042_DATA_BYTE_3(n) (((n) << CAN_WORD042_DATA_BYTE_3_SHIFT) & CAN_WORD042_DATA_BYTE_3_MASK) +#define CAN_WORD042_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD042_DATA_BYTE_2_MASK (0xFF << CAN_WORD042_DATA_BYTE_2_SHIFT) +#define CAN_WORD042_DATA_BYTE_2(n) (((n) << CAN_WORD042_DATA_BYTE_2_SHIFT) & CAN_WORD042_DATA_BYTE_2_MASK) +#define CAN_WORD042_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD042_DATA_BYTE_1_MASK (0xFF << CAN_WORD042_DATA_BYTE_1_SHIFT) +#define CAN_WORD042_DATA_BYTE_1(n) (((n) << CAN_WORD042_DATA_BYTE_1_SHIFT) & CAN_WORD042_DATA_BYTE_1_MASK) +#define CAN_WORD042_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD042_DATA_BYTE_0_MASK (0xFF << CAN_WORD042_DATA_BYTE_0_SHIFT) +#define CAN_WORD042_DATA_BYTE_0(n) (((n) << CAN_WORD042_DATA_BYTE_0_SHIFT) & CAN_WORD042_DATA_BYTE_0_MASK) + +/* Message Buffer 42 WORD1 Register (WORD142) */ +#define CAN_WORD142_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD142_DATA_BYTE_7_MASK (0xFF << CAN_WORD142_DATA_BYTE_7_SHIFT) +#define CAN_WORD142_DATA_BYTE_7(n) (((n) << CAN_WORD142_DATA_BYTE_7_SHIFT) & CAN_WORD142_DATA_BYTE_7_MASK) +#define CAN_WORD142_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD142_DATA_BYTE_6_MASK (0xFF << CAN_WORD142_DATA_BYTE_6_SHIFT) +#define CAN_WORD142_DATA_BYTE_6(n) (((n) << CAN_WORD142_DATA_BYTE_6_SHIFT) & CAN_WORD142_DATA_BYTE_6_MASK) +#define CAN_WORD142_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD142_DATA_BYTE_5_MASK (0xFF << CAN_WORD142_DATA_BYTE_5_SHIFT) +#define CAN_WORD142_DATA_BYTE_5(n) (((n) << CAN_WORD142_DATA_BYTE_5_SHIFT) & CAN_WORD142_DATA_BYTE_5_MASK) +#define CAN_WORD142_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD142_DATA_BYTE_4_MASK (0xFF << CAN_WORD142_DATA_BYTE_4_SHIFT) +#define CAN_WORD142_DATA_BYTE_4(n) (((n) << CAN_WORD142_DATA_BYTE_4_SHIFT) & CAN_WORD142_DATA_BYTE_4_MASK) + +/* Message Buffer 43 CS Register (CS43) */ +#define CAN_CS43_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS43_TIME_STAMP_MASK (0xFFFF << CAN_CS43_TIME_STAMP_SHIFT) +#define CAN_CS43_TIME_STAMP(n) (((n) << CAN_CS43_TIME_STAMP_SHIFT) & CAN_CS43_TIME_STAMP_MASK) +#define CAN_CS43_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS43_DLC_MASK (0xF << CAN_CS43_DLC_SHIFT) +#define CAN_CS43_DLC(n) (((n) << CAN_CS43_DLC_SHIFT) & CAN_CS43_DLC_MASK) +#define CAN_CS43_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS43_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS43_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS43_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS43_CODE_MASK (0xF << CAN_CS43_CODE_SHIFT) +#define CAN_CS43_CODE(n) (((n) << CAN_CS43_CODE_SHIFT) & CAN_CS43_CODE_MASK) +#define CAN_CS43_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS43_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS43_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 43 WORD0 Register (WORD043) */ +#define CAN_WORD043_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD043_DATA_BYTE_3_MASK (0xFF << CAN_WORD043_DATA_BYTE_3_SHIFT) +#define CAN_WORD043_DATA_BYTE_3(n) (((n) << CAN_WORD043_DATA_BYTE_3_SHIFT) & CAN_WORD043_DATA_BYTE_3_MASK) +#define CAN_WORD043_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD043_DATA_BYTE_2_MASK (0xFF << CAN_WORD043_DATA_BYTE_2_SHIFT) +#define CAN_WORD043_DATA_BYTE_2(n) (((n) << CAN_WORD043_DATA_BYTE_2_SHIFT) & CAN_WORD043_DATA_BYTE_2_MASK) +#define CAN_WORD043_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD043_DATA_BYTE_1_MASK (0xFF << CAN_WORD043_DATA_BYTE_1_SHIFT) +#define CAN_WORD043_DATA_BYTE_1(n) (((n) << CAN_WORD043_DATA_BYTE_1_SHIFT) & CAN_WORD043_DATA_BYTE_1_MASK) +#define CAN_WORD043_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD043_DATA_BYTE_0_MASK (0xFF << CAN_WORD043_DATA_BYTE_0_SHIFT) +#define CAN_WORD043_DATA_BYTE_0(n) (((n) << CAN_WORD043_DATA_BYTE_0_SHIFT) & CAN_WORD043_DATA_BYTE_0_MASK) + +/* Message Buffer 43 WORD1 Register (WORD143) */ +#define CAN_WORD143_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD143_DATA_BYTE_7_MASK (0xFF << CAN_WORD143_DATA_BYTE_7_SHIFT) +#define CAN_WORD143_DATA_BYTE_7(n) (((n) << CAN_WORD143_DATA_BYTE_7_SHIFT) & CAN_WORD143_DATA_BYTE_7_MASK) +#define CAN_WORD143_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD143_DATA_BYTE_6_MASK (0xFF << CAN_WORD143_DATA_BYTE_6_SHIFT) +#define CAN_WORD143_DATA_BYTE_6(n) (((n) << CAN_WORD143_DATA_BYTE_6_SHIFT) & CAN_WORD143_DATA_BYTE_6_MASK) +#define CAN_WORD143_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD143_DATA_BYTE_5_MASK (0xFF << CAN_WORD143_DATA_BYTE_5_SHIFT) +#define CAN_WORD143_DATA_BYTE_5(n) (((n) << CAN_WORD143_DATA_BYTE_5_SHIFT) & CAN_WORD143_DATA_BYTE_5_MASK) +#define CAN_WORD143_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD143_DATA_BYTE_4_MASK (0xFF << CAN_WORD143_DATA_BYTE_4_SHIFT) +#define CAN_WORD143_DATA_BYTE_4(n) (((n) << CAN_WORD143_DATA_BYTE_4_SHIFT) & CAN_WORD143_DATA_BYTE_4_MASK) + +/* Message Buffer 44 CS Register (CS44) */ +#define CAN_CS44_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS44_TIME_STAMP_MASK (0xFFFF << CAN_CS44_TIME_STAMP_SHIFT) +#define CAN_CS44_TIME_STAMP(n) (((n) << CAN_CS44_TIME_STAMP_SHIFT) & CAN_CS44_TIME_STAMP_MASK) +#define CAN_CS44_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS44_DLC_MASK (0xF << CAN_CS44_DLC_SHIFT) +#define CAN_CS44_DLC(n) (((n) << CAN_CS44_DLC_SHIFT) & CAN_CS44_DLC_MASK) +#define CAN_CS44_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS44_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS44_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS44_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS44_CODE_MASK (0xF << CAN_CS44_CODE_SHIFT) +#define CAN_CS44_CODE(n) (((n) << CAN_CS44_CODE_SHIFT) & CAN_CS44_CODE_MASK) +#define CAN_CS44_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS44_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS44_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 44 WORD0 Register (WORD044) */ +#define CAN_WORD044_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD044_DATA_BYTE_3_MASK (0xFF << CAN_WORD044_DATA_BYTE_3_SHIFT) +#define CAN_WORD044_DATA_BYTE_3(n) (((n) << CAN_WORD044_DATA_BYTE_3_SHIFT) & CAN_WORD044_DATA_BYTE_3_MASK) +#define CAN_WORD044_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD044_DATA_BYTE_2_MASK (0xFF << CAN_WORD044_DATA_BYTE_2_SHIFT) +#define CAN_WORD044_DATA_BYTE_2(n) (((n) << CAN_WORD044_DATA_BYTE_2_SHIFT) & CAN_WORD044_DATA_BYTE_2_MASK) +#define CAN_WORD044_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD044_DATA_BYTE_1_MASK (0xFF << CAN_WORD044_DATA_BYTE_1_SHIFT) +#define CAN_WORD044_DATA_BYTE_1(n) (((n) << CAN_WORD044_DATA_BYTE_1_SHIFT) & CAN_WORD044_DATA_BYTE_1_MASK) +#define CAN_WORD044_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD044_DATA_BYTE_0_MASK (0xFF << CAN_WORD044_DATA_BYTE_0_SHIFT) +#define CAN_WORD044_DATA_BYTE_0(n) (((n) << CAN_WORD044_DATA_BYTE_0_SHIFT) & CAN_WORD044_DATA_BYTE_0_MASK) + +/* Message Buffer 44 WORD1 Register (WORD144) */ +#define CAN_WORD144_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD144_DATA_BYTE_7_MASK (0xFF << CAN_WORD144_DATA_BYTE_7_SHIFT) +#define CAN_WORD144_DATA_BYTE_7(n) (((n) << CAN_WORD144_DATA_BYTE_7_SHIFT) & CAN_WORD144_DATA_BYTE_7_MASK) +#define CAN_WORD144_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD144_DATA_BYTE_6_MASK (0xFF << CAN_WORD144_DATA_BYTE_6_SHIFT) +#define CAN_WORD144_DATA_BYTE_6(n) (((n) << CAN_WORD144_DATA_BYTE_6_SHIFT) & CAN_WORD144_DATA_BYTE_6_MASK) +#define CAN_WORD144_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD144_DATA_BYTE_5_MASK (0xFF << CAN_WORD144_DATA_BYTE_5_SHIFT) +#define CAN_WORD144_DATA_BYTE_5(n) (((n) << CAN_WORD144_DATA_BYTE_5_SHIFT) & CAN_WORD144_DATA_BYTE_5_MASK) +#define CAN_WORD144_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD144_DATA_BYTE_4_MASK (0xFF << CAN_WORD144_DATA_BYTE_4_SHIFT) +#define CAN_WORD144_DATA_BYTE_4(n) (((n) << CAN_WORD144_DATA_BYTE_4_SHIFT) & CAN_WORD144_DATA_BYTE_4_MASK) + +/* Message Buffer 45 CS Register (CS45) */ +#define CAN_CS45_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS45_TIME_STAMP_MASK (0xFFFF << CAN_CS45_TIME_STAMP_SHIFT) +#define CAN_CS45_TIME_STAMP(n) (((n) << CAN_CS45_TIME_STAMP_SHIFT) & CAN_CS45_TIME_STAMP_MASK) +#define CAN_CS45_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS45_DLC_MASK (0xF << CAN_CS45_DLC_SHIFT) +#define CAN_CS45_DLC(n) (((n) << CAN_CS45_DLC_SHIFT) & CAN_CS45_DLC_MASK) +#define CAN_CS45_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS45_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS45_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS45_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS45_CODE_MASK (0xF << CAN_CS45_CODE_SHIFT) +#define CAN_CS45_CODE(n) (((n) << CAN_CS45_CODE_SHIFT) & CAN_CS45_CODE_MASK) +#define CAN_CS45_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS45_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS45_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 45 WORD0 Register (WORD045) */ +#define CAN_WORD045_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD045_DATA_BYTE_3_MASK (0xFF << CAN_WORD045_DATA_BYTE_3_SHIFT) +#define CAN_WORD045_DATA_BYTE_3(n) (((n) << CAN_WORD045_DATA_BYTE_3_SHIFT) & CAN_WORD045_DATA_BYTE_3_MASK) +#define CAN_WORD045_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD045_DATA_BYTE_2_MASK (0xFF << CAN_WORD045_DATA_BYTE_2_SHIFT) +#define CAN_WORD045_DATA_BYTE_2(n) (((n) << CAN_WORD045_DATA_BYTE_2_SHIFT) & CAN_WORD045_DATA_BYTE_2_MASK) +#define CAN_WORD045_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD045_DATA_BYTE_1_MASK (0xFF << CAN_WORD045_DATA_BYTE_1_SHIFT) +#define CAN_WORD045_DATA_BYTE_1(n) (((n) << CAN_WORD045_DATA_BYTE_1_SHIFT) & CAN_WORD045_DATA_BYTE_1_MASK) +#define CAN_WORD045_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD045_DATA_BYTE_0_MASK (0xFF << CAN_WORD045_DATA_BYTE_0_SHIFT) +#define CAN_WORD045_DATA_BYTE_0(n) (((n) << CAN_WORD045_DATA_BYTE_0_SHIFT) & CAN_WORD045_DATA_BYTE_0_MASK) + +/* Message Buffer 45 WORD1 Register (WORD145) */ +#define CAN_WORD145_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD145_DATA_BYTE_7_MASK (0xFF << CAN_WORD145_DATA_BYTE_7_SHIFT) +#define CAN_WORD145_DATA_BYTE_7(n) (((n) << CAN_WORD145_DATA_BYTE_7_SHIFT) & CAN_WORD145_DATA_BYTE_7_MASK) +#define CAN_WORD145_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD145_DATA_BYTE_6_MASK (0xFF << CAN_WORD145_DATA_BYTE_6_SHIFT) +#define CAN_WORD145_DATA_BYTE_6(n) (((n) << CAN_WORD145_DATA_BYTE_6_SHIFT) & CAN_WORD145_DATA_BYTE_6_MASK) +#define CAN_WORD145_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD145_DATA_BYTE_5_MASK (0xFF << CAN_WORD145_DATA_BYTE_5_SHIFT) +#define CAN_WORD145_DATA_BYTE_5(n) (((n) << CAN_WORD145_DATA_BYTE_5_SHIFT) & CAN_WORD145_DATA_BYTE_5_MASK) +#define CAN_WORD145_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD145_DATA_BYTE_4_MASK (0xFF << CAN_WORD145_DATA_BYTE_4_SHIFT) +#define CAN_WORD145_DATA_BYTE_4(n) (((n) << CAN_WORD145_DATA_BYTE_4_SHIFT) & CAN_WORD145_DATA_BYTE_4_MASK) + +/* Message Buffer 46 CS Register (CS46) */ +#define CAN_CS46_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS46_TIME_STAMP_MASK (0xFFFF << CAN_CS46_TIME_STAMP_SHIFT) +#define CAN_CS46_TIME_STAMP(n) (((n) << CAN_CS46_TIME_STAMP_SHIFT) & CAN_CS46_TIME_STAMP_MASK) +#define CAN_CS46_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS46_DLC_MASK (0xF << CAN_CS46_DLC_SHIFT) +#define CAN_CS46_DLC(n) (((n) << CAN_CS46_DLC_SHIFT) & CAN_CS46_DLC_MASK) +#define CAN_CS46_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS46_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS46_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS46_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS46_CODE_MASK (0xF << CAN_CS46_CODE_SHIFT) +#define CAN_CS46_CODE(n) (((n) << CAN_CS46_CODE_SHIFT) & CAN_CS46_CODE_MASK) +#define CAN_CS46_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS46_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS46_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 46 WORD0 Register (WORD046) */ +#define CAN_WORD046_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD046_DATA_BYTE_3_MASK (0xFF << CAN_WORD046_DATA_BYTE_3_SHIFT) +#define CAN_WORD046_DATA_BYTE_3(n) (((n) << CAN_WORD046_DATA_BYTE_3_SHIFT) & CAN_WORD046_DATA_BYTE_3_MASK) +#define CAN_WORD046_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD046_DATA_BYTE_2_MASK (0xFF << CAN_WORD046_DATA_BYTE_2_SHIFT) +#define CAN_WORD046_DATA_BYTE_2(n) (((n) << CAN_WORD046_DATA_BYTE_2_SHIFT) & CAN_WORD046_DATA_BYTE_2_MASK) +#define CAN_WORD046_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD046_DATA_BYTE_1_MASK (0xFF << CAN_WORD046_DATA_BYTE_1_SHIFT) +#define CAN_WORD046_DATA_BYTE_1(n) (((n) << CAN_WORD046_DATA_BYTE_1_SHIFT) & CAN_WORD046_DATA_BYTE_1_MASK) +#define CAN_WORD046_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD046_DATA_BYTE_0_MASK (0xFF << CAN_WORD046_DATA_BYTE_0_SHIFT) +#define CAN_WORD046_DATA_BYTE_0(n) (((n) << CAN_WORD046_DATA_BYTE_0_SHIFT) & CAN_WORD046_DATA_BYTE_0_MASK) + +/* Message Buffer 46 WORD1 Register (WORD146) */ +#define CAN_WORD146_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD146_DATA_BYTE_7_MASK (0xFF << CAN_WORD146_DATA_BYTE_7_SHIFT) +#define CAN_WORD146_DATA_BYTE_7(n) (((n) << CAN_WORD146_DATA_BYTE_7_SHIFT) & CAN_WORD146_DATA_BYTE_7_MASK) +#define CAN_WORD146_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD146_DATA_BYTE_6_MASK (0xFF << CAN_WORD146_DATA_BYTE_6_SHIFT) +#define CAN_WORD146_DATA_BYTE_6(n) (((n) << CAN_WORD146_DATA_BYTE_6_SHIFT) & CAN_WORD146_DATA_BYTE_6_MASK) +#define CAN_WORD146_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD146_DATA_BYTE_5_MASK (0xFF << CAN_WORD146_DATA_BYTE_5_SHIFT) +#define CAN_WORD146_DATA_BYTE_5(n) (((n) << CAN_WORD146_DATA_BYTE_5_SHIFT) & CAN_WORD146_DATA_BYTE_5_MASK) +#define CAN_WORD146_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD146_DATA_BYTE_4_MASK (0xFF << CAN_WORD146_DATA_BYTE_4_SHIFT) +#define CAN_WORD146_DATA_BYTE_4(n) (((n) << CAN_WORD146_DATA_BYTE_4_SHIFT) & CAN_WORD146_DATA_BYTE_4_MASK) + +/* Message Buffer 47 CS Register (CS47) */ +#define CAN_CS47_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS47_TIME_STAMP_MASK (0xFFFF << CAN_CS47_TIME_STAMP_SHIFT) +#define CAN_CS47_TIME_STAMP(n) (((n) << CAN_CS47_TIME_STAMP_SHIFT) & CAN_CS47_TIME_STAMP_MASK) +#define CAN_CS47_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS47_DLC_MASK (0xF << CAN_CS47_DLC_SHIFT) +#define CAN_CS47_DLC(n) (((n) << CAN_CS47_DLC_SHIFT) & CAN_CS47_DLC_MASK) +#define CAN_CS47_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS47_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS47_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS47_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS47_CODE_MASK (0xF << CAN_CS47_CODE_SHIFT) +#define CAN_CS47_CODE(n) (((n) << CAN_CS47_CODE_SHIFT) & CAN_CS47_CODE_MASK) +#define CAN_CS47_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS47_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS47_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 47 WORD0 Register (WORD047) */ +#define CAN_WORD047_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD047_DATA_BYTE_3_MASK (0xFF << CAN_WORD047_DATA_BYTE_3_SHIFT) +#define CAN_WORD047_DATA_BYTE_3(n) (((n) << CAN_WORD047_DATA_BYTE_3_SHIFT) & CAN_WORD047_DATA_BYTE_3_MASK) +#define CAN_WORD047_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD047_DATA_BYTE_2_MASK (0xFF << CAN_WORD047_DATA_BYTE_2_SHIFT) +#define CAN_WORD047_DATA_BYTE_2(n) (((n) << CAN_WORD047_DATA_BYTE_2_SHIFT) & CAN_WORD047_DATA_BYTE_2_MASK) +#define CAN_WORD047_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD047_DATA_BYTE_1_MASK (0xFF << CAN_WORD047_DATA_BYTE_1_SHIFT) +#define CAN_WORD047_DATA_BYTE_1(n) (((n) << CAN_WORD047_DATA_BYTE_1_SHIFT) & CAN_WORD047_DATA_BYTE_1_MASK) +#define CAN_WORD047_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD047_DATA_BYTE_0_MASK (0xFF << CAN_WORD047_DATA_BYTE_0_SHIFT) +#define CAN_WORD047_DATA_BYTE_0(n) (((n) << CAN_WORD047_DATA_BYTE_0_SHIFT) & CAN_WORD047_DATA_BYTE_0_MASK) + +/* Message Buffer 47 WORD1 Register (WORD147) */ +#define CAN_WORD147_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD147_DATA_BYTE_7_MASK (0xFF << CAN_WORD147_DATA_BYTE_7_SHIFT) +#define CAN_WORD147_DATA_BYTE_7(n) (((n) << CAN_WORD147_DATA_BYTE_7_SHIFT) & CAN_WORD147_DATA_BYTE_7_MASK) +#define CAN_WORD147_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD147_DATA_BYTE_6_MASK (0xFF << CAN_WORD147_DATA_BYTE_6_SHIFT) +#define CAN_WORD147_DATA_BYTE_6(n) (((n) << CAN_WORD147_DATA_BYTE_6_SHIFT) & CAN_WORD147_DATA_BYTE_6_MASK) +#define CAN_WORD147_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD147_DATA_BYTE_5_MASK (0xFF << CAN_WORD147_DATA_BYTE_5_SHIFT) +#define CAN_WORD147_DATA_BYTE_5(n) (((n) << CAN_WORD147_DATA_BYTE_5_SHIFT) & CAN_WORD147_DATA_BYTE_5_MASK) +#define CAN_WORD147_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD147_DATA_BYTE_4_MASK (0xFF << CAN_WORD147_DATA_BYTE_4_SHIFT) +#define CAN_WORD147_DATA_BYTE_4(n) (((n) << CAN_WORD147_DATA_BYTE_4_SHIFT) & CAN_WORD147_DATA_BYTE_4_MASK) + +/* Message Buffer 48 CS Register (CS48) */ +#define CAN_CS48_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS48_TIME_STAMP_MASK (0xFFFF << CAN_CS48_TIME_STAMP_SHIFT) +#define CAN_CS48_TIME_STAMP(n) (((n) << CAN_CS48_TIME_STAMP_SHIFT) & CAN_CS48_TIME_STAMP_MASK) +#define CAN_CS48_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS48_DLC_MASK (0xF << CAN_CS48_DLC_SHIFT) +#define CAN_CS48_DLC(n) (((n) << CAN_CS48_DLC_SHIFT) & CAN_CS48_DLC_MASK) +#define CAN_CS48_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS48_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS48_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS48_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS48_CODE_MASK (0xF << CAN_CS48_CODE_SHIFT) +#define CAN_CS48_CODE(n) (((n) << CAN_CS48_CODE_SHIFT) & CAN_CS48_CODE_MASK) +#define CAN_CS48_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS48_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS48_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 48 WORD0 Register (WORD048) */ +#define CAN_WORD048_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD048_DATA_BYTE_3_MASK (0xFF << CAN_WORD048_DATA_BYTE_3_SHIFT) +#define CAN_WORD048_DATA_BYTE_3(n) (((n) << CAN_WORD048_DATA_BYTE_3_SHIFT) & CAN_WORD048_DATA_BYTE_3_MASK) +#define CAN_WORD048_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD048_DATA_BYTE_2_MASK (0xFF << CAN_WORD048_DATA_BYTE_2_SHIFT) +#define CAN_WORD048_DATA_BYTE_2(n) (((n) << CAN_WORD048_DATA_BYTE_2_SHIFT) & CAN_WORD048_DATA_BYTE_2_MASK) +#define CAN_WORD048_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD048_DATA_BYTE_1_MASK (0xFF << CAN_WORD048_DATA_BYTE_1_SHIFT) +#define CAN_WORD048_DATA_BYTE_1(n) (((n) << CAN_WORD048_DATA_BYTE_1_SHIFT) & CAN_WORD048_DATA_BYTE_1_MASK) +#define CAN_WORD048_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD048_DATA_BYTE_0_MASK (0xFF << CAN_WORD048_DATA_BYTE_0_SHIFT) +#define CAN_WORD048_DATA_BYTE_0(n) (((n) << CAN_WORD048_DATA_BYTE_0_SHIFT) & CAN_WORD048_DATA_BYTE_0_MASK) + +/* Message Buffer 48 WORD1 Register (WORD148) */ +#define CAN_WORD148_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD148_DATA_BYTE_7_MASK (0xFF << CAN_WORD148_DATA_BYTE_7_SHIFT) +#define CAN_WORD148_DATA_BYTE_7(n) (((n) << CAN_WORD148_DATA_BYTE_7_SHIFT) & CAN_WORD148_DATA_BYTE_7_MASK) +#define CAN_WORD148_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD148_DATA_BYTE_6_MASK (0xFF << CAN_WORD148_DATA_BYTE_6_SHIFT) +#define CAN_WORD148_DATA_BYTE_6(n) (((n) << CAN_WORD148_DATA_BYTE_6_SHIFT) & CAN_WORD148_DATA_BYTE_6_MASK) +#define CAN_WORD148_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD148_DATA_BYTE_5_MASK (0xFF << CAN_WORD148_DATA_BYTE_5_SHIFT) +#define CAN_WORD148_DATA_BYTE_5(n) (((n) << CAN_WORD148_DATA_BYTE_5_SHIFT) & CAN_WORD148_DATA_BYTE_5_MASK) +#define CAN_WORD148_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD148_DATA_BYTE_4_MASK (0xFF << CAN_WORD148_DATA_BYTE_4_SHIFT) +#define CAN_WORD148_DATA_BYTE_4(n) (((n) << CAN_WORD148_DATA_BYTE_4_SHIFT) & CAN_WORD148_DATA_BYTE_4_MASK) + +/* Message Buffer 49 CS Register (CS49) */ +#define CAN_CS49_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS49_TIME_STAMP_MASK (0xFFFF << CAN_CS49_TIME_STAMP_SHIFT) +#define CAN_CS49_TIME_STAMP(n) (((n) << CAN_CS49_TIME_STAMP_SHIFT) & CAN_CS49_TIME_STAMP_MASK) +#define CAN_CS49_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS49_DLC_MASK (0xF << CAN_CS49_DLC_SHIFT) +#define CAN_CS49_DLC(n) (((n) << CAN_CS49_DLC_SHIFT) & CAN_CS49_DLC_MASK) +#define CAN_CS49_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS49_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS49_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS49_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS49_CODE_MASK (0xF << CAN_CS49_CODE_SHIFT) +#define CAN_CS49_CODE(n) (((n) << CAN_CS49_CODE_SHIFT) & CAN_CS49_CODE_MASK) +#define CAN_CS49_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS49_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS49_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 49 WORD0 Register (WORD049) */ +#define CAN_WORD049_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD049_DATA_BYTE_3_MASK (0xFF << CAN_WORD049_DATA_BYTE_3_SHIFT) +#define CAN_WORD049_DATA_BYTE_3(n) (((n) << CAN_WORD049_DATA_BYTE_3_SHIFT) & CAN_WORD049_DATA_BYTE_3_MASK) +#define CAN_WORD049_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD049_DATA_BYTE_2_MASK (0xFF << CAN_WORD049_DATA_BYTE_2_SHIFT) +#define CAN_WORD049_DATA_BYTE_2(n) (((n) << CAN_WORD049_DATA_BYTE_2_SHIFT) & CAN_WORD049_DATA_BYTE_2_MASK) +#define CAN_WORD049_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD049_DATA_BYTE_1_MASK (0xFF << CAN_WORD049_DATA_BYTE_1_SHIFT) +#define CAN_WORD049_DATA_BYTE_1(n) (((n) << CAN_WORD049_DATA_BYTE_1_SHIFT) & CAN_WORD049_DATA_BYTE_1_MASK) +#define CAN_WORD049_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD049_DATA_BYTE_0_MASK (0xFF << CAN_WORD049_DATA_BYTE_0_SHIFT) +#define CAN_WORD049_DATA_BYTE_0(n) (((n) << CAN_WORD049_DATA_BYTE_0_SHIFT) & CAN_WORD049_DATA_BYTE_0_MASK) + +/* Message Buffer 49 WORD1 Register (WORD149) */ +#define CAN_WORD149_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD149_DATA_BYTE_7_MASK (0xFF << CAN_WORD149_DATA_BYTE_7_SHIFT) +#define CAN_WORD149_DATA_BYTE_7(n) (((n) << CAN_WORD149_DATA_BYTE_7_SHIFT) & CAN_WORD149_DATA_BYTE_7_MASK) +#define CAN_WORD149_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD149_DATA_BYTE_6_MASK (0xFF << CAN_WORD149_DATA_BYTE_6_SHIFT) +#define CAN_WORD149_DATA_BYTE_6(n) (((n) << CAN_WORD149_DATA_BYTE_6_SHIFT) & CAN_WORD149_DATA_BYTE_6_MASK) +#define CAN_WORD149_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD149_DATA_BYTE_5_MASK (0xFF << CAN_WORD149_DATA_BYTE_5_SHIFT) +#define CAN_WORD149_DATA_BYTE_5(n) (((n) << CAN_WORD149_DATA_BYTE_5_SHIFT) & CAN_WORD149_DATA_BYTE_5_MASK) +#define CAN_WORD149_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD149_DATA_BYTE_4_MASK (0xFF << CAN_WORD149_DATA_BYTE_4_SHIFT) +#define CAN_WORD149_DATA_BYTE_4(n) (((n) << CAN_WORD149_DATA_BYTE_4_SHIFT) & CAN_WORD149_DATA_BYTE_4_MASK) + +/* Message Buffer 50 CS Register (CS50) */ +#define CAN_CS50_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS50_TIME_STAMP_MASK (0xFFFF << CAN_CS50_TIME_STAMP_SHIFT) +#define CAN_CS50_TIME_STAMP(n) (((n) << CAN_CS50_TIME_STAMP_SHIFT) & CAN_CS50_TIME_STAMP_MASK) +#define CAN_CS50_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS50_DLC_MASK (0xF << CAN_CS50_DLC_SHIFT) +#define CAN_CS50_DLC(n) (((n) << CAN_CS50_DLC_SHIFT) & CAN_CS50_DLC_MASK) +#define CAN_CS50_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS50_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS50_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS50_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS50_CODE_MASK (0xF << CAN_CS50_CODE_SHIFT) +#define CAN_CS50_CODE(n) (((n) << CAN_CS50_CODE_SHIFT) & CAN_CS50_CODE_MASK) +#define CAN_CS50_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS50_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS50_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 50 WORD0 Register (WORD050) */ +#define CAN_WORD050_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD050_DATA_BYTE_3_MASK (0xFF << CAN_WORD050_DATA_BYTE_3_SHIFT) +#define CAN_WORD050_DATA_BYTE_3(n) (((n) << CAN_WORD050_DATA_BYTE_3_SHIFT) & CAN_WORD050_DATA_BYTE_3_MASK) +#define CAN_WORD050_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD050_DATA_BYTE_2_MASK (0xFF << CAN_WORD050_DATA_BYTE_2_SHIFT) +#define CAN_WORD050_DATA_BYTE_2(n) (((n) << CAN_WORD050_DATA_BYTE_2_SHIFT) & CAN_WORD050_DATA_BYTE_2_MASK) +#define CAN_WORD050_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD050_DATA_BYTE_1_MASK (0xFF << CAN_WORD050_DATA_BYTE_1_SHIFT) +#define CAN_WORD050_DATA_BYTE_1(n) (((n) << CAN_WORD050_DATA_BYTE_1_SHIFT) & CAN_WORD050_DATA_BYTE_1_MASK) +#define CAN_WORD050_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD050_DATA_BYTE_0_MASK (0xFF << CAN_WORD050_DATA_BYTE_0_SHIFT) +#define CAN_WORD050_DATA_BYTE_0(n) (((n) << CAN_WORD050_DATA_BYTE_0_SHIFT) & CAN_WORD050_DATA_BYTE_0_MASK) + +/* Message Buffer 50 WORD1 Register (WORD150) */ +#define CAN_WORD150_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD150_DATA_BYTE_7_MASK (0xFF << CAN_WORD150_DATA_BYTE_7_SHIFT) +#define CAN_WORD150_DATA_BYTE_7(n) (((n) << CAN_WORD150_DATA_BYTE_7_SHIFT) & CAN_WORD150_DATA_BYTE_7_MASK) +#define CAN_WORD150_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD150_DATA_BYTE_6_MASK (0xFF << CAN_WORD150_DATA_BYTE_6_SHIFT) +#define CAN_WORD150_DATA_BYTE_6(n) (((n) << CAN_WORD150_DATA_BYTE_6_SHIFT) & CAN_WORD150_DATA_BYTE_6_MASK) +#define CAN_WORD150_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD150_DATA_BYTE_5_MASK (0xFF << CAN_WORD150_DATA_BYTE_5_SHIFT) +#define CAN_WORD150_DATA_BYTE_5(n) (((n) << CAN_WORD150_DATA_BYTE_5_SHIFT) & CAN_WORD150_DATA_BYTE_5_MASK) +#define CAN_WORD150_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD150_DATA_BYTE_4_MASK (0xFF << CAN_WORD150_DATA_BYTE_4_SHIFT) +#define CAN_WORD150_DATA_BYTE_4(n) (((n) << CAN_WORD150_DATA_BYTE_4_SHIFT) & CAN_WORD150_DATA_BYTE_4_MASK) + +/* Message Buffer 51 CS Register (CS51) */ +#define CAN_CS51_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS51_TIME_STAMP_MASK (0xFFFF << CAN_CS51_TIME_STAMP_SHIFT) +#define CAN_CS51_TIME_STAMP(n) (((n) << CAN_CS51_TIME_STAMP_SHIFT) & CAN_CS51_TIME_STAMP_MASK) +#define CAN_CS51_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS51_DLC_MASK (0xF << CAN_CS51_DLC_SHIFT) +#define CAN_CS51_DLC(n) (((n) << CAN_CS51_DLC_SHIFT) & CAN_CS51_DLC_MASK) +#define CAN_CS51_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS51_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS51_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS51_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS51_CODE_MASK (0xF << CAN_CS51_CODE_SHIFT) +#define CAN_CS51_CODE(n) (((n) << CAN_CS51_CODE_SHIFT) & CAN_CS51_CODE_MASK) +#define CAN_CS51_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS51_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS51_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 51 WORD0 Register (WORD051) */ +#define CAN_WORD051_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD051_DATA_BYTE_3_MASK (0xFF << CAN_WORD051_DATA_BYTE_3_SHIFT) +#define CAN_WORD051_DATA_BYTE_3(n) (((n) << CAN_WORD051_DATA_BYTE_3_SHIFT) & CAN_WORD051_DATA_BYTE_3_MASK) +#define CAN_WORD051_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD051_DATA_BYTE_2_MASK (0xFF << CAN_WORD051_DATA_BYTE_2_SHIFT) +#define CAN_WORD051_DATA_BYTE_2(n) (((n) << CAN_WORD051_DATA_BYTE_2_SHIFT) & CAN_WORD051_DATA_BYTE_2_MASK) +#define CAN_WORD051_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD051_DATA_BYTE_1_MASK (0xFF << CAN_WORD051_DATA_BYTE_1_SHIFT) +#define CAN_WORD051_DATA_BYTE_1(n) (((n) << CAN_WORD051_DATA_BYTE_1_SHIFT) & CAN_WORD051_DATA_BYTE_1_MASK) +#define CAN_WORD051_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD051_DATA_BYTE_0_MASK (0xFF << CAN_WORD051_DATA_BYTE_0_SHIFT) +#define CAN_WORD051_DATA_BYTE_0(n) (((n) << CAN_WORD051_DATA_BYTE_0_SHIFT) & CAN_WORD051_DATA_BYTE_0_MASK) + +/* Message Buffer 51 WORD1 Register (WORD151) */ +#define CAN_WORD151_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD151_DATA_BYTE_7_MASK (0xFF << CAN_WORD151_DATA_BYTE_7_SHIFT) +#define CAN_WORD151_DATA_BYTE_7(n) (((n) << CAN_WORD151_DATA_BYTE_7_SHIFT) & CAN_WORD151_DATA_BYTE_7_MASK) +#define CAN_WORD151_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD151_DATA_BYTE_6_MASK (0xFF << CAN_WORD151_DATA_BYTE_6_SHIFT) +#define CAN_WORD151_DATA_BYTE_6(n) (((n) << CAN_WORD151_DATA_BYTE_6_SHIFT) & CAN_WORD151_DATA_BYTE_6_MASK) +#define CAN_WORD151_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD151_DATA_BYTE_5_MASK (0xFF << CAN_WORD151_DATA_BYTE_5_SHIFT) +#define CAN_WORD151_DATA_BYTE_5(n) (((n) << CAN_WORD151_DATA_BYTE_5_SHIFT) & CAN_WORD151_DATA_BYTE_5_MASK) +#define CAN_WORD151_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD151_DATA_BYTE_4_MASK (0xFF << CAN_WORD151_DATA_BYTE_4_SHIFT) +#define CAN_WORD151_DATA_BYTE_4(n) (((n) << CAN_WORD151_DATA_BYTE_4_SHIFT) & CAN_WORD151_DATA_BYTE_4_MASK) + +/* Message Buffer 52 CS Register (CS52) */ +#define CAN_CS52_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS52_TIME_STAMP_MASK (0xFFFF << CAN_CS52_TIME_STAMP_SHIFT) +#define CAN_CS52_TIME_STAMP(n) (((n) << CAN_CS52_TIME_STAMP_SHIFT) & CAN_CS52_TIME_STAMP_MASK) +#define CAN_CS52_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS52_DLC_MASK (0xF << CAN_CS52_DLC_SHIFT) +#define CAN_CS52_DLC(n) (((n) << CAN_CS52_DLC_SHIFT) & CAN_CS52_DLC_MASK) +#define CAN_CS52_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS52_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS52_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS52_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS52_CODE_MASK (0xF << CAN_CS52_CODE_SHIFT) +#define CAN_CS52_CODE(n) (((n) << CAN_CS52_CODE_SHIFT) & CAN_CS52_CODE_MASK) +#define CAN_CS52_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS52_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS52_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 52 WORD0 Register (WORD052) */ +#define CAN_WORD052_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD052_DATA_BYTE_3_MASK (0xFF << CAN_WORD052_DATA_BYTE_3_SHIFT) +#define CAN_WORD052_DATA_BYTE_3(n) (((n) << CAN_WORD052_DATA_BYTE_3_SHIFT) & CAN_WORD052_DATA_BYTE_3_MASK) +#define CAN_WORD052_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD052_DATA_BYTE_2_MASK (0xFF << CAN_WORD052_DATA_BYTE_2_SHIFT) +#define CAN_WORD052_DATA_BYTE_2(n) (((n) << CAN_WORD052_DATA_BYTE_2_SHIFT) & CAN_WORD052_DATA_BYTE_2_MASK) +#define CAN_WORD052_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD052_DATA_BYTE_1_MASK (0xFF << CAN_WORD052_DATA_BYTE_1_SHIFT) +#define CAN_WORD052_DATA_BYTE_1(n) (((n) << CAN_WORD052_DATA_BYTE_1_SHIFT) & CAN_WORD052_DATA_BYTE_1_MASK) +#define CAN_WORD052_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD052_DATA_BYTE_0_MASK (0xFF << CAN_WORD052_DATA_BYTE_0_SHIFT) +#define CAN_WORD052_DATA_BYTE_0(n) (((n) << CAN_WORD052_DATA_BYTE_0_SHIFT) & CAN_WORD052_DATA_BYTE_0_MASK) + +/* Message Buffer 52 WORD1 Register (WORD152) */ +#define CAN_WORD152_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD152_DATA_BYTE_7_MASK (0xFF << CAN_WORD152_DATA_BYTE_7_SHIFT) +#define CAN_WORD152_DATA_BYTE_7(n) (((n) << CAN_WORD152_DATA_BYTE_7_SHIFT) & CAN_WORD152_DATA_BYTE_7_MASK) +#define CAN_WORD152_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD152_DATA_BYTE_6_MASK (0xFF << CAN_WORD152_DATA_BYTE_6_SHIFT) +#define CAN_WORD152_DATA_BYTE_6(n) (((n) << CAN_WORD152_DATA_BYTE_6_SHIFT) & CAN_WORD152_DATA_BYTE_6_MASK) +#define CAN_WORD152_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD152_DATA_BYTE_5_MASK (0xFF << CAN_WORD152_DATA_BYTE_5_SHIFT) +#define CAN_WORD152_DATA_BYTE_5(n) (((n) << CAN_WORD152_DATA_BYTE_5_SHIFT) & CAN_WORD152_DATA_BYTE_5_MASK) +#define CAN_WORD152_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD152_DATA_BYTE_4_MASK (0xFF << CAN_WORD152_DATA_BYTE_4_SHIFT) +#define CAN_WORD152_DATA_BYTE_4(n) (((n) << CAN_WORD152_DATA_BYTE_4_SHIFT) & CAN_WORD152_DATA_BYTE_4_MASK) + +/* Message Buffer 53 CS Register (CS53) */ +#define CAN_CS53_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS53_TIME_STAMP_MASK (0xFFFF << CAN_CS53_TIME_STAMP_SHIFT) +#define CAN_CS53_TIME_STAMP(n) (((n) << CAN_CS53_TIME_STAMP_SHIFT) & CAN_CS53_TIME_STAMP_MASK) +#define CAN_CS53_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS53_DLC_MASK (0xF << CAN_CS53_DLC_SHIFT) +#define CAN_CS53_DLC(n) (((n) << CAN_CS53_DLC_SHIFT) & CAN_CS53_DLC_MASK) +#define CAN_CS53_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS53_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS53_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS53_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS53_CODE_MASK (0xF << CAN_CS53_CODE_SHIFT) +#define CAN_CS53_CODE(n) (((n) << CAN_CS53_CODE_SHIFT) & CAN_CS53_CODE_MASK) +#define CAN_CS53_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS53_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS53_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 53 WORD0 Register (WORD053) */ +#define CAN_WORD053_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD053_DATA_BYTE_3_MASK (0xFF << CAN_WORD053_DATA_BYTE_3_SHIFT) +#define CAN_WORD053_DATA_BYTE_3(n) (((n) << CAN_WORD053_DATA_BYTE_3_SHIFT) & CAN_WORD053_DATA_BYTE_3_MASK) +#define CAN_WORD053_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD053_DATA_BYTE_2_MASK (0xFF << CAN_WORD053_DATA_BYTE_2_SHIFT) +#define CAN_WORD053_DATA_BYTE_2(n) (((n) << CAN_WORD053_DATA_BYTE_2_SHIFT) & CAN_WORD053_DATA_BYTE_2_MASK) +#define CAN_WORD053_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD053_DATA_BYTE_1_MASK (0xFF << CAN_WORD053_DATA_BYTE_1_SHIFT) +#define CAN_WORD053_DATA_BYTE_1(n) (((n) << CAN_WORD053_DATA_BYTE_1_SHIFT) & CAN_WORD053_DATA_BYTE_1_MASK) +#define CAN_WORD053_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD053_DATA_BYTE_0_MASK (0xFF << CAN_WORD053_DATA_BYTE_0_SHIFT) +#define CAN_WORD053_DATA_BYTE_0(n) (((n) << CAN_WORD053_DATA_BYTE_0_SHIFT) & CAN_WORD053_DATA_BYTE_0_MASK) + +/* Message Buffer 53 WORD1 Register (WORD153) */ +#define CAN_WORD153_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD153_DATA_BYTE_7_MASK (0xFF << CAN_WORD153_DATA_BYTE_7_SHIFT) +#define CAN_WORD153_DATA_BYTE_7(n) (((n) << CAN_WORD153_DATA_BYTE_7_SHIFT) & CAN_WORD153_DATA_BYTE_7_MASK) +#define CAN_WORD153_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD153_DATA_BYTE_6_MASK (0xFF << CAN_WORD153_DATA_BYTE_6_SHIFT) +#define CAN_WORD153_DATA_BYTE_6(n) (((n) << CAN_WORD153_DATA_BYTE_6_SHIFT) & CAN_WORD153_DATA_BYTE_6_MASK) +#define CAN_WORD153_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD153_DATA_BYTE_5_MASK (0xFF << CAN_WORD153_DATA_BYTE_5_SHIFT) +#define CAN_WORD153_DATA_BYTE_5(n) (((n) << CAN_WORD153_DATA_BYTE_5_SHIFT) & CAN_WORD153_DATA_BYTE_5_MASK) +#define CAN_WORD153_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD153_DATA_BYTE_4_MASK (0xFF << CAN_WORD153_DATA_BYTE_4_SHIFT) +#define CAN_WORD153_DATA_BYTE_4(n) (((n) << CAN_WORD153_DATA_BYTE_4_SHIFT) & CAN_WORD153_DATA_BYTE_4_MASK) + +/* Message Buffer 54 CS Register (CS54) */ +#define CAN_CS54_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS54_TIME_STAMP_MASK (0xFFFF << CAN_CS54_TIME_STAMP_SHIFT) +#define CAN_CS54_TIME_STAMP(n) (((n) << CAN_CS54_TIME_STAMP_SHIFT) & CAN_CS54_TIME_STAMP_MASK) +#define CAN_CS54_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS54_DLC_MASK (0xF << CAN_CS54_DLC_SHIFT) +#define CAN_CS54_DLC(n) (((n) << CAN_CS54_DLC_SHIFT) & CAN_CS54_DLC_MASK) +#define CAN_CS54_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS54_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS54_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS54_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS54_CODE_MASK (0xF << CAN_CS54_CODE_SHIFT) +#define CAN_CS54_CODE(n) (((n) << CAN_CS54_CODE_SHIFT) & CAN_CS54_CODE_MASK) +#define CAN_CS54_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS54_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS54_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 54 WORD0 Register (WORD054) */ +#define CAN_WORD054_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD054_DATA_BYTE_3_MASK (0xFF << CAN_WORD054_DATA_BYTE_3_SHIFT) +#define CAN_WORD054_DATA_BYTE_3(n) (((n) << CAN_WORD054_DATA_BYTE_3_SHIFT) & CAN_WORD054_DATA_BYTE_3_MASK) +#define CAN_WORD054_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD054_DATA_BYTE_2_MASK (0xFF << CAN_WORD054_DATA_BYTE_2_SHIFT) +#define CAN_WORD054_DATA_BYTE_2(n) (((n) << CAN_WORD054_DATA_BYTE_2_SHIFT) & CAN_WORD054_DATA_BYTE_2_MASK) +#define CAN_WORD054_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD054_DATA_BYTE_1_MASK (0xFF << CAN_WORD054_DATA_BYTE_1_SHIFT) +#define CAN_WORD054_DATA_BYTE_1(n) (((n) << CAN_WORD054_DATA_BYTE_1_SHIFT) & CAN_WORD054_DATA_BYTE_1_MASK) +#define CAN_WORD054_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD054_DATA_BYTE_0_MASK (0xFF << CAN_WORD054_DATA_BYTE_0_SHIFT) +#define CAN_WORD054_DATA_BYTE_0(n) (((n) << CAN_WORD054_DATA_BYTE_0_SHIFT) & CAN_WORD054_DATA_BYTE_0_MASK) + +/* Message Buffer 54 WORD1 Register (WORD154) */ +#define CAN_WORD154_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD154_DATA_BYTE_7_MASK (0xFF << CAN_WORD154_DATA_BYTE_7_SHIFT) +#define CAN_WORD154_DATA_BYTE_7(n) (((n) << CAN_WORD154_DATA_BYTE_7_SHIFT) & CAN_WORD154_DATA_BYTE_7_MASK) +#define CAN_WORD154_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD154_DATA_BYTE_6_MASK (0xFF << CAN_WORD154_DATA_BYTE_6_SHIFT) +#define CAN_WORD154_DATA_BYTE_6(n) (((n) << CAN_WORD154_DATA_BYTE_6_SHIFT) & CAN_WORD154_DATA_BYTE_6_MASK) +#define CAN_WORD154_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD154_DATA_BYTE_5_MASK (0xFF << CAN_WORD154_DATA_BYTE_5_SHIFT) +#define CAN_WORD154_DATA_BYTE_5(n) (((n) << CAN_WORD154_DATA_BYTE_5_SHIFT) & CAN_WORD154_DATA_BYTE_5_MASK) +#define CAN_WORD154_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD154_DATA_BYTE_4_MASK (0xFF << CAN_WORD154_DATA_BYTE_4_SHIFT) +#define CAN_WORD154_DATA_BYTE_4(n) (((n) << CAN_WORD154_DATA_BYTE_4_SHIFT) & CAN_WORD154_DATA_BYTE_4_MASK) + +/* Message Buffer 55 CS Register (CS55) */ +#define CAN_CS55_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS55_TIME_STAMP_MASK (0xFFFF << CAN_CS55_TIME_STAMP_SHIFT) +#define CAN_CS55_TIME_STAMP(n) (((n) << CAN_CS55_TIME_STAMP_SHIFT) & CAN_CS55_TIME_STAMP_MASK) +#define CAN_CS55_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS55_DLC_MASK (0xF << CAN_CS55_DLC_SHIFT) +#define CAN_CS55_DLC(n) (((n) << CAN_CS55_DLC_SHIFT) & CAN_CS55_DLC_MASK) +#define CAN_CS55_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS55_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS55_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS55_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS55_CODE_MASK (0xF << CAN_CS55_CODE_SHIFT) +#define CAN_CS55_CODE(n) (((n) << CAN_CS55_CODE_SHIFT) & CAN_CS55_CODE_MASK) +#define CAN_CS55_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS55_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS55_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 55 WORD0 Register (WORD055) */ +#define CAN_WORD055_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD055_DATA_BYTE_3_MASK (0xFF << CAN_WORD055_DATA_BYTE_3_SHIFT) +#define CAN_WORD055_DATA_BYTE_3(n) (((n) << CAN_WORD055_DATA_BYTE_3_SHIFT) & CAN_WORD055_DATA_BYTE_3_MASK) +#define CAN_WORD055_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD055_DATA_BYTE_2_MASK (0xFF << CAN_WORD055_DATA_BYTE_2_SHIFT) +#define CAN_WORD055_DATA_BYTE_2(n) (((n) << CAN_WORD055_DATA_BYTE_2_SHIFT) & CAN_WORD055_DATA_BYTE_2_MASK) +#define CAN_WORD055_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD055_DATA_BYTE_1_MASK (0xFF << CAN_WORD055_DATA_BYTE_1_SHIFT) +#define CAN_WORD055_DATA_BYTE_1(n) (((n) << CAN_WORD055_DATA_BYTE_1_SHIFT) & CAN_WORD055_DATA_BYTE_1_MASK) +#define CAN_WORD055_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD055_DATA_BYTE_0_MASK (0xFF << CAN_WORD055_DATA_BYTE_0_SHIFT) +#define CAN_WORD055_DATA_BYTE_0(n) (((n) << CAN_WORD055_DATA_BYTE_0_SHIFT) & CAN_WORD055_DATA_BYTE_0_MASK) + +/* Message Buffer 55 WORD1 Register (WORD155) */ +#define CAN_WORD155_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD155_DATA_BYTE_7_MASK (0xFF << CAN_WORD155_DATA_BYTE_7_SHIFT) +#define CAN_WORD155_DATA_BYTE_7(n) (((n) << CAN_WORD155_DATA_BYTE_7_SHIFT) & CAN_WORD155_DATA_BYTE_7_MASK) +#define CAN_WORD155_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD155_DATA_BYTE_6_MASK (0xFF << CAN_WORD155_DATA_BYTE_6_SHIFT) +#define CAN_WORD155_DATA_BYTE_6(n) (((n) << CAN_WORD155_DATA_BYTE_6_SHIFT) & CAN_WORD155_DATA_BYTE_6_MASK) +#define CAN_WORD155_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD155_DATA_BYTE_5_MASK (0xFF << CAN_WORD155_DATA_BYTE_5_SHIFT) +#define CAN_WORD155_DATA_BYTE_5(n) (((n) << CAN_WORD155_DATA_BYTE_5_SHIFT) & CAN_WORD155_DATA_BYTE_5_MASK) +#define CAN_WORD155_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD155_DATA_BYTE_4_MASK (0xFF << CAN_WORD155_DATA_BYTE_4_SHIFT) +#define CAN_WORD155_DATA_BYTE_4(n) (((n) << CAN_WORD155_DATA_BYTE_4_SHIFT) & CAN_WORD155_DATA_BYTE_4_MASK) + +/* Message Buffer 56 CS Register (CS56) */ +#define CAN_CS56_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS56_TIME_STAMP_MASK (0xFFFF << CAN_CS56_TIME_STAMP_SHIFT) +#define CAN_CS56_TIME_STAMP(n) (((n) << CAN_CS56_TIME_STAMP_SHIFT) & CAN_CS56_TIME_STAMP_MASK) +#define CAN_CS56_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS56_DLC_MASK (0xF << CAN_CS56_DLC_SHIFT) +#define CAN_CS56_DLC(n) (((n) << CAN_CS56_DLC_SHIFT) & CAN_CS56_DLC_MASK) +#define CAN_CS56_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS56_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS56_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS56_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS56_CODE_MASK (0xF << CAN_CS56_CODE_SHIFT) +#define CAN_CS56_CODE(n) (((n) << CAN_CS56_CODE_SHIFT) & CAN_CS56_CODE_MASK) +#define CAN_CS56_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS56_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS56_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 56 WORD0 Register (WORD056) */ +#define CAN_WORD056_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD056_DATA_BYTE_3_MASK (0xFF << CAN_WORD056_DATA_BYTE_3_SHIFT) +#define CAN_WORD056_DATA_BYTE_3(n) (((n) << CAN_WORD056_DATA_BYTE_3_SHIFT) & CAN_WORD056_DATA_BYTE_3_MASK) +#define CAN_WORD056_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD056_DATA_BYTE_2_MASK (0xFF << CAN_WORD056_DATA_BYTE_2_SHIFT) +#define CAN_WORD056_DATA_BYTE_2(n) (((n) << CAN_WORD056_DATA_BYTE_2_SHIFT) & CAN_WORD056_DATA_BYTE_2_MASK) +#define CAN_WORD056_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD056_DATA_BYTE_1_MASK (0xFF << CAN_WORD056_DATA_BYTE_1_SHIFT) +#define CAN_WORD056_DATA_BYTE_1(n) (((n) << CAN_WORD056_DATA_BYTE_1_SHIFT) & CAN_WORD056_DATA_BYTE_1_MASK) +#define CAN_WORD056_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD056_DATA_BYTE_0_MASK (0xFF << CAN_WORD056_DATA_BYTE_0_SHIFT) +#define CAN_WORD056_DATA_BYTE_0(n) (((n) << CAN_WORD056_DATA_BYTE_0_SHIFT) & CAN_WORD056_DATA_BYTE_0_MASK) + +/* Message Buffer 56 WORD1 Register (WORD156) */ +#define CAN_WORD156_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD156_DATA_BYTE_7_MASK (0xFF << CAN_WORD156_DATA_BYTE_7_SHIFT) +#define CAN_WORD156_DATA_BYTE_7(n) (((n) << CAN_WORD156_DATA_BYTE_7_SHIFT) & CAN_WORD156_DATA_BYTE_7_MASK) +#define CAN_WORD156_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD156_DATA_BYTE_6_MASK (0xFF << CAN_WORD156_DATA_BYTE_6_SHIFT) +#define CAN_WORD156_DATA_BYTE_6(n) (((n) << CAN_WORD156_DATA_BYTE_6_SHIFT) & CAN_WORD156_DATA_BYTE_6_MASK) +#define CAN_WORD156_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD156_DATA_BYTE_5_MASK (0xFF << CAN_WORD156_DATA_BYTE_5_SHIFT) +#define CAN_WORD156_DATA_BYTE_5(n) (((n) << CAN_WORD156_DATA_BYTE_5_SHIFT) & CAN_WORD156_DATA_BYTE_5_MASK) +#define CAN_WORD156_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD156_DATA_BYTE_4_MASK (0xFF << CAN_WORD156_DATA_BYTE_4_SHIFT) +#define CAN_WORD156_DATA_BYTE_4(n) (((n) << CAN_WORD156_DATA_BYTE_4_SHIFT) & CAN_WORD156_DATA_BYTE_4_MASK) + +/* Message Buffer 57 CS Register (CS57) */ +#define CAN_CS57_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS57_TIME_STAMP_MASK (0xFFFF << CAN_CS57_TIME_STAMP_SHIFT) +#define CAN_CS57_TIME_STAMP(n) (((n) << CAN_CS57_TIME_STAMP_SHIFT) & CAN_CS57_TIME_STAMP_MASK) +#define CAN_CS57_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS57_DLC_MASK (0xF << CAN_CS57_DLC_SHIFT) +#define CAN_CS57_DLC(n) (((n) << CAN_CS57_DLC_SHIFT) & CAN_CS57_DLC_MASK) +#define CAN_CS57_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS57_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS57_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS57_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS57_CODE_MASK (0xF << CAN_CS57_CODE_SHIFT) +#define CAN_CS57_CODE(n) (((n) << CAN_CS57_CODE_SHIFT) & CAN_CS57_CODE_MASK) +#define CAN_CS57_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS57_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS57_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 57 WORD0 Register (WORD057) */ +#define CAN_WORD057_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD057_DATA_BYTE_3_MASK (0xFF << CAN_WORD057_DATA_BYTE_3_SHIFT) +#define CAN_WORD057_DATA_BYTE_3(n) (((n) << CAN_WORD057_DATA_BYTE_3_SHIFT) & CAN_WORD057_DATA_BYTE_3_MASK) +#define CAN_WORD057_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD057_DATA_BYTE_2_MASK (0xFF << CAN_WORD057_DATA_BYTE_2_SHIFT) +#define CAN_WORD057_DATA_BYTE_2(n) (((n) << CAN_WORD057_DATA_BYTE_2_SHIFT) & CAN_WORD057_DATA_BYTE_2_MASK) +#define CAN_WORD057_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD057_DATA_BYTE_1_MASK (0xFF << CAN_WORD057_DATA_BYTE_1_SHIFT) +#define CAN_WORD057_DATA_BYTE_1(n) (((n) << CAN_WORD057_DATA_BYTE_1_SHIFT) & CAN_WORD057_DATA_BYTE_1_MASK) +#define CAN_WORD057_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD057_DATA_BYTE_0_MASK (0xFF << CAN_WORD057_DATA_BYTE_0_SHIFT) +#define CAN_WORD057_DATA_BYTE_0(n) (((n) << CAN_WORD057_DATA_BYTE_0_SHIFT) & CAN_WORD057_DATA_BYTE_0_MASK) + +/* Message Buffer 57 WORD1 Register (WORD157) */ +#define CAN_WORD157_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD157_DATA_BYTE_7_MASK (0xFF << CAN_WORD157_DATA_BYTE_7_SHIFT) +#define CAN_WORD157_DATA_BYTE_7(n) (((n) << CAN_WORD157_DATA_BYTE_7_SHIFT) & CAN_WORD157_DATA_BYTE_7_MASK) +#define CAN_WORD157_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD157_DATA_BYTE_6_MASK (0xFF << CAN_WORD157_DATA_BYTE_6_SHIFT) +#define CAN_WORD157_DATA_BYTE_6(n) (((n) << CAN_WORD157_DATA_BYTE_6_SHIFT) & CAN_WORD157_DATA_BYTE_6_MASK) +#define CAN_WORD157_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD157_DATA_BYTE_5_MASK (0xFF << CAN_WORD157_DATA_BYTE_5_SHIFT) +#define CAN_WORD157_DATA_BYTE_5(n) (((n) << CAN_WORD157_DATA_BYTE_5_SHIFT) & CAN_WORD157_DATA_BYTE_5_MASK) +#define CAN_WORD157_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD157_DATA_BYTE_4_MASK (0xFF << CAN_WORD157_DATA_BYTE_4_SHIFT) +#define CAN_WORD157_DATA_BYTE_4(n) (((n) << CAN_WORD157_DATA_BYTE_4_SHIFT) & CAN_WORD157_DATA_BYTE_4_MASK) + +/* Message Buffer 58 CS Register (CS58) */ +#define CAN_CS58_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS58_TIME_STAMP_MASK (0xFFFF << CAN_CS58_TIME_STAMP_SHIFT) +#define CAN_CS58_TIME_STAMP(n) (((n) << CAN_CS58_TIME_STAMP_SHIFT) & CAN_CS58_TIME_STAMP_MASK) +#define CAN_CS58_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS58_DLC_MASK (0xF << CAN_CS58_DLC_SHIFT) +#define CAN_CS58_DLC(n) (((n) << CAN_CS58_DLC_SHIFT) & CAN_CS58_DLC_MASK) +#define CAN_CS58_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS58_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS58_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS58_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS58_CODE_MASK (0xF << CAN_CS58_CODE_SHIFT) +#define CAN_CS58_CODE(n) (((n) << CAN_CS58_CODE_SHIFT) & CAN_CS58_CODE_MASK) +#define CAN_CS58_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS58_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS58_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 58 WORD0 Register (WORD058) */ +#define CAN_WORD058_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD058_DATA_BYTE_3_MASK (0xFF << CAN_WORD058_DATA_BYTE_3_SHIFT) +#define CAN_WORD058_DATA_BYTE_3(n) (((n) << CAN_WORD058_DATA_BYTE_3_SHIFT) & CAN_WORD058_DATA_BYTE_3_MASK) +#define CAN_WORD058_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD058_DATA_BYTE_2_MASK (0xFF << CAN_WORD058_DATA_BYTE_2_SHIFT) +#define CAN_WORD058_DATA_BYTE_2(n) (((n) << CAN_WORD058_DATA_BYTE_2_SHIFT) & CAN_WORD058_DATA_BYTE_2_MASK) +#define CAN_WORD058_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD058_DATA_BYTE_1_MASK (0xFF << CAN_WORD058_DATA_BYTE_1_SHIFT) +#define CAN_WORD058_DATA_BYTE_1(n) (((n) << CAN_WORD058_DATA_BYTE_1_SHIFT) & CAN_WORD058_DATA_BYTE_1_MASK) +#define CAN_WORD058_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD058_DATA_BYTE_0_MASK (0xFF << CAN_WORD058_DATA_BYTE_0_SHIFT) +#define CAN_WORD058_DATA_BYTE_0(n) (((n) << CAN_WORD058_DATA_BYTE_0_SHIFT) & CAN_WORD058_DATA_BYTE_0_MASK) + +/* Message Buffer 58 WORD1 Register (WORD158) */ +#define CAN_WORD158_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD158_DATA_BYTE_7_MASK (0xFF << CAN_WORD158_DATA_BYTE_7_SHIFT) +#define CAN_WORD158_DATA_BYTE_7(n) (((n) << CAN_WORD158_DATA_BYTE_7_SHIFT) & CAN_WORD158_DATA_BYTE_7_MASK) +#define CAN_WORD158_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD158_DATA_BYTE_6_MASK (0xFF << CAN_WORD158_DATA_BYTE_6_SHIFT) +#define CAN_WORD158_DATA_BYTE_6(n) (((n) << CAN_WORD158_DATA_BYTE_6_SHIFT) & CAN_WORD158_DATA_BYTE_6_MASK) +#define CAN_WORD158_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD158_DATA_BYTE_5_MASK (0xFF << CAN_WORD158_DATA_BYTE_5_SHIFT) +#define CAN_WORD158_DATA_BYTE_5(n) (((n) << CAN_WORD158_DATA_BYTE_5_SHIFT) & CAN_WORD158_DATA_BYTE_5_MASK) +#define CAN_WORD158_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD158_DATA_BYTE_4_MASK (0xFF << CAN_WORD158_DATA_BYTE_4_SHIFT) +#define CAN_WORD158_DATA_BYTE_4(n) (((n) << CAN_WORD158_DATA_BYTE_4_SHIFT) & CAN_WORD158_DATA_BYTE_4_MASK) + +/* Message Buffer 59 CS Register (CS59) */ +#define CAN_CS59_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS59_TIME_STAMP_MASK (0xFFFF << CAN_CS59_TIME_STAMP_SHIFT) +#define CAN_CS59_TIME_STAMP(n) (((n) << CAN_CS59_TIME_STAMP_SHIFT) & CAN_CS59_TIME_STAMP_MASK) +#define CAN_CS59_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS59_DLC_MASK (0xF << CAN_CS59_DLC_SHIFT) +#define CAN_CS59_DLC(n) (((n) << CAN_CS59_DLC_SHIFT) & CAN_CS59_DLC_MASK) +#define CAN_CS59_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS59_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS59_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS59_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS59_CODE_MASK (0xF << CAN_CS59_CODE_SHIFT) +#define CAN_CS59_CODE(n) (((n) << CAN_CS59_CODE_SHIFT) & CAN_CS59_CODE_MASK) +#define CAN_CS59_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS59_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS59_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 59 WORD0 Register (WORD059) */ +#define CAN_WORD059_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD059_DATA_BYTE_3_MASK (0xFF << CAN_WORD059_DATA_BYTE_3_SHIFT) +#define CAN_WORD059_DATA_BYTE_3(n) (((n) << CAN_WORD059_DATA_BYTE_3_SHIFT) & CAN_WORD059_DATA_BYTE_3_MASK) +#define CAN_WORD059_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD059_DATA_BYTE_2_MASK (0xFF << CAN_WORD059_DATA_BYTE_2_SHIFT) +#define CAN_WORD059_DATA_BYTE_2(n) (((n) << CAN_WORD059_DATA_BYTE_2_SHIFT) & CAN_WORD059_DATA_BYTE_2_MASK) +#define CAN_WORD059_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD059_DATA_BYTE_1_MASK (0xFF << CAN_WORD059_DATA_BYTE_1_SHIFT) +#define CAN_WORD059_DATA_BYTE_1(n) (((n) << CAN_WORD059_DATA_BYTE_1_SHIFT) & CAN_WORD059_DATA_BYTE_1_MASK) +#define CAN_WORD059_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD059_DATA_BYTE_0_MASK (0xFF << CAN_WORD059_DATA_BYTE_0_SHIFT) +#define CAN_WORD059_DATA_BYTE_0(n) (((n) << CAN_WORD059_DATA_BYTE_0_SHIFT) & CAN_WORD059_DATA_BYTE_0_MASK) + +/* Message Buffer 59 WORD1 Register (WORD159) */ +#define CAN_WORD159_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD159_DATA_BYTE_7_MASK (0xFF << CAN_WORD159_DATA_BYTE_7_SHIFT) +#define CAN_WORD159_DATA_BYTE_7(n) (((n) << CAN_WORD159_DATA_BYTE_7_SHIFT) & CAN_WORD159_DATA_BYTE_7_MASK) +#define CAN_WORD159_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD159_DATA_BYTE_6_MASK (0xFF << CAN_WORD159_DATA_BYTE_6_SHIFT) +#define CAN_WORD159_DATA_BYTE_6(n) (((n) << CAN_WORD159_DATA_BYTE_6_SHIFT) & CAN_WORD159_DATA_BYTE_6_MASK) +#define CAN_WORD159_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD159_DATA_BYTE_5_MASK (0xFF << CAN_WORD159_DATA_BYTE_5_SHIFT) +#define CAN_WORD159_DATA_BYTE_5(n) (((n) << CAN_WORD159_DATA_BYTE_5_SHIFT) & CAN_WORD159_DATA_BYTE_5_MASK) +#define CAN_WORD159_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD159_DATA_BYTE_4_MASK (0xFF << CAN_WORD159_DATA_BYTE_4_SHIFT) +#define CAN_WORD159_DATA_BYTE_4(n) (((n) << CAN_WORD159_DATA_BYTE_4_SHIFT) & CAN_WORD159_DATA_BYTE_4_MASK) + +/* Message Buffer 60 CS Register (CS60) */ +#define CAN_CS60_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS60_TIME_STAMP_MASK (0xFFFF << CAN_CS60_TIME_STAMP_SHIFT) +#define CAN_CS60_TIME_STAMP(n) (((n) << CAN_CS60_TIME_STAMP_SHIFT) & CAN_CS60_TIME_STAMP_MASK) +#define CAN_CS60_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS60_DLC_MASK (0xF << CAN_CS60_DLC_SHIFT) +#define CAN_CS60_DLC(n) (((n) << CAN_CS60_DLC_SHIFT) & CAN_CS60_DLC_MASK) +#define CAN_CS60_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS60_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS60_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS60_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS60_CODE_MASK (0xF << CAN_CS60_CODE_SHIFT) +#define CAN_CS60_CODE(n) (((n) << CAN_CS60_CODE_SHIFT) & CAN_CS60_CODE_MASK) +#define CAN_CS60_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS60_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS60_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 60 WORD0 Register (WORD060) */ +#define CAN_WORD060_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD060_DATA_BYTE_3_MASK (0xFF << CAN_WORD060_DATA_BYTE_3_SHIFT) +#define CAN_WORD060_DATA_BYTE_3(n) (((n) << CAN_WORD060_DATA_BYTE_3_SHIFT) & CAN_WORD060_DATA_BYTE_3_MASK) +#define CAN_WORD060_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD060_DATA_BYTE_2_MASK (0xFF << CAN_WORD060_DATA_BYTE_2_SHIFT) +#define CAN_WORD060_DATA_BYTE_2(n) (((n) << CAN_WORD060_DATA_BYTE_2_SHIFT) & CAN_WORD060_DATA_BYTE_2_MASK) +#define CAN_WORD060_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD060_DATA_BYTE_1_MASK (0xFF << CAN_WORD060_DATA_BYTE_1_SHIFT) +#define CAN_WORD060_DATA_BYTE_1(n) (((n) << CAN_WORD060_DATA_BYTE_1_SHIFT) & CAN_WORD060_DATA_BYTE_1_MASK) +#define CAN_WORD060_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD060_DATA_BYTE_0_MASK (0xFF << CAN_WORD060_DATA_BYTE_0_SHIFT) +#define CAN_WORD060_DATA_BYTE_0(n) (((n) << CAN_WORD060_DATA_BYTE_0_SHIFT) & CAN_WORD060_DATA_BYTE_0_MASK) + +/* Message Buffer 60 WORD1 Register (WORD160) */ +#define CAN_WORD160_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD160_DATA_BYTE_7_MASK (0xFF << CAN_WORD160_DATA_BYTE_7_SHIFT) +#define CAN_WORD160_DATA_BYTE_7(n) (((n) << CAN_WORD160_DATA_BYTE_7_SHIFT) & CAN_WORD160_DATA_BYTE_7_MASK) +#define CAN_WORD160_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD160_DATA_BYTE_6_MASK (0xFF << CAN_WORD160_DATA_BYTE_6_SHIFT) +#define CAN_WORD160_DATA_BYTE_6(n) (((n) << CAN_WORD160_DATA_BYTE_6_SHIFT) & CAN_WORD160_DATA_BYTE_6_MASK) +#define CAN_WORD160_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD160_DATA_BYTE_5_MASK (0xFF << CAN_WORD160_DATA_BYTE_5_SHIFT) +#define CAN_WORD160_DATA_BYTE_5(n) (((n) << CAN_WORD160_DATA_BYTE_5_SHIFT) & CAN_WORD160_DATA_BYTE_5_MASK) +#define CAN_WORD160_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD160_DATA_BYTE_4_MASK (0xFF << CAN_WORD160_DATA_BYTE_4_SHIFT) +#define CAN_WORD160_DATA_BYTE_4(n) (((n) << CAN_WORD160_DATA_BYTE_4_SHIFT) & CAN_WORD160_DATA_BYTE_4_MASK) + +/* Message Buffer 61 CS Register (CS61) */ +#define CAN_CS61_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS61_TIME_STAMP_MASK (0xFFFF << CAN_CS61_TIME_STAMP_SHIFT) +#define CAN_CS61_TIME_STAMP(n) (((n) << CAN_CS61_TIME_STAMP_SHIFT) & CAN_CS61_TIME_STAMP_MASK) +#define CAN_CS61_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS61_DLC_MASK (0xF << CAN_CS61_DLC_SHIFT) +#define CAN_CS61_DLC(n) (((n) << CAN_CS61_DLC_SHIFT) & CAN_CS61_DLC_MASK) +#define CAN_CS61_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS61_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS61_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS61_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS61_CODE_MASK (0xF << CAN_CS61_CODE_SHIFT) +#define CAN_CS61_CODE(n) (((n) << CAN_CS61_CODE_SHIFT) & CAN_CS61_CODE_MASK) +#define CAN_CS61_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS61_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS61_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 61 WORD0 Register (WORD061) */ +#define CAN_WORD061_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD061_DATA_BYTE_3_MASK (0xFF << CAN_WORD061_DATA_BYTE_3_SHIFT) +#define CAN_WORD061_DATA_BYTE_3(n) (((n) << CAN_WORD061_DATA_BYTE_3_SHIFT) & CAN_WORD061_DATA_BYTE_3_MASK) +#define CAN_WORD061_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD061_DATA_BYTE_2_MASK (0xFF << CAN_WORD061_DATA_BYTE_2_SHIFT) +#define CAN_WORD061_DATA_BYTE_2(n) (((n) << CAN_WORD061_DATA_BYTE_2_SHIFT) & CAN_WORD061_DATA_BYTE_2_MASK) +#define CAN_WORD061_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD061_DATA_BYTE_1_MASK (0xFF << CAN_WORD061_DATA_BYTE_1_SHIFT) +#define CAN_WORD061_DATA_BYTE_1(n) (((n) << CAN_WORD061_DATA_BYTE_1_SHIFT) & CAN_WORD061_DATA_BYTE_1_MASK) +#define CAN_WORD061_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD061_DATA_BYTE_0_MASK (0xFF << CAN_WORD061_DATA_BYTE_0_SHIFT) +#define CAN_WORD061_DATA_BYTE_0(n) (((n) << CAN_WORD061_DATA_BYTE_0_SHIFT) & CAN_WORD061_DATA_BYTE_0_MASK) + +/* Message Buffer 61 WORD1 Register (WORD161) */ +#define CAN_WORD161_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD161_DATA_BYTE_7_MASK (0xFF << CAN_WORD161_DATA_BYTE_7_SHIFT) +#define CAN_WORD161_DATA_BYTE_7(n) (((n) << CAN_WORD161_DATA_BYTE_7_SHIFT) & CAN_WORD161_DATA_BYTE_7_MASK) +#define CAN_WORD161_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD161_DATA_BYTE_6_MASK (0xFF << CAN_WORD161_DATA_BYTE_6_SHIFT) +#define CAN_WORD161_DATA_BYTE_6(n) (((n) << CAN_WORD161_DATA_BYTE_6_SHIFT) & CAN_WORD161_DATA_BYTE_6_MASK) +#define CAN_WORD161_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD161_DATA_BYTE_5_MASK (0xFF << CAN_WORD161_DATA_BYTE_5_SHIFT) +#define CAN_WORD161_DATA_BYTE_5(n) (((n) << CAN_WORD161_DATA_BYTE_5_SHIFT) & CAN_WORD161_DATA_BYTE_5_MASK) +#define CAN_WORD161_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD161_DATA_BYTE_4_MASK (0xFF << CAN_WORD161_DATA_BYTE_4_SHIFT) +#define CAN_WORD161_DATA_BYTE_4(n) (((n) << CAN_WORD161_DATA_BYTE_4_SHIFT) & CAN_WORD161_DATA_BYTE_4_MASK) + +/* Message Buffer 62 CS Register (CS62) */ +#define CAN_CS62_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS62_TIME_STAMP_MASK (0xFFFF << CAN_CS62_TIME_STAMP_SHIFT) +#define CAN_CS62_TIME_STAMP(n) (((n) << CAN_CS62_TIME_STAMP_SHIFT) & CAN_CS62_TIME_STAMP_MASK) +#define CAN_CS62_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS62_DLC_MASK (0xF << CAN_CS62_DLC_SHIFT) +#define CAN_CS62_DLC(n) (((n) << CAN_CS62_DLC_SHIFT) & CAN_CS62_DLC_MASK) +#define CAN_CS62_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS62_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS62_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS62_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS62_CODE_MASK (0xF << CAN_CS62_CODE_SHIFT) +#define CAN_CS62_CODE(n) (((n) << CAN_CS62_CODE_SHIFT) & CAN_CS62_CODE_MASK) +#define CAN_CS62_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS62_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS62_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 62 WORD0 Register (WORD062) */ +#define CAN_WORD062_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD062_DATA_BYTE_3_MASK (0xFF << CAN_WORD062_DATA_BYTE_3_SHIFT) +#define CAN_WORD062_DATA_BYTE_3(n) (((n) << CAN_WORD062_DATA_BYTE_3_SHIFT) & CAN_WORD062_DATA_BYTE_3_MASK) +#define CAN_WORD062_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD062_DATA_BYTE_2_MASK (0xFF << CAN_WORD062_DATA_BYTE_2_SHIFT) +#define CAN_WORD062_DATA_BYTE_2(n) (((n) << CAN_WORD062_DATA_BYTE_2_SHIFT) & CAN_WORD062_DATA_BYTE_2_MASK) +#define CAN_WORD062_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD062_DATA_BYTE_1_MASK (0xFF << CAN_WORD062_DATA_BYTE_1_SHIFT) +#define CAN_WORD062_DATA_BYTE_1(n) (((n) << CAN_WORD062_DATA_BYTE_1_SHIFT) & CAN_WORD062_DATA_BYTE_1_MASK) +#define CAN_WORD062_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD062_DATA_BYTE_0_MASK (0xFF << CAN_WORD062_DATA_BYTE_0_SHIFT) +#define CAN_WORD062_DATA_BYTE_0(n) (((n) << CAN_WORD062_DATA_BYTE_0_SHIFT) & CAN_WORD062_DATA_BYTE_0_MASK) + +/* Message Buffer 62 WORD1 Register (WORD162) */ +#define CAN_WORD162_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD162_DATA_BYTE_7_MASK (0xFF << CAN_WORD162_DATA_BYTE_7_SHIFT) +#define CAN_WORD162_DATA_BYTE_7(n) (((n) << CAN_WORD162_DATA_BYTE_7_SHIFT) & CAN_WORD162_DATA_BYTE_7_MASK) +#define CAN_WORD162_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD162_DATA_BYTE_6_MASK (0xFF << CAN_WORD162_DATA_BYTE_6_SHIFT) +#define CAN_WORD162_DATA_BYTE_6(n) (((n) << CAN_WORD162_DATA_BYTE_6_SHIFT) & CAN_WORD162_DATA_BYTE_6_MASK) +#define CAN_WORD162_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD162_DATA_BYTE_5_MASK (0xFF << CAN_WORD162_DATA_BYTE_5_SHIFT) +#define CAN_WORD162_DATA_BYTE_5(n) (((n) << CAN_WORD162_DATA_BYTE_5_SHIFT) & CAN_WORD162_DATA_BYTE_5_MASK) +#define CAN_WORD162_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD162_DATA_BYTE_4_MASK (0xFF << CAN_WORD162_DATA_BYTE_4_SHIFT) +#define CAN_WORD162_DATA_BYTE_4(n) (((n) << CAN_WORD162_DATA_BYTE_4_SHIFT) & CAN_WORD162_DATA_BYTE_4_MASK) + +/* Message Buffer 63 CS Register (CS63) */ +#define CAN_CS63_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS63_TIME_STAMP_MASK (0xFFFF << CAN_CS63_TIME_STAMP_SHIFT) +#define CAN_CS63_TIME_STAMP(n) (((n) << CAN_CS63_TIME_STAMP_SHIFT) & CAN_CS63_TIME_STAMP_MASK) +#define CAN_CS63_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS63_DLC_MASK (0xF << CAN_CS63_DLC_SHIFT) +#define CAN_CS63_DLC(n) (((n) << CAN_CS63_DLC_SHIFT) & CAN_CS63_DLC_MASK) +#define CAN_CS63_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS63_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS63_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS63_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS63_CODE_MASK (0xF << CAN_CS63_CODE_SHIFT) +#define CAN_CS63_CODE(n) (((n) << CAN_CS63_CODE_SHIFT) & CAN_CS63_CODE_MASK) +#define CAN_CS63_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS63_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS63_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 63 WORD0 Register (WORD063) */ +#define CAN_WORD063_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD063_DATA_BYTE_3_MASK (0xFF << CAN_WORD063_DATA_BYTE_3_SHIFT) +#define CAN_WORD063_DATA_BYTE_3(n) (((n) << CAN_WORD063_DATA_BYTE_3_SHIFT) & CAN_WORD063_DATA_BYTE_3_MASK) +#define CAN_WORD063_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD063_DATA_BYTE_2_MASK (0xFF << CAN_WORD063_DATA_BYTE_2_SHIFT) +#define CAN_WORD063_DATA_BYTE_2(n) (((n) << CAN_WORD063_DATA_BYTE_2_SHIFT) & CAN_WORD063_DATA_BYTE_2_MASK) +#define CAN_WORD063_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD063_DATA_BYTE_1_MASK (0xFF << CAN_WORD063_DATA_BYTE_1_SHIFT) +#define CAN_WORD063_DATA_BYTE_1(n) (((n) << CAN_WORD063_DATA_BYTE_1_SHIFT) & CAN_WORD063_DATA_BYTE_1_MASK) +#define CAN_WORD063_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD063_DATA_BYTE_0_MASK (0xFF << CAN_WORD063_DATA_BYTE_0_SHIFT) +#define CAN_WORD063_DATA_BYTE_0(n) (((n) << CAN_WORD063_DATA_BYTE_0_SHIFT) & CAN_WORD063_DATA_BYTE_0_MASK) + +/* Message Buffer 63 WORD1 Register (WORD163) */ +#define CAN_WORD163_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD163_DATA_BYTE_7_MASK (0xFF << CAN_WORD163_DATA_BYTE_7_SHIFT) +#define CAN_WORD163_DATA_BYTE_7(n) (((n) << CAN_WORD163_DATA_BYTE_7_SHIFT) & CAN_WORD163_DATA_BYTE_7_MASK) +#define CAN_WORD163_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD163_DATA_BYTE_6_MASK (0xFF << CAN_WORD163_DATA_BYTE_6_SHIFT) +#define CAN_WORD163_DATA_BYTE_6(n) (((n) << CAN_WORD163_DATA_BYTE_6_SHIFT) & CAN_WORD163_DATA_BYTE_6_MASK) +#define CAN_WORD163_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD163_DATA_BYTE_5_MASK (0xFF << CAN_WORD163_DATA_BYTE_5_SHIFT) +#define CAN_WORD163_DATA_BYTE_5(n) (((n) << CAN_WORD163_DATA_BYTE_5_SHIFT) & CAN_WORD163_DATA_BYTE_5_MASK) +#define CAN_WORD163_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD163_DATA_BYTE_4_MASK (0xFF << CAN_WORD163_DATA_BYTE_4_SHIFT) +#define CAN_WORD163_DATA_BYTE_4(n) (((n) << CAN_WORD163_DATA_BYTE_4_SHIFT) & CAN_WORD163_DATA_BYTE_4_MASK) + +/* Message Buffer 64 CS Register (CS64) */ +#define CAN_CS64_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS64_TIME_STAMP_MASK (0xFFFF << CAN_CS64_TIME_STAMP_SHIFT) +#define CAN_CS64_TIME_STAMP(n) (((n) << CAN_CS64_TIME_STAMP_SHIFT) & CAN_CS64_TIME_STAMP_MASK) +#define CAN_CS64_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS64_DLC_MASK (0xF << CAN_CS64_DLC_SHIFT) +#define CAN_CS64_DLC(n) (((n) << CAN_CS64_DLC_SHIFT) & CAN_CS64_DLC_MASK) +#define CAN_CS64_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS64_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS64_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS64_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS64_CODE_MASK (0xF << CAN_CS64_CODE_SHIFT) +#define CAN_CS64_CODE(n) (((n) << CAN_CS64_CODE_SHIFT) & CAN_CS64_CODE_MASK) +#define CAN_CS64_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS64_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS64_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 64 WORD0 Register (WORD064) */ +#define CAN_WORD064_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD064_DATA_BYTE_3_MASK (0xFF << CAN_WORD064_DATA_BYTE_3_SHIFT) +#define CAN_WORD064_DATA_BYTE_3(n) (((n) << CAN_WORD064_DATA_BYTE_3_SHIFT) & CAN_WORD064_DATA_BYTE_3_MASK) +#define CAN_WORD064_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD064_DATA_BYTE_2_MASK (0xFF << CAN_WORD064_DATA_BYTE_2_SHIFT) +#define CAN_WORD064_DATA_BYTE_2(n) (((n) << CAN_WORD064_DATA_BYTE_2_SHIFT) & CAN_WORD064_DATA_BYTE_2_MASK) +#define CAN_WORD064_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD064_DATA_BYTE_1_MASK (0xFF << CAN_WORD064_DATA_BYTE_1_SHIFT) +#define CAN_WORD064_DATA_BYTE_1(n) (((n) << CAN_WORD064_DATA_BYTE_1_SHIFT) & CAN_WORD064_DATA_BYTE_1_MASK) +#define CAN_WORD064_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD064_DATA_BYTE_0_MASK (0xFF << CAN_WORD064_DATA_BYTE_0_SHIFT) +#define CAN_WORD064_DATA_BYTE_0(n) (((n) << CAN_WORD064_DATA_BYTE_0_SHIFT) & CAN_WORD064_DATA_BYTE_0_MASK) + +/* Message Buffer 64 WORD1 Register (WORD164) */ +#define CAN_WORD164_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD164_DATA_BYTE_7_MASK (0xFF << CAN_WORD164_DATA_BYTE_7_SHIFT) +#define CAN_WORD164_DATA_BYTE_7(n) (((n) << CAN_WORD164_DATA_BYTE_7_SHIFT) & CAN_WORD164_DATA_BYTE_7_MASK) +#define CAN_WORD164_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD164_DATA_BYTE_6_MASK (0xFF << CAN_WORD164_DATA_BYTE_6_SHIFT) +#define CAN_WORD164_DATA_BYTE_6(n) (((n) << CAN_WORD164_DATA_BYTE_6_SHIFT) & CAN_WORD164_DATA_BYTE_6_MASK) +#define CAN_WORD164_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD164_DATA_BYTE_5_MASK (0xFF << CAN_WORD164_DATA_BYTE_5_SHIFT) +#define CAN_WORD164_DATA_BYTE_5(n) (((n) << CAN_WORD164_DATA_BYTE_5_SHIFT) & CAN_WORD164_DATA_BYTE_5_MASK) +#define CAN_WORD164_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD164_DATA_BYTE_4_MASK (0xFF << CAN_WORD164_DATA_BYTE_4_SHIFT) +#define CAN_WORD164_DATA_BYTE_4(n) (((n) << CAN_WORD164_DATA_BYTE_4_SHIFT) & CAN_WORD164_DATA_BYTE_4_MASK) + +/* Message Buffer 65 CS Register (CS65) */ +#define CAN_CS65_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS65_TIME_STAMP_MASK (0xFFFF << CAN_CS65_TIME_STAMP_SHIFT) +#define CAN_CS65_TIME_STAMP(n) (((n) << CAN_CS65_TIME_STAMP_SHIFT) & CAN_CS65_TIME_STAMP_MASK) +#define CAN_CS65_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS65_DLC_MASK (0xF << CAN_CS65_DLC_SHIFT) +#define CAN_CS65_DLC(n) (((n) << CAN_CS65_DLC_SHIFT) & CAN_CS65_DLC_MASK) +#define CAN_CS65_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS65_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS65_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS65_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS65_CODE_MASK (0xF << CAN_CS65_CODE_SHIFT) +#define CAN_CS65_CODE(n) (((n) << CAN_CS65_CODE_SHIFT) & CAN_CS65_CODE_MASK) +#define CAN_CS65_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS65_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS65_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 65 WORD0 Register (WORD065) */ +#define CAN_WORD065_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD065_DATA_BYTE_3_MASK (0xFF << CAN_WORD065_DATA_BYTE_3_SHIFT) +#define CAN_WORD065_DATA_BYTE_3(n) (((n) << CAN_WORD065_DATA_BYTE_3_SHIFT) & CAN_WORD065_DATA_BYTE_3_MASK) +#define CAN_WORD065_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD065_DATA_BYTE_2_MASK (0xFF << CAN_WORD065_DATA_BYTE_2_SHIFT) +#define CAN_WORD065_DATA_BYTE_2(n) (((n) << CAN_WORD065_DATA_BYTE_2_SHIFT) & CAN_WORD065_DATA_BYTE_2_MASK) +#define CAN_WORD065_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD065_DATA_BYTE_1_MASK (0xFF << CAN_WORD065_DATA_BYTE_1_SHIFT) +#define CAN_WORD065_DATA_BYTE_1(n) (((n) << CAN_WORD065_DATA_BYTE_1_SHIFT) & CAN_WORD065_DATA_BYTE_1_MASK) +#define CAN_WORD065_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD065_DATA_BYTE_0_MASK (0xFF << CAN_WORD065_DATA_BYTE_0_SHIFT) +#define CAN_WORD065_DATA_BYTE_0(n) (((n) << CAN_WORD065_DATA_BYTE_0_SHIFT) & CAN_WORD065_DATA_BYTE_0_MASK) + +/* Message Buffer 65 WORD1 Register (WORD165) */ +#define CAN_WORD165_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD165_DATA_BYTE_7_MASK (0xFF << CAN_WORD165_DATA_BYTE_7_SHIFT) +#define CAN_WORD165_DATA_BYTE_7(n) (((n) << CAN_WORD165_DATA_BYTE_7_SHIFT) & CAN_WORD165_DATA_BYTE_7_MASK) +#define CAN_WORD165_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD165_DATA_BYTE_6_MASK (0xFF << CAN_WORD165_DATA_BYTE_6_SHIFT) +#define CAN_WORD165_DATA_BYTE_6(n) (((n) << CAN_WORD165_DATA_BYTE_6_SHIFT) & CAN_WORD165_DATA_BYTE_6_MASK) +#define CAN_WORD165_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD165_DATA_BYTE_5_MASK (0xFF << CAN_WORD165_DATA_BYTE_5_SHIFT) +#define CAN_WORD165_DATA_BYTE_5(n) (((n) << CAN_WORD165_DATA_BYTE_5_SHIFT) & CAN_WORD165_DATA_BYTE_5_MASK) +#define CAN_WORD165_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD165_DATA_BYTE_4_MASK (0xFF << CAN_WORD165_DATA_BYTE_4_SHIFT) +#define CAN_WORD165_DATA_BYTE_4(n) (((n) << CAN_WORD165_DATA_BYTE_4_SHIFT) & CAN_WORD165_DATA_BYTE_4_MASK) + +/* Message Buffer 66 CS Register (CS66) */ +#define CAN_CS66_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS66_TIME_STAMP_MASK (0xFFFF << CAN_CS66_TIME_STAMP_SHIFT) +#define CAN_CS66_TIME_STAMP(n) (((n) << CAN_CS66_TIME_STAMP_SHIFT) & CAN_CS66_TIME_STAMP_MASK) +#define CAN_CS66_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS66_DLC_MASK (0xF << CAN_CS66_DLC_SHIFT) +#define CAN_CS66_DLC(n) (((n) << CAN_CS66_DLC_SHIFT) & CAN_CS66_DLC_MASK) +#define CAN_CS66_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS66_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS66_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS66_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS66_CODE_MASK (0xF << CAN_CS66_CODE_SHIFT) +#define CAN_CS66_CODE(n) (((n) << CAN_CS66_CODE_SHIFT) & CAN_CS66_CODE_MASK) +#define CAN_CS66_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS66_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS66_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 66 WORD0 Register (WORD066) */ +#define CAN_WORD066_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD066_DATA_BYTE_3_MASK (0xFF << CAN_WORD066_DATA_BYTE_3_SHIFT) +#define CAN_WORD066_DATA_BYTE_3(n) (((n) << CAN_WORD066_DATA_BYTE_3_SHIFT) & CAN_WORD066_DATA_BYTE_3_MASK) +#define CAN_WORD066_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD066_DATA_BYTE_2_MASK (0xFF << CAN_WORD066_DATA_BYTE_2_SHIFT) +#define CAN_WORD066_DATA_BYTE_2(n) (((n) << CAN_WORD066_DATA_BYTE_2_SHIFT) & CAN_WORD066_DATA_BYTE_2_MASK) +#define CAN_WORD066_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD066_DATA_BYTE_1_MASK (0xFF << CAN_WORD066_DATA_BYTE_1_SHIFT) +#define CAN_WORD066_DATA_BYTE_1(n) (((n) << CAN_WORD066_DATA_BYTE_1_SHIFT) & CAN_WORD066_DATA_BYTE_1_MASK) +#define CAN_WORD066_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD066_DATA_BYTE_0_MASK (0xFF << CAN_WORD066_DATA_BYTE_0_SHIFT) +#define CAN_WORD066_DATA_BYTE_0(n) (((n) << CAN_WORD066_DATA_BYTE_0_SHIFT) & CAN_WORD066_DATA_BYTE_0_MASK) + +/* Message Buffer 66 WORD1 Register (WORD166) */ +#define CAN_WORD166_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD166_DATA_BYTE_7_MASK (0xFF << CAN_WORD166_DATA_BYTE_7_SHIFT) +#define CAN_WORD166_DATA_BYTE_7(n) (((n) << CAN_WORD166_DATA_BYTE_7_SHIFT) & CAN_WORD166_DATA_BYTE_7_MASK) +#define CAN_WORD166_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD166_DATA_BYTE_6_MASK (0xFF << CAN_WORD166_DATA_BYTE_6_SHIFT) +#define CAN_WORD166_DATA_BYTE_6(n) (((n) << CAN_WORD166_DATA_BYTE_6_SHIFT) & CAN_WORD166_DATA_BYTE_6_MASK) +#define CAN_WORD166_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD166_DATA_BYTE_5_MASK (0xFF << CAN_WORD166_DATA_BYTE_5_SHIFT) +#define CAN_WORD166_DATA_BYTE_5(n) (((n) << CAN_WORD166_DATA_BYTE_5_SHIFT) & CAN_WORD166_DATA_BYTE_5_MASK) +#define CAN_WORD166_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD166_DATA_BYTE_4_MASK (0xFF << CAN_WORD166_DATA_BYTE_4_SHIFT) +#define CAN_WORD166_DATA_BYTE_4(n) (((n) << CAN_WORD166_DATA_BYTE_4_SHIFT) & CAN_WORD166_DATA_BYTE_4_MASK) + +/* Message Buffer 67 CS Register (CS67) */ +#define CAN_CS67_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS67_TIME_STAMP_MASK (0xFFFF << CAN_CS67_TIME_STAMP_SHIFT) +#define CAN_CS67_TIME_STAMP(n) (((n) << CAN_CS67_TIME_STAMP_SHIFT) & CAN_CS67_TIME_STAMP_MASK) +#define CAN_CS67_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS67_DLC_MASK (0xF << CAN_CS67_DLC_SHIFT) +#define CAN_CS67_DLC(n) (((n) << CAN_CS67_DLC_SHIFT) & CAN_CS67_DLC_MASK) +#define CAN_CS67_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS67_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS67_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS67_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS67_CODE_MASK (0xF << CAN_CS67_CODE_SHIFT) +#define CAN_CS67_CODE(n) (((n) << CAN_CS67_CODE_SHIFT) & CAN_CS67_CODE_MASK) +#define CAN_CS67_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS67_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS67_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 67 WORD0 Register (WORD067) */ +#define CAN_WORD067_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD067_DATA_BYTE_3_MASK (0xFF << CAN_WORD067_DATA_BYTE_3_SHIFT) +#define CAN_WORD067_DATA_BYTE_3(n) (((n) << CAN_WORD067_DATA_BYTE_3_SHIFT) & CAN_WORD067_DATA_BYTE_3_MASK) +#define CAN_WORD067_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD067_DATA_BYTE_2_MASK (0xFF << CAN_WORD067_DATA_BYTE_2_SHIFT) +#define CAN_WORD067_DATA_BYTE_2(n) (((n) << CAN_WORD067_DATA_BYTE_2_SHIFT) & CAN_WORD067_DATA_BYTE_2_MASK) +#define CAN_WORD067_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD067_DATA_BYTE_1_MASK (0xFF << CAN_WORD067_DATA_BYTE_1_SHIFT) +#define CAN_WORD067_DATA_BYTE_1(n) (((n) << CAN_WORD067_DATA_BYTE_1_SHIFT) & CAN_WORD067_DATA_BYTE_1_MASK) +#define CAN_WORD067_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD067_DATA_BYTE_0_MASK (0xFF << CAN_WORD067_DATA_BYTE_0_SHIFT) +#define CAN_WORD067_DATA_BYTE_0(n) (((n) << CAN_WORD067_DATA_BYTE_0_SHIFT) & CAN_WORD067_DATA_BYTE_0_MASK) + +/* Message Buffer 67 WORD1 Register (WORD167) */ +#define CAN_WORD167_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD167_DATA_BYTE_7_MASK (0xFF << CAN_WORD167_DATA_BYTE_7_SHIFT) +#define CAN_WORD167_DATA_BYTE_7(n) (((n) << CAN_WORD167_DATA_BYTE_7_SHIFT) & CAN_WORD167_DATA_BYTE_7_MASK) +#define CAN_WORD167_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD167_DATA_BYTE_6_MASK (0xFF << CAN_WORD167_DATA_BYTE_6_SHIFT) +#define CAN_WORD167_DATA_BYTE_6(n) (((n) << CAN_WORD167_DATA_BYTE_6_SHIFT) & CAN_WORD167_DATA_BYTE_6_MASK) +#define CAN_WORD167_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD167_DATA_BYTE_5_MASK (0xFF << CAN_WORD167_DATA_BYTE_5_SHIFT) +#define CAN_WORD167_DATA_BYTE_5(n) (((n) << CAN_WORD167_DATA_BYTE_5_SHIFT) & CAN_WORD167_DATA_BYTE_5_MASK) +#define CAN_WORD167_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD167_DATA_BYTE_4_MASK (0xFF << CAN_WORD167_DATA_BYTE_4_SHIFT) +#define CAN_WORD167_DATA_BYTE_4(n) (((n) << CAN_WORD167_DATA_BYTE_4_SHIFT) & CAN_WORD167_DATA_BYTE_4_MASK) + +/* Message Buffer 68 CS Register (CS68) */ +#define CAN_CS68_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS68_TIME_STAMP_MASK (0xFFFF << CAN_CS68_TIME_STAMP_SHIFT) +#define CAN_CS68_TIME_STAMP(n) (((n) << CAN_CS68_TIME_STAMP_SHIFT) & CAN_CS68_TIME_STAMP_MASK) +#define CAN_CS68_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS68_DLC_MASK (0xF << CAN_CS68_DLC_SHIFT) +#define CAN_CS68_DLC(n) (((n) << CAN_CS68_DLC_SHIFT) & CAN_CS68_DLC_MASK) +#define CAN_CS68_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS68_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS68_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS68_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS68_CODE_MASK (0xF << CAN_CS68_CODE_SHIFT) +#define CAN_CS68_CODE(n) (((n) << CAN_CS68_CODE_SHIFT) & CAN_CS68_CODE_MASK) +#define CAN_CS68_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS68_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS68_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 68 WORD0 Register (WORD068) */ +#define CAN_WORD068_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD068_DATA_BYTE_3_MASK (0xFF << CAN_WORD068_DATA_BYTE_3_SHIFT) +#define CAN_WORD068_DATA_BYTE_3(n) (((n) << CAN_WORD068_DATA_BYTE_3_SHIFT) & CAN_WORD068_DATA_BYTE_3_MASK) +#define CAN_WORD068_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD068_DATA_BYTE_2_MASK (0xFF << CAN_WORD068_DATA_BYTE_2_SHIFT) +#define CAN_WORD068_DATA_BYTE_2(n) (((n) << CAN_WORD068_DATA_BYTE_2_SHIFT) & CAN_WORD068_DATA_BYTE_2_MASK) +#define CAN_WORD068_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD068_DATA_BYTE_1_MASK (0xFF << CAN_WORD068_DATA_BYTE_1_SHIFT) +#define CAN_WORD068_DATA_BYTE_1(n) (((n) << CAN_WORD068_DATA_BYTE_1_SHIFT) & CAN_WORD068_DATA_BYTE_1_MASK) +#define CAN_WORD068_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD068_DATA_BYTE_0_MASK (0xFF << CAN_WORD068_DATA_BYTE_0_SHIFT) +#define CAN_WORD068_DATA_BYTE_0(n) (((n) << CAN_WORD068_DATA_BYTE_0_SHIFT) & CAN_WORD068_DATA_BYTE_0_MASK) + +/* Message Buffer 68 WORD1 Register (WORD168) */ +#define CAN_WORD168_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD168_DATA_BYTE_7_MASK (0xFF << CAN_WORD168_DATA_BYTE_7_SHIFT) +#define CAN_WORD168_DATA_BYTE_7(n) (((n) << CAN_WORD168_DATA_BYTE_7_SHIFT) & CAN_WORD168_DATA_BYTE_7_MASK) +#define CAN_WORD168_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD168_DATA_BYTE_6_MASK (0xFF << CAN_WORD168_DATA_BYTE_6_SHIFT) +#define CAN_WORD168_DATA_BYTE_6(n) (((n) << CAN_WORD168_DATA_BYTE_6_SHIFT) & CAN_WORD168_DATA_BYTE_6_MASK) +#define CAN_WORD168_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD168_DATA_BYTE_5_MASK (0xFF << CAN_WORD168_DATA_BYTE_5_SHIFT) +#define CAN_WORD168_DATA_BYTE_5(n) (((n) << CAN_WORD168_DATA_BYTE_5_SHIFT) & CAN_WORD168_DATA_BYTE_5_MASK) +#define CAN_WORD168_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD168_DATA_BYTE_4_MASK (0xFF << CAN_WORD168_DATA_BYTE_4_SHIFT) +#define CAN_WORD168_DATA_BYTE_4(n) (((n) << CAN_WORD168_DATA_BYTE_4_SHIFT) & CAN_WORD168_DATA_BYTE_4_MASK) + +/* Message Buffer 69 CS Register (CS69) */ +#define CAN_CS69_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS69_TIME_STAMP_MASK (0xFFFF << CAN_CS69_TIME_STAMP_SHIFT) +#define CAN_CS69_TIME_STAMP(n) (((n) << CAN_CS69_TIME_STAMP_SHIFT) & CAN_CS69_TIME_STAMP_MASK) +#define CAN_CS69_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS69_DLC_MASK (0xF << CAN_CS69_DLC_SHIFT) +#define CAN_CS69_DLC(n) (((n) << CAN_CS69_DLC_SHIFT) & CAN_CS69_DLC_MASK) +#define CAN_CS69_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS69_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS69_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS69_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS69_CODE_MASK (0xF << CAN_CS69_CODE_SHIFT) +#define CAN_CS69_CODE(n) (((n) << CAN_CS69_CODE_SHIFT) & CAN_CS69_CODE_MASK) +#define CAN_CS69_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS69_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS69_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 69 WORD0 Register (WORD069) */ +#define CAN_WORD069_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD069_DATA_BYTE_3_MASK (0xFF << CAN_WORD069_DATA_BYTE_3_SHIFT) +#define CAN_WORD069_DATA_BYTE_3(n) (((n) << CAN_WORD069_DATA_BYTE_3_SHIFT) & CAN_WORD069_DATA_BYTE_3_MASK) +#define CAN_WORD069_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD069_DATA_BYTE_2_MASK (0xFF << CAN_WORD069_DATA_BYTE_2_SHIFT) +#define CAN_WORD069_DATA_BYTE_2(n) (((n) << CAN_WORD069_DATA_BYTE_2_SHIFT) & CAN_WORD069_DATA_BYTE_2_MASK) +#define CAN_WORD069_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD069_DATA_BYTE_1_MASK (0xFF << CAN_WORD069_DATA_BYTE_1_SHIFT) +#define CAN_WORD069_DATA_BYTE_1(n) (((n) << CAN_WORD069_DATA_BYTE_1_SHIFT) & CAN_WORD069_DATA_BYTE_1_MASK) +#define CAN_WORD069_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD069_DATA_BYTE_0_MASK (0xFF << CAN_WORD069_DATA_BYTE_0_SHIFT) +#define CAN_WORD069_DATA_BYTE_0(n) (((n) << CAN_WORD069_DATA_BYTE_0_SHIFT) & CAN_WORD069_DATA_BYTE_0_MASK) + +/* Message Buffer 69 WORD1 Register (WORD169) */ +#define CAN_WORD169_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD169_DATA_BYTE_7_MASK (0xFF << CAN_WORD169_DATA_BYTE_7_SHIFT) +#define CAN_WORD169_DATA_BYTE_7(n) (((n) << CAN_WORD169_DATA_BYTE_7_SHIFT) & CAN_WORD169_DATA_BYTE_7_MASK) +#define CAN_WORD169_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD169_DATA_BYTE_6_MASK (0xFF << CAN_WORD169_DATA_BYTE_6_SHIFT) +#define CAN_WORD169_DATA_BYTE_6(n) (((n) << CAN_WORD169_DATA_BYTE_6_SHIFT) & CAN_WORD169_DATA_BYTE_6_MASK) +#define CAN_WORD169_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD169_DATA_BYTE_5_MASK (0xFF << CAN_WORD169_DATA_BYTE_5_SHIFT) +#define CAN_WORD169_DATA_BYTE_5(n) (((n) << CAN_WORD169_DATA_BYTE_5_SHIFT) & CAN_WORD169_DATA_BYTE_5_MASK) +#define CAN_WORD169_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD169_DATA_BYTE_4_MASK (0xFF << CAN_WORD169_DATA_BYTE_4_SHIFT) +#define CAN_WORD169_DATA_BYTE_4(n) (((n) << CAN_WORD169_DATA_BYTE_4_SHIFT) & CAN_WORD169_DATA_BYTE_4_MASK) + +/* Message Buffer 70 CS Register (CS70) */ +#define CAN_CS70_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS70_TIME_STAMP_MASK (0xFFFF << CAN_CS70_TIME_STAMP_SHIFT) +#define CAN_CS70_TIME_STAMP(n) (((n) << CAN_CS70_TIME_STAMP_SHIFT) & CAN_CS70_TIME_STAMP_MASK) +#define CAN_CS70_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS70_DLC_MASK (0xF << CAN_CS70_DLC_SHIFT) +#define CAN_CS70_DLC(n) (((n) << CAN_CS70_DLC_SHIFT) & CAN_CS70_DLC_MASK) +#define CAN_CS70_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS70_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS70_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS70_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS70_CODE_MASK (0xF << CAN_CS70_CODE_SHIFT) +#define CAN_CS70_CODE(n) (((n) << CAN_CS70_CODE_SHIFT) & CAN_CS70_CODE_MASK) +#define CAN_CS70_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS70_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS70_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 70 WORD0 Register (WORD070) */ +#define CAN_WORD070_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD070_DATA_BYTE_3_MASK (0xFF << CAN_WORD070_DATA_BYTE_3_SHIFT) +#define CAN_WORD070_DATA_BYTE_3(n) (((n) << CAN_WORD070_DATA_BYTE_3_SHIFT) & CAN_WORD070_DATA_BYTE_3_MASK) +#define CAN_WORD070_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD070_DATA_BYTE_2_MASK (0xFF << CAN_WORD070_DATA_BYTE_2_SHIFT) +#define CAN_WORD070_DATA_BYTE_2(n) (((n) << CAN_WORD070_DATA_BYTE_2_SHIFT) & CAN_WORD070_DATA_BYTE_2_MASK) +#define CAN_WORD070_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD070_DATA_BYTE_1_MASK (0xFF << CAN_WORD070_DATA_BYTE_1_SHIFT) +#define CAN_WORD070_DATA_BYTE_1(n) (((n) << CAN_WORD070_DATA_BYTE_1_SHIFT) & CAN_WORD070_DATA_BYTE_1_MASK) +#define CAN_WORD070_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD070_DATA_BYTE_0_MASK (0xFF << CAN_WORD070_DATA_BYTE_0_SHIFT) +#define CAN_WORD070_DATA_BYTE_0(n) (((n) << CAN_WORD070_DATA_BYTE_0_SHIFT) & CAN_WORD070_DATA_BYTE_0_MASK) + +/* Message Buffer 70 WORD1 Register (WORD170) */ +#define CAN_WORD170_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD170_DATA_BYTE_7_MASK (0xFF << CAN_WORD170_DATA_BYTE_7_SHIFT) +#define CAN_WORD170_DATA_BYTE_7(n) (((n) << CAN_WORD170_DATA_BYTE_7_SHIFT) & CAN_WORD170_DATA_BYTE_7_MASK) +#define CAN_WORD170_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD170_DATA_BYTE_6_MASK (0xFF << CAN_WORD170_DATA_BYTE_6_SHIFT) +#define CAN_WORD170_DATA_BYTE_6(n) (((n) << CAN_WORD170_DATA_BYTE_6_SHIFT) & CAN_WORD170_DATA_BYTE_6_MASK) +#define CAN_WORD170_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD170_DATA_BYTE_5_MASK (0xFF << CAN_WORD170_DATA_BYTE_5_SHIFT) +#define CAN_WORD170_DATA_BYTE_5(n) (((n) << CAN_WORD170_DATA_BYTE_5_SHIFT) & CAN_WORD170_DATA_BYTE_5_MASK) +#define CAN_WORD170_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD170_DATA_BYTE_4_MASK (0xFF << CAN_WORD170_DATA_BYTE_4_SHIFT) +#define CAN_WORD170_DATA_BYTE_4(n) (((n) << CAN_WORD170_DATA_BYTE_4_SHIFT) & CAN_WORD170_DATA_BYTE_4_MASK) + +/* Message Buffer 71 CS Register (CS71) */ +#define CAN_CS71_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS71_TIME_STAMP_MASK (0xFFFF << CAN_CS71_TIME_STAMP_SHIFT) +#define CAN_CS71_TIME_STAMP(n) (((n) << CAN_CS71_TIME_STAMP_SHIFT) & CAN_CS71_TIME_STAMP_MASK) +#define CAN_CS71_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS71_DLC_MASK (0xF << CAN_CS71_DLC_SHIFT) +#define CAN_CS71_DLC(n) (((n) << CAN_CS71_DLC_SHIFT) & CAN_CS71_DLC_MASK) +#define CAN_CS71_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS71_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS71_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS71_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS71_CODE_MASK (0xF << CAN_CS71_CODE_SHIFT) +#define CAN_CS71_CODE(n) (((n) << CAN_CS71_CODE_SHIFT) & CAN_CS71_CODE_MASK) +#define CAN_CS71_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS71_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS71_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 71 WORD0 Register (WORD071) */ +#define CAN_WORD071_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD071_DATA_BYTE_3_MASK (0xFF << CAN_WORD071_DATA_BYTE_3_SHIFT) +#define CAN_WORD071_DATA_BYTE_3(n) (((n) << CAN_WORD071_DATA_BYTE_3_SHIFT) & CAN_WORD071_DATA_BYTE_3_MASK) +#define CAN_WORD071_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD071_DATA_BYTE_2_MASK (0xFF << CAN_WORD071_DATA_BYTE_2_SHIFT) +#define CAN_WORD071_DATA_BYTE_2(n) (((n) << CAN_WORD071_DATA_BYTE_2_SHIFT) & CAN_WORD071_DATA_BYTE_2_MASK) +#define CAN_WORD071_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD071_DATA_BYTE_1_MASK (0xFF << CAN_WORD071_DATA_BYTE_1_SHIFT) +#define CAN_WORD071_DATA_BYTE_1(n) (((n) << CAN_WORD071_DATA_BYTE_1_SHIFT) & CAN_WORD071_DATA_BYTE_1_MASK) +#define CAN_WORD071_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD071_DATA_BYTE_0_MASK (0xFF << CAN_WORD071_DATA_BYTE_0_SHIFT) +#define CAN_WORD071_DATA_BYTE_0(n) (((n) << CAN_WORD071_DATA_BYTE_0_SHIFT) & CAN_WORD071_DATA_BYTE_0_MASK) + +/* Message Buffer 71 WORD1 Register (WORD171) */ +#define CAN_WORD171_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD171_DATA_BYTE_7_MASK (0xFF << CAN_WORD171_DATA_BYTE_7_SHIFT) +#define CAN_WORD171_DATA_BYTE_7(n) (((n) << CAN_WORD171_DATA_BYTE_7_SHIFT) & CAN_WORD171_DATA_BYTE_7_MASK) +#define CAN_WORD171_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD171_DATA_BYTE_6_MASK (0xFF << CAN_WORD171_DATA_BYTE_6_SHIFT) +#define CAN_WORD171_DATA_BYTE_6(n) (((n) << CAN_WORD171_DATA_BYTE_6_SHIFT) & CAN_WORD171_DATA_BYTE_6_MASK) +#define CAN_WORD171_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD171_DATA_BYTE_5_MASK (0xFF << CAN_WORD171_DATA_BYTE_5_SHIFT) +#define CAN_WORD171_DATA_BYTE_5(n) (((n) << CAN_WORD171_DATA_BYTE_5_SHIFT) & CAN_WORD171_DATA_BYTE_5_MASK) +#define CAN_WORD171_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD171_DATA_BYTE_4_MASK (0xFF << CAN_WORD171_DATA_BYTE_4_SHIFT) +#define CAN_WORD171_DATA_BYTE_4(n) (((n) << CAN_WORD171_DATA_BYTE_4_SHIFT) & CAN_WORD171_DATA_BYTE_4_MASK) + +/* Message Buffer 72 CS Register (CS72) */ +#define CAN_CS72_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS72_TIME_STAMP_MASK (0xFFFF << CAN_CS72_TIME_STAMP_SHIFT) +#define CAN_CS72_TIME_STAMP(n) (((n) << CAN_CS72_TIME_STAMP_SHIFT) & CAN_CS72_TIME_STAMP_MASK) +#define CAN_CS72_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS72_DLC_MASK (0xF << CAN_CS72_DLC_SHIFT) +#define CAN_CS72_DLC(n) (((n) << CAN_CS72_DLC_SHIFT) & CAN_CS72_DLC_MASK) +#define CAN_CS72_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS72_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS72_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS72_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS72_CODE_MASK (0xF << CAN_CS72_CODE_SHIFT) +#define CAN_CS72_CODE(n) (((n) << CAN_CS72_CODE_SHIFT) & CAN_CS72_CODE_MASK) +#define CAN_CS72_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS72_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS72_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 72 WORD0 Register (WORD072) */ +#define CAN_WORD072_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD072_DATA_BYTE_3_MASK (0xFF << CAN_WORD072_DATA_BYTE_3_SHIFT) +#define CAN_WORD072_DATA_BYTE_3(n) (((n) << CAN_WORD072_DATA_BYTE_3_SHIFT) & CAN_WORD072_DATA_BYTE_3_MASK) +#define CAN_WORD072_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD072_DATA_BYTE_2_MASK (0xFF << CAN_WORD072_DATA_BYTE_2_SHIFT) +#define CAN_WORD072_DATA_BYTE_2(n) (((n) << CAN_WORD072_DATA_BYTE_2_SHIFT) & CAN_WORD072_DATA_BYTE_2_MASK) +#define CAN_WORD072_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD072_DATA_BYTE_1_MASK (0xFF << CAN_WORD072_DATA_BYTE_1_SHIFT) +#define CAN_WORD072_DATA_BYTE_1(n) (((n) << CAN_WORD072_DATA_BYTE_1_SHIFT) & CAN_WORD072_DATA_BYTE_1_MASK) +#define CAN_WORD072_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD072_DATA_BYTE_0_MASK (0xFF << CAN_WORD072_DATA_BYTE_0_SHIFT) +#define CAN_WORD072_DATA_BYTE_0(n) (((n) << CAN_WORD072_DATA_BYTE_0_SHIFT) & CAN_WORD072_DATA_BYTE_0_MASK) + +/* Message Buffer 72 WORD1 Register (WORD172) */ +#define CAN_WORD172_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD172_DATA_BYTE_7_MASK (0xFF << CAN_WORD172_DATA_BYTE_7_SHIFT) +#define CAN_WORD172_DATA_BYTE_7(n) (((n) << CAN_WORD172_DATA_BYTE_7_SHIFT) & CAN_WORD172_DATA_BYTE_7_MASK) +#define CAN_WORD172_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD172_DATA_BYTE_6_MASK (0xFF << CAN_WORD172_DATA_BYTE_6_SHIFT) +#define CAN_WORD172_DATA_BYTE_6(n) (((n) << CAN_WORD172_DATA_BYTE_6_SHIFT) & CAN_WORD172_DATA_BYTE_6_MASK) +#define CAN_WORD172_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD172_DATA_BYTE_5_MASK (0xFF << CAN_WORD172_DATA_BYTE_5_SHIFT) +#define CAN_WORD172_DATA_BYTE_5(n) (((n) << CAN_WORD172_DATA_BYTE_5_SHIFT) & CAN_WORD172_DATA_BYTE_5_MASK) +#define CAN_WORD172_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD172_DATA_BYTE_4_MASK (0xFF << CAN_WORD172_DATA_BYTE_4_SHIFT) +#define CAN_WORD172_DATA_BYTE_4(n) (((n) << CAN_WORD172_DATA_BYTE_4_SHIFT) & CAN_WORD172_DATA_BYTE_4_MASK) + +/* Message Buffer 73 CS Register (CS73) */ +#define CAN_CS73_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS73_TIME_STAMP_MASK (0xFFFF << CAN_CS73_TIME_STAMP_SHIFT) +#define CAN_CS73_TIME_STAMP(n) (((n) << CAN_CS73_TIME_STAMP_SHIFT) & CAN_CS73_TIME_STAMP_MASK) +#define CAN_CS73_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS73_DLC_MASK (0xF << CAN_CS73_DLC_SHIFT) +#define CAN_CS73_DLC(n) (((n) << CAN_CS73_DLC_SHIFT) & CAN_CS73_DLC_MASK) +#define CAN_CS73_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS73_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS73_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS73_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS73_CODE_MASK (0xF << CAN_CS73_CODE_SHIFT) +#define CAN_CS73_CODE(n) (((n) << CAN_CS73_CODE_SHIFT) & CAN_CS73_CODE_MASK) +#define CAN_CS73_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS73_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS73_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 73 WORD0 Register (WORD073) */ +#define CAN_WORD073_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD073_DATA_BYTE_3_MASK (0xFF << CAN_WORD073_DATA_BYTE_3_SHIFT) +#define CAN_WORD073_DATA_BYTE_3(n) (((n) << CAN_WORD073_DATA_BYTE_3_SHIFT) & CAN_WORD073_DATA_BYTE_3_MASK) +#define CAN_WORD073_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD073_DATA_BYTE_2_MASK (0xFF << CAN_WORD073_DATA_BYTE_2_SHIFT) +#define CAN_WORD073_DATA_BYTE_2(n) (((n) << CAN_WORD073_DATA_BYTE_2_SHIFT) & CAN_WORD073_DATA_BYTE_2_MASK) +#define CAN_WORD073_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD073_DATA_BYTE_1_MASK (0xFF << CAN_WORD073_DATA_BYTE_1_SHIFT) +#define CAN_WORD073_DATA_BYTE_1(n) (((n) << CAN_WORD073_DATA_BYTE_1_SHIFT) & CAN_WORD073_DATA_BYTE_1_MASK) +#define CAN_WORD073_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD073_DATA_BYTE_0_MASK (0xFF << CAN_WORD073_DATA_BYTE_0_SHIFT) +#define CAN_WORD073_DATA_BYTE_0(n) (((n) << CAN_WORD073_DATA_BYTE_0_SHIFT) & CAN_WORD073_DATA_BYTE_0_MASK) + +/* Message Buffer 73 WORD1 Register (WORD173) */ +#define CAN_WORD173_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD173_DATA_BYTE_7_MASK (0xFF << CAN_WORD173_DATA_BYTE_7_SHIFT) +#define CAN_WORD173_DATA_BYTE_7(n) (((n) << CAN_WORD173_DATA_BYTE_7_SHIFT) & CAN_WORD173_DATA_BYTE_7_MASK) +#define CAN_WORD173_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD173_DATA_BYTE_6_MASK (0xFF << CAN_WORD173_DATA_BYTE_6_SHIFT) +#define CAN_WORD173_DATA_BYTE_6(n) (((n) << CAN_WORD173_DATA_BYTE_6_SHIFT) & CAN_WORD173_DATA_BYTE_6_MASK) +#define CAN_WORD173_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD173_DATA_BYTE_5_MASK (0xFF << CAN_WORD173_DATA_BYTE_5_SHIFT) +#define CAN_WORD173_DATA_BYTE_5(n) (((n) << CAN_WORD173_DATA_BYTE_5_SHIFT) & CAN_WORD173_DATA_BYTE_5_MASK) +#define CAN_WORD173_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD173_DATA_BYTE_4_MASK (0xFF << CAN_WORD173_DATA_BYTE_4_SHIFT) +#define CAN_WORD173_DATA_BYTE_4(n) (((n) << CAN_WORD173_DATA_BYTE_4_SHIFT) & CAN_WORD173_DATA_BYTE_4_MASK) + +/* Message Buffer 74 CS Register (CS74) */ +#define CAN_CS74_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS74_TIME_STAMP_MASK (0xFFFF << CAN_CS74_TIME_STAMP_SHIFT) +#define CAN_CS74_TIME_STAMP(n) (((n) << CAN_CS74_TIME_STAMP_SHIFT) & CAN_CS74_TIME_STAMP_MASK) +#define CAN_CS74_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS74_DLC_MASK (0xF << CAN_CS74_DLC_SHIFT) +#define CAN_CS74_DLC(n) (((n) << CAN_CS74_DLC_SHIFT) & CAN_CS74_DLC_MASK) +#define CAN_CS74_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS74_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS74_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS74_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS74_CODE_MASK (0xF << CAN_CS74_CODE_SHIFT) +#define CAN_CS74_CODE(n) (((n) << CAN_CS74_CODE_SHIFT) & CAN_CS74_CODE_MASK) +#define CAN_CS74_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS74_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS74_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 74 WORD0 Register (WORD074) */ +#define CAN_WORD074_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD074_DATA_BYTE_3_MASK (0xFF << CAN_WORD074_DATA_BYTE_3_SHIFT) +#define CAN_WORD074_DATA_BYTE_3(n) (((n) << CAN_WORD074_DATA_BYTE_3_SHIFT) & CAN_WORD074_DATA_BYTE_3_MASK) +#define CAN_WORD074_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD074_DATA_BYTE_2_MASK (0xFF << CAN_WORD074_DATA_BYTE_2_SHIFT) +#define CAN_WORD074_DATA_BYTE_2(n) (((n) << CAN_WORD074_DATA_BYTE_2_SHIFT) & CAN_WORD074_DATA_BYTE_2_MASK) +#define CAN_WORD074_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD074_DATA_BYTE_1_MASK (0xFF << CAN_WORD074_DATA_BYTE_1_SHIFT) +#define CAN_WORD074_DATA_BYTE_1(n) (((n) << CAN_WORD074_DATA_BYTE_1_SHIFT) & CAN_WORD074_DATA_BYTE_1_MASK) +#define CAN_WORD074_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD074_DATA_BYTE_0_MASK (0xFF << CAN_WORD074_DATA_BYTE_0_SHIFT) +#define CAN_WORD074_DATA_BYTE_0(n) (((n) << CAN_WORD074_DATA_BYTE_0_SHIFT) & CAN_WORD074_DATA_BYTE_0_MASK) + +/* Message Buffer 74 WORD1 Register (WORD174) */ +#define CAN_WORD174_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD174_DATA_BYTE_7_MASK (0xFF << CAN_WORD174_DATA_BYTE_7_SHIFT) +#define CAN_WORD174_DATA_BYTE_7(n) (((n) << CAN_WORD174_DATA_BYTE_7_SHIFT) & CAN_WORD174_DATA_BYTE_7_MASK) +#define CAN_WORD174_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD174_DATA_BYTE_6_MASK (0xFF << CAN_WORD174_DATA_BYTE_6_SHIFT) +#define CAN_WORD174_DATA_BYTE_6(n) (((n) << CAN_WORD174_DATA_BYTE_6_SHIFT) & CAN_WORD174_DATA_BYTE_6_MASK) +#define CAN_WORD174_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD174_DATA_BYTE_5_MASK (0xFF << CAN_WORD174_DATA_BYTE_5_SHIFT) +#define CAN_WORD174_DATA_BYTE_5(n) (((n) << CAN_WORD174_DATA_BYTE_5_SHIFT) & CAN_WORD174_DATA_BYTE_5_MASK) +#define CAN_WORD174_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD174_DATA_BYTE_4_MASK (0xFF << CAN_WORD174_DATA_BYTE_4_SHIFT) +#define CAN_WORD174_DATA_BYTE_4(n) (((n) << CAN_WORD174_DATA_BYTE_4_SHIFT) & CAN_WORD174_DATA_BYTE_4_MASK) + +/* Message Buffer 75 CS Register (CS75) */ +#define CAN_CS75_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS75_TIME_STAMP_MASK (0xFFFF << CAN_CS75_TIME_STAMP_SHIFT) +#define CAN_CS75_TIME_STAMP(n) (((n) << CAN_CS75_TIME_STAMP_SHIFT) & CAN_CS75_TIME_STAMP_MASK) +#define CAN_CS75_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS75_DLC_MASK (0xF << CAN_CS75_DLC_SHIFT) +#define CAN_CS75_DLC(n) (((n) << CAN_CS75_DLC_SHIFT) & CAN_CS75_DLC_MASK) +#define CAN_CS75_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS75_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS75_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS75_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS75_CODE_MASK (0xF << CAN_CS75_CODE_SHIFT) +#define CAN_CS75_CODE(n) (((n) << CAN_CS75_CODE_SHIFT) & CAN_CS75_CODE_MASK) +#define CAN_CS75_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS75_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS75_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 75 WORD0 Register (WORD075) */ +#define CAN_WORD075_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD075_DATA_BYTE_3_MASK (0xFF << CAN_WORD075_DATA_BYTE_3_SHIFT) +#define CAN_WORD075_DATA_BYTE_3(n) (((n) << CAN_WORD075_DATA_BYTE_3_SHIFT) & CAN_WORD075_DATA_BYTE_3_MASK) +#define CAN_WORD075_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD075_DATA_BYTE_2_MASK (0xFF << CAN_WORD075_DATA_BYTE_2_SHIFT) +#define CAN_WORD075_DATA_BYTE_2(n) (((n) << CAN_WORD075_DATA_BYTE_2_SHIFT) & CAN_WORD075_DATA_BYTE_2_MASK) +#define CAN_WORD075_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD075_DATA_BYTE_1_MASK (0xFF << CAN_WORD075_DATA_BYTE_1_SHIFT) +#define CAN_WORD075_DATA_BYTE_1(n) (((n) << CAN_WORD075_DATA_BYTE_1_SHIFT) & CAN_WORD075_DATA_BYTE_1_MASK) +#define CAN_WORD075_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD075_DATA_BYTE_0_MASK (0xFF << CAN_WORD075_DATA_BYTE_0_SHIFT) +#define CAN_WORD075_DATA_BYTE_0(n) (((n) << CAN_WORD075_DATA_BYTE_0_SHIFT) & CAN_WORD075_DATA_BYTE_0_MASK) + +/* Message Buffer 75 WORD1 Register (WORD175) */ +#define CAN_WORD175_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD175_DATA_BYTE_7_MASK (0xFF << CAN_WORD175_DATA_BYTE_7_SHIFT) +#define CAN_WORD175_DATA_BYTE_7(n) (((n) << CAN_WORD175_DATA_BYTE_7_SHIFT) & CAN_WORD175_DATA_BYTE_7_MASK) +#define CAN_WORD175_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD175_DATA_BYTE_6_MASK (0xFF << CAN_WORD175_DATA_BYTE_6_SHIFT) +#define CAN_WORD175_DATA_BYTE_6(n) (((n) << CAN_WORD175_DATA_BYTE_6_SHIFT) & CAN_WORD175_DATA_BYTE_6_MASK) +#define CAN_WORD175_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD175_DATA_BYTE_5_MASK (0xFF << CAN_WORD175_DATA_BYTE_5_SHIFT) +#define CAN_WORD175_DATA_BYTE_5(n) (((n) << CAN_WORD175_DATA_BYTE_5_SHIFT) & CAN_WORD175_DATA_BYTE_5_MASK) +#define CAN_WORD175_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD175_DATA_BYTE_4_MASK (0xFF << CAN_WORD175_DATA_BYTE_4_SHIFT) +#define CAN_WORD175_DATA_BYTE_4(n) (((n) << CAN_WORD175_DATA_BYTE_4_SHIFT) & CAN_WORD175_DATA_BYTE_4_MASK) + +/* Message Buffer 76 CS Register (CS76) */ +#define CAN_CS76_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS76_TIME_STAMP_MASK (0xFFFF << CAN_CS76_TIME_STAMP_SHIFT) +#define CAN_CS76_TIME_STAMP(n) (((n) << CAN_CS76_TIME_STAMP_SHIFT) & CAN_CS76_TIME_STAMP_MASK) +#define CAN_CS76_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS76_DLC_MASK (0xF << CAN_CS76_DLC_SHIFT) +#define CAN_CS76_DLC(n) (((n) << CAN_CS76_DLC_SHIFT) & CAN_CS76_DLC_MASK) +#define CAN_CS76_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS76_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS76_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS76_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS76_CODE_MASK (0xF << CAN_CS76_CODE_SHIFT) +#define CAN_CS76_CODE(n) (((n) << CAN_CS76_CODE_SHIFT) & CAN_CS76_CODE_MASK) +#define CAN_CS76_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS76_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS76_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 76 WORD0 Register (WORD076) */ +#define CAN_WORD076_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD076_DATA_BYTE_3_MASK (0xFF << CAN_WORD076_DATA_BYTE_3_SHIFT) +#define CAN_WORD076_DATA_BYTE_3(n) (((n) << CAN_WORD076_DATA_BYTE_3_SHIFT) & CAN_WORD076_DATA_BYTE_3_MASK) +#define CAN_WORD076_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD076_DATA_BYTE_2_MASK (0xFF << CAN_WORD076_DATA_BYTE_2_SHIFT) +#define CAN_WORD076_DATA_BYTE_2(n) (((n) << CAN_WORD076_DATA_BYTE_2_SHIFT) & CAN_WORD076_DATA_BYTE_2_MASK) +#define CAN_WORD076_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD076_DATA_BYTE_1_MASK (0xFF << CAN_WORD076_DATA_BYTE_1_SHIFT) +#define CAN_WORD076_DATA_BYTE_1(n) (((n) << CAN_WORD076_DATA_BYTE_1_SHIFT) & CAN_WORD076_DATA_BYTE_1_MASK) +#define CAN_WORD076_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD076_DATA_BYTE_0_MASK (0xFF << CAN_WORD076_DATA_BYTE_0_SHIFT) +#define CAN_WORD076_DATA_BYTE_0(n) (((n) << CAN_WORD076_DATA_BYTE_0_SHIFT) & CAN_WORD076_DATA_BYTE_0_MASK) + +/* Message Buffer 76 WORD1 Register (WORD176) */ +#define CAN_WORD176_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD176_DATA_BYTE_7_MASK (0xFF << CAN_WORD176_DATA_BYTE_7_SHIFT) +#define CAN_WORD176_DATA_BYTE_7(n) (((n) << CAN_WORD176_DATA_BYTE_7_SHIFT) & CAN_WORD176_DATA_BYTE_7_MASK) +#define CAN_WORD176_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD176_DATA_BYTE_6_MASK (0xFF << CAN_WORD176_DATA_BYTE_6_SHIFT) +#define CAN_WORD176_DATA_BYTE_6(n) (((n) << CAN_WORD176_DATA_BYTE_6_SHIFT) & CAN_WORD176_DATA_BYTE_6_MASK) +#define CAN_WORD176_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD176_DATA_BYTE_5_MASK (0xFF << CAN_WORD176_DATA_BYTE_5_SHIFT) +#define CAN_WORD176_DATA_BYTE_5(n) (((n) << CAN_WORD176_DATA_BYTE_5_SHIFT) & CAN_WORD176_DATA_BYTE_5_MASK) +#define CAN_WORD176_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD176_DATA_BYTE_4_MASK (0xFF << CAN_WORD176_DATA_BYTE_4_SHIFT) +#define CAN_WORD176_DATA_BYTE_4(n) (((n) << CAN_WORD176_DATA_BYTE_4_SHIFT) & CAN_WORD176_DATA_BYTE_4_MASK) + +/* Message Buffer 77 CS Register (CS77) */ +#define CAN_CS77_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS77_TIME_STAMP_MASK (0xFFFF << CAN_CS77_TIME_STAMP_SHIFT) +#define CAN_CS77_TIME_STAMP(n) (((n) << CAN_CS77_TIME_STAMP_SHIFT) & CAN_CS77_TIME_STAMP_MASK) +#define CAN_CS77_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS77_DLC_MASK (0xF << CAN_CS77_DLC_SHIFT) +#define CAN_CS77_DLC(n) (((n) << CAN_CS77_DLC_SHIFT) & CAN_CS77_DLC_MASK) +#define CAN_CS77_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS77_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS77_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS77_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS77_CODE_MASK (0xF << CAN_CS77_CODE_SHIFT) +#define CAN_CS77_CODE(n) (((n) << CAN_CS77_CODE_SHIFT) & CAN_CS77_CODE_MASK) +#define CAN_CS77_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS77_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS77_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 77 WORD0 Register (WORD077) */ +#define CAN_WORD077_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD077_DATA_BYTE_3_MASK (0xFF << CAN_WORD077_DATA_BYTE_3_SHIFT) +#define CAN_WORD077_DATA_BYTE_3(n) (((n) << CAN_WORD077_DATA_BYTE_3_SHIFT) & CAN_WORD077_DATA_BYTE_3_MASK) +#define CAN_WORD077_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD077_DATA_BYTE_2_MASK (0xFF << CAN_WORD077_DATA_BYTE_2_SHIFT) +#define CAN_WORD077_DATA_BYTE_2(n) (((n) << CAN_WORD077_DATA_BYTE_2_SHIFT) & CAN_WORD077_DATA_BYTE_2_MASK) +#define CAN_WORD077_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD077_DATA_BYTE_1_MASK (0xFF << CAN_WORD077_DATA_BYTE_1_SHIFT) +#define CAN_WORD077_DATA_BYTE_1(n) (((n) << CAN_WORD077_DATA_BYTE_1_SHIFT) & CAN_WORD077_DATA_BYTE_1_MASK) +#define CAN_WORD077_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD077_DATA_BYTE_0_MASK (0xFF << CAN_WORD077_DATA_BYTE_0_SHIFT) +#define CAN_WORD077_DATA_BYTE_0(n) (((n) << CAN_WORD077_DATA_BYTE_0_SHIFT) & CAN_WORD077_DATA_BYTE_0_MASK) + +/* Message Buffer 77 WORD1 Register (WORD177) */ +#define CAN_WORD177_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD177_DATA_BYTE_7_MASK (0xFF << CAN_WORD177_DATA_BYTE_7_SHIFT) +#define CAN_WORD177_DATA_BYTE_7(n) (((n) << CAN_WORD177_DATA_BYTE_7_SHIFT) & CAN_WORD177_DATA_BYTE_7_MASK) +#define CAN_WORD177_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD177_DATA_BYTE_6_MASK (0xFF << CAN_WORD177_DATA_BYTE_6_SHIFT) +#define CAN_WORD177_DATA_BYTE_6(n) (((n) << CAN_WORD177_DATA_BYTE_6_SHIFT) & CAN_WORD177_DATA_BYTE_6_MASK) +#define CAN_WORD177_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD177_DATA_BYTE_5_MASK (0xFF << CAN_WORD177_DATA_BYTE_5_SHIFT) +#define CAN_WORD177_DATA_BYTE_5(n) (((n) << CAN_WORD177_DATA_BYTE_5_SHIFT) & CAN_WORD177_DATA_BYTE_5_MASK) +#define CAN_WORD177_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD177_DATA_BYTE_4_MASK (0xFF << CAN_WORD177_DATA_BYTE_4_SHIFT) +#define CAN_WORD177_DATA_BYTE_4(n) (((n) << CAN_WORD177_DATA_BYTE_4_SHIFT) & CAN_WORD177_DATA_BYTE_4_MASK) + +/* Message Buffer 78 CS Register (CS78) */ +#define CAN_CS78_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS78_TIME_STAMP_MASK (0xFFFF << CAN_CS78_TIME_STAMP_SHIFT) +#define CAN_CS78_TIME_STAMP(n) (((n) << CAN_CS78_TIME_STAMP_SHIFT) & CAN_CS78_TIME_STAMP_MASK) +#define CAN_CS78_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS78_DLC_MASK (0xF << CAN_CS78_DLC_SHIFT) +#define CAN_CS78_DLC(n) (((n) << CAN_CS78_DLC_SHIFT) & CAN_CS78_DLC_MASK) +#define CAN_CS78_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS78_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS78_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS78_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS78_CODE_MASK (0xF << CAN_CS78_CODE_SHIFT) +#define CAN_CS78_CODE(n) (((n) << CAN_CS78_CODE_SHIFT) & CAN_CS78_CODE_MASK) +#define CAN_CS78_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS78_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS78_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 78 WORD0 Register (WORD078) */ +#define CAN_WORD078_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD078_DATA_BYTE_3_MASK (0xFF << CAN_WORD078_DATA_BYTE_3_SHIFT) +#define CAN_WORD078_DATA_BYTE_3(n) (((n) << CAN_WORD078_DATA_BYTE_3_SHIFT) & CAN_WORD078_DATA_BYTE_3_MASK) +#define CAN_WORD078_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD078_DATA_BYTE_2_MASK (0xFF << CAN_WORD078_DATA_BYTE_2_SHIFT) +#define CAN_WORD078_DATA_BYTE_2(n) (((n) << CAN_WORD078_DATA_BYTE_2_SHIFT) & CAN_WORD078_DATA_BYTE_2_MASK) +#define CAN_WORD078_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD078_DATA_BYTE_1_MASK (0xFF << CAN_WORD078_DATA_BYTE_1_SHIFT) +#define CAN_WORD078_DATA_BYTE_1(n) (((n) << CAN_WORD078_DATA_BYTE_1_SHIFT) & CAN_WORD078_DATA_BYTE_1_MASK) +#define CAN_WORD078_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD078_DATA_BYTE_0_MASK (0xFF << CAN_WORD078_DATA_BYTE_0_SHIFT) +#define CAN_WORD078_DATA_BYTE_0(n) (((n) << CAN_WORD078_DATA_BYTE_0_SHIFT) & CAN_WORD078_DATA_BYTE_0_MASK) + +/* Message Buffer 78 WORD1 Register (WORD178) */ +#define CAN_WORD178_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD178_DATA_BYTE_7_MASK (0xFF << CAN_WORD178_DATA_BYTE_7_SHIFT) +#define CAN_WORD178_DATA_BYTE_7(n) (((n) << CAN_WORD178_DATA_BYTE_7_SHIFT) & CAN_WORD178_DATA_BYTE_7_MASK) +#define CAN_WORD178_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD178_DATA_BYTE_6_MASK (0xFF << CAN_WORD178_DATA_BYTE_6_SHIFT) +#define CAN_WORD178_DATA_BYTE_6(n) (((n) << CAN_WORD178_DATA_BYTE_6_SHIFT) & CAN_WORD178_DATA_BYTE_6_MASK) +#define CAN_WORD178_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD178_DATA_BYTE_5_MASK (0xFF << CAN_WORD178_DATA_BYTE_5_SHIFT) +#define CAN_WORD178_DATA_BYTE_5(n) (((n) << CAN_WORD178_DATA_BYTE_5_SHIFT) & CAN_WORD178_DATA_BYTE_5_MASK) +#define CAN_WORD178_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD178_DATA_BYTE_4_MASK (0xFF << CAN_WORD178_DATA_BYTE_4_SHIFT) +#define CAN_WORD178_DATA_BYTE_4(n) (((n) << CAN_WORD178_DATA_BYTE_4_SHIFT) & CAN_WORD178_DATA_BYTE_4_MASK) + +/* Message Buffer 79 CS Register (CS79) */ +#define CAN_CS79_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS79_TIME_STAMP_MASK (0xFFFF << CAN_CS79_TIME_STAMP_SHIFT) +#define CAN_CS79_TIME_STAMP(n) (((n) << CAN_CS79_TIME_STAMP_SHIFT) & CAN_CS79_TIME_STAMP_MASK) +#define CAN_CS79_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS79_DLC_MASK (0xF << CAN_CS79_DLC_SHIFT) +#define CAN_CS79_DLC(n) (((n) << CAN_CS79_DLC_SHIFT) & CAN_CS79_DLC_MASK) +#define CAN_CS79_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS79_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS79_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS79_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS79_CODE_MASK (0xF << CAN_CS79_CODE_SHIFT) +#define CAN_CS79_CODE(n) (((n) << CAN_CS79_CODE_SHIFT) & CAN_CS79_CODE_MASK) +#define CAN_CS79_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS79_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS79_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 79 WORD0 Register (WORD079) */ +#define CAN_WORD079_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD079_DATA_BYTE_3_MASK (0xFF << CAN_WORD079_DATA_BYTE_3_SHIFT) +#define CAN_WORD079_DATA_BYTE_3(n) (((n) << CAN_WORD079_DATA_BYTE_3_SHIFT) & CAN_WORD079_DATA_BYTE_3_MASK) +#define CAN_WORD079_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD079_DATA_BYTE_2_MASK (0xFF << CAN_WORD079_DATA_BYTE_2_SHIFT) +#define CAN_WORD079_DATA_BYTE_2(n) (((n) << CAN_WORD079_DATA_BYTE_2_SHIFT) & CAN_WORD079_DATA_BYTE_2_MASK) +#define CAN_WORD079_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD079_DATA_BYTE_1_MASK (0xFF << CAN_WORD079_DATA_BYTE_1_SHIFT) +#define CAN_WORD079_DATA_BYTE_1(n) (((n) << CAN_WORD079_DATA_BYTE_1_SHIFT) & CAN_WORD079_DATA_BYTE_1_MASK) +#define CAN_WORD079_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD079_DATA_BYTE_0_MASK (0xFF << CAN_WORD079_DATA_BYTE_0_SHIFT) +#define CAN_WORD079_DATA_BYTE_0(n) (((n) << CAN_WORD079_DATA_BYTE_0_SHIFT) & CAN_WORD079_DATA_BYTE_0_MASK) + +/* Message Buffer 79 WORD1 Register (WORD179) */ +#define CAN_WORD179_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD179_DATA_BYTE_7_MASK (0xFF << CAN_WORD179_DATA_BYTE_7_SHIFT) +#define CAN_WORD179_DATA_BYTE_7(n) (((n) << CAN_WORD179_DATA_BYTE_7_SHIFT) & CAN_WORD179_DATA_BYTE_7_MASK) +#define CAN_WORD179_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD179_DATA_BYTE_6_MASK (0xFF << CAN_WORD179_DATA_BYTE_6_SHIFT) +#define CAN_WORD179_DATA_BYTE_6(n) (((n) << CAN_WORD179_DATA_BYTE_6_SHIFT) & CAN_WORD179_DATA_BYTE_6_MASK) +#define CAN_WORD179_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD179_DATA_BYTE_5_MASK (0xFF << CAN_WORD179_DATA_BYTE_5_SHIFT) +#define CAN_WORD179_DATA_BYTE_5(n) (((n) << CAN_WORD179_DATA_BYTE_5_SHIFT) & CAN_WORD179_DATA_BYTE_5_MASK) +#define CAN_WORD179_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD179_DATA_BYTE_4_MASK (0xFF << CAN_WORD179_DATA_BYTE_4_SHIFT) +#define CAN_WORD179_DATA_BYTE_4(n) (((n) << CAN_WORD179_DATA_BYTE_4_SHIFT) & CAN_WORD179_DATA_BYTE_4_MASK) + +/* Message Buffer 80 CS Register (CS80) */ +#define CAN_CS80_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS80_TIME_STAMP_MASK (0xFFFF << CAN_CS80_TIME_STAMP_SHIFT) +#define CAN_CS80_TIME_STAMP(n) (((n) << CAN_CS80_TIME_STAMP_SHIFT) & CAN_CS80_TIME_STAMP_MASK) +#define CAN_CS80_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS80_DLC_MASK (0xF << CAN_CS80_DLC_SHIFT) +#define CAN_CS80_DLC(n) (((n) << CAN_CS80_DLC_SHIFT) & CAN_CS80_DLC_MASK) +#define CAN_CS80_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS80_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS80_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS80_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS80_CODE_MASK (0xF << CAN_CS80_CODE_SHIFT) +#define CAN_CS80_CODE(n) (((n) << CAN_CS80_CODE_SHIFT) & CAN_CS80_CODE_MASK) +#define CAN_CS80_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS80_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS80_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 80 WORD0 Register (WORD080) */ +#define CAN_WORD080_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD080_DATA_BYTE_3_MASK (0xFF << CAN_WORD080_DATA_BYTE_3_SHIFT) +#define CAN_WORD080_DATA_BYTE_3(n) (((n) << CAN_WORD080_DATA_BYTE_3_SHIFT) & CAN_WORD080_DATA_BYTE_3_MASK) +#define CAN_WORD080_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD080_DATA_BYTE_2_MASK (0xFF << CAN_WORD080_DATA_BYTE_2_SHIFT) +#define CAN_WORD080_DATA_BYTE_2(n) (((n) << CAN_WORD080_DATA_BYTE_2_SHIFT) & CAN_WORD080_DATA_BYTE_2_MASK) +#define CAN_WORD080_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD080_DATA_BYTE_1_MASK (0xFF << CAN_WORD080_DATA_BYTE_1_SHIFT) +#define CAN_WORD080_DATA_BYTE_1(n) (((n) << CAN_WORD080_DATA_BYTE_1_SHIFT) & CAN_WORD080_DATA_BYTE_1_MASK) +#define CAN_WORD080_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD080_DATA_BYTE_0_MASK (0xFF << CAN_WORD080_DATA_BYTE_0_SHIFT) +#define CAN_WORD080_DATA_BYTE_0(n) (((n) << CAN_WORD080_DATA_BYTE_0_SHIFT) & CAN_WORD080_DATA_BYTE_0_MASK) + +/* Message Buffer 80 WORD1 Register (WORD180) */ +#define CAN_WORD180_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD180_DATA_BYTE_7_MASK (0xFF << CAN_WORD180_DATA_BYTE_7_SHIFT) +#define CAN_WORD180_DATA_BYTE_7(n) (((n) << CAN_WORD180_DATA_BYTE_7_SHIFT) & CAN_WORD180_DATA_BYTE_7_MASK) +#define CAN_WORD180_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD180_DATA_BYTE_6_MASK (0xFF << CAN_WORD180_DATA_BYTE_6_SHIFT) +#define CAN_WORD180_DATA_BYTE_6(n) (((n) << CAN_WORD180_DATA_BYTE_6_SHIFT) & CAN_WORD180_DATA_BYTE_6_MASK) +#define CAN_WORD180_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD180_DATA_BYTE_5_MASK (0xFF << CAN_WORD180_DATA_BYTE_5_SHIFT) +#define CAN_WORD180_DATA_BYTE_5(n) (((n) << CAN_WORD180_DATA_BYTE_5_SHIFT) & CAN_WORD180_DATA_BYTE_5_MASK) +#define CAN_WORD180_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD180_DATA_BYTE_4_MASK (0xFF << CAN_WORD180_DATA_BYTE_4_SHIFT) +#define CAN_WORD180_DATA_BYTE_4(n) (((n) << CAN_WORD180_DATA_BYTE_4_SHIFT) & CAN_WORD180_DATA_BYTE_4_MASK) + +/* Message Buffer 81 CS Register (CS81) */ +#define CAN_CS81_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS81_TIME_STAMP_MASK (0xFFFF << CAN_CS81_TIME_STAMP_SHIFT) +#define CAN_CS81_TIME_STAMP(n) (((n) << CAN_CS81_TIME_STAMP_SHIFT) & CAN_CS81_TIME_STAMP_MASK) +#define CAN_CS81_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS81_DLC_MASK (0xF << CAN_CS81_DLC_SHIFT) +#define CAN_CS81_DLC(n) (((n) << CAN_CS81_DLC_SHIFT) & CAN_CS81_DLC_MASK) +#define CAN_CS81_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS81_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS81_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS81_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS81_CODE_MASK (0xF << CAN_CS81_CODE_SHIFT) +#define CAN_CS81_CODE(n) (((n) << CAN_CS81_CODE_SHIFT) & CAN_CS81_CODE_MASK) +#define CAN_CS81_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS81_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS81_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 81 WORD0 Register (WORD081) */ +#define CAN_WORD081_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD081_DATA_BYTE_3_MASK (0xFF << CAN_WORD081_DATA_BYTE_3_SHIFT) +#define CAN_WORD081_DATA_BYTE_3(n) (((n) << CAN_WORD081_DATA_BYTE_3_SHIFT) & CAN_WORD081_DATA_BYTE_3_MASK) +#define CAN_WORD081_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD081_DATA_BYTE_2_MASK (0xFF << CAN_WORD081_DATA_BYTE_2_SHIFT) +#define CAN_WORD081_DATA_BYTE_2(n) (((n) << CAN_WORD081_DATA_BYTE_2_SHIFT) & CAN_WORD081_DATA_BYTE_2_MASK) +#define CAN_WORD081_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD081_DATA_BYTE_1_MASK (0xFF << CAN_WORD081_DATA_BYTE_1_SHIFT) +#define CAN_WORD081_DATA_BYTE_1(n) (((n) << CAN_WORD081_DATA_BYTE_1_SHIFT) & CAN_WORD081_DATA_BYTE_1_MASK) +#define CAN_WORD081_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD081_DATA_BYTE_0_MASK (0xFF << CAN_WORD081_DATA_BYTE_0_SHIFT) +#define CAN_WORD081_DATA_BYTE_0(n) (((n) << CAN_WORD081_DATA_BYTE_0_SHIFT) & CAN_WORD081_DATA_BYTE_0_MASK) + +/* Message Buffer 81 WORD1 Register (WORD181) */ +#define CAN_WORD181_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD181_DATA_BYTE_7_MASK (0xFF << CAN_WORD181_DATA_BYTE_7_SHIFT) +#define CAN_WORD181_DATA_BYTE_7(n) (((n) << CAN_WORD181_DATA_BYTE_7_SHIFT) & CAN_WORD181_DATA_BYTE_7_MASK) +#define CAN_WORD181_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD181_DATA_BYTE_6_MASK (0xFF << CAN_WORD181_DATA_BYTE_6_SHIFT) +#define CAN_WORD181_DATA_BYTE_6(n) (((n) << CAN_WORD181_DATA_BYTE_6_SHIFT) & CAN_WORD181_DATA_BYTE_6_MASK) +#define CAN_WORD181_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD181_DATA_BYTE_5_MASK (0xFF << CAN_WORD181_DATA_BYTE_5_SHIFT) +#define CAN_WORD181_DATA_BYTE_5(n) (((n) << CAN_WORD181_DATA_BYTE_5_SHIFT) & CAN_WORD181_DATA_BYTE_5_MASK) +#define CAN_WORD181_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD181_DATA_BYTE_4_MASK (0xFF << CAN_WORD181_DATA_BYTE_4_SHIFT) +#define CAN_WORD181_DATA_BYTE_4(n) (((n) << CAN_WORD181_DATA_BYTE_4_SHIFT) & CAN_WORD181_DATA_BYTE_4_MASK) + +/* Message Buffer 82 CS Register (CS82) */ +#define CAN_CS82_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS82_TIME_STAMP_MASK (0xFFFF << CAN_CS82_TIME_STAMP_SHIFT) +#define CAN_CS82_TIME_STAMP(n) (((n) << CAN_CS82_TIME_STAMP_SHIFT) & CAN_CS82_TIME_STAMP_MASK) +#define CAN_CS82_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS82_DLC_MASK (0xF << CAN_CS82_DLC_SHIFT) +#define CAN_CS82_DLC(n) (((n) << CAN_CS82_DLC_SHIFT) & CAN_CS82_DLC_MASK) +#define CAN_CS82_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS82_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS82_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS82_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS82_CODE_MASK (0xF << CAN_CS82_CODE_SHIFT) +#define CAN_CS82_CODE(n) (((n) << CAN_CS82_CODE_SHIFT) & CAN_CS82_CODE_MASK) +#define CAN_CS82_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS82_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS82_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 82 WORD0 Register (WORD082) */ +#define CAN_WORD082_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD082_DATA_BYTE_3_MASK (0xFF << CAN_WORD082_DATA_BYTE_3_SHIFT) +#define CAN_WORD082_DATA_BYTE_3(n) (((n) << CAN_WORD082_DATA_BYTE_3_SHIFT) & CAN_WORD082_DATA_BYTE_3_MASK) +#define CAN_WORD082_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD082_DATA_BYTE_2_MASK (0xFF << CAN_WORD082_DATA_BYTE_2_SHIFT) +#define CAN_WORD082_DATA_BYTE_2(n) (((n) << CAN_WORD082_DATA_BYTE_2_SHIFT) & CAN_WORD082_DATA_BYTE_2_MASK) +#define CAN_WORD082_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD082_DATA_BYTE_1_MASK (0xFF << CAN_WORD082_DATA_BYTE_1_SHIFT) +#define CAN_WORD082_DATA_BYTE_1(n) (((n) << CAN_WORD082_DATA_BYTE_1_SHIFT) & CAN_WORD082_DATA_BYTE_1_MASK) +#define CAN_WORD082_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD082_DATA_BYTE_0_MASK (0xFF << CAN_WORD082_DATA_BYTE_0_SHIFT) +#define CAN_WORD082_DATA_BYTE_0(n) (((n) << CAN_WORD082_DATA_BYTE_0_SHIFT) & CAN_WORD082_DATA_BYTE_0_MASK) + +/* Message Buffer 82 WORD1 Register (WORD182) */ +#define CAN_WORD182_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD182_DATA_BYTE_7_MASK (0xFF << CAN_WORD182_DATA_BYTE_7_SHIFT) +#define CAN_WORD182_DATA_BYTE_7(n) (((n) << CAN_WORD182_DATA_BYTE_7_SHIFT) & CAN_WORD182_DATA_BYTE_7_MASK) +#define CAN_WORD182_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD182_DATA_BYTE_6_MASK (0xFF << CAN_WORD182_DATA_BYTE_6_SHIFT) +#define CAN_WORD182_DATA_BYTE_6(n) (((n) << CAN_WORD182_DATA_BYTE_6_SHIFT) & CAN_WORD182_DATA_BYTE_6_MASK) +#define CAN_WORD182_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD182_DATA_BYTE_5_MASK (0xFF << CAN_WORD182_DATA_BYTE_5_SHIFT) +#define CAN_WORD182_DATA_BYTE_5(n) (((n) << CAN_WORD182_DATA_BYTE_5_SHIFT) & CAN_WORD182_DATA_BYTE_5_MASK) +#define CAN_WORD182_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD182_DATA_BYTE_4_MASK (0xFF << CAN_WORD182_DATA_BYTE_4_SHIFT) +#define CAN_WORD182_DATA_BYTE_4(n) (((n) << CAN_WORD182_DATA_BYTE_4_SHIFT) & CAN_WORD182_DATA_BYTE_4_MASK) + +/* Message Buffer 83 CS Register (CS83) */ +#define CAN_CS83_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS83_TIME_STAMP_MASK (0xFFFF << CAN_CS83_TIME_STAMP_SHIFT) +#define CAN_CS83_TIME_STAMP(n) (((n) << CAN_CS83_TIME_STAMP_SHIFT) & CAN_CS83_TIME_STAMP_MASK) +#define CAN_CS83_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS83_DLC_MASK (0xF << CAN_CS83_DLC_SHIFT) +#define CAN_CS83_DLC(n) (((n) << CAN_CS83_DLC_SHIFT) & CAN_CS83_DLC_MASK) +#define CAN_CS83_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS83_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS83_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS83_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS83_CODE_MASK (0xF << CAN_CS83_CODE_SHIFT) +#define CAN_CS83_CODE(n) (((n) << CAN_CS83_CODE_SHIFT) & CAN_CS83_CODE_MASK) +#define CAN_CS83_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS83_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS83_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 83 WORD0 Register (WORD083) */ +#define CAN_WORD083_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD083_DATA_BYTE_3_MASK (0xFF << CAN_WORD083_DATA_BYTE_3_SHIFT) +#define CAN_WORD083_DATA_BYTE_3(n) (((n) << CAN_WORD083_DATA_BYTE_3_SHIFT) & CAN_WORD083_DATA_BYTE_3_MASK) +#define CAN_WORD083_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD083_DATA_BYTE_2_MASK (0xFF << CAN_WORD083_DATA_BYTE_2_SHIFT) +#define CAN_WORD083_DATA_BYTE_2(n) (((n) << CAN_WORD083_DATA_BYTE_2_SHIFT) & CAN_WORD083_DATA_BYTE_2_MASK) +#define CAN_WORD083_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD083_DATA_BYTE_1_MASK (0xFF << CAN_WORD083_DATA_BYTE_1_SHIFT) +#define CAN_WORD083_DATA_BYTE_1(n) (((n) << CAN_WORD083_DATA_BYTE_1_SHIFT) & CAN_WORD083_DATA_BYTE_1_MASK) +#define CAN_WORD083_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD083_DATA_BYTE_0_MASK (0xFF << CAN_WORD083_DATA_BYTE_0_SHIFT) +#define CAN_WORD083_DATA_BYTE_0(n) (((n) << CAN_WORD083_DATA_BYTE_0_SHIFT) & CAN_WORD083_DATA_BYTE_0_MASK) + +/* Message Buffer 83 WORD1 Register (WORD183) */ +#define CAN_WORD183_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD183_DATA_BYTE_7_MASK (0xFF << CAN_WORD183_DATA_BYTE_7_SHIFT) +#define CAN_WORD183_DATA_BYTE_7(n) (((n) << CAN_WORD183_DATA_BYTE_7_SHIFT) & CAN_WORD183_DATA_BYTE_7_MASK) +#define CAN_WORD183_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD183_DATA_BYTE_6_MASK (0xFF << CAN_WORD183_DATA_BYTE_6_SHIFT) +#define CAN_WORD183_DATA_BYTE_6(n) (((n) << CAN_WORD183_DATA_BYTE_6_SHIFT) & CAN_WORD183_DATA_BYTE_6_MASK) +#define CAN_WORD183_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD183_DATA_BYTE_5_MASK (0xFF << CAN_WORD183_DATA_BYTE_5_SHIFT) +#define CAN_WORD183_DATA_BYTE_5(n) (((n) << CAN_WORD183_DATA_BYTE_5_SHIFT) & CAN_WORD183_DATA_BYTE_5_MASK) +#define CAN_WORD183_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD183_DATA_BYTE_4_MASK (0xFF << CAN_WORD183_DATA_BYTE_4_SHIFT) +#define CAN_WORD183_DATA_BYTE_4(n) (((n) << CAN_WORD183_DATA_BYTE_4_SHIFT) & CAN_WORD183_DATA_BYTE_4_MASK) + +/* Message Buffer 84 CS Register (CS84) */ +#define CAN_CS84_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS84_TIME_STAMP_MASK (0xFFFF << CAN_CS84_TIME_STAMP_SHIFT) +#define CAN_CS84_TIME_STAMP(n) (((n) << CAN_CS84_TIME_STAMP_SHIFT) & CAN_CS84_TIME_STAMP_MASK) +#define CAN_CS84_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS84_DLC_MASK (0xF << CAN_CS84_DLC_SHIFT) +#define CAN_CS84_DLC(n) (((n) << CAN_CS84_DLC_SHIFT) & CAN_CS84_DLC_MASK) +#define CAN_CS84_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS84_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS84_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS84_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS84_CODE_MASK (0xF << CAN_CS84_CODE_SHIFT) +#define CAN_CS84_CODE(n) (((n) << CAN_CS84_CODE_SHIFT) & CAN_CS84_CODE_MASK) +#define CAN_CS84_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS84_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS84_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 84 WORD0 Register (WORD084) */ +#define CAN_WORD084_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD084_DATA_BYTE_3_MASK (0xFF << CAN_WORD084_DATA_BYTE_3_SHIFT) +#define CAN_WORD084_DATA_BYTE_3(n) (((n) << CAN_WORD084_DATA_BYTE_3_SHIFT) & CAN_WORD084_DATA_BYTE_3_MASK) +#define CAN_WORD084_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD084_DATA_BYTE_2_MASK (0xFF << CAN_WORD084_DATA_BYTE_2_SHIFT) +#define CAN_WORD084_DATA_BYTE_2(n) (((n) << CAN_WORD084_DATA_BYTE_2_SHIFT) & CAN_WORD084_DATA_BYTE_2_MASK) +#define CAN_WORD084_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD084_DATA_BYTE_1_MASK (0xFF << CAN_WORD084_DATA_BYTE_1_SHIFT) +#define CAN_WORD084_DATA_BYTE_1(n) (((n) << CAN_WORD084_DATA_BYTE_1_SHIFT) & CAN_WORD084_DATA_BYTE_1_MASK) +#define CAN_WORD084_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD084_DATA_BYTE_0_MASK (0xFF << CAN_WORD084_DATA_BYTE_0_SHIFT) +#define CAN_WORD084_DATA_BYTE_0(n) (((n) << CAN_WORD084_DATA_BYTE_0_SHIFT) & CAN_WORD084_DATA_BYTE_0_MASK) + +/* Message Buffer 84 WORD1 Register (WORD184) */ +#define CAN_WORD184_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD184_DATA_BYTE_7_MASK (0xFF << CAN_WORD184_DATA_BYTE_7_SHIFT) +#define CAN_WORD184_DATA_BYTE_7(n) (((n) << CAN_WORD184_DATA_BYTE_7_SHIFT) & CAN_WORD184_DATA_BYTE_7_MASK) +#define CAN_WORD184_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD184_DATA_BYTE_6_MASK (0xFF << CAN_WORD184_DATA_BYTE_6_SHIFT) +#define CAN_WORD184_DATA_BYTE_6(n) (((n) << CAN_WORD184_DATA_BYTE_6_SHIFT) & CAN_WORD184_DATA_BYTE_6_MASK) +#define CAN_WORD184_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD184_DATA_BYTE_5_MASK (0xFF << CAN_WORD184_DATA_BYTE_5_SHIFT) +#define CAN_WORD184_DATA_BYTE_5(n) (((n) << CAN_WORD184_DATA_BYTE_5_SHIFT) & CAN_WORD184_DATA_BYTE_5_MASK) +#define CAN_WORD184_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD184_DATA_BYTE_4_MASK (0xFF << CAN_WORD184_DATA_BYTE_4_SHIFT) +#define CAN_WORD184_DATA_BYTE_4(n) (((n) << CAN_WORD184_DATA_BYTE_4_SHIFT) & CAN_WORD184_DATA_BYTE_4_MASK) + +/* Message Buffer 85 CS Register (CS85) */ +#define CAN_CS85_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS85_TIME_STAMP_MASK (0xFFFF << CAN_CS85_TIME_STAMP_SHIFT) +#define CAN_CS85_TIME_STAMP(n) (((n) << CAN_CS85_TIME_STAMP_SHIFT) & CAN_CS85_TIME_STAMP_MASK) +#define CAN_CS85_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS85_DLC_MASK (0xF << CAN_CS85_DLC_SHIFT) +#define CAN_CS85_DLC(n) (((n) << CAN_CS85_DLC_SHIFT) & CAN_CS85_DLC_MASK) +#define CAN_CS85_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS85_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS85_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS85_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS85_CODE_MASK (0xF << CAN_CS85_CODE_SHIFT) +#define CAN_CS85_CODE(n) (((n) << CAN_CS85_CODE_SHIFT) & CAN_CS85_CODE_MASK) +#define CAN_CS85_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS85_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS85_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 85 WORD0 Register (WORD085) */ +#define CAN_WORD085_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD085_DATA_BYTE_3_MASK (0xFF << CAN_WORD085_DATA_BYTE_3_SHIFT) +#define CAN_WORD085_DATA_BYTE_3(n) (((n) << CAN_WORD085_DATA_BYTE_3_SHIFT) & CAN_WORD085_DATA_BYTE_3_MASK) +#define CAN_WORD085_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD085_DATA_BYTE_2_MASK (0xFF << CAN_WORD085_DATA_BYTE_2_SHIFT) +#define CAN_WORD085_DATA_BYTE_2(n) (((n) << CAN_WORD085_DATA_BYTE_2_SHIFT) & CAN_WORD085_DATA_BYTE_2_MASK) +#define CAN_WORD085_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD085_DATA_BYTE_1_MASK (0xFF << CAN_WORD085_DATA_BYTE_1_SHIFT) +#define CAN_WORD085_DATA_BYTE_1(n) (((n) << CAN_WORD085_DATA_BYTE_1_SHIFT) & CAN_WORD085_DATA_BYTE_1_MASK) +#define CAN_WORD085_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD085_DATA_BYTE_0_MASK (0xFF << CAN_WORD085_DATA_BYTE_0_SHIFT) +#define CAN_WORD085_DATA_BYTE_0(n) (((n) << CAN_WORD085_DATA_BYTE_0_SHIFT) & CAN_WORD085_DATA_BYTE_0_MASK) + +/* Message Buffer 85 WORD1 Register (WORD185) */ +#define CAN_WORD185_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD185_DATA_BYTE_7_MASK (0xFF << CAN_WORD185_DATA_BYTE_7_SHIFT) +#define CAN_WORD185_DATA_BYTE_7(n) (((n) << CAN_WORD185_DATA_BYTE_7_SHIFT) & CAN_WORD185_DATA_BYTE_7_MASK) +#define CAN_WORD185_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD185_DATA_BYTE_6_MASK (0xFF << CAN_WORD185_DATA_BYTE_6_SHIFT) +#define CAN_WORD185_DATA_BYTE_6(n) (((n) << CAN_WORD185_DATA_BYTE_6_SHIFT) & CAN_WORD185_DATA_BYTE_6_MASK) +#define CAN_WORD185_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD185_DATA_BYTE_5_MASK (0xFF << CAN_WORD185_DATA_BYTE_5_SHIFT) +#define CAN_WORD185_DATA_BYTE_5(n) (((n) << CAN_WORD185_DATA_BYTE_5_SHIFT) & CAN_WORD185_DATA_BYTE_5_MASK) +#define CAN_WORD185_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD185_DATA_BYTE_4_MASK (0xFF << CAN_WORD185_DATA_BYTE_4_SHIFT) +#define CAN_WORD185_DATA_BYTE_4(n) (((n) << CAN_WORD185_DATA_BYTE_4_SHIFT) & CAN_WORD185_DATA_BYTE_4_MASK) + +/* Message Buffer 86 CS Register (CS86) */ +#define CAN_CS86_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS86_TIME_STAMP_MASK (0xFFFF << CAN_CS86_TIME_STAMP_SHIFT) +#define CAN_CS86_TIME_STAMP(n) (((n) << CAN_CS86_TIME_STAMP_SHIFT) & CAN_CS86_TIME_STAMP_MASK) +#define CAN_CS86_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS86_DLC_MASK (0xF << CAN_CS86_DLC_SHIFT) +#define CAN_CS86_DLC(n) (((n) << CAN_CS86_DLC_SHIFT) & CAN_CS86_DLC_MASK) +#define CAN_CS86_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS86_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS86_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS86_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS86_CODE_MASK (0xF << CAN_CS86_CODE_SHIFT) +#define CAN_CS86_CODE(n) (((n) << CAN_CS86_CODE_SHIFT) & CAN_CS86_CODE_MASK) +#define CAN_CS86_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS86_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS86_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 86 WORD0 Register (WORD086) */ +#define CAN_WORD086_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD086_DATA_BYTE_3_MASK (0xFF << CAN_WORD086_DATA_BYTE_3_SHIFT) +#define CAN_WORD086_DATA_BYTE_3(n) (((n) << CAN_WORD086_DATA_BYTE_3_SHIFT) & CAN_WORD086_DATA_BYTE_3_MASK) +#define CAN_WORD086_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD086_DATA_BYTE_2_MASK (0xFF << CAN_WORD086_DATA_BYTE_2_SHIFT) +#define CAN_WORD086_DATA_BYTE_2(n) (((n) << CAN_WORD086_DATA_BYTE_2_SHIFT) & CAN_WORD086_DATA_BYTE_2_MASK) +#define CAN_WORD086_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD086_DATA_BYTE_1_MASK (0xFF << CAN_WORD086_DATA_BYTE_1_SHIFT) +#define CAN_WORD086_DATA_BYTE_1(n) (((n) << CAN_WORD086_DATA_BYTE_1_SHIFT) & CAN_WORD086_DATA_BYTE_1_MASK) +#define CAN_WORD086_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD086_DATA_BYTE_0_MASK (0xFF << CAN_WORD086_DATA_BYTE_0_SHIFT) +#define CAN_WORD086_DATA_BYTE_0(n) (((n) << CAN_WORD086_DATA_BYTE_0_SHIFT) & CAN_WORD086_DATA_BYTE_0_MASK) + +/* Message Buffer 86 WORD1 Register (WORD186) */ +#define CAN_WORD186_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD186_DATA_BYTE_7_MASK (0xFF << CAN_WORD186_DATA_BYTE_7_SHIFT) +#define CAN_WORD186_DATA_BYTE_7(n) (((n) << CAN_WORD186_DATA_BYTE_7_SHIFT) & CAN_WORD186_DATA_BYTE_7_MASK) +#define CAN_WORD186_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD186_DATA_BYTE_6_MASK (0xFF << CAN_WORD186_DATA_BYTE_6_SHIFT) +#define CAN_WORD186_DATA_BYTE_6(n) (((n) << CAN_WORD186_DATA_BYTE_6_SHIFT) & CAN_WORD186_DATA_BYTE_6_MASK) +#define CAN_WORD186_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD186_DATA_BYTE_5_MASK (0xFF << CAN_WORD186_DATA_BYTE_5_SHIFT) +#define CAN_WORD186_DATA_BYTE_5(n) (((n) << CAN_WORD186_DATA_BYTE_5_SHIFT) & CAN_WORD186_DATA_BYTE_5_MASK) +#define CAN_WORD186_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD186_DATA_BYTE_4_MASK (0xFF << CAN_WORD186_DATA_BYTE_4_SHIFT) +#define CAN_WORD186_DATA_BYTE_4(n) (((n) << CAN_WORD186_DATA_BYTE_4_SHIFT) & CAN_WORD186_DATA_BYTE_4_MASK) + +/* Message Buffer 87 CS Register (CS87) */ +#define CAN_CS87_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS87_TIME_STAMP_MASK (0xFFFF << CAN_CS87_TIME_STAMP_SHIFT) +#define CAN_CS87_TIME_STAMP(n) (((n) << CAN_CS87_TIME_STAMP_SHIFT) & CAN_CS87_TIME_STAMP_MASK) +#define CAN_CS87_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS87_DLC_MASK (0xF << CAN_CS87_DLC_SHIFT) +#define CAN_CS87_DLC(n) (((n) << CAN_CS87_DLC_SHIFT) & CAN_CS87_DLC_MASK) +#define CAN_CS87_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS87_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS87_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS87_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS87_CODE_MASK (0xF << CAN_CS87_CODE_SHIFT) +#define CAN_CS87_CODE(n) (((n) << CAN_CS87_CODE_SHIFT) & CAN_CS87_CODE_MASK) +#define CAN_CS87_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS87_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS87_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 87 WORD0 Register (WORD087) */ +#define CAN_WORD087_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD087_DATA_BYTE_3_MASK (0xFF << CAN_WORD087_DATA_BYTE_3_SHIFT) +#define CAN_WORD087_DATA_BYTE_3(n) (((n) << CAN_WORD087_DATA_BYTE_3_SHIFT) & CAN_WORD087_DATA_BYTE_3_MASK) +#define CAN_WORD087_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD087_DATA_BYTE_2_MASK (0xFF << CAN_WORD087_DATA_BYTE_2_SHIFT) +#define CAN_WORD087_DATA_BYTE_2(n) (((n) << CAN_WORD087_DATA_BYTE_2_SHIFT) & CAN_WORD087_DATA_BYTE_2_MASK) +#define CAN_WORD087_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD087_DATA_BYTE_1_MASK (0xFF << CAN_WORD087_DATA_BYTE_1_SHIFT) +#define CAN_WORD087_DATA_BYTE_1(n) (((n) << CAN_WORD087_DATA_BYTE_1_SHIFT) & CAN_WORD087_DATA_BYTE_1_MASK) +#define CAN_WORD087_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD087_DATA_BYTE_0_MASK (0xFF << CAN_WORD087_DATA_BYTE_0_SHIFT) +#define CAN_WORD087_DATA_BYTE_0(n) (((n) << CAN_WORD087_DATA_BYTE_0_SHIFT) & CAN_WORD087_DATA_BYTE_0_MASK) + +/* Message Buffer 87 WORD1 Register (WORD187) */ +#define CAN_WORD187_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD187_DATA_BYTE_7_MASK (0xFF << CAN_WORD187_DATA_BYTE_7_SHIFT) +#define CAN_WORD187_DATA_BYTE_7(n) (((n) << CAN_WORD187_DATA_BYTE_7_SHIFT) & CAN_WORD187_DATA_BYTE_7_MASK) +#define CAN_WORD187_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD187_DATA_BYTE_6_MASK (0xFF << CAN_WORD187_DATA_BYTE_6_SHIFT) +#define CAN_WORD187_DATA_BYTE_6(n) (((n) << CAN_WORD187_DATA_BYTE_6_SHIFT) & CAN_WORD187_DATA_BYTE_6_MASK) +#define CAN_WORD187_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD187_DATA_BYTE_5_MASK (0xFF << CAN_WORD187_DATA_BYTE_5_SHIFT) +#define CAN_WORD187_DATA_BYTE_5(n) (((n) << CAN_WORD187_DATA_BYTE_5_SHIFT) & CAN_WORD187_DATA_BYTE_5_MASK) +#define CAN_WORD187_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD187_DATA_BYTE_4_MASK (0xFF << CAN_WORD187_DATA_BYTE_4_SHIFT) +#define CAN_WORD187_DATA_BYTE_4(n) (((n) << CAN_WORD187_DATA_BYTE_4_SHIFT) & CAN_WORD187_DATA_BYTE_4_MASK) + +/* Message Buffer 88 CS Register (CS88) */ +#define CAN_CS88_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS88_TIME_STAMP_MASK (0xFFFF << CAN_CS88_TIME_STAMP_SHIFT) +#define CAN_CS88_TIME_STAMP(n) (((n) << CAN_CS88_TIME_STAMP_SHIFT) & CAN_CS88_TIME_STAMP_MASK) +#define CAN_CS88_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS88_DLC_MASK (0xF << CAN_CS88_DLC_SHIFT) +#define CAN_CS88_DLC(n) (((n) << CAN_CS88_DLC_SHIFT) & CAN_CS88_DLC_MASK) +#define CAN_CS88_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS88_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS88_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS88_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS88_CODE_MASK (0xF << CAN_CS88_CODE_SHIFT) +#define CAN_CS88_CODE(n) (((n) << CAN_CS88_CODE_SHIFT) & CAN_CS88_CODE_MASK) +#define CAN_CS88_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS88_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS88_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 88 WORD0 Register (WORD088) */ +#define CAN_WORD088_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD088_DATA_BYTE_3_MASK (0xFF << CAN_WORD088_DATA_BYTE_3_SHIFT) +#define CAN_WORD088_DATA_BYTE_3(n) (((n) << CAN_WORD088_DATA_BYTE_3_SHIFT) & CAN_WORD088_DATA_BYTE_3_MASK) +#define CAN_WORD088_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD088_DATA_BYTE_2_MASK (0xFF << CAN_WORD088_DATA_BYTE_2_SHIFT) +#define CAN_WORD088_DATA_BYTE_2(n) (((n) << CAN_WORD088_DATA_BYTE_2_SHIFT) & CAN_WORD088_DATA_BYTE_2_MASK) +#define CAN_WORD088_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD088_DATA_BYTE_1_MASK (0xFF << CAN_WORD088_DATA_BYTE_1_SHIFT) +#define CAN_WORD088_DATA_BYTE_1(n) (((n) << CAN_WORD088_DATA_BYTE_1_SHIFT) & CAN_WORD088_DATA_BYTE_1_MASK) +#define CAN_WORD088_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD088_DATA_BYTE_0_MASK (0xFF << CAN_WORD088_DATA_BYTE_0_SHIFT) +#define CAN_WORD088_DATA_BYTE_0(n) (((n) << CAN_WORD088_DATA_BYTE_0_SHIFT) & CAN_WORD088_DATA_BYTE_0_MASK) + +/* Message Buffer 88 WORD1 Register (WORD188) */ +#define CAN_WORD188_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD188_DATA_BYTE_7_MASK (0xFF << CAN_WORD188_DATA_BYTE_7_SHIFT) +#define CAN_WORD188_DATA_BYTE_7(n) (((n) << CAN_WORD188_DATA_BYTE_7_SHIFT) & CAN_WORD188_DATA_BYTE_7_MASK) +#define CAN_WORD188_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD188_DATA_BYTE_6_MASK (0xFF << CAN_WORD188_DATA_BYTE_6_SHIFT) +#define CAN_WORD188_DATA_BYTE_6(n) (((n) << CAN_WORD188_DATA_BYTE_6_SHIFT) & CAN_WORD188_DATA_BYTE_6_MASK) +#define CAN_WORD188_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD188_DATA_BYTE_5_MASK (0xFF << CAN_WORD188_DATA_BYTE_5_SHIFT) +#define CAN_WORD188_DATA_BYTE_5(n) (((n) << CAN_WORD188_DATA_BYTE_5_SHIFT) & CAN_WORD188_DATA_BYTE_5_MASK) +#define CAN_WORD188_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD188_DATA_BYTE_4_MASK (0xFF << CAN_WORD188_DATA_BYTE_4_SHIFT) +#define CAN_WORD188_DATA_BYTE_4(n) (((n) << CAN_WORD188_DATA_BYTE_4_SHIFT) & CAN_WORD188_DATA_BYTE_4_MASK) + +/* Message Buffer 89 CS Register (CS89) */ +#define CAN_CS89_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS89_TIME_STAMP_MASK (0xFFFF << CAN_CS89_TIME_STAMP_SHIFT) +#define CAN_CS89_TIME_STAMP(n) (((n) << CAN_CS89_TIME_STAMP_SHIFT) & CAN_CS89_TIME_STAMP_MASK) +#define CAN_CS89_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS89_DLC_MASK (0xF << CAN_CS89_DLC_SHIFT) +#define CAN_CS89_DLC(n) (((n) << CAN_CS89_DLC_SHIFT) & CAN_CS89_DLC_MASK) +#define CAN_CS89_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS89_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS89_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS89_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS89_CODE_MASK (0xF << CAN_CS89_CODE_SHIFT) +#define CAN_CS89_CODE(n) (((n) << CAN_CS89_CODE_SHIFT) & CAN_CS89_CODE_MASK) +#define CAN_CS89_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS89_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS89_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 89 WORD0 Register (WORD089) */ +#define CAN_WORD089_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD089_DATA_BYTE_3_MASK (0xFF << CAN_WORD089_DATA_BYTE_3_SHIFT) +#define CAN_WORD089_DATA_BYTE_3(n) (((n) << CAN_WORD089_DATA_BYTE_3_SHIFT) & CAN_WORD089_DATA_BYTE_3_MASK) +#define CAN_WORD089_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD089_DATA_BYTE_2_MASK (0xFF << CAN_WORD089_DATA_BYTE_2_SHIFT) +#define CAN_WORD089_DATA_BYTE_2(n) (((n) << CAN_WORD089_DATA_BYTE_2_SHIFT) & CAN_WORD089_DATA_BYTE_2_MASK) +#define CAN_WORD089_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD089_DATA_BYTE_1_MASK (0xFF << CAN_WORD089_DATA_BYTE_1_SHIFT) +#define CAN_WORD089_DATA_BYTE_1(n) (((n) << CAN_WORD089_DATA_BYTE_1_SHIFT) & CAN_WORD089_DATA_BYTE_1_MASK) +#define CAN_WORD089_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD089_DATA_BYTE_0_MASK (0xFF << CAN_WORD089_DATA_BYTE_0_SHIFT) +#define CAN_WORD089_DATA_BYTE_0(n) (((n) << CAN_WORD089_DATA_BYTE_0_SHIFT) & CAN_WORD089_DATA_BYTE_0_MASK) + +/* Message Buffer 89 WORD1 Register (WORD189) */ +#define CAN_WORD189_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD189_DATA_BYTE_7_MASK (0xFF << CAN_WORD189_DATA_BYTE_7_SHIFT) +#define CAN_WORD189_DATA_BYTE_7(n) (((n) << CAN_WORD189_DATA_BYTE_7_SHIFT) & CAN_WORD189_DATA_BYTE_7_MASK) +#define CAN_WORD189_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD189_DATA_BYTE_6_MASK (0xFF << CAN_WORD189_DATA_BYTE_6_SHIFT) +#define CAN_WORD189_DATA_BYTE_6(n) (((n) << CAN_WORD189_DATA_BYTE_6_SHIFT) & CAN_WORD189_DATA_BYTE_6_MASK) +#define CAN_WORD189_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD189_DATA_BYTE_5_MASK (0xFF << CAN_WORD189_DATA_BYTE_5_SHIFT) +#define CAN_WORD189_DATA_BYTE_5(n) (((n) << CAN_WORD189_DATA_BYTE_5_SHIFT) & CAN_WORD189_DATA_BYTE_5_MASK) +#define CAN_WORD189_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD189_DATA_BYTE_4_MASK (0xFF << CAN_WORD189_DATA_BYTE_4_SHIFT) +#define CAN_WORD189_DATA_BYTE_4(n) (((n) << CAN_WORD189_DATA_BYTE_4_SHIFT) & CAN_WORD189_DATA_BYTE_4_MASK) + +/* Message Buffer 90 CS Register (CS90) */ +#define CAN_CS90_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS90_TIME_STAMP_MASK (0xFFFF << CAN_CS90_TIME_STAMP_SHIFT) +#define CAN_CS90_TIME_STAMP(n) (((n) << CAN_CS90_TIME_STAMP_SHIFT) & CAN_CS90_TIME_STAMP_MASK) +#define CAN_CS90_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS90_DLC_MASK (0xF << CAN_CS90_DLC_SHIFT) +#define CAN_CS90_DLC(n) (((n) << CAN_CS90_DLC_SHIFT) & CAN_CS90_DLC_MASK) +#define CAN_CS90_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS90_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS90_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS90_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS90_CODE_MASK (0xF << CAN_CS90_CODE_SHIFT) +#define CAN_CS90_CODE(n) (((n) << CAN_CS90_CODE_SHIFT) & CAN_CS90_CODE_MASK) +#define CAN_CS90_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS90_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS90_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 90 WORD0 Register (WORD090) */ +#define CAN_WORD090_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD090_DATA_BYTE_3_MASK (0xFF << CAN_WORD090_DATA_BYTE_3_SHIFT) +#define CAN_WORD090_DATA_BYTE_3(n) (((n) << CAN_WORD090_DATA_BYTE_3_SHIFT) & CAN_WORD090_DATA_BYTE_3_MASK) +#define CAN_WORD090_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD090_DATA_BYTE_2_MASK (0xFF << CAN_WORD090_DATA_BYTE_2_SHIFT) +#define CAN_WORD090_DATA_BYTE_2(n) (((n) << CAN_WORD090_DATA_BYTE_2_SHIFT) & CAN_WORD090_DATA_BYTE_2_MASK) +#define CAN_WORD090_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD090_DATA_BYTE_1_MASK (0xFF << CAN_WORD090_DATA_BYTE_1_SHIFT) +#define CAN_WORD090_DATA_BYTE_1(n) (((n) << CAN_WORD090_DATA_BYTE_1_SHIFT) & CAN_WORD090_DATA_BYTE_1_MASK) +#define CAN_WORD090_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD090_DATA_BYTE_0_MASK (0xFF << CAN_WORD090_DATA_BYTE_0_SHIFT) +#define CAN_WORD090_DATA_BYTE_0(n) (((n) << CAN_WORD090_DATA_BYTE_0_SHIFT) & CAN_WORD090_DATA_BYTE_0_MASK) + +/* Message Buffer 90 WORD1 Register (WORD190) */ +#define CAN_WORD190_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD190_DATA_BYTE_7_MASK (0xFF << CAN_WORD190_DATA_BYTE_7_SHIFT) +#define CAN_WORD190_DATA_BYTE_7(n) (((n) << CAN_WORD190_DATA_BYTE_7_SHIFT) & CAN_WORD190_DATA_BYTE_7_MASK) +#define CAN_WORD190_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD190_DATA_BYTE_6_MASK (0xFF << CAN_WORD190_DATA_BYTE_6_SHIFT) +#define CAN_WORD190_DATA_BYTE_6(n) (((n) << CAN_WORD190_DATA_BYTE_6_SHIFT) & CAN_WORD190_DATA_BYTE_6_MASK) +#define CAN_WORD190_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD190_DATA_BYTE_5_MASK (0xFF << CAN_WORD190_DATA_BYTE_5_SHIFT) +#define CAN_WORD190_DATA_BYTE_5(n) (((n) << CAN_WORD190_DATA_BYTE_5_SHIFT) & CAN_WORD190_DATA_BYTE_5_MASK) +#define CAN_WORD190_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD190_DATA_BYTE_4_MASK (0xFF << CAN_WORD190_DATA_BYTE_4_SHIFT) +#define CAN_WORD190_DATA_BYTE_4(n) (((n) << CAN_WORD190_DATA_BYTE_4_SHIFT) & CAN_WORD190_DATA_BYTE_4_MASK) + +/* Message Buffer 91 CS Register (CS91) */ +#define CAN_CS91_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS91_TIME_STAMP_MASK (0xFFFF << CAN_CS91_TIME_STAMP_SHIFT) +#define CAN_CS91_TIME_STAMP(n) (((n) << CAN_CS91_TIME_STAMP_SHIFT) & CAN_CS91_TIME_STAMP_MASK) +#define CAN_CS91_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS91_DLC_MASK (0xF << CAN_CS91_DLC_SHIFT) +#define CAN_CS91_DLC(n) (((n) << CAN_CS91_DLC_SHIFT) & CAN_CS91_DLC_MASK) +#define CAN_CS91_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS91_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS91_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS91_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS91_CODE_MASK (0xF << CAN_CS91_CODE_SHIFT) +#define CAN_CS91_CODE(n) (((n) << CAN_CS91_CODE_SHIFT) & CAN_CS91_CODE_MASK) +#define CAN_CS91_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS91_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS91_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 91 WORD0 Register (WORD091) */ +#define CAN_WORD091_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD091_DATA_BYTE_3_MASK (0xFF << CAN_WORD091_DATA_BYTE_3_SHIFT) +#define CAN_WORD091_DATA_BYTE_3(n) (((n) << CAN_WORD091_DATA_BYTE_3_SHIFT) & CAN_WORD091_DATA_BYTE_3_MASK) +#define CAN_WORD091_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD091_DATA_BYTE_2_MASK (0xFF << CAN_WORD091_DATA_BYTE_2_SHIFT) +#define CAN_WORD091_DATA_BYTE_2(n) (((n) << CAN_WORD091_DATA_BYTE_2_SHIFT) & CAN_WORD091_DATA_BYTE_2_MASK) +#define CAN_WORD091_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD091_DATA_BYTE_1_MASK (0xFF << CAN_WORD091_DATA_BYTE_1_SHIFT) +#define CAN_WORD091_DATA_BYTE_1(n) (((n) << CAN_WORD091_DATA_BYTE_1_SHIFT) & CAN_WORD091_DATA_BYTE_1_MASK) +#define CAN_WORD091_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD091_DATA_BYTE_0_MASK (0xFF << CAN_WORD091_DATA_BYTE_0_SHIFT) +#define CAN_WORD091_DATA_BYTE_0(n) (((n) << CAN_WORD091_DATA_BYTE_0_SHIFT) & CAN_WORD091_DATA_BYTE_0_MASK) + +/* Message Buffer 91 WORD1 Register (WORD191) */ +#define CAN_WORD191_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD191_DATA_BYTE_7_MASK (0xFF << CAN_WORD191_DATA_BYTE_7_SHIFT) +#define CAN_WORD191_DATA_BYTE_7(n) (((n) << CAN_WORD191_DATA_BYTE_7_SHIFT) & CAN_WORD191_DATA_BYTE_7_MASK) +#define CAN_WORD191_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD191_DATA_BYTE_6_MASK (0xFF << CAN_WORD191_DATA_BYTE_6_SHIFT) +#define CAN_WORD191_DATA_BYTE_6(n) (((n) << CAN_WORD191_DATA_BYTE_6_SHIFT) & CAN_WORD191_DATA_BYTE_6_MASK) +#define CAN_WORD191_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD191_DATA_BYTE_5_MASK (0xFF << CAN_WORD191_DATA_BYTE_5_SHIFT) +#define CAN_WORD191_DATA_BYTE_5(n) (((n) << CAN_WORD191_DATA_BYTE_5_SHIFT) & CAN_WORD191_DATA_BYTE_5_MASK) +#define CAN_WORD191_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD191_DATA_BYTE_4_MASK (0xFF << CAN_WORD191_DATA_BYTE_4_SHIFT) +#define CAN_WORD191_DATA_BYTE_4(n) (((n) << CAN_WORD191_DATA_BYTE_4_SHIFT) & CAN_WORD191_DATA_BYTE_4_MASK) + +/* Message Buffer 92 CS Register (CS92) */ +#define CAN_CS92_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS92_TIME_STAMP_MASK (0xFFFF << CAN_CS92_TIME_STAMP_SHIFT) +#define CAN_CS92_TIME_STAMP(n) (((n) << CAN_CS92_TIME_STAMP_SHIFT) & CAN_CS92_TIME_STAMP_MASK) +#define CAN_CS92_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS92_DLC_MASK (0xF << CAN_CS92_DLC_SHIFT) +#define CAN_CS92_DLC(n) (((n) << CAN_CS92_DLC_SHIFT) & CAN_CS92_DLC_MASK) +#define CAN_CS92_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS92_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS92_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS92_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS92_CODE_MASK (0xF << CAN_CS92_CODE_SHIFT) +#define CAN_CS92_CODE(n) (((n) << CAN_CS92_CODE_SHIFT) & CAN_CS92_CODE_MASK) +#define CAN_CS92_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS92_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS92_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 92 WORD0 Register (WORD092) */ +#define CAN_WORD092_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD092_DATA_BYTE_3_MASK (0xFF << CAN_WORD092_DATA_BYTE_3_SHIFT) +#define CAN_WORD092_DATA_BYTE_3(n) (((n) << CAN_WORD092_DATA_BYTE_3_SHIFT) & CAN_WORD092_DATA_BYTE_3_MASK) +#define CAN_WORD092_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD092_DATA_BYTE_2_MASK (0xFF << CAN_WORD092_DATA_BYTE_2_SHIFT) +#define CAN_WORD092_DATA_BYTE_2(n) (((n) << CAN_WORD092_DATA_BYTE_2_SHIFT) & CAN_WORD092_DATA_BYTE_2_MASK) +#define CAN_WORD092_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD092_DATA_BYTE_1_MASK (0xFF << CAN_WORD092_DATA_BYTE_1_SHIFT) +#define CAN_WORD092_DATA_BYTE_1(n) (((n) << CAN_WORD092_DATA_BYTE_1_SHIFT) & CAN_WORD092_DATA_BYTE_1_MASK) +#define CAN_WORD092_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD092_DATA_BYTE_0_MASK (0xFF << CAN_WORD092_DATA_BYTE_0_SHIFT) +#define CAN_WORD092_DATA_BYTE_0(n) (((n) << CAN_WORD092_DATA_BYTE_0_SHIFT) & CAN_WORD092_DATA_BYTE_0_MASK) + +/* Message Buffer 92 WORD1 Register (WORD192) */ +#define CAN_WORD192_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD192_DATA_BYTE_7_MASK (0xFF << CAN_WORD192_DATA_BYTE_7_SHIFT) +#define CAN_WORD192_DATA_BYTE_7(n) (((n) << CAN_WORD192_DATA_BYTE_7_SHIFT) & CAN_WORD192_DATA_BYTE_7_MASK) +#define CAN_WORD192_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD192_DATA_BYTE_6_MASK (0xFF << CAN_WORD192_DATA_BYTE_6_SHIFT) +#define CAN_WORD192_DATA_BYTE_6(n) (((n) << CAN_WORD192_DATA_BYTE_6_SHIFT) & CAN_WORD192_DATA_BYTE_6_MASK) +#define CAN_WORD192_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD192_DATA_BYTE_5_MASK (0xFF << CAN_WORD192_DATA_BYTE_5_SHIFT) +#define CAN_WORD192_DATA_BYTE_5(n) (((n) << CAN_WORD192_DATA_BYTE_5_SHIFT) & CAN_WORD192_DATA_BYTE_5_MASK) +#define CAN_WORD192_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD192_DATA_BYTE_4_MASK (0xFF << CAN_WORD192_DATA_BYTE_4_SHIFT) +#define CAN_WORD192_DATA_BYTE_4(n) (((n) << CAN_WORD192_DATA_BYTE_4_SHIFT) & CAN_WORD192_DATA_BYTE_4_MASK) + +/* Message Buffer 93 CS Register (CS93) */ +#define CAN_CS93_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS93_TIME_STAMP_MASK (0xFFFF << CAN_CS93_TIME_STAMP_SHIFT) +#define CAN_CS93_TIME_STAMP(n) (((n) << CAN_CS93_TIME_STAMP_SHIFT) & CAN_CS93_TIME_STAMP_MASK) +#define CAN_CS93_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS93_DLC_MASK (0xF << CAN_CS93_DLC_SHIFT) +#define CAN_CS93_DLC(n) (((n) << CAN_CS93_DLC_SHIFT) & CAN_CS93_DLC_MASK) +#define CAN_CS93_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS93_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS93_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS93_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS93_CODE_MASK (0xF << CAN_CS93_CODE_SHIFT) +#define CAN_CS93_CODE(n) (((n) << CAN_CS93_CODE_SHIFT) & CAN_CS93_CODE_MASK) +#define CAN_CS93_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS93_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS93_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 93 WORD0 Register (WORD093) */ +#define CAN_WORD093_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD093_DATA_BYTE_3_MASK (0xFF << CAN_WORD093_DATA_BYTE_3_SHIFT) +#define CAN_WORD093_DATA_BYTE_3(n) (((n) << CAN_WORD093_DATA_BYTE_3_SHIFT) & CAN_WORD093_DATA_BYTE_3_MASK) +#define CAN_WORD093_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD093_DATA_BYTE_2_MASK (0xFF << CAN_WORD093_DATA_BYTE_2_SHIFT) +#define CAN_WORD093_DATA_BYTE_2(n) (((n) << CAN_WORD093_DATA_BYTE_2_SHIFT) & CAN_WORD093_DATA_BYTE_2_MASK) +#define CAN_WORD093_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD093_DATA_BYTE_1_MASK (0xFF << CAN_WORD093_DATA_BYTE_1_SHIFT) +#define CAN_WORD093_DATA_BYTE_1(n) (((n) << CAN_WORD093_DATA_BYTE_1_SHIFT) & CAN_WORD093_DATA_BYTE_1_MASK) +#define CAN_WORD093_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD093_DATA_BYTE_0_MASK (0xFF << CAN_WORD093_DATA_BYTE_0_SHIFT) +#define CAN_WORD093_DATA_BYTE_0(n) (((n) << CAN_WORD093_DATA_BYTE_0_SHIFT) & CAN_WORD093_DATA_BYTE_0_MASK) + +/* Message Buffer 93 WORD1 Register (WORD193) */ +#define CAN_WORD193_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD193_DATA_BYTE_7_MASK (0xFF << CAN_WORD193_DATA_BYTE_7_SHIFT) +#define CAN_WORD193_DATA_BYTE_7(n) (((n) << CAN_WORD193_DATA_BYTE_7_SHIFT) & CAN_WORD193_DATA_BYTE_7_MASK) +#define CAN_WORD193_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD193_DATA_BYTE_6_MASK (0xFF << CAN_WORD193_DATA_BYTE_6_SHIFT) +#define CAN_WORD193_DATA_BYTE_6(n) (((n) << CAN_WORD193_DATA_BYTE_6_SHIFT) & CAN_WORD193_DATA_BYTE_6_MASK) +#define CAN_WORD193_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD193_DATA_BYTE_5_MASK (0xFF << CAN_WORD193_DATA_BYTE_5_SHIFT) +#define CAN_WORD193_DATA_BYTE_5(n) (((n) << CAN_WORD193_DATA_BYTE_5_SHIFT) & CAN_WORD193_DATA_BYTE_5_MASK) +#define CAN_WORD193_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD193_DATA_BYTE_4_MASK (0xFF << CAN_WORD193_DATA_BYTE_4_SHIFT) +#define CAN_WORD193_DATA_BYTE_4(n) (((n) << CAN_WORD193_DATA_BYTE_4_SHIFT) & CAN_WORD193_DATA_BYTE_4_MASK) + +/* Message Buffer 94 CS Register (CS94) */ +#define CAN_CS94_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS94_TIME_STAMP_MASK (0xFFFF << CAN_CS94_TIME_STAMP_SHIFT) +#define CAN_CS94_TIME_STAMP(n) (((n) << CAN_CS94_TIME_STAMP_SHIFT) & CAN_CS94_TIME_STAMP_MASK) +#define CAN_CS94_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS94_DLC_MASK (0xF << CAN_CS94_DLC_SHIFT) +#define CAN_CS94_DLC(n) (((n) << CAN_CS94_DLC_SHIFT) & CAN_CS94_DLC_MASK) +#define CAN_CS94_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS94_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS94_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS94_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS94_CODE_MASK (0xF << CAN_CS94_CODE_SHIFT) +#define CAN_CS94_CODE(n) (((n) << CAN_CS94_CODE_SHIFT) & CAN_CS94_CODE_MASK) +#define CAN_CS94_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS94_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS94_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 94 WORD0 Register (WORD094) */ +#define CAN_WORD094_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD094_DATA_BYTE_3_MASK (0xFF << CAN_WORD094_DATA_BYTE_3_SHIFT) +#define CAN_WORD094_DATA_BYTE_3(n) (((n) << CAN_WORD094_DATA_BYTE_3_SHIFT) & CAN_WORD094_DATA_BYTE_3_MASK) +#define CAN_WORD094_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD094_DATA_BYTE_2_MASK (0xFF << CAN_WORD094_DATA_BYTE_2_SHIFT) +#define CAN_WORD094_DATA_BYTE_2(n) (((n) << CAN_WORD094_DATA_BYTE_2_SHIFT) & CAN_WORD094_DATA_BYTE_2_MASK) +#define CAN_WORD094_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD094_DATA_BYTE_1_MASK (0xFF << CAN_WORD094_DATA_BYTE_1_SHIFT) +#define CAN_WORD094_DATA_BYTE_1(n) (((n) << CAN_WORD094_DATA_BYTE_1_SHIFT) & CAN_WORD094_DATA_BYTE_1_MASK) +#define CAN_WORD094_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD094_DATA_BYTE_0_MASK (0xFF << CAN_WORD094_DATA_BYTE_0_SHIFT) +#define CAN_WORD094_DATA_BYTE_0(n) (((n) << CAN_WORD094_DATA_BYTE_0_SHIFT) & CAN_WORD094_DATA_BYTE_0_MASK) + +/* Message Buffer 94 WORD1 Register (WORD194) */ +#define CAN_WORD194_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD194_DATA_BYTE_7_MASK (0xFF << CAN_WORD194_DATA_BYTE_7_SHIFT) +#define CAN_WORD194_DATA_BYTE_7(n) (((n) << CAN_WORD194_DATA_BYTE_7_SHIFT) & CAN_WORD194_DATA_BYTE_7_MASK) +#define CAN_WORD194_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD194_DATA_BYTE_6_MASK (0xFF << CAN_WORD194_DATA_BYTE_6_SHIFT) +#define CAN_WORD194_DATA_BYTE_6(n) (((n) << CAN_WORD194_DATA_BYTE_6_SHIFT) & CAN_WORD194_DATA_BYTE_6_MASK) +#define CAN_WORD194_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD194_DATA_BYTE_5_MASK (0xFF << CAN_WORD194_DATA_BYTE_5_SHIFT) +#define CAN_WORD194_DATA_BYTE_5(n) (((n) << CAN_WORD194_DATA_BYTE_5_SHIFT) & CAN_WORD194_DATA_BYTE_5_MASK) +#define CAN_WORD194_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD194_DATA_BYTE_4_MASK (0xFF << CAN_WORD194_DATA_BYTE_4_SHIFT) +#define CAN_WORD194_DATA_BYTE_4(n) (((n) << CAN_WORD194_DATA_BYTE_4_SHIFT) & CAN_WORD194_DATA_BYTE_4_MASK) + +/* Message Buffer 95 CS Register (CS95) */ +#define CAN_CS95_TIME_STAMP_SHIFT (0) /* Bits 0-16: Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. */ +#define CAN_CS95_TIME_STAMP_MASK (0xFFFF << CAN_CS95_TIME_STAMP_SHIFT) +#define CAN_CS95_TIME_STAMP(n) (((n) << CAN_CS95_TIME_STAMP_SHIFT) & CAN_CS95_TIME_STAMP_MASK) +#define CAN_CS95_DLC_SHIFT (16) /* Bits 16-20: Length of the data to be stored/transmitted. */ +#define CAN_CS95_DLC_MASK (0xF << CAN_CS95_DLC_SHIFT) +#define CAN_CS95_DLC(n) (((n) << CAN_CS95_DLC_SHIFT) & CAN_CS95_DLC_MASK) +#define CAN_CS95_RTR (1 << 20) /* Bit 20: Remote Transmission Request. One/zero for remote/data frame. */ +#define CAN_CS95_IDE (1 << 21) /* Bit 21: ID Extended. One/zero for extended/standard format frame. */ +#define CAN_CS95_SRR (1 << 22) /* Bit 22: Substitute Remote Request. Contains a fixed recessive bit. */ +#define CAN_CS95_CODE_SHIFT (24) /* Bits 24-28: Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ +#define CAN_CS95_CODE_MASK (0xF << CAN_CS95_CODE_SHIFT) +#define CAN_CS95_CODE(n) (((n) << CAN_CS95_CODE_SHIFT) & CAN_CS95_CODE_MASK) +#define CAN_CS95_ESI (1 << 29) /* Bit 29: Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ +#define CAN_CS95_BRS (1 << 30) /* Bit 30: Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ +#define CAN_CS95_EDL (1 << 31) /* Bit 31: Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010. */ + +/* Message Buffer 95 WORD0 Register (WORD095) */ +#define CAN_WORD095_DATA_BYTE_3_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD095_DATA_BYTE_3_MASK (0xFF << CAN_WORD095_DATA_BYTE_3_SHIFT) +#define CAN_WORD095_DATA_BYTE_3(n) (((n) << CAN_WORD095_DATA_BYTE_3_SHIFT) & CAN_WORD095_DATA_BYTE_3_MASK) +#define CAN_WORD095_DATA_BYTE_2_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD095_DATA_BYTE_2_MASK (0xFF << CAN_WORD095_DATA_BYTE_2_SHIFT) +#define CAN_WORD095_DATA_BYTE_2(n) (((n) << CAN_WORD095_DATA_BYTE_2_SHIFT) & CAN_WORD095_DATA_BYTE_2_MASK) +#define CAN_WORD095_DATA_BYTE_1_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD095_DATA_BYTE_1_MASK (0xFF << CAN_WORD095_DATA_BYTE_1_SHIFT) +#define CAN_WORD095_DATA_BYTE_1(n) (((n) << CAN_WORD095_DATA_BYTE_1_SHIFT) & CAN_WORD095_DATA_BYTE_1_MASK) +#define CAN_WORD095_DATA_BYTE_0_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD095_DATA_BYTE_0_MASK (0xFF << CAN_WORD095_DATA_BYTE_0_SHIFT) +#define CAN_WORD095_DATA_BYTE_0(n) (((n) << CAN_WORD095_DATA_BYTE_0_SHIFT) & CAN_WORD095_DATA_BYTE_0_MASK) + +/* Message Buffer 95 WORD1 Register (WORD195) */ +#define CAN_WORD195_DATA_BYTE_7_SHIFT (0) /* Bits 0-8: Data byte 0 of Rx/Tx frame. */ +#define CAN_WORD195_DATA_BYTE_7_MASK (0xFF << CAN_WORD195_DATA_BYTE_7_SHIFT) +#define CAN_WORD195_DATA_BYTE_7(n) (((n) << CAN_WORD195_DATA_BYTE_7_SHIFT) & CAN_WORD195_DATA_BYTE_7_MASK) +#define CAN_WORD195_DATA_BYTE_6_SHIFT (8) /* Bits 8-16: Data byte 1 of Rx/Tx frame. */ +#define CAN_WORD195_DATA_BYTE_6_MASK (0xFF << CAN_WORD195_DATA_BYTE_6_SHIFT) +#define CAN_WORD195_DATA_BYTE_6(n) (((n) << CAN_WORD195_DATA_BYTE_6_SHIFT) & CAN_WORD195_DATA_BYTE_6_MASK) +#define CAN_WORD195_DATA_BYTE_5_SHIFT (16) /* Bits 16-24: Data byte 2 of Rx/Tx frame. */ +#define CAN_WORD195_DATA_BYTE_5_MASK (0xFF << CAN_WORD195_DATA_BYTE_5_SHIFT) +#define CAN_WORD195_DATA_BYTE_5(n) (((n) << CAN_WORD195_DATA_BYTE_5_SHIFT) & CAN_WORD195_DATA_BYTE_5_MASK) +#define CAN_WORD195_DATA_BYTE_4_SHIFT (24) /* Bits 24-32: Data byte 3 of Rx/Tx frame. */ +#define CAN_WORD195_DATA_BYTE_4_MASK (0xFF << CAN_WORD195_DATA_BYTE_4_SHIFT) +#define CAN_WORD195_DATA_BYTE_4(n) (((n) << CAN_WORD195_DATA_BYTE_4_SHIFT) & CAN_WORD195_DATA_BYTE_4_MASK) + +/* Memory Error Control (MECR) */ +#define CAN_MECR_NCEFAFRZ (1 << 7) /* Bit 7: Noncorrectable Errors in FlexCAN Access Put Chip in Freeze Mode */ +#define CAN_MECR_ECCDIS (1 << 8) /* Bit 8: Error Correction Disable */ +#define CAN_MECR_RERRDIS (1 << 9) /* Bit 9: Error Report Disable */ +#define CAN_MECR_EXTERRIE (1 << 13) /* Bit 13: Extended Error Injection Enable */ +#define CAN_MECR_FAERRIE (1 << 14) /* Bit 14: FlexCAN Access Error Injection Enable */ +#define CAN_MECR_HAERRIE (1 << 15) /* Bit 15: Host Access Error Injection Enable */ +#define CAN_MECR_CEI_MSK (1 << 16) /* Bit 16: Correctable Errors Interrupt Mask */ +#define CAN_MECR_FANCEI_MSK (1 << 18) /* Bit 18: FlexCAN Access with Noncorrectable Errors Interrupt Mask */ +#define CAN_MECR_HANCEI_MSK (1 << 19) /* Bit 19: Host Access with Noncorrectable Errors Interrupt Mask */ +#define CAN_MECR_ECRWRDIS (1 << 31) /* Bit 31: Error Configuration Register Write Disable */ + +/* Error Injection Address (ERRIAR) */ +#define CAN_ERRIAR_INJADDR_L_SHIFT (0) /* Bits 0-2: Error Injection Address Low */ +#define CAN_ERRIAR_INJADDR_L_MASK (0x3 << CAN_ERRIAR_INJADDR_L_SHIFT) +#define CAN_ERRIAR_INJADDR_L(n) (((n) << CAN_ERRIAR_INJADDR_L_SHIFT) & CAN_ERRIAR_INJADDR_L_MASK) +#define CAN_ERRIAR_INJADDR_H_SHIFT (2) /* Bits 2-14: Error Injection Address High */ +#define CAN_ERRIAR_INJADDR_H_MASK (0xFFF << CAN_ERRIAR_INJADDR_H_SHIFT) +#define CAN_ERRIAR_INJADDR_H(n) (((n) << CAN_ERRIAR_INJADDR_H_SHIFT) & CAN_ERRIAR_INJADDR_H_MASK) + +/* Error Injection Data Pattern (ERRIDPR) */ +#define CAN_ERRIDPR_DFLIP_SHIFT (0) /* Bits 0-32: Data Flip Pattern */ +#define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFF << CAN_ERRIDPR_DFLIP_SHIFT) +#define CAN_ERRIDPR_DFLIP(n) (((n) << CAN_ERRIDPR_DFLIP_SHIFT) & CAN_ERRIDPR_DFLIP_MASK) + +/* Error Injection Parity Pattern (ERRIPPR) */ +#define CAN_ERRIPPR_PFLIP0_SHIFT (0) /* Bits 0-5: Parity Flip Pattern for Byte 0 (Least Significant) */ +#define CAN_ERRIPPR_PFLIP0_MASK (0x1F << CAN_ERRIPPR_PFLIP0_SHIFT) +#define CAN_ERRIPPR_PFLIP0(n) (((n) << CAN_ERRIPPR_PFLIP0_SHIFT) & CAN_ERRIPPR_PFLIP0_MASK) +#define CAN_ERRIPPR_PFLIP1_SHIFT (8) /* Bits 8-13: Parity Flip Pattern for Byte 1 */ +#define CAN_ERRIPPR_PFLIP1_MASK (0x1F << CAN_ERRIPPR_PFLIP1_SHIFT) +#define CAN_ERRIPPR_PFLIP1(n) (((n) << CAN_ERRIPPR_PFLIP1_SHIFT) & CAN_ERRIPPR_PFLIP1_MASK) +#define CAN_ERRIPPR_PFLIP2_SHIFT (16) /* Bits 16-21: Parity Flip Pattern for Byte 2 */ +#define CAN_ERRIPPR_PFLIP2_MASK (0x1F << CAN_ERRIPPR_PFLIP2_SHIFT) +#define CAN_ERRIPPR_PFLIP2(n) (((n) << CAN_ERRIPPR_PFLIP2_SHIFT) & CAN_ERRIPPR_PFLIP2_MASK) +#define CAN_ERRIPPR_PFLIP3_SHIFT (24) /* Bits 24-29: Parity Flip Pattern for Byte 3 (Most Significant) */ +#define CAN_ERRIPPR_PFLIP3_MASK (0x1F << CAN_ERRIPPR_PFLIP3_SHIFT) +#define CAN_ERRIPPR_PFLIP3(n) (((n) << CAN_ERRIPPR_PFLIP3_SHIFT) & CAN_ERRIPPR_PFLIP3_MASK) + +/* Error Report Address (RERRAR) */ +#define CAN_RERRAR_ERRADDR_SHIFT (0) /* Bits 0-14: Address Where Error Detected */ +#define CAN_RERRAR_ERRADDR_MASK (0x3FFF << CAN_RERRAR_ERRADDR_SHIFT) +#define CAN_RERRAR_ERRADDR(n) (((n) << CAN_RERRAR_ERRADDR_SHIFT) & CAN_RERRAR_ERRADDR_MASK) +#define CAN_RERRAR_SAID_SHIFT (16) /* Bits 16-19: SAID */ +#define CAN_RERRAR_SAID_MASK (0x7 << CAN_RERRAR_SAID_SHIFT) +#define CAN_RERRAR_SAID(n) (((n) << CAN_RERRAR_SAID_SHIFT) & CAN_RERRAR_SAID_MASK) +#define CAN_RERRAR_NCE (1 << 24) /* Bit 24: Noncorrectable Error */ + +/* Error Report Data (RERRDR) */ +#define CAN_RERRDR_RDATA_SHIFT (0) /* Bits 0-32: Raw Data Word Read from Memory with Error */ +#define CAN_RERRDR_RDATA_MASK (0xFFFFFFFF << CAN_RERRDR_RDATA_SHIFT) +#define CAN_RERRDR_RDATA(n) (((n) << CAN_RERRDR_RDATA_SHIFT) & CAN_RERRDR_RDATA_MASK) + +/* Error Report Syndrome (RERRSYNR) */ +#define CAN_RERRSYNR_SYND0_SHIFT (0) /* Bits 0-5: Error Syndrome for Byte 0 (Least Significant) */ +#define CAN_RERRSYNR_SYND0_MASK (0x1F << CAN_RERRSYNR_SYND0_SHIFT) +#define CAN_RERRSYNR_SYND0(n) (((n) << CAN_RERRSYNR_SYND0_SHIFT) & CAN_RERRSYNR_SYND0_MASK) +#define CAN_RERRSYNR_BE0 (1 << 7) /* Bit 7: Byte Enabled for Byte 0 (Least Significant) */ +#define CAN_RERRSYNR_SYND1_SHIFT (8) /* Bits 8-13: Error Syndrome for Byte 1 */ +#define CAN_RERRSYNR_SYND1_MASK (0x1F << CAN_RERRSYNR_SYND1_SHIFT) +#define CAN_RERRSYNR_SYND1(n) (((n) << CAN_RERRSYNR_SYND1_SHIFT) & CAN_RERRSYNR_SYND1_MASK) +#define CAN_RERRSYNR_BE1 (1 << 15) /* Bit 15: Byte Enabled for Byte 1 */ +#define CAN_RERRSYNR_SYND2_SHIFT (16) /* Bits 16-21: Error Syndrome for Byte 2 */ +#define CAN_RERRSYNR_SYND2_MASK (0x1F << CAN_RERRSYNR_SYND2_SHIFT) +#define CAN_RERRSYNR_SYND2(n) (((n) << CAN_RERRSYNR_SYND2_SHIFT) & CAN_RERRSYNR_SYND2_MASK) +#define CAN_RERRSYNR_BE2 (1 << 23) /* Bit 23: Byte Enabled for Byte 2 */ +#define CAN_RERRSYNR_SYND3_SHIFT (24) /* Bits 24-29: Error Syndrome for Byte 3 (Most Significant) */ +#define CAN_RERRSYNR_SYND3_MASK (0x1F << CAN_RERRSYNR_SYND3_SHIFT) +#define CAN_RERRSYNR_SYND3(n) (((n) << CAN_RERRSYNR_SYND3_SHIFT) & CAN_RERRSYNR_SYND3_MASK) +#define CAN_RERRSYNR_BE3 (1 << 31) /* Bit 31: Byte Enabled for Byte 3 (Most Significant) */ + +/* Error Status (ERRSR) */ +#define CAN_ERRSR_CEIOF (1 << 0) /* Bit 0: Correctable Error Interrupt Overrun Flag */ +#define CAN_ERRSR_FANCEIOF (1 << 2) /* Bit 2: FlexCAN Access with Noncorrectable Error Interrupt Overrun Flag */ +#define CAN_ERRSR_HANCEIOF (1 << 3) /* Bit 3: Host Access With Noncorrectable Error Interrupt Overrun Flag */ +#define CAN_ERRSR_CEIF (1 << 16) /* Bit 16: Correctable Error Interrupt Flag */ +#define CAN_ERRSR_FANCEIF (1 << 18) /* Bit 18: FlexCAN Access with Noncorrectable Error Interrupt Flag */ +#define CAN_ERRSR_HANCEIF (1 << 19) /* Bit 19: Host Access with Noncorrectable Error Interrupt Flag */ + +/* Enhanced CAN Bit Timing Prescalers (EPRS) */ +#define CAN_EPRS_ENPRESDIV_SHIFT (0) /* Bits 0-10: Extended Nominal Prescaler Division Factor */ +#define CAN_EPRS_ENPRESDIV_MASK (0x3FF << CAN_EPRS_ENPRESDIV_SHIFT) +#define CAN_EPRS_ENPRESDIV(n) (((n) << CAN_EPRS_ENPRESDIV_SHIFT) & CAN_EPRS_ENPRESDIV_MASK) +#define CAN_EPRS_EDPRESDIV_SHIFT (16) /* Bits 16-26: Extended Data Phase Prescaler Division Factor */ +#define CAN_EPRS_EDPRESDIV_MASK (0x3FF << CAN_EPRS_EDPRESDIV_SHIFT) +#define CAN_EPRS_EDPRESDIV(n) (((n) << CAN_EPRS_EDPRESDIV_SHIFT) & CAN_EPRS_EDPRESDIV_MASK) + +/* Enhanced Nominal CAN Bit Timing (ENCBT) */ +#define CAN_ENCBT_NTSEG1_SHIFT (0) /* Bits 0-8: Nominal Time Segment 1 */ +#define CAN_ENCBT_NTSEG1_MASK (0xFF << CAN_ENCBT_NTSEG1_SHIFT) +#define CAN_ENCBT_NTSEG1(n) (((n) << CAN_ENCBT_NTSEG1_SHIFT) & CAN_ENCBT_NTSEG1_MASK) +#define CAN_ENCBT_NTSEG2_SHIFT (12) /* Bits 12-19: Nominal Time Segment 2 */ +#define CAN_ENCBT_NTSEG2_MASK (0x7F << CAN_ENCBT_NTSEG2_SHIFT) +#define CAN_ENCBT_NTSEG2(n) (((n) << CAN_ENCBT_NTSEG2_SHIFT) & CAN_ENCBT_NTSEG2_MASK) +#define CAN_ENCBT_NRJW_SHIFT (22) /* Bits 22-29: Nominal Resynchronization Jump Width */ +#define CAN_ENCBT_NRJW_MASK (0x7F << CAN_ENCBT_NRJW_SHIFT) +#define CAN_ENCBT_NRJW(n) (((n) << CAN_ENCBT_NRJW_SHIFT) & CAN_ENCBT_NRJW_MASK) + +/* Enhanced Data Phase CAN Bit Timing (EDCBT) */ +#define CAN_EDCBT_DTSEG1_SHIFT (0) /* Bits 0-5: Data Phase Segment 1 */ +#define CAN_EDCBT_DTSEG1_MASK (0x1F << CAN_EDCBT_DTSEG1_SHIFT) +#define CAN_EDCBT_DTSEG1(n) (((n) << CAN_EDCBT_DTSEG1_SHIFT) & CAN_EDCBT_DTSEG1_MASK) +#define CAN_EDCBT_DTSEG2_SHIFT (12) /* Bits 12-16: Data Phase Time Segment 2 */ +#define CAN_EDCBT_DTSEG2_MASK (0xF << CAN_EDCBT_DTSEG2_SHIFT) +#define CAN_EDCBT_DTSEG2(n) (((n) << CAN_EDCBT_DTSEG2_SHIFT) & CAN_EDCBT_DTSEG2_MASK) +#define CAN_EDCBT_DRJW_SHIFT (22) /* Bits 22-26: Data Phase Resynchronization Jump Width */ +#define CAN_EDCBT_DRJW_MASK (0xF << CAN_EDCBT_DRJW_SHIFT) +#define CAN_EDCBT_DRJW(n) (((n) << CAN_EDCBT_DRJW_SHIFT) & CAN_EDCBT_DRJW_MASK) + +/* Enhanced Transceiver Delay Compensation (ETDC) */ +#define CAN_ETDC_ETDCVAL_SHIFT (0) /* Bits 0-8: Enhanced Transceiver Delay Compensation Value */ +#define CAN_ETDC_ETDCVAL_MASK (0xFF << CAN_ETDC_ETDCVAL_SHIFT) +#define CAN_ETDC_ETDCVAL(n) (((n) << CAN_ETDC_ETDCVAL_SHIFT) & CAN_ETDC_ETDCVAL_MASK) +#define CAN_ETDC_ETDCFAIL (1 << 15) /* Bit 15: Transceiver Delay Compensation Fail */ +#define CAN_ETDC_ETDCOFF_SHIFT (16) /* Bits 16-23: Enhanced Transceiver Delay Compensation Offset */ +#define CAN_ETDC_ETDCOFF_MASK (0x7F << CAN_ETDC_ETDCOFF_SHIFT) +#define CAN_ETDC_ETDCOFF(n) (((n) << CAN_ETDC_ETDCOFF_SHIFT) & CAN_ETDC_ETDCOFF_MASK) +#define CAN_ETDC_TDMDIS (1 << 30) /* Bit 30: Transceiver Delay Measurement Disable */ +#define CAN_ETDC_ETDCEN (1 << 31) /* Bit 31: Transceiver Delay Compensation Enable */ + +/* CAN FD Control (FDCTRL) */ +#define CAN_FDCTRL_TDCVAL_SHIFT (0) /* Bits 0-6: Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL_MASK (0x3F << CAN_FDCTRL_TDCVAL_SHIFT) +#define CAN_FDCTRL_TDCVAL(n) (((n) << CAN_FDCTRL_TDCVAL_SHIFT) & CAN_FDCTRL_TDCVAL_MASK) +#define CAN_FDCTRL_TDCOFF_SHIFT (8) /* Bits 8-13: Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF_MASK (0x1F << CAN_FDCTRL_TDCOFF_SHIFT) +#define CAN_FDCTRL_TDCOFF(n) (((n) << CAN_FDCTRL_TDCOFF_SHIFT) & CAN_FDCTRL_TDCOFF_MASK) +#define CAN_FDCTRL_TDCFAIL (1 << 14) /* Bit 14: Transceiver Delay Compensation Fail */ +#define CAN_FDCTRL_TDCEN (1 << 15) /* Bit 15: Transceiver Delay Compensation Enable */ +#define CAN_FDCTRL_MBDSR0_SHIFT (16) /* Bits 16-18: Message Buffer Data Size for Region 0 */ +#define CAN_FDCTRL_MBDSR0_MASK (0x3 << CAN_FDCTRL_MBDSR0_SHIFT) +#define CAN_FDCTRL_MBDSR0(n) (((n) << CAN_FDCTRL_MBDSR0_SHIFT) & CAN_FDCTRL_MBDSR0_MASK) +#define CAN_FDCTRL_MBDSR1_SHIFT (19) /* Bits 19-21: Message Buffer Data Size for Region 1 */ +#define CAN_FDCTRL_MBDSR1_MASK (0x3 << CAN_FDCTRL_MBDSR1_SHIFT) +#define CAN_FDCTRL_MBDSR1(n) (((n) << CAN_FDCTRL_MBDSR1_SHIFT) & CAN_FDCTRL_MBDSR1_MASK) +#define CAN_FDCTRL_MBDSR2_SHIFT (22) /* Bits 22-24: Message Buffer Data Size for Region 2 */ +#define CAN_FDCTRL_MBDSR2_MASK (0x3 << CAN_FDCTRL_MBDSR2_SHIFT) +#define CAN_FDCTRL_MBDSR2(n) (((n) << CAN_FDCTRL_MBDSR2_SHIFT) & CAN_FDCTRL_MBDSR2_MASK) +#define CAN_FDCTRL_FDRATE (1 << 31) /* Bit 31: Bit Rate Switch Enable */ + +/* CAN FD Bit Timing (FDCBT) */ +#define CAN_FDCBT_FPSEG2_SHIFT (0) /* Bits 0-3: Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2_MASK (0x7 << CAN_FDCBT_FPSEG2_SHIFT) +#define CAN_FDCBT_FPSEG2(n) (((n) << CAN_FDCBT_FPSEG2_SHIFT) & CAN_FDCBT_FPSEG2_MASK) +#define CAN_FDCBT_FPSEG1_SHIFT (5) /* Bits 5-8: Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1_MASK (0x7 << CAN_FDCBT_FPSEG1_SHIFT) +#define CAN_FDCBT_FPSEG1(n) (((n) << CAN_FDCBT_FPSEG1_SHIFT) & CAN_FDCBT_FPSEG1_MASK) +#define CAN_FDCBT_FPROPSEG_SHIFT (10) /* Bits 10-15: Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG_MASK (0x1F << CAN_FDCBT_FPROPSEG_SHIFT) +#define CAN_FDCBT_FPROPSEG(n) (((n) << CAN_FDCBT_FPROPSEG_SHIFT) & CAN_FDCBT_FPROPSEG_MASK) +#define CAN_FDCBT_FRJW_SHIFT (16) /* Bits 16-19: Fast Resync Jump Width */ +#define CAN_FDCBT_FRJW_MASK (0x7 << CAN_FDCBT_FRJW_SHIFT) +#define CAN_FDCBT_FRJW(n) (((n) << CAN_FDCBT_FRJW_SHIFT) & CAN_FDCBT_FRJW_MASK) +#define CAN_FDCBT_FPRESDIV_SHIFT (20) /* Bits 20-30: Fast Prescaler Division Factor */ +#define CAN_FDCBT_FPRESDIV_MASK (0x3FF << CAN_FDCBT_FPRESDIV_SHIFT) +#define CAN_FDCBT_FPRESDIV(n) (((n) << CAN_FDCBT_FPRESDIV_SHIFT) & CAN_FDCBT_FPRESDIV_MASK) + +/* CAN FD CRC (FDCRC) */ +#define CAN_FDCRC_FD_TXCRC_SHIFT (0) /* Bits 0-21: Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFF << CAN_FDCRC_FD_TXCRC_SHIFT) +#define CAN_FDCRC_FD_TXCRC(n) (((n) << CAN_FDCRC_FD_TXCRC_SHIFT) & CAN_FDCRC_FD_TXCRC_MASK) +#define CAN_FDCRC_FD_MBCRC_SHIFT (24) /* Bits 24-31: CRC Message Buffer Number for FD_TXCRC */ +#define CAN_FDCRC_FD_MBCRC_MASK (0x7F << CAN_FDCRC_FD_MBCRC_SHIFT) +#define CAN_FDCRC_FD_MBCRC(n) (((n) << CAN_FDCRC_FD_MBCRC_SHIFT) & CAN_FDCRC_FD_MBCRC_MASK) + +/* Enhanced RX FIFO Control (ERFCR) */ +#define CAN_ERFCR_ERFWM_SHIFT (0) /* Bits 0-5: Enhanced RX FIFO Watermark */ +#define CAN_ERFCR_ERFWM_MASK (0x1F << CAN_ERFCR_ERFWM_SHIFT) +#define CAN_ERFCR_ERFWM(n) (((n) << CAN_ERFCR_ERFWM_SHIFT) & CAN_ERFCR_ERFWM_MASK) +#define CAN_ERFCR_NFE_SHIFT (8) /* Bits 8-14: Number of Enhanced RX FIFO Filter Elements */ +#define CAN_ERFCR_NFE_MASK (0x3F << CAN_ERFCR_NFE_SHIFT) +#define CAN_ERFCR_NFE(n) (((n) << CAN_ERFCR_NFE_SHIFT) & CAN_ERFCR_NFE_MASK) +#define CAN_ERFCR_NEXIF_SHIFT (16) /* Bits 16-23: Number of Extended ID Filter Elements */ +#define CAN_ERFCR_NEXIF_MASK (0x7F << CAN_ERFCR_NEXIF_SHIFT) +#define CAN_ERFCR_NEXIF(n) (((n) << CAN_ERFCR_NEXIF_SHIFT) & CAN_ERFCR_NEXIF_MASK) +#define CAN_ERFCR_DMALW_SHIFT (26) /* Bits 26-31: DMA Last Word */ +#define CAN_ERFCR_DMALW_MASK (0x1F << CAN_ERFCR_DMALW_SHIFT) +#define CAN_ERFCR_DMALW(n) (((n) << CAN_ERFCR_DMALW_SHIFT) & CAN_ERFCR_DMALW_MASK) +#define CAN_ERFCR_ERFEN (1 << 31) /* Bit 31: Enhanced RX FIFO enable */ + +/* Enhanced RX FIFO Interrupt Enable (ERFIER) */ +#define CAN_ERFIER_ERFDAIE (1 << 28) /* Bit 28: Enhanced RX FIFO Data Available Interrupt Enable */ +#define CAN_ERFIER_ERFWMIIE (1 << 29) /* Bit 29: Enhanced RX FIFO Watermark Indication Interrupt Enable */ +#define CAN_ERFIER_ERFOVFIE (1 << 30) /* Bit 30: Enhanced RX FIFO Overflow Interrupt Enable */ +#define CAN_ERFIER_ERFUFWIE (1 << 31) /* Bit 31: Enhanced RX FIFO Underflow Interrupt Enable */ + +/* Enhanced RX FIFO Status (ERFSR) */ +#define CAN_ERFSR_ERFEL_SHIFT (0) /* Bits 0-6: Enhanced RX FIFO Elements */ +#define CAN_ERFSR_ERFEL_MASK (0x3F << CAN_ERFSR_ERFEL_SHIFT) +#define CAN_ERFSR_ERFEL(n) (((n) << CAN_ERFSR_ERFEL_SHIFT) & CAN_ERFSR_ERFEL_MASK) +#define CAN_ERFSR_ERFF (1 << 16) /* Bit 16: Enhanced RX FIFO Full Flag */ +#define CAN_ERFSR_ERFE (1 << 17) /* Bit 17: Enhanced RX FIFO Empty Flag */ +#define CAN_ERFSR_ERFCLR (1 << 27) /* Bit 27: Enhanced RX FIFO Clear */ +#define CAN_ERFSR_ERFDA (1 << 28) /* Bit 28: Enhanced RX FIFO Data Available Flag */ +#define CAN_ERFSR_ERFWMI (1 << 29) /* Bit 29: Enhanced RX FIFO Watermark Indication Flag */ +#define CAN_ERFSR_ERFOVF (1 << 30) /* Bit 30: Enhanced RX FIFO Overflow Flag */ +#define CAN_ERFSR_ERFUFW (1 << 31) /* Bit 31: Enhanced RX FIFO Underflow Flag */ + +/* Receive Individual Mask (RXIMR0) */ +#define CAN_RXIMR0_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR0_MI_MASK (0xFFFFFFFF << CAN_RXIMR0_MI_SHIFT) +#define CAN_RXIMR0_MI(n) (((n) << CAN_RXIMR0_MI_SHIFT) & CAN_RXIMR0_MI_MASK) + +/* Receive Individual Mask (RXIMR1) */ +#define CAN_RXIMR1_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR1_MI_MASK (0xFFFFFFFF << CAN_RXIMR1_MI_SHIFT) +#define CAN_RXIMR1_MI(n) (((n) << CAN_RXIMR1_MI_SHIFT) & CAN_RXIMR1_MI_MASK) + +/* Receive Individual Mask (RXIMR2) */ +#define CAN_RXIMR2_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR2_MI_MASK (0xFFFFFFFF << CAN_RXIMR2_MI_SHIFT) +#define CAN_RXIMR2_MI(n) (((n) << CAN_RXIMR2_MI_SHIFT) & CAN_RXIMR2_MI_MASK) + +/* Receive Individual Mask (RXIMR3) */ +#define CAN_RXIMR3_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR3_MI_MASK (0xFFFFFFFF << CAN_RXIMR3_MI_SHIFT) +#define CAN_RXIMR3_MI(n) (((n) << CAN_RXIMR3_MI_SHIFT) & CAN_RXIMR3_MI_MASK) + +/* Receive Individual Mask (RXIMR4) */ +#define CAN_RXIMR4_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR4_MI_MASK (0xFFFFFFFF << CAN_RXIMR4_MI_SHIFT) +#define CAN_RXIMR4_MI(n) (((n) << CAN_RXIMR4_MI_SHIFT) & CAN_RXIMR4_MI_MASK) + +/* Receive Individual Mask (RXIMR5) */ +#define CAN_RXIMR5_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR5_MI_MASK (0xFFFFFFFF << CAN_RXIMR5_MI_SHIFT) +#define CAN_RXIMR5_MI(n) (((n) << CAN_RXIMR5_MI_SHIFT) & CAN_RXIMR5_MI_MASK) + +/* Receive Individual Mask (RXIMR6) */ +#define CAN_RXIMR6_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR6_MI_MASK (0xFFFFFFFF << CAN_RXIMR6_MI_SHIFT) +#define CAN_RXIMR6_MI(n) (((n) << CAN_RXIMR6_MI_SHIFT) & CAN_RXIMR6_MI_MASK) + +/* Receive Individual Mask (RXIMR7) */ +#define CAN_RXIMR7_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR7_MI_MASK (0xFFFFFFFF << CAN_RXIMR7_MI_SHIFT) +#define CAN_RXIMR7_MI(n) (((n) << CAN_RXIMR7_MI_SHIFT) & CAN_RXIMR7_MI_MASK) + +/* Receive Individual Mask (RXIMR8) */ +#define CAN_RXIMR8_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR8_MI_MASK (0xFFFFFFFF << CAN_RXIMR8_MI_SHIFT) +#define CAN_RXIMR8_MI(n) (((n) << CAN_RXIMR8_MI_SHIFT) & CAN_RXIMR8_MI_MASK) + +/* Receive Individual Mask (RXIMR9) */ +#define CAN_RXIMR9_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR9_MI_MASK (0xFFFFFFFF << CAN_RXIMR9_MI_SHIFT) +#define CAN_RXIMR9_MI(n) (((n) << CAN_RXIMR9_MI_SHIFT) & CAN_RXIMR9_MI_MASK) + +/* Receive Individual Mask (RXIMR10) */ +#define CAN_RXIMR10_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR10_MI_MASK (0xFFFFFFFF << CAN_RXIMR10_MI_SHIFT) +#define CAN_RXIMR10_MI(n) (((n) << CAN_RXIMR10_MI_SHIFT) & CAN_RXIMR10_MI_MASK) + +/* Receive Individual Mask (RXIMR11) */ +#define CAN_RXIMR11_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR11_MI_MASK (0xFFFFFFFF << CAN_RXIMR11_MI_SHIFT) +#define CAN_RXIMR11_MI(n) (((n) << CAN_RXIMR11_MI_SHIFT) & CAN_RXIMR11_MI_MASK) + +/* Receive Individual Mask (RXIMR12) */ +#define CAN_RXIMR12_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR12_MI_MASK (0xFFFFFFFF << CAN_RXIMR12_MI_SHIFT) +#define CAN_RXIMR12_MI(n) (((n) << CAN_RXIMR12_MI_SHIFT) & CAN_RXIMR12_MI_MASK) + +/* Receive Individual Mask (RXIMR13) */ +#define CAN_RXIMR13_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR13_MI_MASK (0xFFFFFFFF << CAN_RXIMR13_MI_SHIFT) +#define CAN_RXIMR13_MI(n) (((n) << CAN_RXIMR13_MI_SHIFT) & CAN_RXIMR13_MI_MASK) + +/* Receive Individual Mask (RXIMR14) */ +#define CAN_RXIMR14_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR14_MI_MASK (0xFFFFFFFF << CAN_RXIMR14_MI_SHIFT) +#define CAN_RXIMR14_MI(n) (((n) << CAN_RXIMR14_MI_SHIFT) & CAN_RXIMR14_MI_MASK) + +/* Receive Individual Mask (RXIMR15) */ +#define CAN_RXIMR15_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR15_MI_MASK (0xFFFFFFFF << CAN_RXIMR15_MI_SHIFT) +#define CAN_RXIMR15_MI(n) (((n) << CAN_RXIMR15_MI_SHIFT) & CAN_RXIMR15_MI_MASK) + +/* Receive Individual Mask (RXIMR16) */ +#define CAN_RXIMR16_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR16_MI_MASK (0xFFFFFFFF << CAN_RXIMR16_MI_SHIFT) +#define CAN_RXIMR16_MI(n) (((n) << CAN_RXIMR16_MI_SHIFT) & CAN_RXIMR16_MI_MASK) + +/* Receive Individual Mask (RXIMR17) */ +#define CAN_RXIMR17_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR17_MI_MASK (0xFFFFFFFF << CAN_RXIMR17_MI_SHIFT) +#define CAN_RXIMR17_MI(n) (((n) << CAN_RXIMR17_MI_SHIFT) & CAN_RXIMR17_MI_MASK) + +/* Receive Individual Mask (RXIMR18) */ +#define CAN_RXIMR18_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR18_MI_MASK (0xFFFFFFFF << CAN_RXIMR18_MI_SHIFT) +#define CAN_RXIMR18_MI(n) (((n) << CAN_RXIMR18_MI_SHIFT) & CAN_RXIMR18_MI_MASK) + +/* Receive Individual Mask (RXIMR19) */ +#define CAN_RXIMR19_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR19_MI_MASK (0xFFFFFFFF << CAN_RXIMR19_MI_SHIFT) +#define CAN_RXIMR19_MI(n) (((n) << CAN_RXIMR19_MI_SHIFT) & CAN_RXIMR19_MI_MASK) + +/* Receive Individual Mask (RXIMR20) */ +#define CAN_RXIMR20_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR20_MI_MASK (0xFFFFFFFF << CAN_RXIMR20_MI_SHIFT) +#define CAN_RXIMR20_MI(n) (((n) << CAN_RXIMR20_MI_SHIFT) & CAN_RXIMR20_MI_MASK) + +/* Receive Individual Mask (RXIMR21) */ +#define CAN_RXIMR21_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR21_MI_MASK (0xFFFFFFFF << CAN_RXIMR21_MI_SHIFT) +#define CAN_RXIMR21_MI(n) (((n) << CAN_RXIMR21_MI_SHIFT) & CAN_RXIMR21_MI_MASK) + +/* Receive Individual Mask (RXIMR22) */ +#define CAN_RXIMR22_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR22_MI_MASK (0xFFFFFFFF << CAN_RXIMR22_MI_SHIFT) +#define CAN_RXIMR22_MI(n) (((n) << CAN_RXIMR22_MI_SHIFT) & CAN_RXIMR22_MI_MASK) + +/* Receive Individual Mask (RXIMR23) */ +#define CAN_RXIMR23_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR23_MI_MASK (0xFFFFFFFF << CAN_RXIMR23_MI_SHIFT) +#define CAN_RXIMR23_MI(n) (((n) << CAN_RXIMR23_MI_SHIFT) & CAN_RXIMR23_MI_MASK) + +/* Receive Individual Mask (RXIMR24) */ +#define CAN_RXIMR24_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR24_MI_MASK (0xFFFFFFFF << CAN_RXIMR24_MI_SHIFT) +#define CAN_RXIMR24_MI(n) (((n) << CAN_RXIMR24_MI_SHIFT) & CAN_RXIMR24_MI_MASK) + +/* Receive Individual Mask (RXIMR25) */ +#define CAN_RXIMR25_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR25_MI_MASK (0xFFFFFFFF << CAN_RXIMR25_MI_SHIFT) +#define CAN_RXIMR25_MI(n) (((n) << CAN_RXIMR25_MI_SHIFT) & CAN_RXIMR25_MI_MASK) + +/* Receive Individual Mask (RXIMR26) */ +#define CAN_RXIMR26_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR26_MI_MASK (0xFFFFFFFF << CAN_RXIMR26_MI_SHIFT) +#define CAN_RXIMR26_MI(n) (((n) << CAN_RXIMR26_MI_SHIFT) & CAN_RXIMR26_MI_MASK) + +/* Receive Individual Mask (RXIMR27) */ +#define CAN_RXIMR27_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR27_MI_MASK (0xFFFFFFFF << CAN_RXIMR27_MI_SHIFT) +#define CAN_RXIMR27_MI(n) (((n) << CAN_RXIMR27_MI_SHIFT) & CAN_RXIMR27_MI_MASK) + +/* Receive Individual Mask (RXIMR28) */ +#define CAN_RXIMR28_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR28_MI_MASK (0xFFFFFFFF << CAN_RXIMR28_MI_SHIFT) +#define CAN_RXIMR28_MI(n) (((n) << CAN_RXIMR28_MI_SHIFT) & CAN_RXIMR28_MI_MASK) + +/* Receive Individual Mask (RXIMR29) */ +#define CAN_RXIMR29_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR29_MI_MASK (0xFFFFFFFF << CAN_RXIMR29_MI_SHIFT) +#define CAN_RXIMR29_MI(n) (((n) << CAN_RXIMR29_MI_SHIFT) & CAN_RXIMR29_MI_MASK) + +/* Receive Individual Mask (RXIMR30) */ +#define CAN_RXIMR30_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR30_MI_MASK (0xFFFFFFFF << CAN_RXIMR30_MI_SHIFT) +#define CAN_RXIMR30_MI(n) (((n) << CAN_RXIMR30_MI_SHIFT) & CAN_RXIMR30_MI_MASK) + +/* Receive Individual Mask (RXIMR31) */ +#define CAN_RXIMR31_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR31_MI_MASK (0xFFFFFFFF << CAN_RXIMR31_MI_SHIFT) +#define CAN_RXIMR31_MI(n) (((n) << CAN_RXIMR31_MI_SHIFT) & CAN_RXIMR31_MI_MASK) + +/* Receive Individual Mask (RXIMR32) */ +#define CAN_RXIMR32_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR32_MI_MASK (0xFFFFFFFF << CAN_RXIMR32_MI_SHIFT) +#define CAN_RXIMR32_MI(n) (((n) << CAN_RXIMR32_MI_SHIFT) & CAN_RXIMR32_MI_MASK) + +/* Receive Individual Mask (RXIMR33) */ +#define CAN_RXIMR33_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR33_MI_MASK (0xFFFFFFFF << CAN_RXIMR33_MI_SHIFT) +#define CAN_RXIMR33_MI(n) (((n) << CAN_RXIMR33_MI_SHIFT) & CAN_RXIMR33_MI_MASK) + +/* Receive Individual Mask (RXIMR34) */ +#define CAN_RXIMR34_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR34_MI_MASK (0xFFFFFFFF << CAN_RXIMR34_MI_SHIFT) +#define CAN_RXIMR34_MI(n) (((n) << CAN_RXIMR34_MI_SHIFT) & CAN_RXIMR34_MI_MASK) + +/* Receive Individual Mask (RXIMR35) */ +#define CAN_RXIMR35_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR35_MI_MASK (0xFFFFFFFF << CAN_RXIMR35_MI_SHIFT) +#define CAN_RXIMR35_MI(n) (((n) << CAN_RXIMR35_MI_SHIFT) & CAN_RXIMR35_MI_MASK) + +/* Receive Individual Mask (RXIMR36) */ +#define CAN_RXIMR36_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR36_MI_MASK (0xFFFFFFFF << CAN_RXIMR36_MI_SHIFT) +#define CAN_RXIMR36_MI(n) (((n) << CAN_RXIMR36_MI_SHIFT) & CAN_RXIMR36_MI_MASK) + +/* Receive Individual Mask (RXIMR37) */ +#define CAN_RXIMR37_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR37_MI_MASK (0xFFFFFFFF << CAN_RXIMR37_MI_SHIFT) +#define CAN_RXIMR37_MI(n) (((n) << CAN_RXIMR37_MI_SHIFT) & CAN_RXIMR37_MI_MASK) + +/* Receive Individual Mask (RXIMR38) */ +#define CAN_RXIMR38_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR38_MI_MASK (0xFFFFFFFF << CAN_RXIMR38_MI_SHIFT) +#define CAN_RXIMR38_MI(n) (((n) << CAN_RXIMR38_MI_SHIFT) & CAN_RXIMR38_MI_MASK) + +/* Receive Individual Mask (RXIMR39) */ +#define CAN_RXIMR39_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR39_MI_MASK (0xFFFFFFFF << CAN_RXIMR39_MI_SHIFT) +#define CAN_RXIMR39_MI(n) (((n) << CAN_RXIMR39_MI_SHIFT) & CAN_RXIMR39_MI_MASK) + +/* Receive Individual Mask (RXIMR40) */ +#define CAN_RXIMR40_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR40_MI_MASK (0xFFFFFFFF << CAN_RXIMR40_MI_SHIFT) +#define CAN_RXIMR40_MI(n) (((n) << CAN_RXIMR40_MI_SHIFT) & CAN_RXIMR40_MI_MASK) + +/* Receive Individual Mask (RXIMR41) */ +#define CAN_RXIMR41_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR41_MI_MASK (0xFFFFFFFF << CAN_RXIMR41_MI_SHIFT) +#define CAN_RXIMR41_MI(n) (((n) << CAN_RXIMR41_MI_SHIFT) & CAN_RXIMR41_MI_MASK) + +/* Receive Individual Mask (RXIMR42) */ +#define CAN_RXIMR42_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR42_MI_MASK (0xFFFFFFFF << CAN_RXIMR42_MI_SHIFT) +#define CAN_RXIMR42_MI(n) (((n) << CAN_RXIMR42_MI_SHIFT) & CAN_RXIMR42_MI_MASK) + +/* Receive Individual Mask (RXIMR43) */ +#define CAN_RXIMR43_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR43_MI_MASK (0xFFFFFFFF << CAN_RXIMR43_MI_SHIFT) +#define CAN_RXIMR43_MI(n) (((n) << CAN_RXIMR43_MI_SHIFT) & CAN_RXIMR43_MI_MASK) + +/* Receive Individual Mask (RXIMR44) */ +#define CAN_RXIMR44_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR44_MI_MASK (0xFFFFFFFF << CAN_RXIMR44_MI_SHIFT) +#define CAN_RXIMR44_MI(n) (((n) << CAN_RXIMR44_MI_SHIFT) & CAN_RXIMR44_MI_MASK) + +/* Receive Individual Mask (RXIMR45) */ +#define CAN_RXIMR45_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR45_MI_MASK (0xFFFFFFFF << CAN_RXIMR45_MI_SHIFT) +#define CAN_RXIMR45_MI(n) (((n) << CAN_RXIMR45_MI_SHIFT) & CAN_RXIMR45_MI_MASK) + +/* Receive Individual Mask (RXIMR46) */ +#define CAN_RXIMR46_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR46_MI_MASK (0xFFFFFFFF << CAN_RXIMR46_MI_SHIFT) +#define CAN_RXIMR46_MI(n) (((n) << CAN_RXIMR46_MI_SHIFT) & CAN_RXIMR46_MI_MASK) + +/* Receive Individual Mask (RXIMR47) */ +#define CAN_RXIMR47_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR47_MI_MASK (0xFFFFFFFF << CAN_RXIMR47_MI_SHIFT) +#define CAN_RXIMR47_MI(n) (((n) << CAN_RXIMR47_MI_SHIFT) & CAN_RXIMR47_MI_MASK) + +/* Receive Individual Mask (RXIMR48) */ +#define CAN_RXIMR48_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR48_MI_MASK (0xFFFFFFFF << CAN_RXIMR48_MI_SHIFT) +#define CAN_RXIMR48_MI(n) (((n) << CAN_RXIMR48_MI_SHIFT) & CAN_RXIMR48_MI_MASK) + +/* Receive Individual Mask (RXIMR49) */ +#define CAN_RXIMR49_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR49_MI_MASK (0xFFFFFFFF << CAN_RXIMR49_MI_SHIFT) +#define CAN_RXIMR49_MI(n) (((n) << CAN_RXIMR49_MI_SHIFT) & CAN_RXIMR49_MI_MASK) + +/* Receive Individual Mask (RXIMR50) */ +#define CAN_RXIMR50_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR50_MI_MASK (0xFFFFFFFF << CAN_RXIMR50_MI_SHIFT) +#define CAN_RXIMR50_MI(n) (((n) << CAN_RXIMR50_MI_SHIFT) & CAN_RXIMR50_MI_MASK) + +/* Receive Individual Mask (RXIMR51) */ +#define CAN_RXIMR51_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR51_MI_MASK (0xFFFFFFFF << CAN_RXIMR51_MI_SHIFT) +#define CAN_RXIMR51_MI(n) (((n) << CAN_RXIMR51_MI_SHIFT) & CAN_RXIMR51_MI_MASK) + +/* Receive Individual Mask (RXIMR52) */ +#define CAN_RXIMR52_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR52_MI_MASK (0xFFFFFFFF << CAN_RXIMR52_MI_SHIFT) +#define CAN_RXIMR52_MI(n) (((n) << CAN_RXIMR52_MI_SHIFT) & CAN_RXIMR52_MI_MASK) + +/* Receive Individual Mask (RXIMR53) */ +#define CAN_RXIMR53_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR53_MI_MASK (0xFFFFFFFF << CAN_RXIMR53_MI_SHIFT) +#define CAN_RXIMR53_MI(n) (((n) << CAN_RXIMR53_MI_SHIFT) & CAN_RXIMR53_MI_MASK) + +/* Receive Individual Mask (RXIMR54) */ +#define CAN_RXIMR54_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR54_MI_MASK (0xFFFFFFFF << CAN_RXIMR54_MI_SHIFT) +#define CAN_RXIMR54_MI(n) (((n) << CAN_RXIMR54_MI_SHIFT) & CAN_RXIMR54_MI_MASK) + +/* Receive Individual Mask (RXIMR55) */ +#define CAN_RXIMR55_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR55_MI_MASK (0xFFFFFFFF << CAN_RXIMR55_MI_SHIFT) +#define CAN_RXIMR55_MI(n) (((n) << CAN_RXIMR55_MI_SHIFT) & CAN_RXIMR55_MI_MASK) + +/* Receive Individual Mask (RXIMR56) */ +#define CAN_RXIMR56_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR56_MI_MASK (0xFFFFFFFF << CAN_RXIMR56_MI_SHIFT) +#define CAN_RXIMR56_MI(n) (((n) << CAN_RXIMR56_MI_SHIFT) & CAN_RXIMR56_MI_MASK) + +/* Receive Individual Mask (RXIMR57) */ +#define CAN_RXIMR57_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR57_MI_MASK (0xFFFFFFFF << CAN_RXIMR57_MI_SHIFT) +#define CAN_RXIMR57_MI(n) (((n) << CAN_RXIMR57_MI_SHIFT) & CAN_RXIMR57_MI_MASK) + +/* Receive Individual Mask (RXIMR58) */ +#define CAN_RXIMR58_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR58_MI_MASK (0xFFFFFFFF << CAN_RXIMR58_MI_SHIFT) +#define CAN_RXIMR58_MI(n) (((n) << CAN_RXIMR58_MI_SHIFT) & CAN_RXIMR58_MI_MASK) + +/* Receive Individual Mask (RXIMR59) */ +#define CAN_RXIMR59_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR59_MI_MASK (0xFFFFFFFF << CAN_RXIMR59_MI_SHIFT) +#define CAN_RXIMR59_MI(n) (((n) << CAN_RXIMR59_MI_SHIFT) & CAN_RXIMR59_MI_MASK) + +/* Receive Individual Mask (RXIMR60) */ +#define CAN_RXIMR60_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR60_MI_MASK (0xFFFFFFFF << CAN_RXIMR60_MI_SHIFT) +#define CAN_RXIMR60_MI(n) (((n) << CAN_RXIMR60_MI_SHIFT) & CAN_RXIMR60_MI_MASK) + +/* Receive Individual Mask (RXIMR61) */ +#define CAN_RXIMR61_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR61_MI_MASK (0xFFFFFFFF << CAN_RXIMR61_MI_SHIFT) +#define CAN_RXIMR61_MI(n) (((n) << CAN_RXIMR61_MI_SHIFT) & CAN_RXIMR61_MI_MASK) + +/* Receive Individual Mask (RXIMR62) */ +#define CAN_RXIMR62_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR62_MI_MASK (0xFFFFFFFF << CAN_RXIMR62_MI_SHIFT) +#define CAN_RXIMR62_MI(n) (((n) << CAN_RXIMR62_MI_SHIFT) & CAN_RXIMR62_MI_MASK) + +/* Receive Individual Mask (RXIMR63) */ +#define CAN_RXIMR63_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR63_MI_MASK (0xFFFFFFFF << CAN_RXIMR63_MI_SHIFT) +#define CAN_RXIMR63_MI(n) (((n) << CAN_RXIMR63_MI_SHIFT) & CAN_RXIMR63_MI_MASK) + +/* Receive Individual Mask (RXIMR64) */ +#define CAN_RXIMR64_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR64_MI_MASK (0xFFFFFFFF << CAN_RXIMR64_MI_SHIFT) +#define CAN_RXIMR64_MI(n) (((n) << CAN_RXIMR64_MI_SHIFT) & CAN_RXIMR64_MI_MASK) + +/* Receive Individual Mask (RXIMR65) */ +#define CAN_RXIMR65_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR65_MI_MASK (0xFFFFFFFF << CAN_RXIMR65_MI_SHIFT) +#define CAN_RXIMR65_MI(n) (((n) << CAN_RXIMR65_MI_SHIFT) & CAN_RXIMR65_MI_MASK) + +/* Receive Individual Mask (RXIMR66) */ +#define CAN_RXIMR66_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR66_MI_MASK (0xFFFFFFFF << CAN_RXIMR66_MI_SHIFT) +#define CAN_RXIMR66_MI(n) (((n) << CAN_RXIMR66_MI_SHIFT) & CAN_RXIMR66_MI_MASK) + +/* Receive Individual Mask (RXIMR67) */ +#define CAN_RXIMR67_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR67_MI_MASK (0xFFFFFFFF << CAN_RXIMR67_MI_SHIFT) +#define CAN_RXIMR67_MI(n) (((n) << CAN_RXIMR67_MI_SHIFT) & CAN_RXIMR67_MI_MASK) + +/* Receive Individual Mask (RXIMR68) */ +#define CAN_RXIMR68_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR68_MI_MASK (0xFFFFFFFF << CAN_RXIMR68_MI_SHIFT) +#define CAN_RXIMR68_MI(n) (((n) << CAN_RXIMR68_MI_SHIFT) & CAN_RXIMR68_MI_MASK) + +/* Receive Individual Mask (RXIMR69) */ +#define CAN_RXIMR69_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR69_MI_MASK (0xFFFFFFFF << CAN_RXIMR69_MI_SHIFT) +#define CAN_RXIMR69_MI(n) (((n) << CAN_RXIMR69_MI_SHIFT) & CAN_RXIMR69_MI_MASK) + +/* Receive Individual Mask (RXIMR70) */ +#define CAN_RXIMR70_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR70_MI_MASK (0xFFFFFFFF << CAN_RXIMR70_MI_SHIFT) +#define CAN_RXIMR70_MI(n) (((n) << CAN_RXIMR70_MI_SHIFT) & CAN_RXIMR70_MI_MASK) + +/* Receive Individual Mask (RXIMR71) */ +#define CAN_RXIMR71_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR71_MI_MASK (0xFFFFFFFF << CAN_RXIMR71_MI_SHIFT) +#define CAN_RXIMR71_MI(n) (((n) << CAN_RXIMR71_MI_SHIFT) & CAN_RXIMR71_MI_MASK) + +/* Receive Individual Mask (RXIMR72) */ +#define CAN_RXIMR72_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR72_MI_MASK (0xFFFFFFFF << CAN_RXIMR72_MI_SHIFT) +#define CAN_RXIMR72_MI(n) (((n) << CAN_RXIMR72_MI_SHIFT) & CAN_RXIMR72_MI_MASK) + +/* Receive Individual Mask (RXIMR73) */ +#define CAN_RXIMR73_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR73_MI_MASK (0xFFFFFFFF << CAN_RXIMR73_MI_SHIFT) +#define CAN_RXIMR73_MI(n) (((n) << CAN_RXIMR73_MI_SHIFT) & CAN_RXIMR73_MI_MASK) + +/* Receive Individual Mask (RXIMR74) */ +#define CAN_RXIMR74_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR74_MI_MASK (0xFFFFFFFF << CAN_RXIMR74_MI_SHIFT) +#define CAN_RXIMR74_MI(n) (((n) << CAN_RXIMR74_MI_SHIFT) & CAN_RXIMR74_MI_MASK) + +/* Receive Individual Mask (RXIMR75) */ +#define CAN_RXIMR75_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR75_MI_MASK (0xFFFFFFFF << CAN_RXIMR75_MI_SHIFT) +#define CAN_RXIMR75_MI(n) (((n) << CAN_RXIMR75_MI_SHIFT) & CAN_RXIMR75_MI_MASK) + +/* Receive Individual Mask (RXIMR76) */ +#define CAN_RXIMR76_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR76_MI_MASK (0xFFFFFFFF << CAN_RXIMR76_MI_SHIFT) +#define CAN_RXIMR76_MI(n) (((n) << CAN_RXIMR76_MI_SHIFT) & CAN_RXIMR76_MI_MASK) + +/* Receive Individual Mask (RXIMR77) */ +#define CAN_RXIMR77_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR77_MI_MASK (0xFFFFFFFF << CAN_RXIMR77_MI_SHIFT) +#define CAN_RXIMR77_MI(n) (((n) << CAN_RXIMR77_MI_SHIFT) & CAN_RXIMR77_MI_MASK) + +/* Receive Individual Mask (RXIMR78) */ +#define CAN_RXIMR78_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR78_MI_MASK (0xFFFFFFFF << CAN_RXIMR78_MI_SHIFT) +#define CAN_RXIMR78_MI(n) (((n) << CAN_RXIMR78_MI_SHIFT) & CAN_RXIMR78_MI_MASK) + +/* Receive Individual Mask (RXIMR79) */ +#define CAN_RXIMR79_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR79_MI_MASK (0xFFFFFFFF << CAN_RXIMR79_MI_SHIFT) +#define CAN_RXIMR79_MI(n) (((n) << CAN_RXIMR79_MI_SHIFT) & CAN_RXIMR79_MI_MASK) + +/* Receive Individual Mask (RXIMR80) */ +#define CAN_RXIMR80_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR80_MI_MASK (0xFFFFFFFF << CAN_RXIMR80_MI_SHIFT) +#define CAN_RXIMR80_MI(n) (((n) << CAN_RXIMR80_MI_SHIFT) & CAN_RXIMR80_MI_MASK) + +/* Receive Individual Mask (RXIMR81) */ +#define CAN_RXIMR81_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR81_MI_MASK (0xFFFFFFFF << CAN_RXIMR81_MI_SHIFT) +#define CAN_RXIMR81_MI(n) (((n) << CAN_RXIMR81_MI_SHIFT) & CAN_RXIMR81_MI_MASK) + +/* Receive Individual Mask (RXIMR82) */ +#define CAN_RXIMR82_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR82_MI_MASK (0xFFFFFFFF << CAN_RXIMR82_MI_SHIFT) +#define CAN_RXIMR82_MI(n) (((n) << CAN_RXIMR82_MI_SHIFT) & CAN_RXIMR82_MI_MASK) + +/* Receive Individual Mask (RXIMR83) */ +#define CAN_RXIMR83_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR83_MI_MASK (0xFFFFFFFF << CAN_RXIMR83_MI_SHIFT) +#define CAN_RXIMR83_MI(n) (((n) << CAN_RXIMR83_MI_SHIFT) & CAN_RXIMR83_MI_MASK) + +/* Receive Individual Mask (RXIMR84) */ +#define CAN_RXIMR84_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR84_MI_MASK (0xFFFFFFFF << CAN_RXIMR84_MI_SHIFT) +#define CAN_RXIMR84_MI(n) (((n) << CAN_RXIMR84_MI_SHIFT) & CAN_RXIMR84_MI_MASK) + +/* Receive Individual Mask (RXIMR85) */ +#define CAN_RXIMR85_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR85_MI_MASK (0xFFFFFFFF << CAN_RXIMR85_MI_SHIFT) +#define CAN_RXIMR85_MI(n) (((n) << CAN_RXIMR85_MI_SHIFT) & CAN_RXIMR85_MI_MASK) + +/* Receive Individual Mask (RXIMR86) */ +#define CAN_RXIMR86_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR86_MI_MASK (0xFFFFFFFF << CAN_RXIMR86_MI_SHIFT) +#define CAN_RXIMR86_MI(n) (((n) << CAN_RXIMR86_MI_SHIFT) & CAN_RXIMR86_MI_MASK) + +/* Receive Individual Mask (RXIMR87) */ +#define CAN_RXIMR87_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR87_MI_MASK (0xFFFFFFFF << CAN_RXIMR87_MI_SHIFT) +#define CAN_RXIMR87_MI(n) (((n) << CAN_RXIMR87_MI_SHIFT) & CAN_RXIMR87_MI_MASK) + +/* Receive Individual Mask (RXIMR88) */ +#define CAN_RXIMR88_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR88_MI_MASK (0xFFFFFFFF << CAN_RXIMR88_MI_SHIFT) +#define CAN_RXIMR88_MI(n) (((n) << CAN_RXIMR88_MI_SHIFT) & CAN_RXIMR88_MI_MASK) + +/* Receive Individual Mask (RXIMR89) */ +#define CAN_RXIMR89_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR89_MI_MASK (0xFFFFFFFF << CAN_RXIMR89_MI_SHIFT) +#define CAN_RXIMR89_MI(n) (((n) << CAN_RXIMR89_MI_SHIFT) & CAN_RXIMR89_MI_MASK) + +/* Receive Individual Mask (RXIMR90) */ +#define CAN_RXIMR90_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR90_MI_MASK (0xFFFFFFFF << CAN_RXIMR90_MI_SHIFT) +#define CAN_RXIMR90_MI(n) (((n) << CAN_RXIMR90_MI_SHIFT) & CAN_RXIMR90_MI_MASK) + +/* Receive Individual Mask (RXIMR91) */ +#define CAN_RXIMR91_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR91_MI_MASK (0xFFFFFFFF << CAN_RXIMR91_MI_SHIFT) +#define CAN_RXIMR91_MI(n) (((n) << CAN_RXIMR91_MI_SHIFT) & CAN_RXIMR91_MI_MASK) + +/* Receive Individual Mask (RXIMR92) */ +#define CAN_RXIMR92_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR92_MI_MASK (0xFFFFFFFF << CAN_RXIMR92_MI_SHIFT) +#define CAN_RXIMR92_MI(n) (((n) << CAN_RXIMR92_MI_SHIFT) & CAN_RXIMR92_MI_MASK) + +/* Receive Individual Mask (RXIMR93) */ +#define CAN_RXIMR93_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR93_MI_MASK (0xFFFFFFFF << CAN_RXIMR93_MI_SHIFT) +#define CAN_RXIMR93_MI(n) (((n) << CAN_RXIMR93_MI_SHIFT) & CAN_RXIMR93_MI_MASK) + +/* Receive Individual Mask (RXIMR94) */ +#define CAN_RXIMR94_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR94_MI_MASK (0xFFFFFFFF << CAN_RXIMR94_MI_SHIFT) +#define CAN_RXIMR94_MI(n) (((n) << CAN_RXIMR94_MI_SHIFT) & CAN_RXIMR94_MI_MASK) + +/* Receive Individual Mask (RXIMR95) */ +#define CAN_RXIMR95_MI_SHIFT (0) /* Bits 0-32: Individual Mask Bits */ +#define CAN_RXIMR95_MI_MASK (0xFFFFFFFF << CAN_RXIMR95_MI_SHIFT) +#define CAN_RXIMR95_MI(n) (((n) << CAN_RXIMR95_MI_SHIFT) & CAN_RXIMR95_MI_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP0) */ +#define CAN_HR_TIME_STAMP0_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP0_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP0_TS_SHIFT) +#define CAN_HR_TIME_STAMP0_TS(n) (((n) << CAN_HR_TIME_STAMP0_TS_SHIFT) & CAN_HR_TIME_STAMP0_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP1) */ +#define CAN_HR_TIME_STAMP1_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP1_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP1_TS_SHIFT) +#define CAN_HR_TIME_STAMP1_TS(n) (((n) << CAN_HR_TIME_STAMP1_TS_SHIFT) & CAN_HR_TIME_STAMP1_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP2) */ +#define CAN_HR_TIME_STAMP2_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP2_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP2_TS_SHIFT) +#define CAN_HR_TIME_STAMP2_TS(n) (((n) << CAN_HR_TIME_STAMP2_TS_SHIFT) & CAN_HR_TIME_STAMP2_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP3) */ +#define CAN_HR_TIME_STAMP3_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP3_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP3_TS_SHIFT) +#define CAN_HR_TIME_STAMP3_TS(n) (((n) << CAN_HR_TIME_STAMP3_TS_SHIFT) & CAN_HR_TIME_STAMP3_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP4) */ +#define CAN_HR_TIME_STAMP4_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP4_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP4_TS_SHIFT) +#define CAN_HR_TIME_STAMP4_TS(n) (((n) << CAN_HR_TIME_STAMP4_TS_SHIFT) & CAN_HR_TIME_STAMP4_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP5) */ +#define CAN_HR_TIME_STAMP5_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP5_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP5_TS_SHIFT) +#define CAN_HR_TIME_STAMP5_TS(n) (((n) << CAN_HR_TIME_STAMP5_TS_SHIFT) & CAN_HR_TIME_STAMP5_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP6) */ +#define CAN_HR_TIME_STAMP6_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP6_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP6_TS_SHIFT) +#define CAN_HR_TIME_STAMP6_TS(n) (((n) << CAN_HR_TIME_STAMP6_TS_SHIFT) & CAN_HR_TIME_STAMP6_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP7) */ +#define CAN_HR_TIME_STAMP7_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP7_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP7_TS_SHIFT) +#define CAN_HR_TIME_STAMP7_TS(n) (((n) << CAN_HR_TIME_STAMP7_TS_SHIFT) & CAN_HR_TIME_STAMP7_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP8) */ +#define CAN_HR_TIME_STAMP8_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP8_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP8_TS_SHIFT) +#define CAN_HR_TIME_STAMP8_TS(n) (((n) << CAN_HR_TIME_STAMP8_TS_SHIFT) & CAN_HR_TIME_STAMP8_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP9) */ +#define CAN_HR_TIME_STAMP9_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP9_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP9_TS_SHIFT) +#define CAN_HR_TIME_STAMP9_TS(n) (((n) << CAN_HR_TIME_STAMP9_TS_SHIFT) & CAN_HR_TIME_STAMP9_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP10) */ +#define CAN_HR_TIME_STAMP10_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP10_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP10_TS_SHIFT) +#define CAN_HR_TIME_STAMP10_TS(n) (((n) << CAN_HR_TIME_STAMP10_TS_SHIFT) & CAN_HR_TIME_STAMP10_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP11) */ +#define CAN_HR_TIME_STAMP11_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP11_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP11_TS_SHIFT) +#define CAN_HR_TIME_STAMP11_TS(n) (((n) << CAN_HR_TIME_STAMP11_TS_SHIFT) & CAN_HR_TIME_STAMP11_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP12) */ +#define CAN_HR_TIME_STAMP12_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP12_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP12_TS_SHIFT) +#define CAN_HR_TIME_STAMP12_TS(n) (((n) << CAN_HR_TIME_STAMP12_TS_SHIFT) & CAN_HR_TIME_STAMP12_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP13) */ +#define CAN_HR_TIME_STAMP13_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP13_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP13_TS_SHIFT) +#define CAN_HR_TIME_STAMP13_TS(n) (((n) << CAN_HR_TIME_STAMP13_TS_SHIFT) & CAN_HR_TIME_STAMP13_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP14) */ +#define CAN_HR_TIME_STAMP14_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP14_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP14_TS_SHIFT) +#define CAN_HR_TIME_STAMP14_TS(n) (((n) << CAN_HR_TIME_STAMP14_TS_SHIFT) & CAN_HR_TIME_STAMP14_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP15) */ +#define CAN_HR_TIME_STAMP15_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP15_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP15_TS_SHIFT) +#define CAN_HR_TIME_STAMP15_TS(n) (((n) << CAN_HR_TIME_STAMP15_TS_SHIFT) & CAN_HR_TIME_STAMP15_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP16) */ +#define CAN_HR_TIME_STAMP16_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP16_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP16_TS_SHIFT) +#define CAN_HR_TIME_STAMP16_TS(n) (((n) << CAN_HR_TIME_STAMP16_TS_SHIFT) & CAN_HR_TIME_STAMP16_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP17) */ +#define CAN_HR_TIME_STAMP17_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP17_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP17_TS_SHIFT) +#define CAN_HR_TIME_STAMP17_TS(n) (((n) << CAN_HR_TIME_STAMP17_TS_SHIFT) & CAN_HR_TIME_STAMP17_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP18) */ +#define CAN_HR_TIME_STAMP18_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP18_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP18_TS_SHIFT) +#define CAN_HR_TIME_STAMP18_TS(n) (((n) << CAN_HR_TIME_STAMP18_TS_SHIFT) & CAN_HR_TIME_STAMP18_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP19) */ +#define CAN_HR_TIME_STAMP19_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP19_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP19_TS_SHIFT) +#define CAN_HR_TIME_STAMP19_TS(n) (((n) << CAN_HR_TIME_STAMP19_TS_SHIFT) & CAN_HR_TIME_STAMP19_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP20) */ +#define CAN_HR_TIME_STAMP20_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP20_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP20_TS_SHIFT) +#define CAN_HR_TIME_STAMP20_TS(n) (((n) << CAN_HR_TIME_STAMP20_TS_SHIFT) & CAN_HR_TIME_STAMP20_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP21) */ +#define CAN_HR_TIME_STAMP21_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP21_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP21_TS_SHIFT) +#define CAN_HR_TIME_STAMP21_TS(n) (((n) << CAN_HR_TIME_STAMP21_TS_SHIFT) & CAN_HR_TIME_STAMP21_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP22) */ +#define CAN_HR_TIME_STAMP22_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP22_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP22_TS_SHIFT) +#define CAN_HR_TIME_STAMP22_TS(n) (((n) << CAN_HR_TIME_STAMP22_TS_SHIFT) & CAN_HR_TIME_STAMP22_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP23) */ +#define CAN_HR_TIME_STAMP23_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP23_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP23_TS_SHIFT) +#define CAN_HR_TIME_STAMP23_TS(n) (((n) << CAN_HR_TIME_STAMP23_TS_SHIFT) & CAN_HR_TIME_STAMP23_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP24) */ +#define CAN_HR_TIME_STAMP24_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP24_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP24_TS_SHIFT) +#define CAN_HR_TIME_STAMP24_TS(n) (((n) << CAN_HR_TIME_STAMP24_TS_SHIFT) & CAN_HR_TIME_STAMP24_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP25) */ +#define CAN_HR_TIME_STAMP25_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP25_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP25_TS_SHIFT) +#define CAN_HR_TIME_STAMP25_TS(n) (((n) << CAN_HR_TIME_STAMP25_TS_SHIFT) & CAN_HR_TIME_STAMP25_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP26) */ +#define CAN_HR_TIME_STAMP26_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP26_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP26_TS_SHIFT) +#define CAN_HR_TIME_STAMP26_TS(n) (((n) << CAN_HR_TIME_STAMP26_TS_SHIFT) & CAN_HR_TIME_STAMP26_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP27) */ +#define CAN_HR_TIME_STAMP27_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP27_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP27_TS_SHIFT) +#define CAN_HR_TIME_STAMP27_TS(n) (((n) << CAN_HR_TIME_STAMP27_TS_SHIFT) & CAN_HR_TIME_STAMP27_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP28) */ +#define CAN_HR_TIME_STAMP28_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP28_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP28_TS_SHIFT) +#define CAN_HR_TIME_STAMP28_TS(n) (((n) << CAN_HR_TIME_STAMP28_TS_SHIFT) & CAN_HR_TIME_STAMP28_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP29) */ +#define CAN_HR_TIME_STAMP29_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP29_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP29_TS_SHIFT) +#define CAN_HR_TIME_STAMP29_TS(n) (((n) << CAN_HR_TIME_STAMP29_TS_SHIFT) & CAN_HR_TIME_STAMP29_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP30) */ +#define CAN_HR_TIME_STAMP30_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP30_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP30_TS_SHIFT) +#define CAN_HR_TIME_STAMP30_TS(n) (((n) << CAN_HR_TIME_STAMP30_TS_SHIFT) & CAN_HR_TIME_STAMP30_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP31) */ +#define CAN_HR_TIME_STAMP31_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP31_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP31_TS_SHIFT) +#define CAN_HR_TIME_STAMP31_TS(n) (((n) << CAN_HR_TIME_STAMP31_TS_SHIFT) & CAN_HR_TIME_STAMP31_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP32) */ +#define CAN_HR_TIME_STAMP32_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP32_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP32_TS_SHIFT) +#define CAN_HR_TIME_STAMP32_TS(n) (((n) << CAN_HR_TIME_STAMP32_TS_SHIFT) & CAN_HR_TIME_STAMP32_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP33) */ +#define CAN_HR_TIME_STAMP33_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP33_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP33_TS_SHIFT) +#define CAN_HR_TIME_STAMP33_TS(n) (((n) << CAN_HR_TIME_STAMP33_TS_SHIFT) & CAN_HR_TIME_STAMP33_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP34) */ +#define CAN_HR_TIME_STAMP34_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP34_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP34_TS_SHIFT) +#define CAN_HR_TIME_STAMP34_TS(n) (((n) << CAN_HR_TIME_STAMP34_TS_SHIFT) & CAN_HR_TIME_STAMP34_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP35) */ +#define CAN_HR_TIME_STAMP35_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP35_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP35_TS_SHIFT) +#define CAN_HR_TIME_STAMP35_TS(n) (((n) << CAN_HR_TIME_STAMP35_TS_SHIFT) & CAN_HR_TIME_STAMP35_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP36) */ +#define CAN_HR_TIME_STAMP36_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP36_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP36_TS_SHIFT) +#define CAN_HR_TIME_STAMP36_TS(n) (((n) << CAN_HR_TIME_STAMP36_TS_SHIFT) & CAN_HR_TIME_STAMP36_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP37) */ +#define CAN_HR_TIME_STAMP37_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP37_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP37_TS_SHIFT) +#define CAN_HR_TIME_STAMP37_TS(n) (((n) << CAN_HR_TIME_STAMP37_TS_SHIFT) & CAN_HR_TIME_STAMP37_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP38) */ +#define CAN_HR_TIME_STAMP38_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP38_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP38_TS_SHIFT) +#define CAN_HR_TIME_STAMP38_TS(n) (((n) << CAN_HR_TIME_STAMP38_TS_SHIFT) & CAN_HR_TIME_STAMP38_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP39) */ +#define CAN_HR_TIME_STAMP39_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP39_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP39_TS_SHIFT) +#define CAN_HR_TIME_STAMP39_TS(n) (((n) << CAN_HR_TIME_STAMP39_TS_SHIFT) & CAN_HR_TIME_STAMP39_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP40) */ +#define CAN_HR_TIME_STAMP40_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP40_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP40_TS_SHIFT) +#define CAN_HR_TIME_STAMP40_TS(n) (((n) << CAN_HR_TIME_STAMP40_TS_SHIFT) & CAN_HR_TIME_STAMP40_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP41) */ +#define CAN_HR_TIME_STAMP41_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP41_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP41_TS_SHIFT) +#define CAN_HR_TIME_STAMP41_TS(n) (((n) << CAN_HR_TIME_STAMP41_TS_SHIFT) & CAN_HR_TIME_STAMP41_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP42) */ +#define CAN_HR_TIME_STAMP42_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP42_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP42_TS_SHIFT) +#define CAN_HR_TIME_STAMP42_TS(n) (((n) << CAN_HR_TIME_STAMP42_TS_SHIFT) & CAN_HR_TIME_STAMP42_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP43) */ +#define CAN_HR_TIME_STAMP43_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP43_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP43_TS_SHIFT) +#define CAN_HR_TIME_STAMP43_TS(n) (((n) << CAN_HR_TIME_STAMP43_TS_SHIFT) & CAN_HR_TIME_STAMP43_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP44) */ +#define CAN_HR_TIME_STAMP44_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP44_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP44_TS_SHIFT) +#define CAN_HR_TIME_STAMP44_TS(n) (((n) << CAN_HR_TIME_STAMP44_TS_SHIFT) & CAN_HR_TIME_STAMP44_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP45) */ +#define CAN_HR_TIME_STAMP45_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP45_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP45_TS_SHIFT) +#define CAN_HR_TIME_STAMP45_TS(n) (((n) << CAN_HR_TIME_STAMP45_TS_SHIFT) & CAN_HR_TIME_STAMP45_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP46) */ +#define CAN_HR_TIME_STAMP46_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP46_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP46_TS_SHIFT) +#define CAN_HR_TIME_STAMP46_TS(n) (((n) << CAN_HR_TIME_STAMP46_TS_SHIFT) & CAN_HR_TIME_STAMP46_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP47) */ +#define CAN_HR_TIME_STAMP47_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP47_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP47_TS_SHIFT) +#define CAN_HR_TIME_STAMP47_TS(n) (((n) << CAN_HR_TIME_STAMP47_TS_SHIFT) & CAN_HR_TIME_STAMP47_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP48) */ +#define CAN_HR_TIME_STAMP48_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP48_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP48_TS_SHIFT) +#define CAN_HR_TIME_STAMP48_TS(n) (((n) << CAN_HR_TIME_STAMP48_TS_SHIFT) & CAN_HR_TIME_STAMP48_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP49) */ +#define CAN_HR_TIME_STAMP49_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP49_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP49_TS_SHIFT) +#define CAN_HR_TIME_STAMP49_TS(n) (((n) << CAN_HR_TIME_STAMP49_TS_SHIFT) & CAN_HR_TIME_STAMP49_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP50) */ +#define CAN_HR_TIME_STAMP50_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP50_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP50_TS_SHIFT) +#define CAN_HR_TIME_STAMP50_TS(n) (((n) << CAN_HR_TIME_STAMP50_TS_SHIFT) & CAN_HR_TIME_STAMP50_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP51) */ +#define CAN_HR_TIME_STAMP51_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP51_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP51_TS_SHIFT) +#define CAN_HR_TIME_STAMP51_TS(n) (((n) << CAN_HR_TIME_STAMP51_TS_SHIFT) & CAN_HR_TIME_STAMP51_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP52) */ +#define CAN_HR_TIME_STAMP52_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP52_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP52_TS_SHIFT) +#define CAN_HR_TIME_STAMP52_TS(n) (((n) << CAN_HR_TIME_STAMP52_TS_SHIFT) & CAN_HR_TIME_STAMP52_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP53) */ +#define CAN_HR_TIME_STAMP53_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP53_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP53_TS_SHIFT) +#define CAN_HR_TIME_STAMP53_TS(n) (((n) << CAN_HR_TIME_STAMP53_TS_SHIFT) & CAN_HR_TIME_STAMP53_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP54) */ +#define CAN_HR_TIME_STAMP54_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP54_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP54_TS_SHIFT) +#define CAN_HR_TIME_STAMP54_TS(n) (((n) << CAN_HR_TIME_STAMP54_TS_SHIFT) & CAN_HR_TIME_STAMP54_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP55) */ +#define CAN_HR_TIME_STAMP55_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP55_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP55_TS_SHIFT) +#define CAN_HR_TIME_STAMP55_TS(n) (((n) << CAN_HR_TIME_STAMP55_TS_SHIFT) & CAN_HR_TIME_STAMP55_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP56) */ +#define CAN_HR_TIME_STAMP56_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP56_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP56_TS_SHIFT) +#define CAN_HR_TIME_STAMP56_TS(n) (((n) << CAN_HR_TIME_STAMP56_TS_SHIFT) & CAN_HR_TIME_STAMP56_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP57) */ +#define CAN_HR_TIME_STAMP57_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP57_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP57_TS_SHIFT) +#define CAN_HR_TIME_STAMP57_TS(n) (((n) << CAN_HR_TIME_STAMP57_TS_SHIFT) & CAN_HR_TIME_STAMP57_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP58) */ +#define CAN_HR_TIME_STAMP58_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP58_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP58_TS_SHIFT) +#define CAN_HR_TIME_STAMP58_TS(n) (((n) << CAN_HR_TIME_STAMP58_TS_SHIFT) & CAN_HR_TIME_STAMP58_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP59) */ +#define CAN_HR_TIME_STAMP59_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP59_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP59_TS_SHIFT) +#define CAN_HR_TIME_STAMP59_TS(n) (((n) << CAN_HR_TIME_STAMP59_TS_SHIFT) & CAN_HR_TIME_STAMP59_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP60) */ +#define CAN_HR_TIME_STAMP60_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP60_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP60_TS_SHIFT) +#define CAN_HR_TIME_STAMP60_TS(n) (((n) << CAN_HR_TIME_STAMP60_TS_SHIFT) & CAN_HR_TIME_STAMP60_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP61) */ +#define CAN_HR_TIME_STAMP61_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP61_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP61_TS_SHIFT) +#define CAN_HR_TIME_STAMP61_TS(n) (((n) << CAN_HR_TIME_STAMP61_TS_SHIFT) & CAN_HR_TIME_STAMP61_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP62) */ +#define CAN_HR_TIME_STAMP62_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP62_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP62_TS_SHIFT) +#define CAN_HR_TIME_STAMP62_TS(n) (((n) << CAN_HR_TIME_STAMP62_TS_SHIFT) & CAN_HR_TIME_STAMP62_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP63) */ +#define CAN_HR_TIME_STAMP63_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP63_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP63_TS_SHIFT) +#define CAN_HR_TIME_STAMP63_TS(n) (((n) << CAN_HR_TIME_STAMP63_TS_SHIFT) & CAN_HR_TIME_STAMP63_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP64) */ +#define CAN_HR_TIME_STAMP64_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP64_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP64_TS_SHIFT) +#define CAN_HR_TIME_STAMP64_TS(n) (((n) << CAN_HR_TIME_STAMP64_TS_SHIFT) & CAN_HR_TIME_STAMP64_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP65) */ +#define CAN_HR_TIME_STAMP65_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP65_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP65_TS_SHIFT) +#define CAN_HR_TIME_STAMP65_TS(n) (((n) << CAN_HR_TIME_STAMP65_TS_SHIFT) & CAN_HR_TIME_STAMP65_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP66) */ +#define CAN_HR_TIME_STAMP66_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP66_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP66_TS_SHIFT) +#define CAN_HR_TIME_STAMP66_TS(n) (((n) << CAN_HR_TIME_STAMP66_TS_SHIFT) & CAN_HR_TIME_STAMP66_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP67) */ +#define CAN_HR_TIME_STAMP67_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP67_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP67_TS_SHIFT) +#define CAN_HR_TIME_STAMP67_TS(n) (((n) << CAN_HR_TIME_STAMP67_TS_SHIFT) & CAN_HR_TIME_STAMP67_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP68) */ +#define CAN_HR_TIME_STAMP68_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP68_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP68_TS_SHIFT) +#define CAN_HR_TIME_STAMP68_TS(n) (((n) << CAN_HR_TIME_STAMP68_TS_SHIFT) & CAN_HR_TIME_STAMP68_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP69) */ +#define CAN_HR_TIME_STAMP69_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP69_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP69_TS_SHIFT) +#define CAN_HR_TIME_STAMP69_TS(n) (((n) << CAN_HR_TIME_STAMP69_TS_SHIFT) & CAN_HR_TIME_STAMP69_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP70) */ +#define CAN_HR_TIME_STAMP70_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP70_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP70_TS_SHIFT) +#define CAN_HR_TIME_STAMP70_TS(n) (((n) << CAN_HR_TIME_STAMP70_TS_SHIFT) & CAN_HR_TIME_STAMP70_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP71) */ +#define CAN_HR_TIME_STAMP71_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP71_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP71_TS_SHIFT) +#define CAN_HR_TIME_STAMP71_TS(n) (((n) << CAN_HR_TIME_STAMP71_TS_SHIFT) & CAN_HR_TIME_STAMP71_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP72) */ +#define CAN_HR_TIME_STAMP72_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP72_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP72_TS_SHIFT) +#define CAN_HR_TIME_STAMP72_TS(n) (((n) << CAN_HR_TIME_STAMP72_TS_SHIFT) & CAN_HR_TIME_STAMP72_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP73) */ +#define CAN_HR_TIME_STAMP73_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP73_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP73_TS_SHIFT) +#define CAN_HR_TIME_STAMP73_TS(n) (((n) << CAN_HR_TIME_STAMP73_TS_SHIFT) & CAN_HR_TIME_STAMP73_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP74) */ +#define CAN_HR_TIME_STAMP74_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP74_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP74_TS_SHIFT) +#define CAN_HR_TIME_STAMP74_TS(n) (((n) << CAN_HR_TIME_STAMP74_TS_SHIFT) & CAN_HR_TIME_STAMP74_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP75) */ +#define CAN_HR_TIME_STAMP75_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP75_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP75_TS_SHIFT) +#define CAN_HR_TIME_STAMP75_TS(n) (((n) << CAN_HR_TIME_STAMP75_TS_SHIFT) & CAN_HR_TIME_STAMP75_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP76) */ +#define CAN_HR_TIME_STAMP76_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP76_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP76_TS_SHIFT) +#define CAN_HR_TIME_STAMP76_TS(n) (((n) << CAN_HR_TIME_STAMP76_TS_SHIFT) & CAN_HR_TIME_STAMP76_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP77) */ +#define CAN_HR_TIME_STAMP77_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP77_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP77_TS_SHIFT) +#define CAN_HR_TIME_STAMP77_TS(n) (((n) << CAN_HR_TIME_STAMP77_TS_SHIFT) & CAN_HR_TIME_STAMP77_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP78) */ +#define CAN_HR_TIME_STAMP78_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP78_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP78_TS_SHIFT) +#define CAN_HR_TIME_STAMP78_TS(n) (((n) << CAN_HR_TIME_STAMP78_TS_SHIFT) & CAN_HR_TIME_STAMP78_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP79) */ +#define CAN_HR_TIME_STAMP79_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP79_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP79_TS_SHIFT) +#define CAN_HR_TIME_STAMP79_TS(n) (((n) << CAN_HR_TIME_STAMP79_TS_SHIFT) & CAN_HR_TIME_STAMP79_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP80) */ +#define CAN_HR_TIME_STAMP80_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP80_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP80_TS_SHIFT) +#define CAN_HR_TIME_STAMP80_TS(n) (((n) << CAN_HR_TIME_STAMP80_TS_SHIFT) & CAN_HR_TIME_STAMP80_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP81) */ +#define CAN_HR_TIME_STAMP81_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP81_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP81_TS_SHIFT) +#define CAN_HR_TIME_STAMP81_TS(n) (((n) << CAN_HR_TIME_STAMP81_TS_SHIFT) & CAN_HR_TIME_STAMP81_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP82) */ +#define CAN_HR_TIME_STAMP82_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP82_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP82_TS_SHIFT) +#define CAN_HR_TIME_STAMP82_TS(n) (((n) << CAN_HR_TIME_STAMP82_TS_SHIFT) & CAN_HR_TIME_STAMP82_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP83) */ +#define CAN_HR_TIME_STAMP83_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP83_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP83_TS_SHIFT) +#define CAN_HR_TIME_STAMP83_TS(n) (((n) << CAN_HR_TIME_STAMP83_TS_SHIFT) & CAN_HR_TIME_STAMP83_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP84) */ +#define CAN_HR_TIME_STAMP84_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP84_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP84_TS_SHIFT) +#define CAN_HR_TIME_STAMP84_TS(n) (((n) << CAN_HR_TIME_STAMP84_TS_SHIFT) & CAN_HR_TIME_STAMP84_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP85) */ +#define CAN_HR_TIME_STAMP85_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP85_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP85_TS_SHIFT) +#define CAN_HR_TIME_STAMP85_TS(n) (((n) << CAN_HR_TIME_STAMP85_TS_SHIFT) & CAN_HR_TIME_STAMP85_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP86) */ +#define CAN_HR_TIME_STAMP86_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP86_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP86_TS_SHIFT) +#define CAN_HR_TIME_STAMP86_TS(n) (((n) << CAN_HR_TIME_STAMP86_TS_SHIFT) & CAN_HR_TIME_STAMP86_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP87) */ +#define CAN_HR_TIME_STAMP87_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP87_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP87_TS_SHIFT) +#define CAN_HR_TIME_STAMP87_TS(n) (((n) << CAN_HR_TIME_STAMP87_TS_SHIFT) & CAN_HR_TIME_STAMP87_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP88) */ +#define CAN_HR_TIME_STAMP88_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP88_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP88_TS_SHIFT) +#define CAN_HR_TIME_STAMP88_TS(n) (((n) << CAN_HR_TIME_STAMP88_TS_SHIFT) & CAN_HR_TIME_STAMP88_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP89) */ +#define CAN_HR_TIME_STAMP89_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP89_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP89_TS_SHIFT) +#define CAN_HR_TIME_STAMP89_TS(n) (((n) << CAN_HR_TIME_STAMP89_TS_SHIFT) & CAN_HR_TIME_STAMP89_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP90) */ +#define CAN_HR_TIME_STAMP90_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP90_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP90_TS_SHIFT) +#define CAN_HR_TIME_STAMP90_TS(n) (((n) << CAN_HR_TIME_STAMP90_TS_SHIFT) & CAN_HR_TIME_STAMP90_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP91) */ +#define CAN_HR_TIME_STAMP91_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP91_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP91_TS_SHIFT) +#define CAN_HR_TIME_STAMP91_TS(n) (((n) << CAN_HR_TIME_STAMP91_TS_SHIFT) & CAN_HR_TIME_STAMP91_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP92) */ +#define CAN_HR_TIME_STAMP92_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP92_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP92_TS_SHIFT) +#define CAN_HR_TIME_STAMP92_TS(n) (((n) << CAN_HR_TIME_STAMP92_TS_SHIFT) & CAN_HR_TIME_STAMP92_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP93) */ +#define CAN_HR_TIME_STAMP93_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP93_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP93_TS_SHIFT) +#define CAN_HR_TIME_STAMP93_TS(n) (((n) << CAN_HR_TIME_STAMP93_TS_SHIFT) & CAN_HR_TIME_STAMP93_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP94) */ +#define CAN_HR_TIME_STAMP94_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP94_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP94_TS_SHIFT) +#define CAN_HR_TIME_STAMP94_TS(n) (((n) << CAN_HR_TIME_STAMP94_TS_SHIFT) & CAN_HR_TIME_STAMP94_TS_MASK) + +/* High-Resolution Timestamp (HR_TIME_STAMP95) */ +#define CAN_HR_TIME_STAMP95_TS_SHIFT (0) /* Bits 0-32: High-Resolution Timestamp */ +#define CAN_HR_TIME_STAMP95_TS_MASK (0xFFFFFFFF << CAN_HR_TIME_STAMP95_TS_SHIFT) +#define CAN_HR_TIME_STAMP95_TS(n) (((n) << CAN_HR_TIME_STAMP95_TS_SHIFT) & CAN_HR_TIME_STAMP95_TS_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL0) */ +#define CAN_ERFFEL0_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL0_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL0_FEL_SHIFT) +#define CAN_ERFFEL0_FEL(n) (((n) << CAN_ERFFEL0_FEL_SHIFT) & CAN_ERFFEL0_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL1) */ +#define CAN_ERFFEL1_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL1_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL1_FEL_SHIFT) +#define CAN_ERFFEL1_FEL(n) (((n) << CAN_ERFFEL1_FEL_SHIFT) & CAN_ERFFEL1_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL2) */ +#define CAN_ERFFEL2_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL2_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL2_FEL_SHIFT) +#define CAN_ERFFEL2_FEL(n) (((n) << CAN_ERFFEL2_FEL_SHIFT) & CAN_ERFFEL2_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL3) */ +#define CAN_ERFFEL3_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL3_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL3_FEL_SHIFT) +#define CAN_ERFFEL3_FEL(n) (((n) << CAN_ERFFEL3_FEL_SHIFT) & CAN_ERFFEL3_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL4) */ +#define CAN_ERFFEL4_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL4_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL4_FEL_SHIFT) +#define CAN_ERFFEL4_FEL(n) (((n) << CAN_ERFFEL4_FEL_SHIFT) & CAN_ERFFEL4_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL5) */ +#define CAN_ERFFEL5_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL5_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL5_FEL_SHIFT) +#define CAN_ERFFEL5_FEL(n) (((n) << CAN_ERFFEL5_FEL_SHIFT) & CAN_ERFFEL5_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL6) */ +#define CAN_ERFFEL6_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL6_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL6_FEL_SHIFT) +#define CAN_ERFFEL6_FEL(n) (((n) << CAN_ERFFEL6_FEL_SHIFT) & CAN_ERFFEL6_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL7) */ +#define CAN_ERFFEL7_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL7_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL7_FEL_SHIFT) +#define CAN_ERFFEL7_FEL(n) (((n) << CAN_ERFFEL7_FEL_SHIFT) & CAN_ERFFEL7_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL8) */ +#define CAN_ERFFEL8_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL8_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL8_FEL_SHIFT) +#define CAN_ERFFEL8_FEL(n) (((n) << CAN_ERFFEL8_FEL_SHIFT) & CAN_ERFFEL8_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL9) */ +#define CAN_ERFFEL9_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL9_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL9_FEL_SHIFT) +#define CAN_ERFFEL9_FEL(n) (((n) << CAN_ERFFEL9_FEL_SHIFT) & CAN_ERFFEL9_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL10) */ +#define CAN_ERFFEL10_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL10_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL10_FEL_SHIFT) +#define CAN_ERFFEL10_FEL(n) (((n) << CAN_ERFFEL10_FEL_SHIFT) & CAN_ERFFEL10_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL11) */ +#define CAN_ERFFEL11_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL11_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL11_FEL_SHIFT) +#define CAN_ERFFEL11_FEL(n) (((n) << CAN_ERFFEL11_FEL_SHIFT) & CAN_ERFFEL11_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL12) */ +#define CAN_ERFFEL12_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL12_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL12_FEL_SHIFT) +#define CAN_ERFFEL12_FEL(n) (((n) << CAN_ERFFEL12_FEL_SHIFT) & CAN_ERFFEL12_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL13) */ +#define CAN_ERFFEL13_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL13_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL13_FEL_SHIFT) +#define CAN_ERFFEL13_FEL(n) (((n) << CAN_ERFFEL13_FEL_SHIFT) & CAN_ERFFEL13_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL14) */ +#define CAN_ERFFEL14_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL14_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL14_FEL_SHIFT) +#define CAN_ERFFEL14_FEL(n) (((n) << CAN_ERFFEL14_FEL_SHIFT) & CAN_ERFFEL14_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL15) */ +#define CAN_ERFFEL15_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL15_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL15_FEL_SHIFT) +#define CAN_ERFFEL15_FEL(n) (((n) << CAN_ERFFEL15_FEL_SHIFT) & CAN_ERFFEL15_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL16) */ +#define CAN_ERFFEL16_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL16_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL16_FEL_SHIFT) +#define CAN_ERFFEL16_FEL(n) (((n) << CAN_ERFFEL16_FEL_SHIFT) & CAN_ERFFEL16_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL17) */ +#define CAN_ERFFEL17_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL17_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL17_FEL_SHIFT) +#define CAN_ERFFEL17_FEL(n) (((n) << CAN_ERFFEL17_FEL_SHIFT) & CAN_ERFFEL17_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL18) */ +#define CAN_ERFFEL18_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL18_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL18_FEL_SHIFT) +#define CAN_ERFFEL18_FEL(n) (((n) << CAN_ERFFEL18_FEL_SHIFT) & CAN_ERFFEL18_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL19) */ +#define CAN_ERFFEL19_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL19_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL19_FEL_SHIFT) +#define CAN_ERFFEL19_FEL(n) (((n) << CAN_ERFFEL19_FEL_SHIFT) & CAN_ERFFEL19_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL20) */ +#define CAN_ERFFEL20_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL20_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL20_FEL_SHIFT) +#define CAN_ERFFEL20_FEL(n) (((n) << CAN_ERFFEL20_FEL_SHIFT) & CAN_ERFFEL20_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL21) */ +#define CAN_ERFFEL21_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL21_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL21_FEL_SHIFT) +#define CAN_ERFFEL21_FEL(n) (((n) << CAN_ERFFEL21_FEL_SHIFT) & CAN_ERFFEL21_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL22) */ +#define CAN_ERFFEL22_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL22_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL22_FEL_SHIFT) +#define CAN_ERFFEL22_FEL(n) (((n) << CAN_ERFFEL22_FEL_SHIFT) & CAN_ERFFEL22_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL23) */ +#define CAN_ERFFEL23_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL23_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL23_FEL_SHIFT) +#define CAN_ERFFEL23_FEL(n) (((n) << CAN_ERFFEL23_FEL_SHIFT) & CAN_ERFFEL23_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL24) */ +#define CAN_ERFFEL24_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL24_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL24_FEL_SHIFT) +#define CAN_ERFFEL24_FEL(n) (((n) << CAN_ERFFEL24_FEL_SHIFT) & CAN_ERFFEL24_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL25) */ +#define CAN_ERFFEL25_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL25_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL25_FEL_SHIFT) +#define CAN_ERFFEL25_FEL(n) (((n) << CAN_ERFFEL25_FEL_SHIFT) & CAN_ERFFEL25_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL26) */ +#define CAN_ERFFEL26_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL26_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL26_FEL_SHIFT) +#define CAN_ERFFEL26_FEL(n) (((n) << CAN_ERFFEL26_FEL_SHIFT) & CAN_ERFFEL26_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL27) */ +#define CAN_ERFFEL27_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL27_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL27_FEL_SHIFT) +#define CAN_ERFFEL27_FEL(n) (((n) << CAN_ERFFEL27_FEL_SHIFT) & CAN_ERFFEL27_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL28) */ +#define CAN_ERFFEL28_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL28_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL28_FEL_SHIFT) +#define CAN_ERFFEL28_FEL(n) (((n) << CAN_ERFFEL28_FEL_SHIFT) & CAN_ERFFEL28_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL29) */ +#define CAN_ERFFEL29_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL29_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL29_FEL_SHIFT) +#define CAN_ERFFEL29_FEL(n) (((n) << CAN_ERFFEL29_FEL_SHIFT) & CAN_ERFFEL29_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL30) */ +#define CAN_ERFFEL30_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL30_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL30_FEL_SHIFT) +#define CAN_ERFFEL30_FEL(n) (((n) << CAN_ERFFEL30_FEL_SHIFT) & CAN_ERFFEL30_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL31) */ +#define CAN_ERFFEL31_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL31_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL31_FEL_SHIFT) +#define CAN_ERFFEL31_FEL(n) (((n) << CAN_ERFFEL31_FEL_SHIFT) & CAN_ERFFEL31_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL32) */ +#define CAN_ERFFEL32_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL32_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL32_FEL_SHIFT) +#define CAN_ERFFEL32_FEL(n) (((n) << CAN_ERFFEL32_FEL_SHIFT) & CAN_ERFFEL32_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL33) */ +#define CAN_ERFFEL33_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL33_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL33_FEL_SHIFT) +#define CAN_ERFFEL33_FEL(n) (((n) << CAN_ERFFEL33_FEL_SHIFT) & CAN_ERFFEL33_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL34) */ +#define CAN_ERFFEL34_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL34_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL34_FEL_SHIFT) +#define CAN_ERFFEL34_FEL(n) (((n) << CAN_ERFFEL34_FEL_SHIFT) & CAN_ERFFEL34_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL35) */ +#define CAN_ERFFEL35_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL35_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL35_FEL_SHIFT) +#define CAN_ERFFEL35_FEL(n) (((n) << CAN_ERFFEL35_FEL_SHIFT) & CAN_ERFFEL35_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL36) */ +#define CAN_ERFFEL36_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL36_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL36_FEL_SHIFT) +#define CAN_ERFFEL36_FEL(n) (((n) << CAN_ERFFEL36_FEL_SHIFT) & CAN_ERFFEL36_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL37) */ +#define CAN_ERFFEL37_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL37_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL37_FEL_SHIFT) +#define CAN_ERFFEL37_FEL(n) (((n) << CAN_ERFFEL37_FEL_SHIFT) & CAN_ERFFEL37_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL38) */ +#define CAN_ERFFEL38_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL38_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL38_FEL_SHIFT) +#define CAN_ERFFEL38_FEL(n) (((n) << CAN_ERFFEL38_FEL_SHIFT) & CAN_ERFFEL38_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL39) */ +#define CAN_ERFFEL39_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL39_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL39_FEL_SHIFT) +#define CAN_ERFFEL39_FEL(n) (((n) << CAN_ERFFEL39_FEL_SHIFT) & CAN_ERFFEL39_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL40) */ +#define CAN_ERFFEL40_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL40_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL40_FEL_SHIFT) +#define CAN_ERFFEL40_FEL(n) (((n) << CAN_ERFFEL40_FEL_SHIFT) & CAN_ERFFEL40_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL41) */ +#define CAN_ERFFEL41_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL41_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL41_FEL_SHIFT) +#define CAN_ERFFEL41_FEL(n) (((n) << CAN_ERFFEL41_FEL_SHIFT) & CAN_ERFFEL41_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL42) */ +#define CAN_ERFFEL42_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL42_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL42_FEL_SHIFT) +#define CAN_ERFFEL42_FEL(n) (((n) << CAN_ERFFEL42_FEL_SHIFT) & CAN_ERFFEL42_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL43) */ +#define CAN_ERFFEL43_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL43_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL43_FEL_SHIFT) +#define CAN_ERFFEL43_FEL(n) (((n) << CAN_ERFFEL43_FEL_SHIFT) & CAN_ERFFEL43_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL44) */ +#define CAN_ERFFEL44_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL44_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL44_FEL_SHIFT) +#define CAN_ERFFEL44_FEL(n) (((n) << CAN_ERFFEL44_FEL_SHIFT) & CAN_ERFFEL44_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL45) */ +#define CAN_ERFFEL45_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL45_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL45_FEL_SHIFT) +#define CAN_ERFFEL45_FEL(n) (((n) << CAN_ERFFEL45_FEL_SHIFT) & CAN_ERFFEL45_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL46) */ +#define CAN_ERFFEL46_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL46_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL46_FEL_SHIFT) +#define CAN_ERFFEL46_FEL(n) (((n) << CAN_ERFFEL46_FEL_SHIFT) & CAN_ERFFEL46_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL47) */ +#define CAN_ERFFEL47_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL47_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL47_FEL_SHIFT) +#define CAN_ERFFEL47_FEL(n) (((n) << CAN_ERFFEL47_FEL_SHIFT) & CAN_ERFFEL47_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL48) */ +#define CAN_ERFFEL48_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL48_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL48_FEL_SHIFT) +#define CAN_ERFFEL48_FEL(n) (((n) << CAN_ERFFEL48_FEL_SHIFT) & CAN_ERFFEL48_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL49) */ +#define CAN_ERFFEL49_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL49_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL49_FEL_SHIFT) +#define CAN_ERFFEL49_FEL(n) (((n) << CAN_ERFFEL49_FEL_SHIFT) & CAN_ERFFEL49_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL50) */ +#define CAN_ERFFEL50_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL50_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL50_FEL_SHIFT) +#define CAN_ERFFEL50_FEL(n) (((n) << CAN_ERFFEL50_FEL_SHIFT) & CAN_ERFFEL50_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL51) */ +#define CAN_ERFFEL51_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL51_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL51_FEL_SHIFT) +#define CAN_ERFFEL51_FEL(n) (((n) << CAN_ERFFEL51_FEL_SHIFT) & CAN_ERFFEL51_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL52) */ +#define CAN_ERFFEL52_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL52_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL52_FEL_SHIFT) +#define CAN_ERFFEL52_FEL(n) (((n) << CAN_ERFFEL52_FEL_SHIFT) & CAN_ERFFEL52_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL53) */ +#define CAN_ERFFEL53_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL53_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL53_FEL_SHIFT) +#define CAN_ERFFEL53_FEL(n) (((n) << CAN_ERFFEL53_FEL_SHIFT) & CAN_ERFFEL53_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL54) */ +#define CAN_ERFFEL54_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL54_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL54_FEL_SHIFT) +#define CAN_ERFFEL54_FEL(n) (((n) << CAN_ERFFEL54_FEL_SHIFT) & CAN_ERFFEL54_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL55) */ +#define CAN_ERFFEL55_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL55_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL55_FEL_SHIFT) +#define CAN_ERFFEL55_FEL(n) (((n) << CAN_ERFFEL55_FEL_SHIFT) & CAN_ERFFEL55_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL56) */ +#define CAN_ERFFEL56_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL56_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL56_FEL_SHIFT) +#define CAN_ERFFEL56_FEL(n) (((n) << CAN_ERFFEL56_FEL_SHIFT) & CAN_ERFFEL56_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL57) */ +#define CAN_ERFFEL57_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL57_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL57_FEL_SHIFT) +#define CAN_ERFFEL57_FEL(n) (((n) << CAN_ERFFEL57_FEL_SHIFT) & CAN_ERFFEL57_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL58) */ +#define CAN_ERFFEL58_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL58_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL58_FEL_SHIFT) +#define CAN_ERFFEL58_FEL(n) (((n) << CAN_ERFFEL58_FEL_SHIFT) & CAN_ERFFEL58_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL59) */ +#define CAN_ERFFEL59_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL59_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL59_FEL_SHIFT) +#define CAN_ERFFEL59_FEL(n) (((n) << CAN_ERFFEL59_FEL_SHIFT) & CAN_ERFFEL59_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL60) */ +#define CAN_ERFFEL60_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL60_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL60_FEL_SHIFT) +#define CAN_ERFFEL60_FEL(n) (((n) << CAN_ERFFEL60_FEL_SHIFT) & CAN_ERFFEL60_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL61) */ +#define CAN_ERFFEL61_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL61_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL61_FEL_SHIFT) +#define CAN_ERFFEL61_FEL(n) (((n) << CAN_ERFFEL61_FEL_SHIFT) & CAN_ERFFEL61_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL62) */ +#define CAN_ERFFEL62_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL62_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL62_FEL_SHIFT) +#define CAN_ERFFEL62_FEL(n) (((n) << CAN_ERFFEL62_FEL_SHIFT) & CAN_ERFFEL62_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL63) */ +#define CAN_ERFFEL63_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL63_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL63_FEL_SHIFT) +#define CAN_ERFFEL63_FEL(n) (((n) << CAN_ERFFEL63_FEL_SHIFT) & CAN_ERFFEL63_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL64) */ +#define CAN_ERFFEL64_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL64_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL64_FEL_SHIFT) +#define CAN_ERFFEL64_FEL(n) (((n) << CAN_ERFFEL64_FEL_SHIFT) & CAN_ERFFEL64_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL65) */ +#define CAN_ERFFEL65_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL65_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL65_FEL_SHIFT) +#define CAN_ERFFEL65_FEL(n) (((n) << CAN_ERFFEL65_FEL_SHIFT) & CAN_ERFFEL65_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL66) */ +#define CAN_ERFFEL66_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL66_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL66_FEL_SHIFT) +#define CAN_ERFFEL66_FEL(n) (((n) << CAN_ERFFEL66_FEL_SHIFT) & CAN_ERFFEL66_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL67) */ +#define CAN_ERFFEL67_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL67_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL67_FEL_SHIFT) +#define CAN_ERFFEL67_FEL(n) (((n) << CAN_ERFFEL67_FEL_SHIFT) & CAN_ERFFEL67_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL68) */ +#define CAN_ERFFEL68_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL68_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL68_FEL_SHIFT) +#define CAN_ERFFEL68_FEL(n) (((n) << CAN_ERFFEL68_FEL_SHIFT) & CAN_ERFFEL68_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL69) */ +#define CAN_ERFFEL69_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL69_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL69_FEL_SHIFT) +#define CAN_ERFFEL69_FEL(n) (((n) << CAN_ERFFEL69_FEL_SHIFT) & CAN_ERFFEL69_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL70) */ +#define CAN_ERFFEL70_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL70_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL70_FEL_SHIFT) +#define CAN_ERFFEL70_FEL(n) (((n) << CAN_ERFFEL70_FEL_SHIFT) & CAN_ERFFEL70_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL71) */ +#define CAN_ERFFEL71_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL71_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL71_FEL_SHIFT) +#define CAN_ERFFEL71_FEL(n) (((n) << CAN_ERFFEL71_FEL_SHIFT) & CAN_ERFFEL71_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL72) */ +#define CAN_ERFFEL72_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL72_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL72_FEL_SHIFT) +#define CAN_ERFFEL72_FEL(n) (((n) << CAN_ERFFEL72_FEL_SHIFT) & CAN_ERFFEL72_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL73) */ +#define CAN_ERFFEL73_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL73_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL73_FEL_SHIFT) +#define CAN_ERFFEL73_FEL(n) (((n) << CAN_ERFFEL73_FEL_SHIFT) & CAN_ERFFEL73_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL74) */ +#define CAN_ERFFEL74_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL74_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL74_FEL_SHIFT) +#define CAN_ERFFEL74_FEL(n) (((n) << CAN_ERFFEL74_FEL_SHIFT) & CAN_ERFFEL74_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL75) */ +#define CAN_ERFFEL75_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL75_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL75_FEL_SHIFT) +#define CAN_ERFFEL75_FEL(n) (((n) << CAN_ERFFEL75_FEL_SHIFT) & CAN_ERFFEL75_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL76) */ +#define CAN_ERFFEL76_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL76_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL76_FEL_SHIFT) +#define CAN_ERFFEL76_FEL(n) (((n) << CAN_ERFFEL76_FEL_SHIFT) & CAN_ERFFEL76_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL77) */ +#define CAN_ERFFEL77_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL77_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL77_FEL_SHIFT) +#define CAN_ERFFEL77_FEL(n) (((n) << CAN_ERFFEL77_FEL_SHIFT) & CAN_ERFFEL77_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL78) */ +#define CAN_ERFFEL78_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL78_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL78_FEL_SHIFT) +#define CAN_ERFFEL78_FEL(n) (((n) << CAN_ERFFEL78_FEL_SHIFT) & CAN_ERFFEL78_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL79) */ +#define CAN_ERFFEL79_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL79_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL79_FEL_SHIFT) +#define CAN_ERFFEL79_FEL(n) (((n) << CAN_ERFFEL79_FEL_SHIFT) & CAN_ERFFEL79_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL80) */ +#define CAN_ERFFEL80_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL80_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL80_FEL_SHIFT) +#define CAN_ERFFEL80_FEL(n) (((n) << CAN_ERFFEL80_FEL_SHIFT) & CAN_ERFFEL80_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL81) */ +#define CAN_ERFFEL81_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL81_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL81_FEL_SHIFT) +#define CAN_ERFFEL81_FEL(n) (((n) << CAN_ERFFEL81_FEL_SHIFT) & CAN_ERFFEL81_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL82) */ +#define CAN_ERFFEL82_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL82_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL82_FEL_SHIFT) +#define CAN_ERFFEL82_FEL(n) (((n) << CAN_ERFFEL82_FEL_SHIFT) & CAN_ERFFEL82_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL83) */ +#define CAN_ERFFEL83_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL83_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL83_FEL_SHIFT) +#define CAN_ERFFEL83_FEL(n) (((n) << CAN_ERFFEL83_FEL_SHIFT) & CAN_ERFFEL83_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL84) */ +#define CAN_ERFFEL84_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL84_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL84_FEL_SHIFT) +#define CAN_ERFFEL84_FEL(n) (((n) << CAN_ERFFEL84_FEL_SHIFT) & CAN_ERFFEL84_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL85) */ +#define CAN_ERFFEL85_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL85_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL85_FEL_SHIFT) +#define CAN_ERFFEL85_FEL(n) (((n) << CAN_ERFFEL85_FEL_SHIFT) & CAN_ERFFEL85_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL86) */ +#define CAN_ERFFEL86_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL86_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL86_FEL_SHIFT) +#define CAN_ERFFEL86_FEL(n) (((n) << CAN_ERFFEL86_FEL_SHIFT) & CAN_ERFFEL86_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL87) */ +#define CAN_ERFFEL87_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL87_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL87_FEL_SHIFT) +#define CAN_ERFFEL87_FEL(n) (((n) << CAN_ERFFEL87_FEL_SHIFT) & CAN_ERFFEL87_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL88) */ +#define CAN_ERFFEL88_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL88_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL88_FEL_SHIFT) +#define CAN_ERFFEL88_FEL(n) (((n) << CAN_ERFFEL88_FEL_SHIFT) & CAN_ERFFEL88_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL89) */ +#define CAN_ERFFEL89_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL89_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL89_FEL_SHIFT) +#define CAN_ERFFEL89_FEL(n) (((n) << CAN_ERFFEL89_FEL_SHIFT) & CAN_ERFFEL89_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL90) */ +#define CAN_ERFFEL90_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL90_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL90_FEL_SHIFT) +#define CAN_ERFFEL90_FEL(n) (((n) << CAN_ERFFEL90_FEL_SHIFT) & CAN_ERFFEL90_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL91) */ +#define CAN_ERFFEL91_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL91_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL91_FEL_SHIFT) +#define CAN_ERFFEL91_FEL(n) (((n) << CAN_ERFFEL91_FEL_SHIFT) & CAN_ERFFEL91_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL92) */ +#define CAN_ERFFEL92_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL92_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL92_FEL_SHIFT) +#define CAN_ERFFEL92_FEL(n) (((n) << CAN_ERFFEL92_FEL_SHIFT) & CAN_ERFFEL92_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL93) */ +#define CAN_ERFFEL93_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL93_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL93_FEL_SHIFT) +#define CAN_ERFFEL93_FEL(n) (((n) << CAN_ERFFEL93_FEL_SHIFT) & CAN_ERFFEL93_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL94) */ +#define CAN_ERFFEL94_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL94_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL94_FEL_SHIFT) +#define CAN_ERFFEL94_FEL(n) (((n) << CAN_ERFFEL94_FEL_SHIFT) & CAN_ERFFEL94_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL95) */ +#define CAN_ERFFEL95_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL95_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL95_FEL_SHIFT) +#define CAN_ERFFEL95_FEL(n) (((n) << CAN_ERFFEL95_FEL_SHIFT) & CAN_ERFFEL95_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL96) */ +#define CAN_ERFFEL96_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL96_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL96_FEL_SHIFT) +#define CAN_ERFFEL96_FEL(n) (((n) << CAN_ERFFEL96_FEL_SHIFT) & CAN_ERFFEL96_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL97) */ +#define CAN_ERFFEL97_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL97_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL97_FEL_SHIFT) +#define CAN_ERFFEL97_FEL(n) (((n) << CAN_ERFFEL97_FEL_SHIFT) & CAN_ERFFEL97_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL98) */ +#define CAN_ERFFEL98_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL98_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL98_FEL_SHIFT) +#define CAN_ERFFEL98_FEL(n) (((n) << CAN_ERFFEL98_FEL_SHIFT) & CAN_ERFFEL98_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL99) */ +#define CAN_ERFFEL99_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL99_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL99_FEL_SHIFT) +#define CAN_ERFFEL99_FEL(n) (((n) << CAN_ERFFEL99_FEL_SHIFT) & CAN_ERFFEL99_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL100) */ +#define CAN_ERFFEL100_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL100_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL100_FEL_SHIFT) +#define CAN_ERFFEL100_FEL(n) (((n) << CAN_ERFFEL100_FEL_SHIFT) & CAN_ERFFEL100_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL101) */ +#define CAN_ERFFEL101_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL101_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL101_FEL_SHIFT) +#define CAN_ERFFEL101_FEL(n) (((n) << CAN_ERFFEL101_FEL_SHIFT) & CAN_ERFFEL101_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL102) */ +#define CAN_ERFFEL102_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL102_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL102_FEL_SHIFT) +#define CAN_ERFFEL102_FEL(n) (((n) << CAN_ERFFEL102_FEL_SHIFT) & CAN_ERFFEL102_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL103) */ +#define CAN_ERFFEL103_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL103_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL103_FEL_SHIFT) +#define CAN_ERFFEL103_FEL(n) (((n) << CAN_ERFFEL103_FEL_SHIFT) & CAN_ERFFEL103_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL104) */ +#define CAN_ERFFEL104_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL104_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL104_FEL_SHIFT) +#define CAN_ERFFEL104_FEL(n) (((n) << CAN_ERFFEL104_FEL_SHIFT) & CAN_ERFFEL104_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL105) */ +#define CAN_ERFFEL105_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL105_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL105_FEL_SHIFT) +#define CAN_ERFFEL105_FEL(n) (((n) << CAN_ERFFEL105_FEL_SHIFT) & CAN_ERFFEL105_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL106) */ +#define CAN_ERFFEL106_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL106_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL106_FEL_SHIFT) +#define CAN_ERFFEL106_FEL(n) (((n) << CAN_ERFFEL106_FEL_SHIFT) & CAN_ERFFEL106_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL107) */ +#define CAN_ERFFEL107_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL107_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL107_FEL_SHIFT) +#define CAN_ERFFEL107_FEL(n) (((n) << CAN_ERFFEL107_FEL_SHIFT) & CAN_ERFFEL107_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL108) */ +#define CAN_ERFFEL108_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL108_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL108_FEL_SHIFT) +#define CAN_ERFFEL108_FEL(n) (((n) << CAN_ERFFEL108_FEL_SHIFT) & CAN_ERFFEL108_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL109) */ +#define CAN_ERFFEL109_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL109_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL109_FEL_SHIFT) +#define CAN_ERFFEL109_FEL(n) (((n) << CAN_ERFFEL109_FEL_SHIFT) & CAN_ERFFEL109_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL110) */ +#define CAN_ERFFEL110_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL110_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL110_FEL_SHIFT) +#define CAN_ERFFEL110_FEL(n) (((n) << CAN_ERFFEL110_FEL_SHIFT) & CAN_ERFFEL110_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL111) */ +#define CAN_ERFFEL111_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL111_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL111_FEL_SHIFT) +#define CAN_ERFFEL111_FEL(n) (((n) << CAN_ERFFEL111_FEL_SHIFT) & CAN_ERFFEL111_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL112) */ +#define CAN_ERFFEL112_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL112_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL112_FEL_SHIFT) +#define CAN_ERFFEL112_FEL(n) (((n) << CAN_ERFFEL112_FEL_SHIFT) & CAN_ERFFEL112_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL113) */ +#define CAN_ERFFEL113_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL113_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL113_FEL_SHIFT) +#define CAN_ERFFEL113_FEL(n) (((n) << CAN_ERFFEL113_FEL_SHIFT) & CAN_ERFFEL113_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL114) */ +#define CAN_ERFFEL114_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL114_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL114_FEL_SHIFT) +#define CAN_ERFFEL114_FEL(n) (((n) << CAN_ERFFEL114_FEL_SHIFT) & CAN_ERFFEL114_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL115) */ +#define CAN_ERFFEL115_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL115_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL115_FEL_SHIFT) +#define CAN_ERFFEL115_FEL(n) (((n) << CAN_ERFFEL115_FEL_SHIFT) & CAN_ERFFEL115_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL116) */ +#define CAN_ERFFEL116_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL116_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL116_FEL_SHIFT) +#define CAN_ERFFEL116_FEL(n) (((n) << CAN_ERFFEL116_FEL_SHIFT) & CAN_ERFFEL116_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL117) */ +#define CAN_ERFFEL117_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL117_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL117_FEL_SHIFT) +#define CAN_ERFFEL117_FEL(n) (((n) << CAN_ERFFEL117_FEL_SHIFT) & CAN_ERFFEL117_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL118) */ +#define CAN_ERFFEL118_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL118_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL118_FEL_SHIFT) +#define CAN_ERFFEL118_FEL(n) (((n) << CAN_ERFFEL118_FEL_SHIFT) & CAN_ERFFEL118_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL119) */ +#define CAN_ERFFEL119_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL119_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL119_FEL_SHIFT) +#define CAN_ERFFEL119_FEL(n) (((n) << CAN_ERFFEL119_FEL_SHIFT) & CAN_ERFFEL119_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL120) */ +#define CAN_ERFFEL120_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL120_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL120_FEL_SHIFT) +#define CAN_ERFFEL120_FEL(n) (((n) << CAN_ERFFEL120_FEL_SHIFT) & CAN_ERFFEL120_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL121) */ +#define CAN_ERFFEL121_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL121_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL121_FEL_SHIFT) +#define CAN_ERFFEL121_FEL(n) (((n) << CAN_ERFFEL121_FEL_SHIFT) & CAN_ERFFEL121_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL122) */ +#define CAN_ERFFEL122_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL122_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL122_FEL_SHIFT) +#define CAN_ERFFEL122_FEL(n) (((n) << CAN_ERFFEL122_FEL_SHIFT) & CAN_ERFFEL122_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL123) */ +#define CAN_ERFFEL123_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL123_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL123_FEL_SHIFT) +#define CAN_ERFFEL123_FEL(n) (((n) << CAN_ERFFEL123_FEL_SHIFT) & CAN_ERFFEL123_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL124) */ +#define CAN_ERFFEL124_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL124_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL124_FEL_SHIFT) +#define CAN_ERFFEL124_FEL(n) (((n) << CAN_ERFFEL124_FEL_SHIFT) & CAN_ERFFEL124_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL125) */ +#define CAN_ERFFEL125_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL125_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL125_FEL_SHIFT) +#define CAN_ERFFEL125_FEL(n) (((n) << CAN_ERFFEL125_FEL_SHIFT) & CAN_ERFFEL125_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL126) */ +#define CAN_ERFFEL126_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL126_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL126_FEL_SHIFT) +#define CAN_ERFFEL126_FEL(n) (((n) << CAN_ERFFEL126_FEL_SHIFT) & CAN_ERFFEL126_FEL_MASK) + +/* Enhanced RX FIFO Filter Element (ERFFEL127) */ +#define CAN_ERFFEL127_FEL_SHIFT (0) /* Bits 0-32: Filter Element Bits */ +#define CAN_ERFFEL127_FEL_MASK (0xFFFFFFFF << CAN_ERFFEL127_FEL_SHIFT) +#define CAN_ERFFEL127_FEL(n) (((n) << CAN_ERFFEL127_FEL_SHIFT) & CAN_ERFFEL127_FEL_MASK) + +/* CAN MB TX codes */ +#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */ +#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */ +#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */ + /* MB is a TX Remote Request Frame (when MB RTR = 1). */ +#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */ + /* an incoming Remote Request Frame. */ +#define CAN_TXMB_NOTUSED 0xF /* Not used.*/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_FLEXCAN_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_gpc.h b/arch/arm/src/imx9/hardware/imx9_gpc.h new file mode 100644 index 0000000000000..a2ad93f9f55b9 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_gpc.h @@ -0,0 +1,434 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_gpc.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_OFFSET 0x0004 /* CMC Authentication Control */ +#define IMX9_GPC_CTRL_CMC_MISC_OFFSET 0x000c /* Miscellaneous */ +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_OFFSET 0x0010 /* CPU mode control */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_OFFSET 0x0014 /* CPU mode Status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_OFFSET 0x0018 /* CMC pin Status */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1_OFFSET 0x0100 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2_OFFSET 0x0104 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3_OFFSET 0x0108 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4_OFFSET 0x010c /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5_OFFSET 0x0110 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6_OFFSET 0x0114 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7_OFFSET 0x0118 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8_OFFSET 0x011c /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9_OFFSET 0x0120 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10_OFFSET 0x0124 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11_OFFSET 0x0128 /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12_OFFSET 0x012c /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_OFFSET 0x0140 /* CMC non-IRQ wakeup mask */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1_OFFSET 0x0150 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2_OFFSET 0x0154 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3_OFFSET 0x0158 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4_OFFSET 0x015c /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5_OFFSET 0x0160 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6_OFFSET 0x0164 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7_OFFSET 0x0168 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8_OFFSET 0x016c /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9_OFFSET 0x0170 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10_OFFSET 0x0174 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11_OFFSET 0x0178 /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12_OFFSET 0x017c /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_OFFSET 0x0190 /* CMC non-IRQ wakeup status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_OFFSET 0x0200 /* CMC sleep A55_HDSK control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_OFFSET 0x0204 /* CMC sleep A55_HDSK status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_OFFSET 0x0208 /* CMC sleep SSAR control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_OFFSET 0x020c /* CMC sleep SSAR status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_OFFSET 0x0230 /* CMC sleep reset control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_OFFSET 0x0234 /* CMC sleep reset status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_OFFSET 0x0248 /* CMC sleep Sysman control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_OFFSET 0x024c /* CMC Sleep Sysman status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_OFFSET 0x0290 /* CMC wakeup power control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_OFFSET 0x0294 /* CMC wakeup power status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_OFFSET 0x02c8 /* CMC wakeup SSAR control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_OFFSET 0x02cc /* CMC wakeup SSAR status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_OFFSET 0x02d0 /* CMC wakeup A55_HDSK control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_OFFSET 0x02d4 /* CMC wakeup A55_HDSK status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_OFFSET 0x02d8 /* CMC wakeup Sysman control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_OFFSET 0x02dc /* CMC wakeup Sysman status */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_OFFSET 0x0380 /* CMC system sleep control */ +#define IMX9_GPC_CTRL_CMC_DEBUG_OFFSET 0x0390 /* CMC debug */ + +/* Register macros */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_OFFSET) /* CMC Authentication Control */ +#define IMX9_GPC_CTRL_CMC_MISC(n) ((n) + IMX9_GPC_CTRL_CMC_MISC_OFFSET) /* Miscellaneous */ +#define IMX9_GPC_CTRL_CMC_MODE_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_MODE_CTRL_OFFSET) /* CPU mode control */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_MODE_STAT_OFFSET) /* CPU mode Status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_PIN_STAT_OFFSET) /* CMC pin Status */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12_OFFSET) /* IRQ wake-up mask register */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK(n) ((n) + IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_OFFSET) /* CMC non-IRQ wakeup mask */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12_OFFSET) /* IRQ status register */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_OFFSET) /* CMC non-IRQ wakeup status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_OFFSET) /* CMC sleep A55_HDSK control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_OFFSET) /* CMC sleep A55_HDSK status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_OFFSET) /* CMC sleep SSAR control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_OFFSET) /* CMC sleep SSAR status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_OFFSET) /* CMC sleep reset control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_OFFSET) /* CMC sleep reset status */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_OFFSET) /* CMC sleep Sysman control */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_OFFSET) /* CMC Sleep Sysman status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_OFFSET) /* CMC wakeup power control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_OFFSET) /* CMC wakeup power status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_OFFSET) /* CMC wakeup SSAR control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_OFFSET) /* CMC wakeup SSAR status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_OFFSET) /* CMC wakeup A55_HDSK control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_OFFSET) /* CMC wakeup A55_HDSK status */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_OFFSET) /* CMC wakeup Sysman control */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_OFFSET) /* CMC wakeup Sysman status */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_OFFSET) /* CMC system sleep control */ +#define IMX9_GPC_CTRL_CMC_DEBUG(n) ((n) + IMX9_GPC_CTRL_CMC_DEBUG_OFFSET) /* CMC debug */ + +/* Field definitions */ + +/* CMC_AUTHEN_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT 7 /* Configuration lock */ +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT) /* Configuration lock */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_SHIFT 8 /* Allow user mode access */ +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_SHIFT) /* Allow user mode access */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_SHIFT 9 /* Allow non-secure mode access */ +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_SHIFT) /* Allow non-secure mode access */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT 11 /* Lock NONSECURE and USER */ +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT) /* Lock NONSECURE and USER */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT 15 /* White list lock */ +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT) /* White list lock */ + +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_WHITE_LIST_SHIFT 16 /* Domain ID white list */ +#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_WHITE_LIST_MASK 0xffff /* Domain ID white list */ + +/* CMC_MISC register */ + +#define IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_SHIFT 0 /* Non-masked interrupt status */ +#define IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_SHIFT) /* Non-masked interrupt status */ + +#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_SHIFT 1 /* Allow cpu_sleep_hold_req assert during CPU low power status */ +#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_SHIFT) /* Allow cpu_sleep_hold_req assert during CPU low power status */ + +#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_SHIFT 2 /* Status of cpu_sleep_hold_ack_b */ +#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_SHIFT) /* Status of cpu_sleep_hold_ack_b */ + +#define IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_SHIFT 4 /* GIC wakeup request status */ +#define IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_SHIFT) /* GIC wakeup request status */ + +#define IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_SHIFT 5 /* IRQ select */ +#define IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_SHIFT) /* IRQ select */ + +#define IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_SHIFT 6 /* Software wakeup. Used for CPU hotplug. */ +#define IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_SHIFT) /* Software wakeup. Used for CPU hotplug. */ + +/* CMC_MODE_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT 0 /* The CPU mode the CPU platform should transit to on next sleep event */ +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK 0x3 /* The CPU mode the CPU platform should transit to on next sleep event */ + +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_STAY_IN_RUN_MODE 0 +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_WAIT 1 +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_STOP 2 +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_SUSPEND 3 + +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET(n) (n << IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT) + +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_SHIFT 4 /* WFE assertion can be sleep event */ +#define IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_SHIFT) /* WFE assertion can be sleep event */ + +/* CMC_MODE_STAT register */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_CURRENT_SHIFT 0 /* Current CPU mode */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_CURRENT_MASK 0x3 /* Current CPU mode */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT 2 /* Previous CPU mode */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_PREVIOUS_MASK 0x3 /* Previous CPU mode */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT 8 /* Busy on CPU mode transition of sleep, not include set point trans busy. */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT) /* Busy on CPU mode transition of sleep, not include set point trans busy. */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT 9 /* Busy on CPU mode transition of wakeup, not include set point trans busy. */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT) /* Busy on CPU mode transition of wakeup, not include set point trans busy. */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT 10 /* Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT) /* Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT 16 /* Status of sleep_request input port */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT) /* Status of sleep_request input port */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_SHIFT 17 /* Status of standby_wfe input port */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_SHIFT) /* Status of standby_wfe input port */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT 18 /* "ORed" of all unmasked IRQ */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT) /* "ORed" of all unmasked IRQ */ + +#define IMX9_GPC_CTRL_CMC_MODE_STAT_FSM_STATE_SHIFT 24 /* CPU mode trans FSM state. */ +#define IMX9_GPC_CTRL_CMC_MODE_STAT_FSM_STATE_MASK 0x1f /* CPU mode trans FSM state. */ + +/* CMC_PIN_STAT register */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT 0 /* cpu_mode_trans_a55_hdsk_request pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT) /* cpu_mode_trans_a55_hdsk_request pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT 1 /* cpu_mode_trans_ssar_request pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT) /* cpu_mode_trans_ssar_request pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT 6 /* cpu_mode_trans_reset_request pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT) /* cpu_mode_trans_reset_request pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT 7 /* cpu_mode_trans_power_request pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT) /* cpu_mode_trans_power_request pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT 9 /* cpu_mode_trans_sysman_request pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT) /* cpu_mode_trans_sysman_request pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT 16 /* cpu_mode_trans_a55_hdsk_done pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT) /* cpu_mode_trans_a55_hdsk_done pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT 17 /* cpu_mode_trans_ssar_done pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT) /* cpu_mode_trans_ssar_done pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT 22 /* cpu_mode_trans_reset_done pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT) /* cpu_mode_trans_reset_done pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT 23 /* cpu_mode_trans_power_done pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT) /* cpu_mode_trans_power_done pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT 25 /* cpu_mode_trans_sysman_done pin status. */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT) /* cpu_mode_trans_sysman_done pin status. */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_CPU_MODE_STAT_SHIFT 29 /* cpu_power_mode pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_CPU_MODE_STAT_MASK 0x3 /* cpu_power_mode pin status */ + +#define IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT 31 /* Debug wakeup acknowledge pin status */ +#define IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT) /* Debug wakeup acknowledge pin status */ + +/* CMC_NON_IRQ_WAKEUP_MASK register */ + +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT 0 /* "1" means the event cannot wakeup CPU platform */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT) /* "1" means the event cannot wakeup CPU platform */ + +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT 1 /* "1" means the debug_wakeup_request cannot wakeup CPU platform */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT) /* "1" means the debug_wakeup_request cannot wakeup CPU platform */ + +/* CMC_NON_IRQ_WAKEUP_STAT register */ + +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT 0 /* Event wakeup status */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT) /* Event wakeup status */ + +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT 1 /* Debug wakeup status */ +#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT) /* Debug wakeup status */ + +/* CMC_SLEEP_A55_HDSK_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_SLEEP_A55_HDSK_STAT register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_SLEEP_SSAR_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_SLEEP_SSAR_STAT register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_SLEEP_RESET_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_SLEEP_RESET_STAT register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_SLEEP_SYSMAN_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_SLEEP_SYSMAN_STAT register */ + +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_WAKEUP_POWER_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_WAKEUP_POWER_STAT register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_WAKEUP_SSAR_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_WAKEUP_SSAR_STAT register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_WAKEUP_A55_HDSK_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_WAKEUP_A55_HDSK_STAT register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_WAKEUP_SYSMAN_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT 31 /* Disable this step */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT) /* Disable this step */ + +/* CMC_WAKEUP_SYSMAN_STAT register */ + +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */ +#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */ + +/* CMC_SYS_SLEEP_CTRL register */ + +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT 0 /* Request system sleep when CPU is in WAIT mode */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT) /* Request system sleep when CPU is in WAIT mode */ + +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT 1 /* Request system sleep when CPU is in STOP mode */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT) /* Request system sleep when CPU is in STOP mode */ + +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT 2 /* Request system sleep when CPU is in SUSPEND mode */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT) /* Request system sleep when CPU is in SUSPEND mode */ + +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT 16 /* Indicates the CPU is busy entering system sleep mode. */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT) /* Indicates the CPU is busy entering system sleep mode. */ + +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT 17 /* Indicates the CPU is busy exiting system sleep mode. */ +#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT) /* Indicates the CPU is busy exiting system sleep mode. */ + +/* CMC_DEBUG register */ + +#define IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_SHIFT 0 /* Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */ +#define IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_FLAG (1 << IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_SHIFT) /* Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */ + +/* Register array dimensions */ + +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK__REGARRAY_SIZE 12 +#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT__REGARRAY_SIZE 12 + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_gpio.h b/arch/arm/src/imx9/hardware/imx9_gpio.h new file mode 100644 index 0000000000000..6c8f76a941942 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_gpio.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_gpio.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO1 0 /* Port 1 index */ +#define GPIO2 1 /* Port 2 index */ +#define GPIO3 2 /* Port 3 index */ +#define GPIO4 3 /* Port 4 index */ +#define GPIO5 4 /* Port 5 index */ +#define GPIO6 5 /* Port 6 index */ +#define GPIO7 6 /* Port 7 index */ +#define GPIO8 7 /* Port 8 index */ +#define GPIO9 8 /* Port 9 index */ +#define GPIO10 9 /* Port 10 index */ +#define GPIO11 10 /* Port 11 index */ +#define GPIO12 11 /* Port 12 index */ +#define GPIO13 12 /* Port 13 index */ + +#define IMX9_GPIO_NPINS 32 /* Up to 32 pins per port */ + +/* Register bit definitions *************************************************/ + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ + +/* ICRN Register */ + +#define IMX9_GPIO_ICRN_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */ +#define IMX9_GPIO_ICRN_LK (1 << 23) /* Bit 23: Lock Register */ +#define IMX9_GPIO_ICRN_IRQS (1 << 20) /* Bit 20: Configures the selected interrupt, or DMA request. */ +#define IMX9_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ +#define IMX9_GPIO_ICRN_MASK (0xf << IMX9_GPIO_ICRN_SHIFT) +# define IMX9_GPIO_ICRN_DISABLED (0 << IMX9_GPIO_ICRN_SHIFT) /* Interrupt Status Flag (ISF) is disabled */ +# define IMX9_GPIO_ICRN_DMARISING (1 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on rising edge */ +# define IMX9_GPIO_ICRN_DMAFALLING (2 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on falling edge */ +# define IMX9_GPIO_ICRN_DMABOTH (3 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on either edge */ +# define IMX9_GPIO_ICRN_ISFRISING (5 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on rising edge */ +# define IMX9_GPIO_ICRN_ISFFALLING (6 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on falling edge */ +# define IMX9_GPIO_ICRN_ISFBOTH (7 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on either edge */ +# define IMX9_GPIO_ICRN_ZERO (8 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 0 */ +# define IMX9_GPIO_ICRN_RISING (9 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on rising-edge */ +# define IMX9_GPIO_ICRN_FALLING (10 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on falling-edge */ +# define IMX9_GPIO_ICRN_BOTH (11 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on either edge */ +# define IMX9_GPIO_ICRN_ONE (12 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 1 */ + +/* Global Interrupt Control Low Register */ + +#define IMX9_GPIO_GICLR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ +#define IMX9_GPIO_GICLR_GIWD_MASK (0xffff << IMX9_GPIO_GICLR_GIWD_SHIFT) +# define IMX9_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWD_SHIFT) /* Pin n=0..15 */ + +#define IMX9_GPIO_GICLR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ +#define IMX9_GPIO_GICLR_GIWE_MASK (0xffff << IMX9_GPIO_GICLR_GIWE_SHIFT) +# define IMX9_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWE_SHIFT) /* Pin n=0..15 */ + +/* Global Interrupt Control High Register */ + +#define IMX9_GPIO_GICHR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ +#define IMX9_GPIO_GICHR_GIWD_MASK (0xffff << IMX9_GPIO_GICHR_GIWD_SHIFT) +# define IMX9_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWD_SHIFT) /* Pin n=16..31 */ + +#define IMX9_GPIO_GICHR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ +#define IMX9_GPIO_GICHR_GIWE_MASK (0xffff << IMX9_GPIO_GICHR_GIWE_SHIFT) +# define IMX9_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWE_SHIFT) /* Pin n=16..31 */ + +/* Interrupt Status Flag Register */ + +#define IMX9_GPIO_ISFR(n) (1 << (n)) /* Interrupt Status Flag, n=0-31 */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_iomuxc.h b/arch/arm/src/imx9/hardware/imx9_iomuxc.h new file mode 100644 index 0000000000000..3b4ccc128229a --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_iomuxc.h @@ -0,0 +1,107 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_iomuxc.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_iomuxc.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pad muxing */ + +#define IOMUXC_MUX_MODE_SHIFT (0) /* MODE: pin alternate function */ +#define IOMUXC_MUX_MODE_MASK (0x03 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT0 (0 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT1 (1 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT2 (2 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT3 (3 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT4 (4 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT5 (5 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT6 (6 << IOMUXC_MUX_MODE_SHIFT) + +#define IOMUXC_MUX_SION_SHIFT (4) /* SION: Force input path */ +#define IPMUXC_MUX_SION_MASK (0x01 << IOMUXC_MUX_SION_SHIFT) +#define IOMUXC_MUX_SION_OFF (0 << IOMUXC_MUX_SION_SHIFT) +#define IOMUXC_MUX_SION_ON (1 << IOMUXC_MUX_SION_SHIFT) + +/* Pad control */ + +#define IOMUXC_PAD_DSE_SHIFT (1) /* DSE: Drive strength */ +#define IOMUXC_PAD_DSE_MASK (0x3f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X0 (0x00 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X1 (0x01 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X2 (0x03 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X3 (0x07 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X4 (0x0f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X5 (0x1f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X6 (0x3f << IOMUXC_PAD_DSE_SHIFT) + +#define IOMUXC_PAD_FSEL_SHIFT (7) /* FSEL: Slew rate control */ +#define IOMUXC_PAD_FSEL_MASK (0x02 << IOMUXC_PAD_FSEL_SHIFT) +#define IOMUXC_PAD_FSEL_SLOW (0 << IOMUXC_PAD_FSEL_SHIFT) +#define IOMUXC_PAD_FSEL_SSLOW (1 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly slow */ +#define IOMUXC_PAD_FSEL_SFAST (2 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly fast */ +#define IOMUXC_PAD_FSEL_FAST (3 << IOMUXC_PAD_FSEL_SHIFT) + +#define IOMUXC_PAD_PU_SHIFT (9) /* PU: Pull-up */ +#define IOMUXC_PAD_PU_MASK (0x01 << IOMUXC_PAD_PU_SHIFT) +#define IOMUXC_PAD_PU_OFF (0 << IOMUXC_PAD_PU_SHIFT) +#define IOMUXC_PAD_PU_ON (1 << IOMUXC_PAD_PU_SHIFT) + +#define IOMUXC_PAD_PD_SHIFT (10) /* PD: Pull-down */ +#define IOMUXC_PAD_PD_MASK (0x01 << IOMUXC_PAD_PD_SHIFT) +#define IOMUXC_PAD_PD_OFF (0 << IOMUXC_PAD_PD_SHIFT) +#define IOMUXC_PAD_PD_ON (1 << IOMUXC_PAD_PD_SHIFT) + +#define IOMUXC_PAD_OD_SHIFT (11) /* OD: Open-drain */ +#define IOMUXC_PAD_OD_MASK (0x01 << IOMUXC_PAD_OD_SHIFT) +#define IOMUXC_PAD_OD_DISABE (0 << IOMUXC_PAD_OD_SHIFT) +#define IOMUXC_PAD_OD_ENABLE (1 << IOMUXC_PAD_OD_SHIFT) + +#define IOMUXC_PAD_HYS_SHIFT (12) /* HYS: Enable schmitt-trigger on input */ +#define IOMUXC_PAD_HYS_MASK (0x01 << IOMUXC_PAD_HYS_SHIFT) +#define IOMUXC_PAD_HYS_ST_OFF (0 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger off */ +#define IOMUXC_PAD_HYS_ST_ON (1 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger on */ + +#define IOMUXC_PAD_APC_SHIFT (24) /* APC: Access control */ +#define IOMUXC_PAD_APC_MASK (0xff << IOMUXC_PAD_APC_SHIFT) + +/* Daisy chain control, 2 bits seems to be enough */ + +#define IOMUXC_DSY_SHIFT (0) +#define IOMUXC_DSY_MASK (0x03 << IOMUXC_DSY_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_lpi2c.h b/arch/arm/src/imx9/hardware/imx9_lpi2c.h new file mode 100644 index 0000000000000..c3178809f34cd --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_lpi2c.h @@ -0,0 +1,628 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_lpi2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMX9_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */ +#define IMX9_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */ +#define IMX9_LPI2C_MCR_OFFSET 0x0010 /* Master Control Register offset */ +#define IMX9_LPI2C_MSR_OFFSET 0x0014 /* Master Status Register offset */ +#define IMX9_LPI2C_MIER_OFFSET 0x0018 /* Master Interrupt Enable Register offset */ +#define IMX9_LPI2C_MDER_OFFSET 0x001c /* Master DMA Enable Register offset */ +#define IMX9_LPI2C_MCFGR0_OFFSET 0x0020 /* Master Config Register 0 offset */ +#define IMX9_LPI2C_MCFGR1_OFFSET 0x0024 /* Master Config Register 1 offset */ +#define IMX9_LPI2C_MCFGR2_OFFSET 0x0028 /* Master Config Register 2 offset */ +#define IMX9_LPI2C_MCFGR3_OFFSET 0x002c /* Master Config Register 3 offset */ +#define IMX9_LPI2C_MDMR_OFFSET 0x0040 /* Master Data Match Register offset */ +#define IMX9_LPI2C_MCCR0_OFFSET 0x0048 /* Master Clock Configuration Register 0 offset */ +#define IMX9_LPI2C_MCCR1_OFFSET 0x0050 /* Master Clock Configuration Register 1 offset */ +#define IMX9_LPI2C_MFCR_OFFSET 0x0058 /* Master FIFO Control Register offset */ +#define IMX9_LPI2C_MFSR_OFFSET 0x005C /* Master FIFO Status Register offset */ +#define IMX9_LPI2C_MTDR_OFFSET 0x0060 /* Master Transmit Data Register offset */ +#define IMX9_LPI2C_MRDR_OFFSET 0x0070 /* Master Receive Data Register offset */ +#define IMX9_LPI2C_SCR_OFFSET 0x0110 /* Slave Control Register offset */ +#define IMX9_LPI2C_SSR_OFFSET 0x0114 /* Slave Status Register offset */ +#define IMX9_LPI2C_SIER_OFFSET 0x0118 /* Slave Interrupt Enable Register offset */ +#define IMX9_LPI2C_SDER_OFFSET 0x011c /* Slave DMA Enable Register offset */ +#define IMX9_LPI2C_SCFGR1_OFFSET 0x0124 /* Slave Config Register 1 offset */ +#define IMX9_LPI2C_SCFGR2_OFFSET 0x0128 /* Slave Config Register 2 offset */ +#define IMX9_LPI2C_SAMR_OFFSET 0x0140 /* Slave Address Match Register offset */ +#define IMX9_LPI2C_SASR_OFFSET 0x0150 /* Slave Address Status Register offset */ +#define IMX9_LPI2C_STAR_OFFSET 0x0154 /* Slave Transmit ACK Register offset */ +#define IMX9_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */ +#define IMX9_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */ + +/* Register addresses *******************************************************/ + +/* LPI2C1 Registers */ + +#define IMX9_LPI2C1_VERID (IMX9_LPI2C1_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C1_PARAM (IMX9_LPI2C1_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C1_MCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C1_MSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C1_MIER (IMX9_LPI2C1_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C1_MDER (IMX9_LPI2C1_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C1_MCFGR0 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C1_MCFGR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C1_MCFGR2 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C1_MCFGR3 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C1_MDMR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C1_MCCR0 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C1_MCCR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C1_MFCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C1_MFSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C1_MTDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C1_MRDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C1_SCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C1_SSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C1_SIER (IMX9_LPI2C1_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C1_SDER (IMX9_LPI2C1_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C1_SCFGR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C1_SCFGR2 (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C1_SAMR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C1_SASR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C1_STAR (IMX9_LPI2C1_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C1_STDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C1_SRDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* LPI2C2 Registers */ + +#define IMX9_LPI2C2_VERID (IMX9_LPI2C2_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C2_PARAM (IMX9_LPI2C2_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C2_MCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C2_MSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C2_MIER (IMX9_LPI2C2_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C2_MDER (IMX9_LPI2C2_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C2_MCFGR0 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C2_MCFGR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C2_MCFGR2 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C2_MCFGR3 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C2_MDMR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C2_MCCR0 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C2_MCCR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C2_MFCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C2_MFSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C2_MTDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C2_MRDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C2_SCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C2_SSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C2_SIER (IMX9_LPI2C2_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C2_SDER (IMX9_LPI2C2_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C2_SCFGR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C2_SCFGR2 (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C2_SAMR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C2_SASR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C2_STAR (IMX9_LPI2C2_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C2_STDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C2_SRDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* LPI2C3 Registers */ + +#define IMX9_LPI2C3_VERID (IMX9_LPI2C3_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C3_PARAM (IMX9_LPI2C3_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C3_MCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C3_MSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C3_MIER (IMX9_LPI2C3_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C3_MDER (IMX9_LPI2C3_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C3_MCFGR0 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C3_MCFGR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C3_MCFGR2 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C3_MCFGR3 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C3_MDMR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C3_MCCR0 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C3_MCCR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C3_MFCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C3_MFSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C3_MTDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C3_MRDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C3_SCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C3_SSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C3_SIER (IMX9_LPI2C3_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C3_SDER (IMX9_LPI2C3_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C3_SCFGR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C3_SCFGR2 (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C3_SAMR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C3_SASR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C3_STAR (IMX9_LPI2C3_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C3_STDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C3_SRDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* LPI2C4 Registers */ + +#define IMX9_LPI2C4_VERID (IMX9_LPI2C4_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C4_PARAM (IMX9_LPI2C4_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C4_MCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C4_MSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C4_MIER (IMX9_LPI2C4_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C4_MDER (IMX9_LPI2C4_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C4_MCFGR0 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C4_MCFGR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C4_MCFGR2 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C4_MCFGR3 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C4_MDMR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C4_MCCR0 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C4_MCCR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C4_MFCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C4_MFSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C4_MTDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C4_MRDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C4_SCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C4_SSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C4_SIER (IMX9_LPI2C4_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C4_SDER (IMX9_LPI2C4_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C4_SCFGR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C4_SCFGR2 (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C4_SAMR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C4_SASR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C4_STAR (IMX9_LPI2C4_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C4_STDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C4_SRDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* Register bit definitions *************************************************/ + +/* LPI2C Version ID Register */ + +#define LPI2C_VERID_FEATURE_SHIFT (0) +#define LPI2C_VERID_FEATURE_MASK (0xffff << LPI2C_VERID_FEATURE_SHIFT) +#define LPI2C_VERID_MINOR_SHIFT (16) +#define LPI2C_VERID_MINOR_MASK (0xff << LPI2C_VERID_MINOR_SHIFT) +#define LPI2C_VERID_MAJOR_SHIFT (24) +#define LPI2C_VERID_MAJOR_MASK (0xff << LPI2C_VERID_MAJOR_SHIFT) + +/* LPI2C Parameter Register */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0x0f) /* Config number of words in master transmit fifo to 2^MTXFIFO (pow(2,MTXFIFO )) */ +# define LPI2C_PARAM_MTXFIFO_1_WORDS (0) +# define LPI2C_PARAM_MTXFIFO_2_WORDS (1) +# define LPI2C_PARAM_MTXFIFO_4_WORDS (2) +# define LPI2C_PARAM_MTXFIFO_8_WORDS (3) +# define LPI2C_PARAM_MTXFIFO_16_WORDS (4) +# define LPI2C_PARAM_MTXFIFO_32_WORDS (5) +# define LPI2C_PARAM_MTXFIFO_64_WORDS (6) +# define LPI2C_PARAM_MTXFIFO_128_WORDS (7) +# define LPI2C_PARAM_MTXFIFO_256_WORDS (8) +# define LPI2C_PARAM_MTXFIFO_512_WORDS (9) +# define LPI2C_PARAM_MTXFIFO_1024_WORDS (10) +# define LPI2C_PARAM_MTXFIFO_2048_WORDS (11) +# define LPI2C_PARAM_MTXFIFO_4096_WORDS (12) +# define LPI2C_PARAM_MTXFIFO_8192_WORDS (13) +# define LPI2C_PARAM_MTXFIFO_16384_WORDS (14) +# define LPI2C_PARAM_MTXFIFO_32768_WORDS (15) + +#define LPI2C_PARAM_MRXFIFO_SHIFT (8) +#define LPI2C_PARAM_MRXFIFO_MASK (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT) /* Config number of words in master receive fifo 2^MRXFIFO (pow(2,MTRFIFO )) */ +# define LPI2C_PARAM_MRXFIFO_1_WORDS (0 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_2_WORDS (1 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_4_WORDS (2 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_8_WORDS (3 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_16_WORDS (4 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_32_WORDS (5 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_64_WORDS (6 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_128_WORDS (7 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_256_WORDS (8 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_512_WORDS (9 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_1024_WORDS (10 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_2048_WORDS (11 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_4096_WORDS (12 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_8192_WORDS (13 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_16384_WORDS (14 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_32768_WORDS (15 << LPI2C_PARAM_MRXFIFO_SHIFT) + +/* LPI2C Master Control Register */ + +#define LPI2C_MCR_MEN (1 << 0) /* Master Enable Bit */ +#define LPI2C_MCR_RST (1 << 1) /* Software Reset Bit */ +#define LPI2C_MCR_DOZEN (1 << 2) /* Doze Mode Enable Bit */ +#define LPI2C_MCR_DBGEN (1 << 3) /* Debug Enable Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_MCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */ +#define LPI2C_MCR_RRF (1 << 9) /* Reset Receive FIFO Bit */ + /* Bits 31-10 Reserved */ + +/* LPI2C Master Status Register */ + +#define LPI2C_MSR_TDF (1 << 0) /* Transmit Data Flag Bit */ +#define LPI2C_MSR_RDF (1 << 1) /* Receive Data Flag Bit */ + /* Bits 7-2 Reserved */ +#define LPI2C_MSR_EPF (1 << 8) /* End Packet Flag Bit */ +#define LPI2C_MSR_SDF (1 << 9) /* STOP Detect Flag Bit */ +#define LPI2C_MSR_NDF (1 << 10) /* NACK Detect Flag Bit */ +#define LPI2C_MSR_ALF (1 << 11) /* Arbitration Lost Flag Bit */ +#define LPI2C_MSR_FEF (1 << 12) /* FIFO Error Flag Bit */ +#define LPI2C_MSR_PLTF (1 << 13) /* Pin Low Timeout Flag Bit */ +#define LPI2C_MSR_DMF (1 << 14) /* Data Match Flag Bit */ + /* Bits 23-15 Reserved */ +#define LPI2C_MSR_MBF (1 << 24) /* Master Busy Flag Bit */ +#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */ + /* Bits 31-26 Reserved */ +#define LPI2C_MSR_ERROR_MASK (LPI2C_MSR_NDF | LPI2C_MSR_ALF | \ + LPI2C_MSR_FEF) + +/* LPI2C Master Interrupt Enable Register */ + +#define LPI2C_MIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */ +#define LPI2C_MIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */ + /* Bits 7-2 Reserved */ +#define LPI2C_MIER_EPIE (1 << 8) /* End Packet Interrupt Enable Bit */ +#define LPI2C_MIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */ +#define LPI2C_MIER_NDIE (1 << 10) /* NACK Detect Interrupt Enable Bit */ +#define LPI2C_MIER_ALIE (1 << 11) /* Arbitration Lost Interrupt Enable Bit */ +#define LPI2C_MIER_FEIE (1 << 12) /* FIFO Error Interrupt Enable Bit */ +#define LPI2C_MIER_PLTIE (1 << 13) /* Pin Low Timeout Interrupt Enable Bit */ +#define LPI2C_MIER_DMIE (1 << 14) /* Data Match Interrupt Enable Bit */ + /* Bits 31-15 Reserved */ + +/* LPI2C Master DMA Enable Register */ + +#define LPI2C_MDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */ +#define LPI2C_MDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */ + /* Bits 31-2 Reserved */ + +/* LPI2C Master Config Register 0 */ + +#define LPI2C_MCFG0_HREN (1 << 0) /* Host Request Enable Bit */ +#define LPI2C_MCFG0_HRPOL (1 << 1) /* Host Request Polarity Bit */ +#define LPI2C_MCFG0_HRSEL (1 << 2) /* Host Request Select Bit */ + /* Bits 7-3 Reserved */ +#define LPI2C_MCFG0_CIRFIFO (1 << 8) /* Circular FIFO Enable Bit */ +#define LPI2C_MCFG0_RDMO (1 << 9) /* Receive Data Match Only Bit */ + /* Bits 15-10 Reserved */ +#define LPI2C_MCFG0_RELAX (1 << 16) /* Relaxed Mode */ +#define LPI2C_MCFG0_ABORT (1 << 17) /* Abort Transfer */ + /* Bits 31-18 Reserved */ + +/* LPI2C Master Config Register 1 */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */ +#define LPI2C_MCFGR1_PRESCALE(n) ((n) & LPI2C_MCFGR1_PRESCALE_MASK) +# define LPI2C_MCFGR1_PRESCALE_1 (0) +# define LPI2C_MCFGR1_PRESCALE_2 (1) +# define LPI2C_MCFGR1_PRESCALE_4 (2) +# define LPI2C_MCFGR1_PRESCALE_8 (3) +# define LPI2C_MCFGR1_PRESCALE_16 (4) +# define LPI2C_MCFGR1_PRESCALE_32 (5) +# define LPI2C_MCFGR1_PRESCALE_64 (6) +# define LPI2C_MCFGR1_PRESCALE_128 (7) +#define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */ +#define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */ +#define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */ + /* Bits 15-11 Reserved */ +#define LPI2C_MCFGR1_MATCFG_SHIFT (16) +#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */ +#define LPI2C_MCFGR1_MATCFG(n) (((n) << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK) +# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT) + /* LPI2C_MCFG1_MATCFG = 001b Reserved */ +# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG3 (3 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG4 (4 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG5 (5 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG6 (6 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG7 (7 << LPI2C_MCFGR1_MATCFG_SHIFT) + /* Bits 23-19 Reserved */ +#define LPI2C_MCFGR1_PINCFG_SHIFT (24) +#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */ +#define LPI2C_MCFGR1_PINCFG(n) (((n) << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK) +# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG3 (3 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG4 (4 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG5 (5 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG6 (6 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG7 (7 << LPI2C_MCFGR1_PINCFG_SHIFT) + /* Bits 31-27 Reserved */ + +/* LPI2C Master Config Register 2 */ + +#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */ +#define LPI2C_MCFG2_BUSIDLE_DISABLE (0) +#define LPI2C_MCFG2_BUSIDLE(n) ((n) & LPI2C_MCFG2_BUSIDLE_MASK) + /* Bits 15-12 Reserved */ +#define LPI2C_MCFG2_FILTSCL_SHIFT (16) +#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */ +#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT) +#define LPI2C_MCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK) + /* Bits 23-20 Reserved */ +#define LPI2C_MCFG2_FILTSDA_SHIFT (24) +#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */ +#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT) +#define LPI2C_MCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK) + /* Bits 31-28 Reserved */ + +/* LPI2C Master Config Register 3 */ + + /* Bits 7-0 Reserved */ +#define LPI2C_MCFG3_PINLOW_SHIFT (8) +#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */ +#define LPI2C_MCFG3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK) + /* Bits 31-20 Reserved */ + +/* LPI2C Master Data Match Register */ + +#define LPI2C_MDMR_MATCH0_SHIFT (0) +#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */ +#define LPI2C_MDMR_MATCH0(n) (((n) << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK) + /* Bits 15-8 Reserved */ +#define LPI2C_MDMR_MATCH1_SHIFT (16) +#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */ +#define LPI2C_MDMR_MATCH1(n) (((n) << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK) + /* Bits 31-24 Reserved */ + +/* LPI2C Master Clock Configuration Register 0 */ + +#define LPI2C_MCCR0_CLKLO_SHIFT (0) +#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(n) (((n) << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK) + /* Bits 7-6 Reserved */ +#define LPI2C_MCCR0_CLKHI_SHIFT (8) +#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */ +#define LPI2C_MCCR0_CLKHI(n) (((n) << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK) + /* Bits 15-14 Reserved */ +#define LPI2C_MCCR0_SETHOLD_SHIFT (16) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(n) (((n) << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK) + /* Bits 23-22 Reserved */ +#define LPI2C_MCCR0_DATAVD_SHIFT (24) +#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR0_DATAVD(n) (((n) << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK) + /* Bits 31-30 Reserved */ + +/* LPI2C Master Clock Configuration Register 1 */ + +#define LPI2C_MCCR1_CLKLO_SHIFT (0) +#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(n) (((n) << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK) + /* Bits 7-6 Reserved */ +#define LPI2C_MCCR1_CLKHI_SHIFT (8) +#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */ +#define LPI2C_MCCR1_CLKHI(n) (((n) << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK) + /* Bits 15-14 Reserved */ +#define LPI2C_MCCR1_SETHOLD_SHIFT (16) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(n) (((n) << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK) + + /* Bits 23-22 Reserved */ +#define LPI2C_MCCR1_DATAVD_SHIFT (24) +#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR1_DATAVD(n) (((n) << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK) + + /* Bits 31-30 Reserved */ + +/* LPI2C Master FIFO Control Register */ + +#define LPI2C_MFCR_TXWATER_SHIFT (0) +#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/ + +#define LPI2C_MFCR_TXWATER(n) (((n) << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark */ + + /* Bits 15-2 Reserved */ +#define LPI2C_MFCR_RXWATER_SHIFT (16) +#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */ + +#define LPI2C_MFCR_RXWATER(n) (((n) << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark */ + + /* Bits 31-18 Reserved */ + +/* LPI2C Master FIFO Status Register */ + +#define LPI2C_MFSR_TXCOUNT_SHIFT (0) +#define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */ + + /* Bits 15-2 Reserved */ +#define LPI2C_MFSR_RXCOUNT_SHIFT (16) +#define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */ + + /* Bits 31-18 Reserved */ + +/* LPI2C Master Transmit Data Register */ + +#define LPI2C_MTDR_DATA_SHIFT (0) +#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */ +#define LPI2C_MTDR_DATA(n) ((n) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_SHIFT (8) +#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */ +#define LPI2C_MTDR_CMD(n) (((n) << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK) +# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_RXD_DISC (3 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START (4 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START_NACK (5 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START_HI (6 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START_HI_NACK (7 << LPI2C_MTDR_CMD_SHIFT) + + /* Bits 31-11 Reserved */ + +/* LPI2C Master Receive Data Register */ + +#define LPI2C_MRDR_DATA_SHIFT (0) +#define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */ + + /* Bits 13-8 Reserved */ +#define LPI2C_MRDR_RXEMPTY_SHIFT (14) +#define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */ + + /* Bits 31-15 Reserved */ + +/* LPI2C Slave Control Register */ + +#define LPI2C_SCR_SEN (1 << 0) /* Slave Enable Bit */ +#define LPI2C_SCR_RST (1 << 1) /* Software Reset Bit */ + /* Bits 3-2 Reserved */ +#define LPI2C_SCR_FILTEN (1 << 4) /* Filter Enable Bit */ +#define LPI2C_SCR_FILTDZ (1 << 5) /* Filter Doze Enable Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_SCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */ +#define LPI2C_SCR_RRF (1 << 9) /* Reset Receive FIFO Bit */ + /* Bits 31-10 Reserved */ + +/* LPI2C Slave Status Register */ + +#define LPI2C_SSR_TDF (1 << 0) /* Transmit Data Flag Bit */ +#define LPI2C_SSR_RDF (1 << 1) /* Receive Data Flag Bit */ +#define LPI2C_SSR_AVF (1 << 2) /* Address Valid Flag Bit */ +#define LPI2C_SSR_TAF (1 << 3) /* Transmit ACK Flag Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_SSR_RSF (1 << 8) /* Repeated Start Flag Bit */ +#define LPI2C_SSR_SDF (1 << 9) /* STOP Detect Flag Bit */ +#define LPI2C_SSR_BEF (1 << 10) /* Bit Error Flag Bit */ +#define LPI2C_SSR_FEF (1 << 11) /* FIFO Error Flag Bit */ +#define LPI2C_SSR_AM0F (1 << 12) /* Address Match 0 Flag Bit */ +#define LPI2C_SSR_AM1F (1 << 13) /* Address Match 1 Flag Bit */ +#define LPI2C_SSR_GCF (1 << 14) /* General Call Flag Bit */ +#define LPI2C_SSR_SARF (1 << 15) /* SMBus Alert Response Flag Bit */ + /* Bits 23-16 Reserved */ +#define LPI2C_MSR_SBF (1 << 24) /* Slave Busy Flag Bit */ +#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */ + /* Bits 31-26 Reserved */ + +/* LPI2C Slave Interrupt Enable Register */ + +#define LPI2C_SIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */ +#define LPI2C_SIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */ +#define LPI2C_SIER_AVIE (1 << 2) /* Address Valid Interrupt Enable Bit */ +#define LPI2C_SIER_TAIE (1 << 3) /* Transmit ACK Interrupt Enable Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_SIER_RSIE (1 << 8) /* Repeated Start Interrupt Enable Bit */ +#define LPI2C_SIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */ +#define LPI2C_SIER_BEIE (1 << 10) /* Bit Error Interrupt Enable Bit */ +#define LPI2C_SIER_FEIE (1 << 11) /* FIFO Error Interrupt Enable Bit */ +#define LPI2C_SIER_AM0IE (1 << 12) /* Address Match 0 Interrupt Enable Bit */ +#define LPI2C_SIER_AM1IE (1 << 13) /* Address Match 1 Interrupt Enable Bit */ +#define LPI2C_SIER_GCIE (1 << 14) /* General Call Interrupt Enable Bit */ +#define LPI2C_SIER_SARIE (1 << 15) /* SMBus Alert Response Interrupt Enable Bit */ + /* Bits 31-16 Reserved */ + +/* LPI2C Slave DMA Enable Register */ + +#define LPI2C_SDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */ +#define LPI2C_SDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */ +#define LPI2C_SDER_AVDE (1 << 2) /* Address Valid DMA Enable Bit */ + /* Bits 31-3 Reserved */ + +/* LPI2C Slave Configuration Register 1 */ + +#define LPI2C_SCFGR1_ADRSTALL (1 << 0) /* Address SCL Stall */ +#define LPI2C_SCFGR1_RXSTALL (1 << 1) /* RX SCL Stall */ +#define LPI2C_SCFGR1_TXSTALL (1 << 2) /* TX Data SCL Stall */ +#define LPI2C_SCFGR1_ACKSTALL (1 << 3) /* ACK SCL Stall */ + /* Bits 7-4 Reserved */ +#define LPI2C_SCFGR1_GCEN (1 << 8) /* General Call Enable */ +#define LPI2C_SCFGR1_SAEN (1 << 9) /* SMBus Alert Enable */ +#define LPI2C_SCFGR1_TXCFG (1 << 10) /* Transmit Flag Configuration */ +#define LPI2C_SCFGR1_RXCFG (1 << 11) /* Receive Data Configuration */ +#define LPI2C_SCFGR1_IFNACK (1 << 12) /* Ignore NACK */ +#define LPI2C_SCFGR1_HSMEN (1 << 13) /* High Speed Mode Enable */ + /* Bits 15-14 Reserved */ +#define LPI2C_SCFG1_ADDRCFG_SHIFT (16) +#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */ +#define LPI2C_SCFG1_ADDRCFG(n) (((n) << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK) +# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG3 (3 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG4 (4 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG5 (5 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG6 (6 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG7 (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) + /* Bits 31-19 Reserved */ + +/* LPI2C Slave Configuration Register 2 */ + +#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */ +#define LPI2C_SCFG2_CLKHOLD(n) ((n) & LPI2C_SCFG2_CLKHOLD_MASK) + /* Bits 7-4 Reserved */ +#define LPI2C_SCFG2_DATAVD_SHIFT (8) +#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */ +#define LPI2C_SCFG2_DATAVD(n) (((n) << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK) + /* Bits 15-14 Reserved */ +#define LPI2C_SCFG2_FILTSCL_SHIFT (16) +#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */ +#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT) +#define LPI2C_SCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK) + /* Bits 23-20 Reserved */ +#define LPI2C_SCFG2_FILTSDA_SHIFT (24) +#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */ +#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT) +#define LPI2C_SCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK) + /* Bits 31-28 Reserved */ + +/* LPI2C Slave Address Match Register */ + + /* Bit 0 Reserved */ +#define LPI2C_SAMR_ADDR0_SHIFT (1) +#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */ +#define LPI2C_SAMR_ADDR0(n) (((n) << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK) + /* Bits 16-11 Reserved */ +#define LPI2C_SAMR_ADDR1_SHIFT (17) +#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */ +#define LPI2C_SAMR_ADDR1(n) (((n) << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK) + /* Bits 31-27 Reserved */ + +/* LPI2C Slave Address Status Register */ + +#define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */ + +/* Bits 16-11 + * Reserved + */ + +#define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */ + /* Bits 31-15 Reserved */ + +/* LPI2C Slave Transmit ACK Register */ + +#define LPI2C_STAR_TXNACK (1 << 0) /* Transmit NACK */ + /* Bits 31-1 Reserved */ + +/* LPI2C Slave Transmit Data Register */ + +#define LPI2C_STDR_DATA_SHIFT (0) +#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */ +#define LPI2C_STDR_DATA(n) (((n) << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK) + /* Bits 31-8 Reserved */ + +/* LPI2C Slave Receive Data Register */ + +#define LPI2C_SRDR_DATA_SHIFT (0) +#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */ +#define LPI2C_SRDR_DATA(n) (((n) << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK) + /* Bits 13-8 Reserved */ +#define LPI2C_STAR_SOF (1 << 14) /* RX Empty */ +#define LPI2C_STAR_RXEMPTY (1 << 15) /* Start Of Frame */ + /* Bits 31-16 Reserved */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ */ diff --git a/arch/arm/src/imx9/hardware/imx9_lpit.h b/arch/arm/src/imx9/hardware/imx9_lpit.h new file mode 100644 index 0000000000000..f6f7af42a8635 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_lpit.h @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_lpit.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_LPIT_VERID_OFFSET 0x0000 /* Version ID */ +#define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */ +#define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */ +#define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */ +#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */ +#define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */ +#define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */ +#define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */ +#define IMX9_LPIT_CVAL0_OFFSET 0x0024 /* Current Timer Channel 0 Value */ +#define IMX9_LPIT_TCTRL0_OFFSET 0x0028 /* Timer Channel 0 Control */ +#define IMX9_LPIT_TVAL1_OFFSET 0x0030 /* Timer Channel 1 Value */ +#define IMX9_LPIT_CVAL1_OFFSET 0x0034 /* Current Timer Channel 1 Value */ +#define IMX9_LPIT_TCTRL1_OFFSET 0x0048 /* Timer Channel 1 Control */ +#define IMX9_LPIT_TVAL2_OFFSET 0x0040 /* Timer Channel 2 Value */ +#define IMX9_LPIT_CVAL2_OFFSET 0x0044 /* Current Timer Channel 2 Value */ +#define IMX9_LPIT_TCTRL2_OFFSET 0x0048 /* Timer Channel 2 Control */ +#define IMX9_LPIT_TVAL3_OFFSET 0x0050 /* Timer Channel 3 Value */ +#define IMX9_LPIT_CVAL3_OFFSET 0x0054 /* Current Timer Channel 3 Value */ +#define IMX9_LPIT_TCTRL3_OFFSET 0x0058 /* Timer Channel 3 Control */ + +/* Register access */ + +#define LPIT_VERID(n) ((n) + IMX9_LPIT_VERID_OFFSET) +#define LPIT_PARAM(n) ((n) + IMX9_LPIT_PARAM_OFFSET) +#define LPIT_MCR(n) ((n) + IMX9_LPIT_MCR_OFFSET) +#define LPIT_MSR(n) ((n) + IMX9_LPIT_MSR_OFFSET) +#define LPIT_MIER(n) ((n) + IMX9_LPIT_MIER_OFFSET) +#define LPIT_SETTEN(n) ((n) + IMX9_LPIT_SETTEN_OFFSET) +#define LPIT_CLRTEN(n) ((n) + IMX9_LPIT_CLRTEN_OFFSET) +#define LPIT_TVAL0(n) ((n) + IMX9_LPIT_TVAL0_OFFSET) +#define LPIT_CVAL0(n) ((n) + IMX9_LPIT_CVAL0_OFFSET) +#define LPIT_TCTRL0(n) ((n) + IMX9_LPIT_TCTRL0_OFFSET) +#define LPIT_TVAL1(n) ((n) + IMX9_LPIT_TVAL1_OFFSET) +#define LPIT_CVAL1(n) ((n) + IMX9_LPIT_CVAL1_OFFSET) +#define LPIT_TCTRL1(n) ((n) + IMX9_LPIT_TCTRL1_OFFSET) +#define LPIT_TVAL2(n) ((n) + IMX9_LPIT_TVAL2_OFFSET) +#define LPIT_CVAL2(n) ((n) + IMX9_LPIT_CVAL2_OFFSET) +#define LPIT_TCTRL2(n) ((n) + IMX9_LPIT_TCTRL2_OFFSET) +#define LPIT_TVAL3(n) ((n) + IMX9_LPIT_TVAL3_OFFSET) +#define LPIT_CVAL3(n) ((n) + IMX9_LPIT_CVAL3_OFFSET) +#define LPIT_TCTRL3(n) ((n) + IMX9_LPIT_TCTRL3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define LPIT_PARAM_EXT_TRIG_SHIFT (8) /* Bit[15:8]: Number of External Trigger Inputs */ +#define LPIT_PARAM_EXT_TRIG_MASK (0xff << LPIT_PARAM_EXT_TRIG_SHIFT) + +#define LPIT_PARAM_CHANNEL_SHIFT (0) /* Bit[7:0]: Number of Timer Channels */ +#define LPIT_PARAM_CHANNEL_MASK (0xff << LPIT_PARAM_CHANNEL_SHIFT) + +#define LPIT_MCR_DBG_EN (1 << 3) /* Stop Timer when in Debug Mode */ +#define LPIT_MCR_DOZE_EN (1 << 2) /* DOZE Mode Enable */ +#define LPIT_MCR_SW_RST (1 << 1) /* Software Reset Bit */ +#define LPIT_MCR_M_CEN (1 << 0) /* Module Clock Enable */ + +#define LPIT_MSR_TIF3 (1 << 3) /* Channel 3 Timer Interrupt Flag */ +#define LPIT_MSR_TIF2 (1 << 2) /* Channel 2 Timer Interrupt Flag */ +#define LPIT_MSR_TIF1 (1 << 1) /* Channel 1 Timer Interrupt Flag */ +#define LPIT_MSR_TIF0 (1 << 0) /* Channel 0 Timer Interrupt Flag */ + +#define LPIT_MIER_TIE3 (1 << 3) /* Channel 3 Timer Interrupt Enable */ +#define LPIT_MIER_TIE2 (1 << 2) /* Channel 2 Timer Interrupt Enable */ +#define LPIT_MIER_TIE1 (1 << 1) /* Channel 1 Timer Interrupt Enable */ +#define LPIT_MIER_TIE0 (1 << 0) /* Channel 0 Timer Interrupt Enable */ + +#define LPIT_TCTRL_TRG_SEL_SHIFT (27) /* Bit[27:24]: Trigger Select */ +#define LPIT_TCTRL_TRG_SEL_MASK (0xf << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN0 (0 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN1 (1 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN2 (2 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN3 (3 << LPIT_TCTRL_TRG_SEL_SHIFT) + +#define LPIT_TCTRL_TRG_SRC_SHIFT (23) /* Bit23: Trigger Source */ +#define LPIT_TCTRL_TRG_SRC_MASK (1 << LPIT_TCTRL_TRG_SRC_SHIFT) +#define LPIT_TCTRL_TRG_SRC_EXTER (0 << LPIT_TCTRL_TRG_SRC_SHIFT) /* external */ +#define LPIT_TCTRL_TRG_SRC_INTER (1 << LPIT_TCTRL_TRG_SRC_SHIFT) /* internal */ + +#define LPIT_TCTRL_TROT (1 << 18) /* Timer Reload On Trigger */ +#define LPIT_TCTRL_TSOI (1 << 17) /* Timer Stop On Interrupt */ +#define LPIT_TCTRL_TSOT (1 << 16) /* Timer Start On Trigger */ + +#define LPIT_TCTRL_MODE_SHIFT (2) +#define LPIT_TCTRL_MODE_MASK (3 << LPIT_TCTRL_MODE_SHIFT) +#define LPIT_TCTRL_MODE_32PC (0 << LPIT_TCTRL_MODE_SHIFT) /* 32 Bit periodic Counter */ +#define LPIT_TCTRL_MODE_D16PC (1 << LPIT_TCTRL_MODE_SHIFT) /* Dual 16-bit periodic Counter */ +#define LPIT_TCTRL_MODE_32TA (2 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Accumulator */ +#define LPIT_TCTRL_MODE_32TIC (3 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Input Capture */ + +#define LPIT_TCTRL_CHAIN (1 << 1) /* Chain Channel */ +#define LPIT_TCTRL_T_EN (1 << 0) /* Timer Enable */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_lpspi.h b/arch/arm/src/imx9/hardware/imx9_lpspi.h new file mode 100644 index 0000000000000..0859674944b77 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_lpspi.h @@ -0,0 +1,355 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_lpspi.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMX9_LPSPI_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */ +#define IMX9_LPSPI_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */ +#define IMX9_LPSPI_CR_OFFSET (0x0010) /* Control Register (CR) */ +#define IMX9_LPSPI_SR_OFFSET (0x0014) /* Status Register (SR) */ +#define IMX9_LPSPI_IER_OFFSET (0x0018) /* Interrupt Enable Register (IER) */ +#define IMX9_LPSPI_DER_OFFSET (0x001c) /* DMA Enable Register (DER) */ +#define IMX9_LPSPI_CFGR0_OFFSET (0x0020) /* Configuration Register 0 (CFGR0) */ +#define IMX9_LPSPI_CFGR1_OFFSET (0x0024) /* Configuration Register 1 (CFGR1) */ +#define IMX9_LPSPI_DMR0_OFFSET (0x0030) /* Data Match Register 0 (DMR0) */ +#define IMX9_LPSPI_DMR1_OFFSET (0x0034) /* Data Match Register 1 (DMR1) */ +#define IMX9_LPSPI_CCR_OFFSET (0x0040) /* Clock Configuration Register (CCR) */ +#define IMX9_LPSPI_CCR1_OFFSET (0x0044) /* Clock Configuration Register 1 (CCR1) */ +#define IMX9_LPSPI_FCR_OFFSET (0x0058) /* FIFO Control Register (FCR) */ +#define IMX9_LPSPI_FSR_OFFSET (0x005c) /* FIFO Status Register (FSR) */ +#define IMX9_LPSPI_TCR_OFFSET (0x0060) /* Transmit Command Register (TCR) */ +#define IMX9_LPSPI_TDR_OFFSET (0x0064) /* Transmit Data Register (TDR) */ +#define IMX9_LPSPI_RSR_OFFSET (0x0070) /* Receive Status Register (RSR) */ +#define IMX9_LPSPI_RDR_OFFSET (0x0074) /* Receive Data Register (RDR) */ +#define IMX9_LPSPI_RDROR_OFFSET (0x0078) /* Receive Data Read Only Register (RDROR) */ +#define IMX9_LPSPI_TCBR_OFFSET (0x03fc) /* Transmit Command Burst Register (TCBR) */ + +#define IMX9_LPSPI_TDBR_OFFSET(n) (0x0400 + ((n) << 2)) /* Transmit Data Burst Register n=0..127 (TDBRn) */ +#define IMX9_LPSPI_RDBR_OFFSET(n) (0x0600 + ((n) << 2)) /* Receive Data Burst Register n=0..127 (RDBRn) */ + +/* Register addresses *******************************************************/ + +#define IMX9_LPSPI0_VERID(n) ((n) + IMX9_LPSPI_VERID_OFFSET) +#define IMX9_LPSPI0_PARAM(n) ((n) + IMX9_LPSPI_PARAM_OFFSET) +#define IMX9_LPSPI0_CR(n) ((n) + IMX9_LPSPI_CR_OFFSET) +#define IMX9_LPSPI0_SR(n) ((n) + IMX9_LPSPI_SR_OFFSET) +#define IMX9_LPSPI0_IER(n) ((n) + IMX9_LPSPI_IER_OFFSET) +#define IMX9_LPSPI0_DER(n) ((n) + IMX9_LPSPI_DER_OFFSET) +#define IMX9_LPSPI0_CFGR0(n) ((n) + IMX9_LPSPI_CFGR0_OFFSET) +#define IMX9_LPSPI0_CFGR1(n) ((n) + IMX9_LPSPI_CFGR1_OFFSET) +#define IMX9_LPSPI0_DMR0(n) ((n) + IMX9_LPSPI_DMR0_OFFSET) +#define IMX9_LPSPI0_DMR1(n) ((n) + IMX9_LPSPI_DMR1_OFFSET) +#define IMX9_LPSPI0_CCR(n) ((n) + IMX9_LPSPI_CCR_OFFSET) +#define IMX9_LPSPI0_CCR1(n) ((n) + IMX9_LPSPI_CCR1_OFFSET) +#define IMX9_LPSPI0_FCR(n) ((n) + IMX9_LPSPI_FCR_OFFSET) +#define IMX9_LPSPI0_FSR(n) ((n) + IMX9_LPSPI_FSR_OFFSET) +#define IMX9_LPSPI0_TCR(n) ((n) + IMX9_LPSPI_TCR_OFFSET) +#define IMX9_LPSPI0_TDR(n) ((n) + IMX9_LPSPI_TDR_OFFSET) +#define IMX9_LPSPI0_RSR(n) ((n) + IMX9_LPSPI_RSR_OFFSET) +#define IMX9_LPSPI0_RDR(n) ((n) + IMX9_LPSPI_RDR_OFFSET) +#define IMX9_LPSPI0_RDROR(n) ((n) + IMX9_LPSPI_RDROR_OFFSET) +#define IMX9_LPSPI0_TCBR(n) ((n) + IMX9_LPSPI_TCBR_OFFSET) +#define IMX9_LPSPI0_TDBR(n,v) ((n) + IMX9_LPSPI_TDBR_OFFSET(v)) +#define IMX9_LPSPI0_RDBR(n,v) ((n) + IMX9_LPSPI_RDBR_OFFSET(v)) + +/* Register bit definitions *************************************************/ + +/* Version ID Register (VERID) */ + +#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number (FEATURE) */ +#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT) +#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */ +#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT) +#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */ +#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT) + +/* Parameter Register (PARAM) */ + +#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */ +#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT) +#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */ +#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT) +#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number (PCSNUM) */ +#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT) + /* Bits 24-31: Reserved */ + +/* Control Register (CR) */ + +#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable (MEN) */ +#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset (RST) */ + /* Bit 2: Reserved */ +#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable (DBGEN) */ + /* Bits 4-7: Reserved */ +#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */ +#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */ + /* Bits 10-31: Reserved */ + +/* Status Register (SR) */ + +#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */ +#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */ + /* Bits 2-7: Reserved */ +#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag (WCF) */ +#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag (FCF) */ +#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag (TCF) */ +#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag (TEF) */ +#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag (REF) */ +#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag (DMF) */ + /* Bits 14-23: Reserved */ +#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag (MBF) */ + /* Bits 25-31: Reserved */ + +/* Interrupt Enable Register (IER) */ + +#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */ +#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */ + /* Bits 2-7: Reserved */ +#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable (WCIE) */ +#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable (FCIE) */ +#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable (TCIE) */ +#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable (TEIE) */ +#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable (REIE) */ +#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable (DMIE) */ + /* Bits 14-31: Reserved */ + +/* DMA Enable Register (DER) */ + +#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */ +#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */ + /* Bits 2-31: Reserved */ + +/* Configuration Register 0 (CFGR0) */ + +#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable (HREN) */ +#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity (HRPOL) */ +# define LPSPI_CFGR0_HRPOL_HIGH (0 << 1) /* HREQ pin or input trigger is active high */ +# define LPSPI_CFGR0_HRPOL_LOW (1 << 1) /* HREQ pin or input trigger is active low */ +#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select (HRSEL) */ +# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */ +# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */ +#define LPSPI_CFGR0_HRDIR (1 << 3) /* Bit 3: Host Request Direction (HRDIR) */ +# define LPSPI_CFGR0_HRDIR_INPUT (0 << 3) /* HREQ pin is configured as input */ +# define LPSPI_CFGR0_HRDIR_OUTPUT (1 << 3) /* HREQ pin is configured as output */ + /* Bits 4-7: Reserved */ +#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bit 8: Circular FIFO Enable (CIRCFIFO) */ +#define LPSPI_CFGR0_RDMO (1 << 9) /* Bit 9: Receive Data Match Only (RDMO) */ +# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* Received data is stored in the receive FIFO as in normal operations */ +# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* Received data is discarded unless the Data Match Flag (DMF) is set */ + /* Bits 10-31: Reserved */ + +/* Configuration Register 1 (CFGR1) */ + +#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode (MASTER) */ +#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point (SAMPLE) */ +# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */ +# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */ +#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS (AUTOPCS) */ +#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall (NOSTALL) */ +#define LPSPI_CFGR1_PARTIAL (1 << 4) /* Bit 4: Partial Enable (PARTIAL) */ + /* Bits 5-7: Reserved */ +#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-15: Peripheral Chip Select Polarity (PCSPOL) */ +#define LPSPI_CFGR1_PCSPOL_MASK (0xff << LPSPI_CFGR1_PCSPOL_SHIFT) +# define LPSPI_CFGR1_PCSPOL_LOW(n) (0 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active low */ +# define LPSPI_CFGR1_PCSPOL_HIGH(n) (1 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active high */ + +#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration (MATCFG) */ +#define LPSPI_CFGR1_MATCFG_MASK (0x07 << LPSPI_CFGR1_MATCFG_SHIFT) +#define LPSPI_CFGR1_MATCFG_DIS (0x00 << LPSPI_CFGR1_MATCFG_SHIFT) /* Match is disabled */ + + /* Bits 19-23: Reserved */ +#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration (PINCFG) */ +#define LPSPI_CFGR1_PINCFG_MASK (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) +# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0x00 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */ +# define LPSPI_CFGR1_PINCFG_SIN_SIN (0x01 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */ +# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (0x02 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */ +# define LPSPI_CFGR1_PINCFG_SOUT_SIN (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */ +# define LPSPI_CFGR1_PINCFG(n) ((n) << LPSPI_CFGR1_PINCFG_SHIFT) + +#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config (OUTCFG) */ +# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ +# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */ +#define LPSPI_CFGR1_PCSCFG_SHIFT (27) /* Bits 27-28: Peripheral Chip Select Configuration (PCSCFG) */ +#define LPSPI_CFGR1_PCSCFG_MASK (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) +# define LPSPI_CFGR1_PCSCFG_PCS (0x00 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for chip select function */ +# define LPSPI_CFGR1_PCSCFG_4BIT (0x01 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:3] are configured for half-duplex 4-bit transfers */ +# define LPSPI_CFGR1_PCSCFG_8BIT (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for half-duplex 4-bit and 8-bit transfers */ + + /* Bits 29-31: Reserved */ + +/* Data Match Register 0 (DMR0) */ + +#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value (MATCH0) */ +#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT) + +/* Data Match Register 0 (DMR1) */ + +#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value (MATCH1) */ +#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT) + +/* Clock Configuration Register (CCR) */ + +#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider (SCKDIV) */ +#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT) +# define LPSPI_CCR_SCKDIV(n) (((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers (DBT) */ +#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT) +# define LPSPI_CCR_DBT(n) (((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay (PCSSCK) */ +#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT) +# define LPSPI_CCR_PCSSCK(n) (((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay (SCKPCS) */ +#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT) +# define LPSPI_CCR_SCKPCS(n) (((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT) & LPSPI_CCR_SCKPCS_MASK) + +/* Clock Configuration Register 1 (CCR1) */ + +#define LPSPI_CCR1_SCKSET_SHIFT (0) /* Bits 0-7: SCK Setup (SCKSET) */ +#define LPSPI_CCR1_SCKSET_MASK (0xff << LPSPI_CCR1_SCKSET_SHIFT) +#define LPSPI_CCR1_SCKHLD_SHIFT (8) /* Bits 8-15: SCK Hold (SCKHLD) */ +#define LPSPI_CCR1_SCKHLD_MASK (0xff << LPSPI_CCR1_SCKHLD_SHIFT) +#define LPSPI_CCR1_PCSPCS_SHIFT (16) /* Bits 16-23: PCS to PCS Delay (PCSPCS) */ +#define LPSPI_CCR1_PCSPCS_MASK (0xff << LPSPI_CCR1_PCSPCS_SHIFT) +#define LPSPI_CCR1_SCKSCK_SHIFT (24) /* Bits 24-31: SCK Inter-Frame Delay (SCKSCK) */ +#define LPSPI_CCR1_SCKSCK_MASK (0xff << LPSPI_CCR1_SCKSCK_SHIFT) + +/* FIFO Control Register (FCR) */ + +#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-1: Transmit FIFO Watermark (TXWATER) */ +#define LPSPI_FCR_TXWATER_MASK (0x03 << LPSPI_FCR_TXWATER_SHIFT) +# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT) + /* Bits 2-15: Reserved */ +#define LPSPI_FCR_RXWATER_SHIFT (16) /* Bits 16-17: Receive FIFO Watermark (RXWATER) */ +#define LPSPI_FCR_RXWATER_MASK (0x03 << LPSPI_FCR_RXWATER_SHIFT) +# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT) + /* Bits 18-31: Reserved */ + +/* FIFO Status Register (FSR) */ + +#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-2: Transmit FIFO Count (TXCOUNT) */ +#define LPSPI_FSR_TXCOUNT_MASK (0x07 << LPSPI_FSR_TXCOUNT_SHIFT) + /* Bits 3-15: Reserved */ +#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-18: Receive FIFO Count (RXCOUNT) */ +#define LPSPI_FSR_RXCOUNT_MASK (0x07 << LPSPI_FSR_RXCOUNT_SHIFT) + /* Bits 19-31: Reserved */ + +/* Transmit Command Register (TCR) */ + +#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size (FRAMESZ) */ +#define LPSPI_TCR_FRAMESZ_MASK (0x0fff << LPSPI_TCR_FRAMESZ_SHIFT) +# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT) + /* Bits 12-15: Reserved */ +#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width (WIDTH) */ +#define LPSPI_TCR_WIDTH_MASK (0x03 << LPSPI_TCR_WIDTH_SHIFT) +# define LPSPI_TCR_WIDTH_1BIT (0x00 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */ +# define LPSPI_TCR_WIDTH_2BIT (0x01 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */ +# define LPSPI_TCR_WIDTH_4BIT (0x02 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */ +# define LPSPI_TCR_WIDTH_8BIT (0x03 << LPSPI_TCR_WIDTH_SHIFT) /* 8 bit transfer */ + +#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask (TXMSK) */ +#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask (RXMSK) */ +#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command (CONTC) */ +#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer (CONT) */ +#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap (BYSW) */ +#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First (LSBF) */ +# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */ +#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-26: Peripheral Chip Select (PCS) */ +#define LPSPI_TCR_PCS_MASK (0x07 << LPSPI_TCR_PCS_SHIFT) +# define LPSPI_TCR_PCS_0 (0x00 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[0] */ +# define LPSPI_TCR_PCS_1 (0x01 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[1] */ +# define LPSPI_TCR_PCS_2 (0x02 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[2] */ +# define LPSPI_TCR_PCS_3 (0x03 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[3] */ +# define LPSPI_TCR_PCS_4 (0x04 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[4] */ +# define LPSPI_TCR_PCS_5 (0x05 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[5] */ +# define LPSPI_TCR_PCS_6 (0x06 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[6] */ +# define LPSPI_TCR_PCS_7 (0x07 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[7] */ +# define LPSPI_TCR_PCS(n) (((n) << LPSPI_TCR_PCS_SHIFT) & LPSPI_TCR_PCS_MASK) + +#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value (PRESCALE) */ +#define LPSPI_TCR_PRESCALE_MASK (0x07 << LPSPI_TCR_PRESCALE_SHIFT) +# define LPSPI_TCR_PRESCALE_DIV1 (0x00 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */ +# define LPSPI_TCR_PRESCALE_DIV2 (0x01 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */ +# define LPSPI_TCR_PRESCALE_DIV4 (0x02 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */ +# define LPSPI_TCR_PRESCALE_DIV8 (0x03 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */ +# define LPSPI_TCR_PRESCALE_DIV16 (0x04 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */ +# define LPSPI_TCR_PRESCALE_DIV32 (0x05 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */ +# define LPSPI_TCR_PRESCALE_DIV64 (0x06 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */ +# define LPSPI_TCR_PRESCALE_DIV128 (0x07 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */ +# define LPSPI_TCR_PRESCALE(n) ((n) << LPSPI_TCR_PRESCALE_SHIFT) + +#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase (CPHA) */ +# define LPSPI_TCR_CPHA_CAPTURED (0 << 30) /* Data is captured on the leading edge of SCK and changed on the following edge of SCK */ +# define LPSPI_TCR_CPHA_CHANGED (1 << 30) /* Data is changed on the leading edge of SCK and captured on the following edge of SCK */ +#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity (CPOL) */ +# define LPSPI_TCR_CPOL_LOW (0 << 31) /* The inactive state value of SCK is low */ +# define LPSPI_TCR_CPOL_HIGH (1 << 31) /* The inactive state value of SCK is high */ + +/* Transmit Data Register (TDR) */ + +#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data (DATA) */ +#define LPSPI_TDR_DATA_MASK (0xffffffff << LPSPI_TDR_DATA_SHIFT) + +/* Receive Status Register (RSR) */ + +#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame (SOF) */ +#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty (RXEMPTY) */ + /* Bits 2-31: Reserved */ + +/* Receive Data Register (RDR) */ + +#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */ +#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT) + +/* Receive Data Read Only Register (RDROR) */ + +#define LPSPI_RDROR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */ +#define LPSPI_RDROR_DATA_MASK (0xffffffff << LPSPI_RDROR_DATA_SHIFT) + +/* Transmit Command Burst Register (TCBR) */ + +#define LPSPI_TCBR_DATA_SHIFT (0) /* Bits 0-31: Command Data (DATA) */ +#define LPSPI_TCBR_DATA_MASK (0xffffffff << LPSPI_TCBR_DATA_SHIFT) + +/* Transmit Data Burst Register (TDBR) */ + +#define LPSPI_TDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */ +#define LPSPI_TDBR_DATA_MASK (0xffffffff << LPSPI_TDBR_DATA_SHIFT) + +/* Receive Data Burst Register (RDBR) */ + +#define LPSPI_RDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */ +#define LPSPI_RDBR_DATA_MASK (0xffffffff << LPSPI_RDBR_DATA_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ */ diff --git a/arch/arm/src/imx9/hardware/imx9_lptmr.h b/arch/arm/src/imx9/hardware/imx9_lptmr.h new file mode 100644 index 0000000000000..9836dd15ce30e --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_lptmr.h @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_lptmr.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_LPTMR_CSR_OFFSET 0x0000 /* Control Status */ +#define IMX9_LPTMR_PSR_OFFSET 0x0004 /* Prescale */ +#define IMX9_LPTMR_CMR_OFFSET 0x0008 /* Compare */ +#define IMX9_LPTMR_CNR_OFFSET 0x000c /* Counter */ + +/* Register Address *********************************************************/ + +#define LPTMR_CSR(n) ((n) + IMX9_LPTMR_CSR_OFFSET) +#define LPTMR_PSR(n) ((n) + IMX9_LPTMR_PSR_OFFSET) +#define LPTMR_CMR(n) ((n) + IMX9_LPTMR_CMR_OFFSET) +#define LPTMR_CNR(n) ((n) + IMX9_LPTMR_CNR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define LPTMR_CSR_TDRE (1 << 8) /* Timer DMA Request Enable */ +#define LPTMR_CSR_TCF (1 << 7) /* Timer Compare Flag */ +#define LPTMR_CSR_TIE (1 << 6) /* Timer Interrupt Enable */ + +#define LPTMR_CSR_TPS_SHIFT (4) /* Bit[5:4]: Timer Pin Select */ +#define LPTMR_CSR_TPS_MASK (3 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS0 (0 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS1 (1 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS2 (2 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS3 (3 << LPTMR_CSR_TPS_SHIFT) + +#define LPTMR_CSR_TPP (1 << 3) /* Timer Pin Polarity */ +#define LPTMR_CSR_TFC (1 << 2) /* Timer Free-Running Counter */ +#define LPTMR_CSR_TMS (1 << 1) /* Timer Mode Select */ +#define LPTMR_CSR_TEN (1 << 0) /* Timer Enable */ + +#define LPTMR_PSR_PRESCALE_SHIFT (3) /* Bit[6:3]: Prescale Value */ +#define LPTMR_PSR_PRESCALE_MASK (0xf << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV8 (2 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV16 (3 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV32 (4 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV64 (5 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV128 (6 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV256 (7 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV512 (8 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV1024 (9 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV2048 (10 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV4096 (11 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV8192 (12 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV16384 (13 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV32768 (14 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV65536 (15 << LPTMR_PSR_PRESCALE_SHIFT) + +#define LPTMR_PSR_PBYP (1 << 2) /* Prescaler Bypass */ + +/* Clock sources (module clock / root clock) + * ipg_clk_irclk -> lptmrx_clk_root + * ipg_clk_1khz -> 32k_clk_root + * ipg_clk_32khz -> 32k_clk_root + * ipg_clk_ercl -> 32k_clk_root + */ + +#define LPTMR_PSR_PCS_SHIFT (0) /* Bit[1:0]: Prescaler Clock Select */ +#define LPTMR_PSR_PCS_MASK (3 << LPTMR_PSR_PCS_SHIFT) +#define LPTMR_PSR_PCS_REF_INT (0 << LPTMR_PSR_PCS_SHIFT) /* Internal reference clock */ +#define LPTMR_PSR_PCS_LPO (1 << LPTMR_PSR_PCS_SHIFT) /* LPO 1K Hz */ +#define LPTMR_PSR_PCS_RTC (2 << LPTMR_PSR_PCS_SHIFT) /* RTC 32768 Hz */ +#define LPTMR_PSR_PCS_REF_EXT (3 << LPTMR_PSR_PCS_SHIFT) /* External reference clock */ +# define LPTMR_PSR_PCS_SOSC LPTMR_PSR_PCS_RFOSC + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ */ diff --git a/arch/arm/src/imx9/hardware/imx9_lpuart.h b/arch/arm/src/imx9/hardware/imx9_lpuart.h new file mode 100644 index 0000000000000..49850875a919f --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_lpuart.h @@ -0,0 +1,316 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_lpuart.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LPUART Register Offsets **************************************************/ + +#define IMX9_LPUART_VERID_OFFSET (0x00) /* Version ID Register (VERID) */ +#define IMX9_LPUART_PARAM_OFFSET (0x04) /* Parameter Register (PARAM) */ +#define IMX9_LPUART_GLOBAL_OFFSET (0x08) /* LPUART Global Register (GLOBAL) */ +#define IMX9_LPUART_PINCFG_OFFSET (0x0c) /* LPUART Pin Configuration Register (PINCFG) */ +#define IMX9_LPUART_BAUD_OFFSET (0x10) /* LPUART Baud Rate Register (BAUD) */ +#define IMX9_LPUART_STAT_OFFSET (0x14) /* LPUART Status Register (STAT) */ +#define IMX9_LPUART_CTRL_OFFSET (0x18) /* LPUART Control Register (CTRL) */ +#define IMX9_LPUART_DATA_OFFSET (0x1c) /* LPUART Data Register (DATA) */ +#define IMX9_LPUART_MATCH_OFFSET (0x20) /* LPUART Match Address Register (MATCH) */ +#define IMX9_LPUART_MODIR_OFFSET (0x24) /* LPUART Modem IrDA Register (MODIR) */ +#define IMX9_LPUART_FIFO_OFFSET (0x28) /* LPUART FIFO Register (FIFO) */ +#define IMX9_LPUART_WATER_OFFSET (0x2c) /* LPUART Watermark Register (WATER) */ +#define IMX9_LPUART_DATARO_OFFSET (0x30) /* Data read-only Register (DATARO) */ + +/* Register bit definitions *************************************************/ + +/* Version ID Register (VERID) */ + +#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number (FEATURE) */ +#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT) +# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */ +# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */ + +#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */ +#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT) +#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */ +#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT) + +/* Parameter Register (PARAM) */ + +#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */ +#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT) +#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */ +#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT) + /* Bits 16-31: Reserved */ + +/* LPUART Global Register (GLOBAL) */ + + /* Bit 0: Reserved */ +#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset (RST) */ + /* Bits 2-31: Reserved */ + +/* LPUART Pin Configuration Register (PINCFG) */ + +#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select (TRGSEL) */ +#define LPUART_PINCFG_TRGSEL_MASK (0x03 << LPUART_PINCFG_TRGSEL_SHIFT) +# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */ +# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */ +# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */ +# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */ + + /* Bits 2-31: Reserved */ + +/* LPUART Baud Rate Register (BAUD) */ + +#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor (SBR) */ +#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT) +# define LPUART_BAUD_SBR(n) ((n) << LPUART_BAUD_SBR_SHIFT) +#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select (SBNS) */ +#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable (RXEDGIE) */ +#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable (LBKDIE) */ +#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable (RESYNCDIS) */ +#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling (BOTHEDGE) */ +#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration (MATCFG) */ +#define LPUART_BAUD_MATCFG_MASK (0x03 << LPUART_BAUD_MATCFG_SHIFT) +# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */ +# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */ +# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ +# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */ + + /* Bit 20: Reserved */ +#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable (RDMAE) */ + /* Bit 22: Reserved */ +#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable (TDMAE) */ +#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-29: Oversampling Ratio (OSR) */ +#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT) +# define LPUART_BAUD_OSR(n) (((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */ + +#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode Select (M10) */ +#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 (MAEN2) */ +#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 (MAEN1) */ + +/* LPUART Status Register (STAT) */ + +#define LPUART_STAT_LBKFE (1 << 0) /* Bit 0: LIN Break Flag Enable (LBKFE) */ +#define LPUART_STAT_AME (1 << 1) /* Bit 1: Address Mark Enable (AME) */ + /* Bits 2-13: Reserved */ +#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag (MA2F) */ +#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag (MA1F) */ +#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag (PF) */ +#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag (FE) */ +#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag (NF) */ +#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag (OR) */ +#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag (IDLE) */ +#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag (RDRF) */ +#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag (TC) */ +#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag (TDRE) */ +#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag (RAF) */ +#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable (LBKDE) */ +#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length (BRK13) */ +#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect (RWUID) */ +#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion (RXINV) */ +#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First (MSBF) */ +#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag (RXEDGIF) */ +#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag (LBKDIF) */ + +/* LPUART Control Register (CTRL) */ + +#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */ +# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */ +# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */ +#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */ +#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */ +#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */ +#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */ +#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */ +#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */ +#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */ +#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */ +#define LPUART_CTRL_IDLECFG_MASK (0x07 << LPUART_CTRL_IDLECFG_SHIFT) +# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */ +# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */ +# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */ +# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */ +# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */ +# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ +# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ +# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ + +#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select (M7) */ + /* Bits 12-13: Reserved */ +#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable (MA2IE) */ +#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable (MA1IE) */ +#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break (SBK) */ +#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control (RWU) */ +#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable (RE) */ +#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable (TE) */ +#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable (ILIE) */ +#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable (RIE) */ +#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable (TCIE) */ +#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable (TIE) */ +#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable (PEIE) */ +#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable (FEIE) */ +#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable (NEIE) */ +#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable (ORIE) */ +#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion (TXINV) */ +#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode (TXDIR) */ +#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 (R9T8) */ +#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 (R8T9) */ + +#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \ + LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \ + LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \ + LPUART_CTRL_MA2IE) + +/* LPUART Data Register (DATA) */ + +#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 (DATA)*/ +#define LPUART_DATA_MASK (0x03ff << LPUART_DATA_SHIFT) +#define LPUART_DATA_LINBRK (1 << 10) /* Bit 10: LIN Break (LINBRK) */ +#define LPUART_DATA_STATUS_SHIFT (11) /* Bits 11-15: Status */ +#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line (IDLINE) */ +#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty (RXEMPT) */ +#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character (FRETSC) */ +#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error (PARITYE) */ +#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy Data Received (NOISY) */ + /* Bits 16-31: Reserved */ + +/* LPUART Match Address Register (MATCH) */ + +#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 (MA1) */ +#define LPUART_MATCH_MA1_MASK (0x03ff << LPUART_MATCH_MA1_SHIFT) +# define LPUART_MATCH_MA1(n) ((n) << LPUART_MATCH_MA1_SHIFT) + /* Bits 10-15: Reserved */ +#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 (MA2) */ +#define LPUART_MATCH_MA2_MASK (0x03ff << LPUART_MATCH_MA2_SHIFT) +# define LPUART_MATCH_MA2(n) ((n) << LPUART_MATCH_MA2_SHIFT) + /* Bits 26-31: Reserved */ + +/* LPUART Modem IrDA Register (MODIR) */ + +#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable (TXCTSE) */ +#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable (TXRTSE) */ +#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity (TXRTSPOL) */ +#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable (RXRTSE) */ +#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration (TXCTSC) */ +# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */ +# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */ +#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source (TXCTSSRC) */ +# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* CTS input is CTS_B pin */ +# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* CTS input is receiver address match result */ + /* Bits 6-7: Reserved */ +#define LPUART_MODIR_RTSWATER_SHIFT (8) /* Bits 8-9: Receive RTS Configuration (RTSWATER) */ +#define LPUART_MODIR_RTSWATER_MASK (0x03 << LPUART_MODIR_RTSWATER_SHIFT) +# define LPUART_MODIR_RTSWATER(n) ((n) << LPUART_MODIR_RTSWATER_SHIFT) + /* Bits 10-15: Reserved */ +#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse (TNP) */ +#define LPUART_MODIR_TNP_MASK (0x03 << LPUART_MODIR_TNP_SHIFT) +# define LPUART_MODIR_TNP(n) (((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */ + +#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable (IREN) */ + /* Bits 19-31: Reserved */ + +/* LPUART FIFO Register (FIFO) */ + +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO Buffer Depth (RXFIFOSIZE) */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x07 << LPUART_FIFO_RXFIFOSIZE_SHIFT) +# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 dataword */ +# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */ + +#define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable (RXFE) */ +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO Buffer Depth (TXFIFOSIZE) */ +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x07 << LPUART_FIFO_TXFIFOSIZE_SHIFT) +# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 dataword */ +# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */ + +#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable (TXFE) */ +#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable (RXUFE) */ +#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable (TXOFE) */ +#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable (RXIDEN) */ +#define LPUART_FIFO_RXIDEN_MASK (0x07 << LPUART_FIFO_RXIDEN_SHIFT) +# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */ +# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 character */ +# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 characters */ +# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 characters */ +# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 characters */ +# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 characters */ +# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 characters */ +# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 characters */ + + /* Bit 13: Reserved */ +#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO Flush (RXFLUSH) */ +#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO Flush (TXFLUSH) */ +#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver FIFO Underflow Flag (RXUF) */ +#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter FIFO Overflow Flag (TXOF) */ + /* Bits 18-21: Reserved */ +#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty (RXEMPT) */ +#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty (TXEMPT) */ + /* Bits 24-31: Reserved */ + +/* LPUART Watermark Register (WATER) */ + +#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-3: Transmit Watermark (TXWATER) */ +#define LPUART_WATER_TXWATER_MASK (0x0f << LPUART_WATER_TXWATER_SHIFT) +# define LPUART_WATER_TXWATER(n) ((n) << LPUART_WATER_TXWATER_SHIFT) + /* Bits 4-7: Reserved */ +#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-12: Transmit Counter (TXCOUNT) */ +#define LPUART_WATER_TXCOUNT_MASK (0x1f << LPUART_WATER_TXCOUNT_SHIFT) +# define LPUART_WATER_TXCOUNT(n) ((n) << LPUART_WATER_TXCOUNT_SHIFT) + /* Bits 13-15: Reserved */ +#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-19: Receive Watermark (RXWATER) */ +#define LPUART_WATER_RXWATER_MASK (0x0f << LPUART_WATER_RXWATER_SHIFT) +# define LPUART_WATER_RXWATER(n) ((n) << LPUART_WATER_RXWATER_SHIFT) + /* Bits 20-23: Reserved */ +#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-28: Receive Counter (RXCOUNT) */ +#define LPUART_WATER_RXCOUNT_MASK (0x1f << LPUART_WATER_RXCOUNT_SHIFT) +# define LPUART_WATER_RXCOUNT(n) ((n) << LPUART_WATER_RXCOUNT_SHIFT) + /* Bits 29-31: Reserved */ + +/* Data read-only Register (DATARO) */ + +#define LPUART_DATARO_DATA_SHIFT (0) /* Bits 0-15: Receive Data (DATA) */ +#define LPUART_DATARO_DATA_MASK (0xffff << LPUART_DATARO_DATA_SHIFT) + /* Bits 16-31: Reserved */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_memorymap.h b/arch/arm/src/imx9/hardware/imx9_memorymap.h new file mode 100644 index 0000000000000..f500ae6939992 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_memorymap.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_memorymap.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_mu.h b/arch/arm/src/imx9/hardware/imx9_mu.h new file mode 100644 index 0000000000000..e720529fe2829 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_mu.h @@ -0,0 +1,257 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_mu.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define IMX9_MU_VER_OFFSET 0x0000 /* Version ID */ +#define IMX9_MU_PAR_OFFSET 0x0004 /* Parameter */ +#define IMX9_MU_CR_OFFSET 0x0008 /* Control */ +#define IMX9_MU_SR_OFFSET 0x000c /* Status */ +#define IMX9_MU_FCR_OFFSET 0x0100 /* Flag Control */ +#define IMX9_MU_FSR_OFFSET 0x0104 /* Flag Status */ +#define IMX9_MU_GIER_OFFSET 0x0110 /* General-Purpose Interrupt Enable */ +#define IMX9_MU_GCR_OFFSET 0x0114 /* General-Purpose Control */ +#define IMX9_MU_GSR_OFFSET 0x0118 /* General-purpose Status */ +#define IMX9_MU_TCR_OFFSET 0x0120 /* Transmit Control */ +#define IMX9_MU_TSR_OFFSET 0x0124 /* Transmit Status */ +#define IMX9_MU_RCR_OFFSET 0x0128 /* Receive Control */ +#define IMX9_MU_RSR_OFFSET 0x012c /* Receive Status */ +#define IMX9_MU_TR1_OFFSET 0x0200 /* Transmit */ +#define IMX9_MU_TR2_OFFSET 0x0200 /* Transmit */ +#define IMX9_MU_TR3_OFFSET 0x0200 /* Transmit */ +#define IMX9_MU_TR4_OFFSET 0x0200 /* Transmit */ +#define IMX9_MU_RR1_OFFSET 0x0280 /* Receive */ +#define IMX9_MU_RR2_OFFSET 0x0280 /* Receive */ +#define IMX9_MU_RR3_OFFSET 0x0280 /* Receive */ +#define IMX9_MU_RR4_OFFSET 0x0280 /* Receive */ + +/* Register macros */ + +#define IMX9_MU_VER(n) ((n) + IMX9_MU_VER_OFFSET) /* Version ID */ +#define IMX9_MU_PAR(n) ((n) + IMX9_MU_PAR_OFFSET) /* Parameter */ +#define IMX9_MU_CR(n) ((n) + IMX9_MU_CR_OFFSET) /* Control */ +#define IMX9_MU_SR(n) ((n) + IMX9_MU_SR_OFFSET) /* Status */ +#define IMX9_MU_FCR(n) ((n) + IMX9_MU_FCR_OFFSET) /* Flag Control */ +#define IMX9_MU_FSR(n) ((n) + IMX9_MU_FSR_OFFSET) /* Flag Status */ +#define IMX9_MU_GIER(n) ((n) + IMX9_MU_GIER_OFFSET) /* General-Purpose Interrupt Enable */ +#define IMX9_MU_GCR(n) ((n) + IMX9_MU_GCR_OFFSET) /* General-Purpose Control */ +#define IMX9_MU_GSR(n) ((n) + IMX9_MU_GSR_OFFSET) /* General-purpose Status */ +#define IMX9_MU_TCR(n) ((n) + IMX9_MU_TCR_OFFSET) /* Transmit Control */ +#define IMX9_MU_TSR(n) ((n) + IMX9_MU_TSR_OFFSET) /* Transmit Status */ +#define IMX9_MU_RCR(n) ((n) + IMX9_MU_RCR_OFFSET) /* Receive Control */ +#define IMX9_MU_RSR(n) ((n) + IMX9_MU_RSR_OFFSET) /* Receive Status */ +#define IMX9_MU_TR1(n) ((n) + IMX9_MU_TR1_OFFSET) /* Transmit */ +#define IMX9_MU_TR2(n) ((n) + IMX9_MU_TR2_OFFSET) /* Transmit */ +#define IMX9_MU_TR3(n) ((n) + IMX9_MU_TR3_OFFSET) /* Transmit */ +#define IMX9_MU_TR4(n) ((n) + IMX9_MU_TR4_OFFSET) /* Transmit */ +#define IMX9_MU_RR1(n) ((n) + IMX9_MU_RR1_OFFSET) /* Receive */ +#define IMX9_MU_RR2(n) ((n) + IMX9_MU_RR2_OFFSET) /* Receive */ +#define IMX9_MU_RR3(n) ((n) + IMX9_MU_RR3_OFFSET) /* Receive */ +#define IMX9_MU_RR4(n) ((n) + IMX9_MU_RR4_OFFSET) /* Receive */ + +/* Field definitions */ + +/* VER register */ + +#define IMX9_MU_VER_FEATURE_SHIFT 0 /* Feature Set Number */ +#define IMX9_MU_VER_FEATURE_MASK 0xffff /* Feature Set Number */ + +#define IMX9_MU_VER_MINOR_SHIFT 16 /* Minor Version Number */ +#define IMX9_MU_VER_MINOR_MASK 0xff /* Minor Version Number */ + +#define IMX9_MU_VER_MAJOR_SHIFT 24 /* Major Version Number */ +#define IMX9_MU_VER_MAJOR_MASK 0xff /* Major Version Number */ + +/* PAR register */ + +#define IMX9_MU_PAR_TR_NUM_SHIFT 0 /* Transmit Register Number */ +#define IMX9_MU_PAR_TR_NUM_MASK 0xff /* Transmit Register Number */ + +#define IMX9_MU_PAR_RR_NUM_SHIFT 8 /* Receive Register Number */ +#define IMX9_MU_PAR_RR_NUM_MASK 0xff /* Receive Register Number */ + +#define IMX9_MU_PAR_GIR_NUM_SHIFT 16 /* General-Purpose Interrupt Request Number */ +#define IMX9_MU_PAR_GIR_NUM_MASK 0xff /* General-Purpose Interrupt Request Number */ + +#define IMX9_MU_PAR_FLAG_WIDTH_SHIFT 24 /* Flag Width */ +#define IMX9_MU_PAR_FLAG_WIDTH_MASK 0xff /* Flag Width */ + +/* CR register */ + +#define IMX9_MU_CR_MUR_SHIFT 0 /* MU Reset */ +#define IMX9_MU_CR_MUR_FLAG (1 << IMX9_MU_CR_MUR_SHIFT) /* MU Reset */ + +#define IMX9_MU_CR_MURIE_SHIFT 1 /* MUA Reset Interrupt Enable */ +#define IMX9_MU_CR_MURIE_FLAG (1 << IMX9_MU_CR_MURIE_SHIFT) /* MUA Reset Interrupt Enable */ + +/* SR register */ + +#define IMX9_MU_SR_MURS_SHIFT 0 /* MUA and MUB Reset State */ +#define IMX9_MU_SR_MURS_FLAG (1 << IMX9_MU_SR_MURS_SHIFT) /* MUA and MUB Reset State */ + +#define IMX9_MU_SR_MURIP_SHIFT 1 /* MU Reset Interrupt Pending Flag */ +#define IMX9_MU_SR_MURIP_FLAG (1 << IMX9_MU_SR_MURIP_SHIFT) /* MU Reset Interrupt Pending Flag */ + +#define IMX9_MU_SR_EP_SHIFT 2 /* MUA Side Event Pending */ +#define IMX9_MU_SR_EP_FLAG (1 << IMX9_MU_SR_EP_SHIFT) /* MUA Side Event Pending */ + +#define IMX9_MU_SR_FUP_SHIFT 3 /* MUA Flag Update Pending */ +#define IMX9_MU_SR_FUP_FLAG (1 << IMX9_MU_SR_FUP_SHIFT) /* MUA Flag Update Pending */ + +#define IMX9_MU_SR_GIRP_SHIFT 4 /* MUA General-Purpose Interrupt Pending */ +#define IMX9_MU_SR_GIRP_FLAG (1 << IMX9_MU_SR_GIRP_SHIFT) /* MUA General-Purpose Interrupt Pending */ + +#define IMX9_MU_SR_TEP_SHIFT 5 /* MUA Transmit Empty Pending */ +#define IMX9_MU_SR_TEP_FLAG (1 << IMX9_MU_SR_TEP_SHIFT) /* MUA Transmit Empty Pending */ + +#define IMX9_MU_SR_RFP_SHIFT 6 /* MUA Receive Full Pending */ +#define IMX9_MU_SR_RFP_FLAG (1 << IMX9_MU_SR_RFP_SHIFT) /* MUA Receive Full Pending */ + +/* FCR register */ + +#define IMX9_MU_FCR_F0_SHIFT 0 /* MUA to MUB Flag */ +#define IMX9_MU_FCR_F0_FLAG (1 << IMX9_MU_FCR_F0_SHIFT) /* MUA to MUB Flag */ + +#define IMX9_MU_FCR_F1_SHIFT 1 /* MUA to MUB Flag */ +#define IMX9_MU_FCR_F1_FLAG (1 << IMX9_MU_FCR_F1_SHIFT) /* MUA to MUB Flag */ + +#define IMX9_MU_FCR_F2_SHIFT 2 /* MUA to MUB Flag */ +#define IMX9_MU_FCR_F2_FLAG (1 << IMX9_MU_FCR_F2_SHIFT) /* MUA to MUB Flag */ + +/* FSR register */ + +#define IMX9_MU_FSR_F0_SHIFT 0 /* MUB to MUA-Side Flag */ +#define IMX9_MU_FSR_F0_FLAG (1 << IMX9_MU_FSR_F0_SHIFT) /* MUB to MUA-Side Flag */ + +#define IMX9_MU_FSR_F1_SHIFT 1 /* MUB to MUA-Side Flag */ +#define IMX9_MU_FSR_F1_FLAG (1 << IMX9_MU_FSR_F1_SHIFT) /* MUB to MUA-Side Flag */ + +#define IMX9_MU_FSR_F2_SHIFT 2 /* MUB to MUA-Side Flag */ +#define IMX9_MU_FSR_F2_FLAG (1 << IMX9_MU_FSR_F2_SHIFT) /* MUB to MUA-Side Flag */ + +/* GIER register */ + +#define IMX9_MU_GIER_GIE0_SHIFT 0 /* MUA General-purpose Interrupt Enable */ +#define IMX9_MU_GIER_GIE0_FLAG (1 << IMX9_MU_GIER_GIE0_SHIFT) /* MUA General-purpose Interrupt Enable */ + +#define IMX9_MU_GIER_GIE1_SHIFT 1 /* MUA General-purpose Interrupt Enable */ +#define IMX9_MU_GIER_GIE1_FLAG (1 << IMX9_MU_GIER_GIE1_SHIFT) /* MUA General-purpose Interrupt Enable */ + +#define IMX9_MU_GIER_GIE2_SHIFT 2 /* MUA General-purpose Interrupt Enable */ +#define IMX9_MU_GIER_GIE2_FLAG (1 << IMX9_MU_GIER_GIE2_SHIFT) /* MUA General-purpose Interrupt Enable */ + +#define IMX9_MU_GIER_GIE3_SHIFT 3 /* MUA General-purpose Interrupt Enable */ +#define IMX9_MU_GIER_GIE3_FLAG (1 << IMX9_MU_GIER_GIE3_SHIFT) /* MUA General-purpose Interrupt Enable */ + +/* GCR register */ + +#define IMX9_MU_GCR_GIR0_SHIFT 0 /* MUA General-Purpose Interrupt Request */ +#define IMX9_MU_GCR_GIR0_FLAG (1 << IMX9_MU_GCR_GIR0_SHIFT) /* MUA General-Purpose Interrupt Request */ + +#define IMX9_MU_GCR_GIR1_SHIFT 1 /* MUA General-Purpose Interrupt Request */ +#define IMX9_MU_GCR_GIR1_FLAG (1 << IMX9_MU_GCR_GIR1_SHIFT) /* MUA General-Purpose Interrupt Request */ + +#define IMX9_MU_GCR_GIR2_SHIFT 2 /* MUA General-Purpose Interrupt Request */ +#define IMX9_MU_GCR_GIR2_FLAG (1 << IMX9_MU_GCR_GIR2_SHIFT) /* MUA General-Purpose Interrupt Request */ + +#define IMX9_MU_GCR_GIR3_SHIFT 3 /* MUA General-Purpose Interrupt Request */ +#define IMX9_MU_GCR_GIR3_FLAG (1 << IMX9_MU_GCR_GIR3_SHIFT) /* MUA General-Purpose Interrupt Request */ + +/* GSR register */ + +#define IMX9_MU_GSR_GIP0_SHIFT 0 /* MUA General-Purpose Interrupt Request Pending */ +#define IMX9_MU_GSR_GIP0_FLAG (1 << IMX9_MU_GSR_GIP0_SHIFT) /* MUA General-Purpose Interrupt Request Pending */ + +#define IMX9_MU_GSR_GIP1_SHIFT 1 /* MUA General-Purpose Interrupt Request Pending */ +#define IMX9_MU_GSR_GIP1_FLAG (1 << IMX9_MU_GSR_GIP1_SHIFT) /* MUA General-Purpose Interrupt Request Pending */ + +#define IMX9_MU_GSR_GIP2_SHIFT 2 /* MUA General-Purpose Interrupt Request Pending */ +#define IMX9_MU_GSR_GIP2_FLAG (1 << IMX9_MU_GSR_GIP2_SHIFT) /* MUA General-Purpose Interrupt Request Pending */ + +#define IMX9_MU_GSR_GIP3_SHIFT 3 /* MUA General-Purpose Interrupt Request Pending */ +#define IMX9_MU_GSR_GIP3_FLAG (1 << IMX9_MU_GSR_GIP3_SHIFT) /* MUA General-Purpose Interrupt Request Pending */ + +/* TCR register */ + +#define IMX9_MU_TCR_TIE0_SHIFT 0 /* MUA Transmit Interrupt Enable */ +#define IMX9_MU_TCR_TIE0_FLAG (1 << IMX9_MU_TCR_TIE0_SHIFT) /* MUA Transmit Interrupt Enable */ + +#define IMX9_MU_TCR_TIE1_SHIFT 1 /* MUA Transmit Interrupt Enable */ +#define IMX9_MU_TCR_TIE1_FLAG (1 << IMX9_MU_TCR_TIE1_SHIFT) /* MUA Transmit Interrupt Enable */ + +#define IMX9_MU_TCR_TIE2_SHIFT 2 /* MUA Transmit Interrupt Enable */ +#define IMX9_MU_TCR_TIE2_FLAG (1 << IMX9_MU_TCR_TIE2_SHIFT) /* MUA Transmit Interrupt Enable */ + +#define IMX9_MU_TCR_TIE3_SHIFT 3 /* MUA Transmit Interrupt Enable */ +#define IMX9_MU_TCR_TIE3_FLAG (1 << IMX9_MU_TCR_TIE3_SHIFT) /* MUA Transmit Interrupt Enable */ + +/* TSR register */ + +#define IMX9_MU_TSR_TE0_SHIFT 0 /* MUA Transmit Empty */ +#define IMX9_MU_TSR_TE0_FLAG (1 << IMX9_MU_TSR_TE0_SHIFT) /* MUA Transmit Empty */ + +#define IMX9_MU_TSR_TE1_SHIFT 1 /* MUA Transmit Empty */ +#define IMX9_MU_TSR_TE1_FLAG (1 << IMX9_MU_TSR_TE1_SHIFT) /* MUA Transmit Empty */ + +#define IMX9_MU_TSR_TE2_SHIFT 2 /* MUA Transmit Empty */ +#define IMX9_MU_TSR_TE2_FLAG (1 << IMX9_MU_TSR_TE2_SHIFT) /* MUA Transmit Empty */ + +#define IMX9_MU_TSR_TE3_SHIFT 3 /* MUA Transmit Empty */ +#define IMX9_MU_TSR_TE3_FLAG (1 << IMX9_MU_TSR_TE3_SHIFT) /* MUA Transmit Empty */ + +/* RCR register */ + +#define IMX9_MU_RCR_RIE0_SHIFT 0 /* MUA Receive Interrupt Enable */ +#define IMX9_MU_RCR_RIE0_FLAG (1 << IMX9_MU_RCR_RIE0_SHIFT) /* MUA Receive Interrupt Enable */ + +#define IMX9_MU_RCR_RIE1_SHIFT 1 /* MUA Receive Interrupt Enable */ +#define IMX9_MU_RCR_RIE1_FLAG (1 << IMX9_MU_RCR_RIE1_SHIFT) /* MUA Receive Interrupt Enable */ + +#define IMX9_MU_RCR_RIE2_SHIFT 2 /* MUA Receive Interrupt Enable */ +#define IMX9_MU_RCR_RIE2_FLAG (1 << IMX9_MU_RCR_RIE2_SHIFT) /* MUA Receive Interrupt Enable */ + +#define IMX9_MU_RCR_RIE3_SHIFT 3 /* MUA Receive Interrupt Enable */ +#define IMX9_MU_RCR_RIE3_FLAG (1 << IMX9_MU_RCR_RIE3_SHIFT) /* MUA Receive Interrupt Enable */ + +/* RSR register */ + +#define IMX9_MU_RSR_RF0_SHIFT 0 /* MUA Receive Register Full */ +#define IMX9_MU_RSR_RF0_FLAG (1 << IMX9_MU_RSR_RF0_SHIFT) /* MUA Receive Register Full */ + +#define IMX9_MU_RSR_RF1_SHIFT 1 /* MUA Receive Register Full */ +#define IMX9_MU_RSR_RF1_FLAG (1 << IMX9_MU_RSR_RF1_SHIFT) /* MUA Receive Register Full */ + +#define IMX9_MU_RSR_RF2_SHIFT 2 /* MUA Receive Register Full */ +#define IMX9_MU_RSR_RF2_FLAG (1 << IMX9_MU_RSR_RF2_SHIFT) /* MUA Receive Register Full */ + +#define IMX9_MU_RSR_RF3_SHIFT 3 /* MUA Receive Register Full */ +#define IMX9_MU_RSR_RF3_FLAG (1 << IMX9_MU_RSR_RF3_SHIFT) /* MUA Receive Register Full */ + +/* Register array dimensions */ + +#define IMX9_MU_TR_REGARRAY_SIZE 4 +#define IMX9_MU_RR_REGARRAY_SIZE 4 diff --git a/arch/arm/src/imx9/hardware/imx9_pinmux.h b/arch/arm/src/imx9/hardware/imx9_pinmux.h new file mode 100644 index 0000000000000..d93dd9078668d --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_pinmux.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_pinmux.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX95_M7) +# include "hardware/imx95/imx95_pinmux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_tpm.h b/arch/arm/src/imx9/hardware/imx9_tpm.h new file mode 100644 index 0000000000000..c823cea983753 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_tpm.h @@ -0,0 +1,216 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_tpm.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_TPM_VERID_OFFSET 0x0000 /* Version ID */ +#define IMX9_TPM_PARAM_OFFSET 0x0004 /* Parameter */ +#define IMX9_TPM_GLOBAL_OFFSET 0x0008 /* TPM Global */ +#define IMX9_TPM_SC_OFFSET 0x0010 /* Status and Control */ +#define IMX9_TPM_CNT_OFFSET 0x0014 /* Counter */ +#define IMX9_TPM_MOD_OFFSET 0x0018 /* Modulo */ +#define IMX9_TPM_STATUS_OFFSET 0x001c /* Capture and Compare Status */ +#define IMX9_TPM_CXSC_OFFSET(ch) (0x0020 + (ch) * 8) /* Channel Status and Control */ +#define IMX9_TPM_CXV_OFFSET(ch) (0x0024 + (ch) * 8) /* Channel Value */ +#define IMX9_TPM_C1SC_OFFSET 0x0028 /* Channel n Status and Control */ +#define IMX9_TPM_C1V_OFFSET 0x002c /* Channel n Value */ +#define IMX9_TPM_C2SC_OFFSET 0x0030 /* Channel n Status and Control */ +#define IMX9_TPM_C2V_OFFSET 0x0034 /* Channel n Value */ +#define IMX9_TPM_C3SC_OFFSET 0x0038 /* Channel n Status and Control */ +#define IMX9_TPM_C3V_OFFSET 0x003c /* Channel n Value */ +#define IMX9_TPM_COMBINE_OFFSET 0x0064 /* Combine Channel */ +#define IMX9_TPM_TRIG_OFFSET 0x006c /* Channel Trigger */ +#define IMX9_TPM_POL_OFFSET 0x0070 /* Channel Polarity */ +#define IMX9_TPM_FILTER_OFFSET 0x0078 /* Filter Control */ +#define IMX9_TPM_QDCTRL_OFFSET 0x0080 /* Quadrature Decoder Control and Status */ +#define IMX9_TPM_CONF_OFFSET 0x0084 /* Configuration */ + +/* Register Bitfield Definitions ********************************************/ + +/* PARAM */ + +#define TPM_PARAM_WIDTH_SHIFT (16) /* Bit[23:16]: Width of the counter and timer channels */ +#define TPM_PARAM_WIDTH_MASK (0xff << TPM_PARAM_WIDTH_SHIFT) + +#define TPM_PARAM_TRIG_SHIFT (8) /* Bit[15:8]: Number of triggers that TPM implements */ +#define TPM_PARAM_TRIG_MASK (0xff << LPIT_PARAM_TRIG_SHIFT) + +#define TPM_PARAM_CHAN_SHIFT (0) /* Bit[7:0]: Number of timer channels */ +#define TPM_PARAM_CHAN_MASK (0xff << TPM_PARAM_CHAN_SHIFT) + +/* GLOBAL */ + +#define TPM_GLOBAL_RST_SHIFT (1) /* Bit[1]: Software Reset */ +#define TPM_GLOBAL_RST_MASK (0x1 << TPM_GLOBAL_RST_SHIFT) + +#define TPM_GLOBAL_NOUPDATE_SHIFT (0) /* Bit[0]: Block updates to internal registers */ +#define TPM_GLOBAL_NOUPDATE_MASK (0x1 << TPM_GLOBAL_NOUPDATE_SHIFT) + +/* SC */ + +#define TPM_SC_DMA_SHIFT (8) /* Bit[8]: DMA Enable */ +#define TPM_SC_DMA_MASK (0x1 << TPM_SC_DMA_SHIFT) + +#define TPM_SC_TOF_SHIFT (7) /* Bit[7]: Timer Overflow Flag */ +#define TPM_SC_TOF_MASK (0x1 << TPM_SC_TOF_SHIFT) + +#define TPM_SC_TOIE_SHIFT (6) /* Bit[6]: Timer Overflow Interrupt Enable */ +#define TPM_SC_TOIE_MASK (0x1 << TPM_SC_TOIE_SHIFT) + +#define TPM_SC_CPWMS_SHIFT (5) /* Bit[5]: Center-Aligned PWM Select */ +#define TPM_SC_CPWMS_MASK (0x1 << TPM_SC_CPWMS_SHIFT) + +#define TPM_SC_CMOD_SHIFT (3) /* Bit[4:3]: Clock Mode Selection */ +#define TPM_SC_CMOD_MASK (0x3 << TPM_SC_CMOD_SHIFT) + +#define TPM_SC_CMOD_VALUE_DISABLE 0 +#define TPM_SC_CMOD_VALUE_COUNTER 1 +#define TPM_SC_CMOD_VALUE_EXTCLK 2 +#define TPM_SC_CMOD_VALUE_TRIG 3 +#define TPM_SC_CMOD(n) ((n << TPM_SC_CMOD_SHIFT) & TPM_SC_CMOD_MASK) + +#define TPM_SC_PS_SHIFT (0) /* Bit[2:0]: Prescale Factor Selection */ +#define TPM_SC_PS_MASK (0x7 << TPM_SC_PS_SHIFT) + +/* STATUS */ + +#define TPM_STATUS_TOF_SHIFT (8) /* Bit[8]: Timer Overflow Flag */ +#define TPM_STATUS_TOF_MASK (0x1 << TPM_STATUS_TOF_SHIFT) + +#define TPM_STATUS_CH3F_SHIFT (3) /* Bit[3]: Channel 3 Flag */ +#define TPM_STATUS_CH3F_MASK (0x1 << TPM_STATUS_CH3F_SHIFT) + +#define TPM_STATUS_CH2F_SHIFT (2) /* Bit[2]: Channel 2 Flag */ +#define TPM_STATUS_CH2F_MASK (0x1 << TPM_STATUS_CH2F_SHIFT) + +#define TPM_STATUS_CH1F_SHIFT (1) /* Bit[1]: Channel 1 Flag */ +#define TPM_STATUS_CH1F_MASK (0x1 << TPM_STATUS_CH1F_SHIFT) + +#define TPM_STATUS_CH0F_SHIFT (0) /* Bit[0]: Channel 0 Flag */ +#define TPM_STATUS_CH0F_MASK (0x1 << TPM_STATUS_CH0F_SHIFT) + +/* C0SC - C3SC */ + +#define TPM_CXSC_CHF_SHIFT (7) /* Bit[7]: Channel Flag */ +#define TPM_CXSC_CHF_MASK (0x1 << TPM_CXSC_CHF_SHIFT) + +#define TPM_CXSC_CHIE_SHIFT (6) /* Bit[6]: Channel Interrupt Enable */ +#define TPM_CXSC_CHIE_MASK (0x1 << TPM_CXSC_CHIE_SHIFT) + +#define TPM_CXSC_MSB_SHIFT (5) /* Bit[5]: Channel Mode Select B */ +#define TPM_CXSC_MSB_MASK (0x1 << TPM_CXSC_MSB_SHIFT) + +#define TPM_CXSC_MSA_SHIFT (4) /* Bit[4]: Channel Mode Select A */ +#define TPM_CXSC_MSA_MASK (0x1 << TPM_CXSC_MSA_SHIFT) + +#define TPM_CXSC_ELSB_SHIFT (3) /* Bit[3]: Edge or Level Select B */ +#define TPM_CXSC_ELSB_MASK (0x1 << TPM_CXSC_ELSB_SHIFT) + +#define TPM_CXSC_ELSA_SHIFT (2) /* Bit[2]: Edge or Level Select A */ +#define TPM_CXSC_ELSA_MASK (0x1 << TPM_CXSC_ELSA_SHIFT) + +#define TPM_CXSC_DMA_SHIFT (0) /* Bit[0]: DMA Enable */ +#define TPM_CXSC_DMA_MASK (0x1 << TPM_CXSC_DMA_SHIFT) + +/* COMBINE */ + +#define TPM_COMBINE_COMSWAP1_SHIFT (9) /* Bit[9]: Combine Channels 2 and 3 Swap */ +#define TPM_COMBINE_COMSWAP1_MASK (0x1 << TPM_COMBINE_COMSWAP1_SHIFT) + +#define TPM_COMBINE_COMBINE1_SHIFT (8) /* Bit[8]: Combine Channels 2 and 3 */ +#define TPM_COMBINE_COMBINE1_MASK (0x1 << TPM_COMBINE_COMBINE1_SHIFT) + +#define TPM_COMBINE_COMSWAP0_SHIFT (1) /* Bit[1]: Combine Channel 0 and 1 Swap */ +#define TPM_COMBINE_COMSWAP0_MASK (0x1 << TPM_COMBINE_COMSWAP0_SHIFT) + +#define TPM_COMBINE_COMBINE0_SHIFT (0) /* Bit[0]: Combine Channels 0 and 1 */ +#define TPM_COMBINE_COMBINE0_MASK (0x1 << TPM_COMBINE_COMBINE0_SHIFT) + +/* TRIG */ + +#define TPM_TRIG_TRIGX_MASK(ch) (0x1 << (ch)) /* Channel trigger configure */ + +/* POL */ + +#define TPM_POL_POLX_MASK(ch) (0x1 < (ch)) /* Channel polarity active low */ + +/* FILTER */ + +#define TPM_FILTER_CHXFVAL_SHIFT(ch) ((ch) * 4) /* Channel filter value */ +#define TPM_FILTER_CHXFVAL_MASK(ch) (0xf << TPM_FILTER_CHXFVAL_SHIFT(ch)) + +/* QDCTRL */ + +#define TPM_QDCTRL_QUADMODE_SHIFT (3) /* Bit[3]: Quadrature Decoder Mode */ +#define TPM_QDCTRL_QUADMODE_MASK (0x1 << TPM_QDCTRL_QUADMODE_SHIFT) + +#define TPM_QDCTRL_QUADIR_SHIFT (2) /* Bit[2]: Counter Direction */ +#define TPM_QDCTRL_QUADIR_MASK (0x1 << TPM_QDCTRL_QUADIR_SHIFT) + +#define TPM_QDCTRL_TOFDIR_SHIFT (1) /* Bit[1]: Timer Overflow Direction */ +#define TPM_QDCTRL_TOFDIR_MASK (0x1 << TPM_QDCTRL_TOFDIR_SHIFT) + +#define TPM_QDCTRL_QUADEN_SHIFT (0) /* Bit[0]: Quadrature Decoder Enable */ +#define TPM_QDCTRL_QUADEN_MASK (0x1 << TPM_QDCTRL_QUADEN_SHIFT) + +/* CONF */ + +#define TPM_CONF_TRGSEL_SHIFT (24) /* Bit[25:24]: Trigger Select */ +#define TPM_CONF_TRGSEL_MASK (0x3 << TPM_CONF_TRGSEL_SHIFT) + +#define TPM_CONF_TRGSRC_SHIFT (23) /* Bit[23]: Trigger Source select */ +#define TPM_CONF_TRGSRC_MASK (0x1 << TPM_CONF_TRGSRC_SHIFT) + +#define TPM_CONF_TRGPOL_SHIFT (22) /* Bit[22]: Trigger Polarity */ +#define TPM_CONF_TRGPOL_MASK (0x1 << TPM_CONF_TRGPOL_SHIFT) + +#define TPM_CONF_CPOT_SHIFT (19) /* Bit[19]: Counter Pause on Trigger */ +#define TPM_CONF_CPOT_MASK (0x1 << TPM_CONF_CPOT_SHIFT) + +#define TPM_CONF_CROT_SHIFT (18) /* Bit[18]: Counter Reload on Trigger */ +#define TPM_CONF_CROT_MASK (0x1 << TPM_CONF_CROT_SHIFT) + +#define TPM_CONF_CSOO_SHIFT (17) /* Bit[17]: Counter Stop on Overflow */ +#define TPM_CONF_CSOO_MASK (0x1 << TPM_CONF_CSOO_SHIFT) + +#define TPM_CONF_CSOT_SHIFT (16) /* Bit[16]: Counter Start on Trigger */ +#define TPM_CONF_CSOT_MASK (0x1 << TPM_CONF_CSOT_SHIFT) + +#define TPM_CONF_DBGMODE_SHIFT (6) /* Bit[7:6]: Debug Mode */ +#define TPM_CONF_DBGMODE_MASK (0x3 << TPM_CONF_DBGMODE_SHIFT) + +#define TPM_CONF_DOZEEN_SHIFT (5) /* Bit[5]: Doze Enable */ +#define TPM_CONF_DOZEEN_MASK (0x1 << TPM_CONF_DOZEEN_SHIFT) + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H */ diff --git a/arch/arm/src/imx9/hardware/imx9_tstmr.h b/arch/arm/src/imx9/hardware/imx9_tstmr.h new file mode 100644 index 0000000000000..0e011d08273b6 --- /dev/null +++ b/arch/arm/src/imx9/hardware/imx9_tstmr.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/imx9/hardware/imx9_tstmr.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define IMX9_TSTMR_LOW_OFFSET 0x0000 /* Timestamp Timer Low */ +#define IMX9_TSTMR_HIGH_OFFSET 0x0004 /* Timestamp Timer High */ + +/* Register macros */ + +#define IMX9_TSTMR_LOW(n) ((n) + IMX9_TSTMR_LOW_OFFSET) /* Timestamp Timer Low */ +#define IMX9_TSTMR_HIGH(n) ((n) + IMX9_TSTMR_HIGH_OFFSET) /* Timestamp Timer High */ + +/* Field definitions */ + +/* HIGH register */ + +#define IMX9_TSTMR_HIGH_VALUE_SHIFT 0 /* Timestamp Timer High */ +#define IMX9_TSTMR_HIGH_VALUE_MASK 0xffffff /* Timestamp Timer High */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H */ diff --git a/arch/arm/src/imx9/imx9_allocateheap.c b/arch/arm/src/imx9/imx9_allocateheap.c new file mode 100644 index 0000000000000..c39536501d1aa --- /dev/null +++ b/arch/arm/src/imx9/imx9_allocateheap.c @@ -0,0 +1,314 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_allocateheap.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/imx9_memorymap.h" +#include "imx9_mpuinit.h" +#include "mpu.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Primary RAM: The Linker script positions the system BLOB's .data and + * .bss in some RAM. We refer to that RAM as the primary RAM. It also + * holds the IDLE threads stack and any remaining portion of the primary + * OCRAM is automatically added to the heap. The linker provided address, + * ... .sbss, .ebss, .sdat, etc. ... are expected to lie in the the region + * defined by the OCRAM configuration settings. + * + * Other RAM regions must be selected use configuration options and the + * start and end of those RAM regions must also be provided in the + * configuration. CONFIG_MM_REGIONS must also be set to determined the + * number of regions to be added to the heap. + * + * + * IMX9_ITCM_BASE 0x00000000 256KB M7 ITCM + * IMX9_DTCM_BASE 0x20000000 256KB M7 DTCM + * IMX9_OCRAM_BASE 0x20480000 352KB OCRAM + */ + +/* There there then several memory configurations with a one primary memory + * region and up to two additional memory regions which may be OCRAM, DTCM + * external DDR. + */ + +#undef IMX9_OCRAM_ASSIGNED +#undef IMX9_DCTM_ASSIGNED + +#define _IMX9_OCRAM_BASE IMX9_OCRAM_BASE + +/* See linker script */ + +extern const uint32_t _ram_start[]; +extern const uint32_t _ram_size[]; +extern const uint32_t _ocram_start[]; +extern const uint32_t _ocram_size[]; + +/* by default DTCM size is 256k + * Can be configured by AON__BLK_CTRL_Secure_AON.M7_CFG (0x444f0124) + */ + +#define PRIMARY_RAM_START (uint32_t) _ram_start +#define PRIMARY_RAM_SIZE (uint32_t) _ram_size +#define PRIMARY_RAM_END ((uint32_t)_ram_start + (uint32_t)_ram_size) + +#define OCRAM_START (uint32_t) _ocram_start +#define OCRAM_SIZE (uint32_t) _ocram_size + +#if CONFIG_MM_REGIONS > 1 +/* Pick the first region to add to the heap could be any one of OCRAM, DTCM, + * SDRAM, or SRAM depending upon which are enabled and which has not + * already been assigned as the primary RAM. + */ + +#if defined(CONFIG_IMX9_OCRAM_HEAP) && !defined(IMX9_OCRAM_ASSIGNED) +#define REGION1_RAM_START OCRAM_START +#define REGION1_RAM_SIZE OCRAM_SIZE +#define IMX9_OCRAM_ASSIGNED 1 +#else +#warning CONFIG_MM_REGIONS > 1 but no available memory region +#endif + +#define REGION1_RAM_END (REGION1_RAM_START + REGION1_RAM_SIZE) +#endif + +#if CONFIG_MM_REGIONS > 2 +#warning CONFIG_MM_REGIONS > 2 but no available memory region +#endif + +#if CONFIG_MM_REGIONS > 3 +#warning CONFIG_MM_REGIONS > 3 but no available memory region +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS regions (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uintptr_t g_idle_topstack + = (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap/up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * - For the normal "flat" build, this function returns the size of the + * single heap. + * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function + * provides the size of the unprotected, user-space heap. + * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides + * the size of the protected, kernel-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated by an analogous up_allocate_kheap(). A custom version of this + * file is needed if memory protection of the kernel heap is required. + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. (size determined by + * CONFIG_IDLETHREAD_STACKSIZE). + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +void up_allocate_kheap(void **heap_start, size_t *heap_size) +#else +void up_allocate_heap(void **heap_start, size_t *heap_size) +#endif +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase + = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = PRIMARY_RAM_END - ubase; + int log2; + + DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the PRIMARY_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((PRIMARY_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = PRIMARY_RAM_END - usize; + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)ubase; + *heap_size = usize; + + /* Allow user-mode access to the user heap memory */ + + imx9_mpu_uheap((uintptr_t)ubase, usize); +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (void *)g_idle_topstack; + *heap_size = PRIMARY_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * the kernel-space heap. A custom version of this function is needed if + * memory protection of the kernel heap is required. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase + = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = PRIMARY_RAM_END - ubase; + int log2; + DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END); + + /* Adjust that size to account for MPU alignment requirements. + * NOTE that there is an implicit assumption that the CONFIG_RAM_END + * is aligned to the MPU requirement. + */ + + log2 = (int)mpu_log2regionfloor(usize); + DEBUGASSERT((PRIMARY_RAM_END & ((1 << log2) - 1)) == 0); + + usize = (1 << log2); + ubase = PRIMARY_RAM_END - usize; + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: arm_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void arm_addregion(void) +{ + /* Add region 1 to the user heap */ + + kumm_addregion((void *)REGION1_RAM_START, REGION1_RAM_SIZE); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to region 1 */ + + imx9_mpu_uheap((uintptr_t)REGION1_RAM_START, REGION1_RAM_SIZE); +#endif + +#if CONFIG_MM_REGIONS > 2 + /* Add region 2 to the user heap */ + + kumm_addregion((void *)REGION2_RAM_START, REGION2_RAM_SIZE); + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Allow user-mode access to region 2 */ + + imx9_mpu_uheap((uintptr_t)REGION2_RAM_START, REGION2_RAM_SIZE); +#endif +#endif /* CONFIG_MM_REGIONS > 2 */ +} +#endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/imx9/imx9_clockconfig.c b/arch/arm/src/imx9/imx9_clockconfig.c new file mode 100644 index 0000000000000..5036ff165228a --- /dev/null +++ b/arch/arm/src/imx9/imx9_clockconfig.c @@ -0,0 +1,267 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_clockconfig.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "barriers.h" + +#include "arm_internal.h" +#include "hardware/imx9_gpc.h" +#include "imx9_clockconfig.h" +#include "imx9_scmi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The base oscillator frequency is 24MHz */ + +#define XTAL_FREQ 24000000u + +#define ROOT_CLOCK_OFFSET 41 + +/* Common barrier */ + +#define mb() \ + do \ + { \ + ARM_DSB(); \ + ARM_ISB(); \ + } \ + while (0) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_clockconfig + * + * Description: + * Called to initialize the i.IMX9. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void imx9_clockconfig(void) +{ + /* Keep the system clock running so SYSTICK can wake up the system from + * wfi. + */ + + modifyreg32( + IMX9_GPC_CTRL_CMC_MODE_CTRL(IMX9_GPC_CTRL_CM7_BASE), + IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK, + IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET( + IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_STAY_IN_RUN_MODE)); + + modifyreg32(IMX9_GPC_CTRL_CMC_MISC(IMX9_GPC_CTRL_CM7_BASE), + IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG, 0); + + /* Cortex-M33 with SM does PLL initalization */ +} + +#ifdef CONFIG_IMX9_CLK_OVER_SCMI +int imx9_sm_setrootclock(sm_clock_t *sm_clk) +{ + scmi_clock_rate_t rate = /* clang-format off */ + { + 0, 0 + }; /* clang-format on */ + + uint32_t channel = sm_clk->channel; + uint32_t clock_id = sm_clk->clk_id; + uint32_t pclk_id = sm_clk->pclk_id; + uint32_t div = sm_clk->div; + uint32_t attributes = sm_clk->attributes; + uint32_t oem_config_val = sm_clk->oem_config_val; + uint32_t flags = sm_clk->flags; + uint32_t old_pclk_id = 0; /* parent clock id */ + uint64_t src_rate, root_rate; + int32_t status = -1; + + if (div == 0) + { + return -EINVAL; + } + + status = imx9_scmi_clockparentget(channel, clock_id, &old_pclk_id); + if (status != 0) + { + return status; + } + + if (old_pclk_id != pclk_id) + { + status = imx9_scmi_clockparentset(channel, clock_id, pclk_id); + if (status != 0) + { + return status; + } + } + + status = imx9_scmi_clockrateget(channel, pclk_id, &rate); + if (status != 0) + { + return status; + } + + src_rate = rate.upper; + src_rate = (src_rate << 32); + src_rate |= rate.lower; + + root_rate = src_rate / div; + + rate.lower = root_rate & SM_CLOCK_RATE_MASK; + rate.upper = (root_rate >> 32) & SM_CLOCK_RATE_MASK; + + status = imx9_scmi_clockrateset(channel, clock_id, flags, rate); + if (status != 0) + { + return status; + } + + status = imx9_scmi_clockconfigset(channel, clock_id, attributes, + oem_config_val); + if (status != 0) + { + return status; + } + + return OK; +} + +int imx9_sm_getipfreq(sm_clock_t *sm_clk) +{ + scmi_clock_rate_t rate = /* clang-format off */ + { + 0, 0 + }; /* clang-format on */ + + uint32_t channel = sm_clk->channel; + uint32_t clock_id = sm_clk->clk_id; + uint32_t pclk_id = sm_clk->pclk_id; + int status = 0; + + status = imx9_scmi_clockparentget(channel, clock_id, &pclk_id); + if (status < 0) + { + return status; + } + + status = imx9_scmi_clockrateget(channel, clock_id, &rate); + if (status < 0) + { + return status; + } + + return rate.lower; +} +#endif + +int imx9_configure_clock(clock_config_t clk_config, bool enabled) +{ + sm_clock_t sm_clk = /* clang-format off */ + { + 0 + }; /* clang-format on */ + + sm_clk.clk_id = GET_CLOCK_ROOT(clk_config) + ROOT_CLOCK_OFFSET; + sm_clk.pclk_id = GET_CLOCK_ID(clk_config); + sm_clk.channel = SM_PLATFORM_A2P; + sm_clk.div = GET_CLOCK_DIV(clk_config); + + if (sm_clk.div == 0) + { + /* Make sure div is always 1 */ + + sm_clk.div = 1; + } + + sm_clk.attributes = SCMI_CLOCK_CONFIG_SET_ENABLE(enabled); + sm_clk.flags = SCMI_CLOCK_RATE_FLAGS_ROUND(SCMI_CLOCK_ROUND_AUTO); + + return imx9_sm_setrootclock(&sm_clk); +} + +/**************************************************************************** + * Name: imx9_get_rootclock + * + * Description: + * This function returns the clock frequency of the specified root + * functional clock. + * + * Input Parameters: + * clkroot - Identifies the peripheral clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +int imx9_get_rootclock(int clkroot, uint32_t *frequency) +{ + if (clkroot <= CCM_CR_COUNT) + { + uint32_t ret = 0; + + sm_clock_t sm_clk = /* clang-format off */ + { + 0 + }; /* clang-format on */ + + sm_clk.clk_id = (uint32_t)(clkroot + ROOT_CLOCK_OFFSET); + sm_clk.channel = SM_PLATFORM_A2P; + + ret = imx9_sm_getipfreq(&sm_clk); + + if (ret < 0) + { + return -ENODEV; + } + else + { + *frequency = ret; + return OK; + } + } + + return -ENODEV; +} diff --git a/arch/arm/src/imx9/imx9_clockconfig.h b/arch/arm/src/imx9/imx9_clockconfig.h new file mode 100644 index 0000000000000..9389095a9a25a --- /dev/null +++ b/arch/arm/src/imx9/imx9_clockconfig.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_clockconfig.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "hardware/imx9_clock.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_clockconfig + * + * Description: + * Called to initialize the i.IMX9. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void imx9_clockconfig(void); + +int imx9_configure_clock(clock_config_t clk_config, bool enabled); + +/**************************************************************************** + * Name: imx9_get_rootclock + * + * Description: + * This function returns the clock frequency of the specified root + * functional clock. + * + * Input Parameters: + * clkroot - Identifies the peripheral clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +int imx9_get_rootclock(int clkroot, uint32_t *frequency); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H */ diff --git a/arch/arm/src/imx9/imx9_edma.c b/arch/arm/src/imx9/imx9_edma.c new file mode 100644 index 0000000000000..e37c00abbce64 --- /dev/null +++ b/arch/arm/src/imx9/imx9_edma.c @@ -0,0 +1,1622 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_edma.c + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2024 NXP + * SPDX-FileCopyrightText: 2019, 2021, 2023 Gregory Nutt. + * SPDX-FileCopyrightText: 2022 NXP + * SPDX-FileCopyrightText: 2016-2017 NXP + * SPDX-FileCopyrightText: 2015, Freescale Semiconductor, Inc. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: David Sidrane + * SPDX-FileContributor: Peter van der Perk + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "sched/sched.h" + +#include "chip.h" +#include "imx9_edma.h" + +#include "hardware/imx9_edma.h" +#include "hardware/imx9_dmamux.h" + +#ifdef CONFIG_IMX9_EDMA + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TCD Alignment. + * + * eDMA TCDs must be aligned with the D-Cache line boundaries to facilitate + * cache operations on the TCDs when the D-Cache is enabled. + * + * NOTE: The TCDs are 32-bytes in length. We implicitly assume that the + * D-Cache line size is also 32-bits. Otherwise, padding would be required + * at the ends of the TCDS and buffers to protect data after the end of from + * invalidation. + */ + +#define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE +#define EDMA_ALIGN_MASK (EDMA_ALIGN - 1) +#define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK) + +#define DTCM_BACKDOOR_OFFSET 0x400000 + +extern uint8_t _ram_start[]; +extern uint8_t _ram_end[]; + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* State of a DMA channel */ + +enum imx9_dmastate_e +{ + IMX9_DMA_IDLE = 0, /* No DMA in progress */ + IMX9_DMA_CONFIGURED, /* DMA configured, but not yet started */ + IMX9_DMA_ACTIVE /* DMA has been started and is in progress */ +}; + +/* This structure describes one DMA channel */ + +struct imx9_dmach_s +{ + uintptr_t base; /* DMA engine base address */ + uint32_t flags; /* DMA channel flags */ + bool inuse; /* true: The DMA channel is in use */ + uint8_t dmamux; /* DMAMUX channel number */ + uint8_t chan; /* DMA channel number (either eDMA3 or eDMA4) */ + uint8_t state; /* Channel state. See enum imx9_dmastate_e */ + edma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* That TCD list is linked through the DLAST SGA field. The first transfer + * to be performed is at the head of the list. Subsequent TCDs are added + * at the tail of the list. + */ + + struct imx9_edmatcd_s *head; /* First TCD in the list */ + struct imx9_edmatcd_s *tail; /* Last TCD in the list */ +#endif +}; + +/* This structure describes the state of the eDMA controller */ + +struct imx9_edma_s +{ + /* These mutex protect the DMA channel and descriptor tables */ + + mutex_t chlock; /* Protects channel table */ +#if CONFIG_IMX9_EDMA_NTCD > 0 + sem_t dsem; /* Supports wait for free descriptors */ +#endif + + /* This array describes each DMA channel */ + + struct imx9_dmach_s dmach[IMX9_EDMA_NCHANNELS]; + spinlock_t lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The state of the eDMA */ + +static struct imx9_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_IMX9_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_IMX9_EDMA_NTCD), +#endif + .lock = SP_UNLOCKED +}; + +#if CONFIG_IMX9_EDMA_NTCD > 0 +/* This is a singly-linked list of free TCDs */ + +static sq_queue_t g_tcd_free; + +/* This is a pool of pre-allocated TCDs */ + +static struct imx9_edmatcd_s g_tcd_pool[CONFIG_IMX9_EDMA_NTCD] + aligned_data(EDMA_ALIGN); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_tcd_alloc + * + * Description: + * Allocate an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static struct imx9_edmatcd_s *imx9_tcd_alloc(void) +{ + struct imx9_edmatcd_s *tcd; + irqstate_t flags; + + /* Take the 'dsem'. When we hold the the 'dsem', then we know that one + * TCD is reserved for us in the free list. + * + * NOTE: We use a critical section here because we may block waiting for + * the 'dsem'. The critical section will be suspended while we are + * waiting. + */ + + nxsem_wait_uninterruptible(&g_edma.dsem); + + /* Now there should be a TCD in the free list reserved just for us */ + + flags = spin_lock_irqsave(&g_edma.lock); + tcd = (struct imx9_edmatcd_s *)sq_remfirst(&g_tcd_free); + DEBUGASSERT(tcd != NULL); + + spin_unlock_irqrestore(&g_edma.lock, flags); + return tcd; +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_free + * + * Description: + * Free an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static void imx9_tcd_free_nolock(struct imx9_edmatcd_s *tcd) +{ + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); +} + +static void imx9_tcd_free(struct imx9_edmatcd_s *tcd) +{ + irqstate_t flags; + + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + imx9_tcd_free_nolock(tcd); + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_initialize() + * + * Description: + * Initialize the TCD free list from the pool of pre-allocated TCDs. + * + * Assumptions: + * Called early in the initialization sequence so no special protection is + * necessary. + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static inline void imx9_tcd_initialize(void) +{ + sq_entry_t *tcd; + int i; + + /* Add each pre-allocated TCD to the tail of the TCD free list */ + + sq_init(&g_tcd_free); + for (i = 0; i < CONFIG_IMX9_EDMA_NTCD; i++) + { + tcd = (sq_entry_t *)&g_tcd_pool[i]; + sq_addlast(tcd, &g_tcd_free); + } +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_chanlink + * + * Description: + * This function configures either a minor link or a major link. The minor + * link means the channel link is triggered every time CITER decreases by 1 + * The major link means that the channel link is triggered when the CITER + * is exhausted. + * + * NOTE: Users should ensure that DONE flag is cleared before calling this + * interface, or the configuration is invalid. + * + * Input Parameters: + * tcd - Point to the TCD structure. + * type - Channel link type. + * chan - The linked channel number. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_EDMA_ELINK +static inline void imx9_tcd_chanlink(uint8_t flags, + struct imx9_dmach_s *linkch, + struct imx9_edmatcd_s *tcd) +{ + uint16_t regval16; + + flags &= EDMA_CONFIG_LINKTYPE_MASK; + + if (linkch == NULL || flags == EDMA_CONFIG_LINKTYPE_LINKNONE) + { + /* No link or no link channel provided */ + + /* Disable minor links */ + + /* Disable major link */ + + tcd->csr &= ~EDMA_TCD_CSR_MAJORELINK; + } + else if (flags == EDMA_CONFIG_LINKTYPE_MINORLINK) /* Minor link config */ + { + /* Enable minor link */ + + tcd->citer |= EDMA_TCD_CITER_ELINK; + tcd->biter |= EDMA_TCD_BITER_ELINK; + + /* Set linked channel */ + + regval16 = tcd->citer; + regval16 &= ~EDMA_TCD_CITER_LINKCH_MASK; + regval16 |= EDMA_TCD_CITER_LINKCH(linkch->chan); + tcd->citer = regval16; + + regval16 = tcd->biter; + regval16 &= ~EDMA_TCD_BITER_LINKCH_MASK; + regval16 |= EDMA_TCD_BITER_LINKCH(linkch->chan); + tcd->biter = regval16; + } + else /* if (flags == EDMA_CONFIG_LINKTYPE_MAJORLINK) Major link config */ + { + /* Enable major link */ + + regval16 = tcd->csr; + regval16 |= EDMA_TCD_CSR_MAJORELINK; + tcd->csr = regval16; + + /* Set major linked channel */ + + regval16 &= ~EDMA_TCD_CSR_MAJORLINKCH_MASK; + regval16 |= EDMA_TCD_CSR_MAJORLINKCH(linkch->chan); + tcd->csr = regval16; + } +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_configure + * + * Description: + * Configure all TCD registers to the specified values. 'tcd' is an + * 'overlay' that may refer either to either the TCD register set or to an + * in-memory TCD structure. + * + ****************************************************************************/ + +static inline void imx9_tcd_configure(struct imx9_edmatcd_s *tcd, + const struct imx9_edma_xfrconfig_s *config) +{ + tcd->saddr = config->saddr; + tcd->soff = config->soff; + tcd->attr = EDMA_TCD_ATTR_SSIZE(config->ssize) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DSIZE(config->dsize); +#ifdef CONFIG_IMX9_EDMA_MOD + tcd->attr |= EDMA_TCD_ATTR_SMOD(config->smod) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DMOD(config->dmod); +#endif + tcd->nbytes = config->nbytes; + tcd->slast = config->flags & EDMA_CONFIG_LOOPSRC ? + -(config->iter * config->nbytes) : 0; + + tcd->daddr = config->daddr; + tcd->doff = config->doff; + tcd->citer = config->iter & EDMA_TCD_CITER_MASK; + tcd->biter = config->iter & EDMA_TCD_BITER_MASK; + tcd->csr = config->flags & EDMA_CONFIG_LOOP_MASK ? + 0 : EDMA_TCD_CSR_DREQ; + tcd->csr |= config->flags & EDMA_CONFIG_INTHALF ? + EDMA_TCD_CSR_INTHALF : 0; + tcd->dlastsga = config->flags & EDMA_CONFIG_LOOPDEST ? + -(config->iter * config->nbytes) : 0; + +#ifdef CONFIG_ARCH_CHIP_IMX95_M7 + /* Remap address to backdoor address for eDMA */ + + if (tcd->saddr >= (uint32_t)_ram_start && + tcd->saddr < (uint32_t)_ram_end) + { + tcd->saddr += DTCM_BACKDOOR_OFFSET; + } + + if (tcd->daddr >= (uint32_t)_ram_start && + tcd->daddr < (uint32_t)_ram_end) + { + tcd->daddr += DTCM_BACKDOOR_OFFSET; + } +#endif + + /* And special case flags */ + +#ifdef CONFIG_IMX9_EDMA_ELINK + /* Configure major/minor link mapping */ + + imx9_tcd_chanlink(config->flags, (struct imx9_dmach_s *)config->linkch, + tcd); +#endif +} + +/**************************************************************************** + * Name: imx9_tcd_instantiate + * + * Description: + * Copy an in-memory TCD into eDMA channel TCD registers + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static void imx9_tcd_instantiate(struct imx9_dmach_s *dmach, + const struct imx9_edmatcd_s *tcd) +{ + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + /* Push tcd into hardware TCD register */ + + /* Clear DONE bit first, otherwise ESG cannot be set */ + + putreg16(0, base + IMX9_EDMA_TCD_CSR_OFFSET); + + putreg32(tcd->saddr, base + IMX9_EDMA_TCD_SADDR_OFFSET); + putreg16(tcd->soff, base + IMX9_EDMA_TCD_SOFF_OFFSET); + putreg16(tcd->attr, base + IMX9_EDMA_TCD_ATTR_OFFSET); + putreg32(tcd->nbytes, base + IMX9_EDMA_TCD_NBYTES_OFFSET); + putreg32(tcd->slast, base + IMX9_EDMA_TCD_SLAST_SDA_OFFSET); + putreg32(tcd->daddr, base + IMX9_EDMA_TCD_DADDR_OFFSET); + putreg16(tcd->doff, base + IMX9_EDMA_TCD_DOFF_OFFSET); + putreg16(tcd->citer, base + IMX9_EDMA_TCD_CITER_OFFSET); + putreg32(tcd->dlastsga, base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + + putreg16(tcd->csr, base + IMX9_EDMA_TCD_CSR_OFFSET); + + putreg16(tcd->biter, base + IMX9_EDMA_TCD_BITER_OFFSET); +} +#endif + +/**************************************************************************** + * Name: imx9_dmaterminate + * + * Description: + * Terminate the DMA transfer and disable the DMA channel + * + ****************************************************************************/ + +static void imx9_dmaterminate(struct imx9_dmach_s *dmach, int result) +{ + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); +#if CONFIG_IMX9_EDMA_NTCD > 0 + struct imx9_edmatcd_s *tcd; + struct imx9_edmatcd_s *next; +#endif + edma_callback_t callback; + void *arg; + + irqstate_t flags; + + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + + /* Disable channel IRQ requests */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Clear CSR to disable channel. Because if the given channel started, + * transfer CSR will be not zero. Because if it is the last transfer, DREQ + * will be set. If not, ESG will be set. + */ + + putreg32(0, base + IMX9_EDMA_CH_CSR_OFFSET); + + putreg16(0, base + IMX9_EDMA_TCD_CSR_OFFSET); + + /* Cancel next TCD transfer. */ + + putreg32(0, base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Return all allocated TCDs to the free list */ + + for (tcd = dmach->head; tcd != NULL; tcd = next) + { + /* If channel looped to itself we are done + * if not continue to free tcds in chain + */ + + next = dmach->flags & EDMA_CONFIG_LOOPDEST ? + NULL : (struct imx9_edmatcd_s *)((uintptr_t)tcd->dlastsga); + + imx9_tcd_free_nolock(tcd); + } + + dmach->head = NULL; + dmach->tail = NULL; +#endif + + /* Perform the DMA complete callback */ + + callback = dmach->callback; + arg = dmach->arg; + + dmach->callback = NULL; + dmach->arg = NULL; + dmach->state = IMX9_DMA_IDLE; + + if (callback) + { + callback((DMACH_HANDLE)dmach, arg, true, result); + } + + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); +} + +/**************************************************************************** + * Name: imx9_edma_intstatus + * + * Description: + * DMA interrupt status per eDMA engine and channel. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_intstatus(uintptr_t base, uint8_t chan) +{ + /* The status register varies depending on eDMA instance and channel */ + +#ifdef IMX9_DMA3_BASE + /* eDMA3 uses the normal INT register */ + + if (base == IMX9_DMA3_BASE) + { + return getreg32(IMX9_EDMA_INT); + } +#endif + +#if defined(IMX9_DMA4_BASE) || defined(IMX9_EDMA5_2_BASE) + /* eDMA4/5 has two INT status registers, holding 32 statuses each */ + + if (chan > 31) + { + return getreg32(IMX9_EDMA_INT_HIGH); + } + + return getreg32(IMX9_EDMA_INT_LOW); +#endif +} + +/**************************************************************************** + * Name: imx9_edma_isr + * + * Description: + * DMA interrupt service routine. The vector handler calls this with the + * appropriate parameters. + * + ****************************************************************************/ + +static int imx9_edma_isr(int irq, void *context, void *arg) +{ + struct imx9_dmach_s *dmach; + uintptr_t base; + uint32_t regval32; + uint32_t errval32; + uint8_t chan; + int result; + + /* 'arg' should the DMA channel instance. */ + + dmach = (struct imx9_dmach_s *)arg; + DEBUGASSERT(dmach != NULL); + + chan = dmach->chan; + base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + /* Get the eDMA Error Status register value. */ + + errval32 = getreg32(base + IMX9_EDMA_CH_ES_OFFSET); + + if (errval32 & EDMA_CH_ES_ERR) + { + DEBUGASSERT(dmach->state == IMX9_DMA_ACTIVE); + + /* Clear the error */ + + putreg32(EDMA_CH_ES_ERR, base + IMX9_EDMA_CH_ES_OFFSET); + + /* Clear the pending eDMA channel interrupt */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + imx9_dmaterminate(dmach, -EIO); + return OK; + } + + /* Check for an eDMA pending interrupt on this channel */ + + regval32 = imx9_edma_intstatus(dmach->base, dmach->chan); + if ((regval32 & EDMA_INT(chan % 31)) != 0) + { + /* An interrupt is pending. + * This should only happen if the channel is active. + */ + + DEBUGASSERT(dmach->state == IMX9_DMA_ACTIVE); + + /* Clear the pending eDMA channel interrupt */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Get the eDMA TCD Control and Status register value. */ + + regval32 = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + + /* Check if transfer has finished. */ + + if ((regval32 & EDMA_CH_CSR_DONE) != 0) + { + /* Clear the pending DONE interrupt status. */ + + regval32 |= EDMA_CH_CSR_DONE; + putreg32(regval32, base + IMX9_EDMA_CH_CSR_OFFSET); + result = OK; + } + else + { + /* Perform the half or end-of-major-cycle DMA callback */ + + if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, false, OK); + } + + return OK; + } + + /* Terminate the transfer when it is done. */ + + if ((dmach->flags & EDMA_CONFIG_LOOP_MASK) == 0) + { + imx9_dmaterminate(dmach, result); + } + else if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, true, result); + } + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_edma_interrupt + * + * Description: + * DMA interrupt handler. This function clears the channel major + * interrupt flag and calls the callback function if it is not NULL. + * + * NOTE: For the case using TCD queue, when the major iteration count is + * exhausted, additional operations are performed. These include the + * final address adjustments and reloading of the BITER field into the + * CITER. Assertion of an optional interrupt request also occurs at this + * time, as does a possible fetch of a new TCD from memory using the + * scatter/gather address pointer included in the descriptor (if scatter/ + * gather is enabled). + * + ****************************************************************************/ + +static int imx9_edma_interrupt(int irq, void *context, void *arg) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)arg; + +#ifdef IMX9_DMA3_BASE + if ((irq >= IMX9_IRQ_DMA3_0) && (irq <= IMX9_IRQ_DMA3_30)) + { + /* eDMA3 interrupt has a single source */ + + imx9_edma_isr(irq, context, dmach); + } +#endif + +#ifdef IMX9_DMA4_BASE + if ((irq >= IMX9_IRQ_DMA4_0_1) && (irq <= IMX9_IRQ_DMA4_62_63)) + { + /* eDMA4 interrupt has two sources */ + + imx9_edma_isr(irq, context, dmach); + imx9_edma_isr(irq, context, dmach + 1); + } +#endif + +#ifdef IMX9_EDMA5_2_BASE + if ((irq >= IMX9_IRQ_DMA5_2_0_1) && (irq <= IMX9_IRQ_DMA5_2_62_63)) + { + /* eDMA4 interrupt has two sources */ + + imx9_edma_isr(irq, context, dmach); + imx9_edma_isr(irq, context, dmach + 1); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: imx9_edma_configure + * + * Description: + * Configure eDMA instance. + * + ****************************************************************************/ + +static void imx9_edma_configure(uintptr_t base) +{ + uint32_t regval; + + /* Configure the eDMA controllers */ + + regval = getreg32(IMX9_EDMA_CSR(base)); + regval &= ~(EDMA_CSR_EDBG | EDMA_CSR_ERCA | EDMA_CSR_HAE | EDMA_CSR_GCLC | + EDMA_CSR_GMRC); + +#ifdef CONFIG_IMX9_EDMA_EDBG + regval |= EDMA_CSR_EDBG; /* Enable Debug */ +#endif +#ifdef CONFIG_IMX9_EDMA_ERCA + regval |= EDMA_CSR_ERCA; /* Enable Round Robin Channel Arbitration */ +#endif +#ifdef CONFIG_IMX9_EDMA_ERGA + regval |= EDMA_CSR_ERGA; /* Enable Round Robin Group Arbitration */ +#endif +#ifdef CONFIG_IMX9_EDMA_HOE + regval |= EDMA_CSR_HAE; /* Halt On Error */ +#endif +#ifdef CONFIG_IMX9_EDMA_CLM + regval |= EDMA_CSR_GCLC; /* Continuous Link Mode / Global Channel Linking Control */ +#endif +#ifdef CONFIG_IMX9_EDMA_EMLIM + regval |= EDMA_CSR_GMRC; /* Enable Minor Loop Mapping / Global Master ID Replication Control */ +#endif + + putreg32(regval, IMX9_EDMA_CSR(base)); +} + +/**************************************************************************** + * Name: imx9_find_free_ch + * + * Description: + * Configure eDMA instance. + * + ****************************************************************************/ + +static struct imx9_dmach_s * imx9_find_free_ch(uint16_t dmamux) +{ + struct imx9_dmach_s *candidate; + uintptr_t base; + unsigned int chndx; + + /* eDMA base for MUX */ + + base = imx9_dmamux_get_dmabase(dmamux); + +#ifdef IMX9_DMA3_BASE + /* For eDMA3 the channel must match the MUX number */ + + if (base == IMX9_DMA3_BASE) + { + chndx = dmamux & EDMA_MUX_MASK; + candidate = &g_edma.dmach[chndx]; + if (!candidate->inuse) + { + return candidate; + } + } +#endif + +#if defined(IMX9_DMA4_BASE) || defined(IMX9_EDMA5_2_BASE) + /* For eDMA4/5 any free channel is good */ + +#if defined(IMX9_DMA4_BASE + if (base == IMX9_DMA4_BASE) +#else + if (base == IMX9_EDMA5_2_BASE) +#endif + { + unsigned int offset; + unsigned int max; + + /* Iterate relevant channel range from the global LUT */ + + offset = imx9_edma_choffset(base); + max = imx9_edma_chmax(base); + + for (chndx = offset; chndx < max; chndx++) + { + candidate = &g_edma.dmach[chndx]; + if (!candidate->inuse) + { + return candidate; + } + } + } +#endif + + return NULL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dma_initialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm_dma_initialize(void) +{ + struct imx9_dmach_s *dmach; + uintptr_t base; + int chan; + int i; + + dmainfo("Initialize eDMA\n"); + + /* Enable root clock */ + +#ifdef CCM_CR_WAKEUPAXI + imx9_ccm_configure_root_clock(CCM_CR_WAKEUPAXI, SYS_PLL1PFD0, 4); +#endif + + /* Configure the instances */ + + dmach = &g_edma.dmach[0]; + +#ifdef IMX9_DMA3_BASE + /* Enable peripheral clock */ + +#ifdef CCM_LPCG_EDMA3 + imx9_ccm_gate_on(CCM_LPCG_EDMA3, true); +#endif + + imx9_edma_configure(IMX9_DMA3_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA3_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMX9_DMA3_BASE; + dmach->chan = i; + + irq_attach(IMX9_IRQ_DMA3_0 + i, imx9_edma_interrupt, dmach); + } +#endif + +#ifdef IMX9_DMA4_BASE + /* Enable peripheral clock */ + +#ifdef CCM_LPCG_EDMA4 + imx9_ccm_gate_on(CCM_LPCG_EDMA4, true); +#endif + + imx9_edma_configure(IMX9_DMA4_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA4_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMX9_DMA4_BASE; + dmach->chan = i; + + /* Attach interrupt for every second channel */ + + if ((i & 0x01) == 0) + { + irq_attach(IMX9_IRQ_DMA4_0_1 + (i >> 1), imx9_edma_interrupt, + dmach); + } + } +#endif + +#ifdef IMX9_EDMA5_2_BASE + /* Enable peripheral clock */ + + imx9_edma_configure(IMX9_EDMA5_2_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA4_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMX9_EDMA5_2_BASE; + dmach->chan = i; + + /* Attach interrupt for every second channel */ + + if ((i & 0x01) == 0) + { + irq_attach(IMX9_IRQ_DMA5_2_0_1 + (i >> 1), imx9_edma_interrupt, + dmach); + } + } +#endif + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ + + imx9_tcd_initialize(); +#endif + + /* Disable all DMA channel interrupts at the eDMA controller */ + + for (i = 0; i < IMX9_EDMA_NCHANNELS; i++) + { + /* DMA engine base and TCD channel */ + + if (g_edma.dmach[i].base == 0) + { + dmaerr("ERROR: Channel %i base is null\n", i); + continue; + } + + base = g_edma.dmach[i].base; + chan = g_edma.dmach[i].chan; + + /* Disable all DMA channels and DMA channel interrupts */ + + putreg32(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_CH_CSR_OFFSET); + + /* Clear interrupt if any */ + + putreg32(1, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_CH_INT_OFFSET); + + /* Set all TCD CSR, biter and citer entries to 0 so that + * will be 0 when DONE is not set so that imx9_dmach_getcount + * reports 0. + */ + + putreg16(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_TCD_CSR_OFFSET); + putreg16(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_TCD_CITER_OFFSET); + putreg16(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_TCD_BITER_OFFSET); + } + +#ifdef IMX9_DMA3_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMX9_EDMA_INT); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA3_IRQ_COUNT; i++) + { + up_enable_irq(IMX9_IRQ_DMA3_0 + i); + } +#endif + +#ifdef IMX9_DMA4_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMX9_EDMA_INT_LOW); + putreg32(0xffffffff, IMX9_EDMA_INT_HIGH); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA4_IRQ_COUNT; i++) + { + up_enable_irq(IMX9_IRQ_DMA4_0_1 + i); + } +#endif + +#ifdef IMX9_EDMA5_2_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMX9_EDMA_INT_LOW); + putreg32(0xffffffff, IMX9_EDMA_INT_HIGH); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA4_IRQ_COUNT; i++) + { + up_enable_irq(IMX9_IRQ_DMA5_2_0_1 + i); + } +#endif +} + +/**************************************************************************** + * Name: imx9_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/imx9_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/imx9_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE imx9_dmach_alloc(uint16_t dmamux, uint8_t dchpri) +{ + struct imx9_dmach_s *dmach; + uintptr_t base; + int ret; + + /* Search for an available DMA channel */ + + dmach = NULL; + ret = nxmutex_lock(&g_edma.chlock); + if (ret < 0) + { + return NULL; + } + + /* Find channel for this DMA MUX */ + + dmach = imx9_find_free_ch(dmamux); + if (dmach) + { + dmach->inuse = true; + dmach->state = IMX9_DMA_IDLE; + dmach->dmamux = dmamux & EDMA_MUX_MASK; + + /* TCD register base */ + + base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + /* Clear any pending interrupts on the channel */ + + putreg32(0, base + IMX9_EDMA_CH_CSR_OFFSET); + + /* Make sure that the channel is disabled. */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Set the DMAMUX source */ + + if (imx9_edma_tcdhasmux(dmach->base)) + { + /* Set reset value first to CH MUX */ +#ifdef CONFIG_ARCH_CHIP_IMX95_M7 + putreg8(0, dmach->base + IMX9_EDMA_MP_CH_MUX_OFFSET(dmach->chan)); + dmainfo("CH%d: MUX:%u->%p\n", dmach->chan, dmach->dmamux, + (void *)(dmach->base + + IMX9_EDMA_MP_CH_MUX_OFFSET(dmach->chan))); + putreg8(dmach->dmamux, + dmach->base + IMX9_EDMA_MP_CH_MUX_OFFSET(dmach->chan)); +#else + putreg8(0, base + IMX9_EDMA_CH_MUX_OFFSET); + dmainfo("CH%d: MUX:%u->%p\n", dmach->chan, dmach->dmamux, + (void *)(base + IMX9_EDMA_CH_MUX_OFFSET)); + putreg8(dmach->dmamux, base + IMX9_EDMA_CH_MUX_OFFSET); +#endif + } + } + + nxmutex_unlock(&g_edma.chlock); + + /* Show the result of the allocation */ + + if (dmach != NULL) + { + dmainfo("CH%d: returning dmach: %p\n", dmach->chan, dmach); + } + else + { + dmaerr("ERROR: Failed allocate eDMA channel\n"); + } + + return (DMACH_HANDLE)dmach; +} + +/**************************************************************************** + * Name: imx9_dmach_free + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until imx9_dmach_alloc() is called again to + * re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_dmach_free(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL && dmach->inuse && + dmach->state != IMX9_DMA_ACTIVE); + + /* Mark the channel no longer in use. Clearing the inuse flag is an atomic + * operation and so should be safe. + */ + + dmach->flags = 0; + dmach->inuse = false; /* No longer in use */ + dmach->state = IMX9_DMA_IDLE; /* Better not be active! */ + + /* Make sure that the channel is disabled. */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Disable the associated DMAMUX */ + + if (imx9_edma_tcdhasmux(dmach->base)) + { + putreg8(0, base + IMX9_EDMA_CH_MUX_OFFSET); + } +} + +/**************************************************************************** + * Name: imx9_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, imx9_dmach_xfrsetup is called only once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_xfrsetup(DMACH_HANDLE handle, + const struct imx9_edma_xfrconfig_s *config) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); +#if CONFIG_IMX9_EDMA_NTCD > 0 + struct imx9_edmatcd_s *tcd; + struct imx9_edmatcd_s *prev; + uint16_t mask = config->flags & EDMA_CONFIG_INTMAJOR ? 0 : + EDMA_TCD_CSR_INTMAJOR; + uint16_t regval16; +#else + uint32_t regval32; +#endif + + DEBUGASSERT(dmach != NULL); + dmainfo("dmach%u: %p config: %p\n", dmach->chan, dmach, config); + + dmach->flags = config->flags; + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Scatter/gather DMA is supported */ + + /* Allocate a TCD, waiting if necessary */ + + tcd = imx9_tcd_alloc(); + + /* Configure current TCD block transfer. */ + + imx9_tcd_configure(tcd, config); + + /* Enable the interrupt when the major iteration count completes for this + * TCD. For "normal" DMAs, this will correspond to the DMA DONE + * interrupt; for scatter gather DMAs, multiple interrupts will be + * generated with the final being the DONE interrupt. + */ + + tcd->csr |= EDMA_TCD_CSR_INTMAJOR; + + /* Is this the first descriptor in the list? */ + + if (dmach->head == NULL) + { + /* Yes.. add it to the list */ + + dmach->head = tcd; + dmach->tail = tcd; + + /* And instantiate the first TCD in the DMA channel TCD registers. */ + + imx9_tcd_instantiate(dmach, tcd); + } + else + { + /* Cannot mix transfer types */ + + if (dmach->flags & EDMA_CONFIG_LOOP_MASK) + { + imx9_tcd_free(tcd); + return -EINVAL; + } + + /* Chain from previous descriptor in the list. */ + + /* Enable scatter/gather feature in the previous TCD. */ + + prev = dmach->tail; + regval16 = prev->csr; + regval16 &= ~(EDMA_TCD_CSR_DREQ | mask); + regval16 |= EDMA_TCD_CSR_ESG; + prev->csr = regval16; + + prev->dlastsga = (uint32_t)((uintptr_t)tcd); + dmach->tail = tcd; + + /* Clean cache associated with the previous TCD memory */ + + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct imx9_edmatcd_s)); + + /* Check if the TCD block in the DMA channel registers is the same as + * the previous previous TCD. This can happen if the previous TCD was + * the first TCD and has already be loaded into the TCD registers. + */ + + if (dmach->head == prev) + { + /* Enable scatter/gather also in the TCD registers. */ + + regval16 = getreg16(base + IMX9_EDMA_TCD_CSR_OFFSET); + regval16 &= ~(EDMA_TCD_CSR_DREQ | mask); + regval16 |= EDMA_TCD_CSR_ESG; + putreg16(regval16, base + IMX9_EDMA_TCD_CSR_OFFSET); + + putreg32((uint32_t)((uintptr_t)tcd), + base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + } + } + + /* Clean cache associated with the TCD memory */ + + up_clean_dcache((uintptr_t)tcd, + (uintptr_t)tcd + sizeof(struct imx9_edmatcd_s)); +#else + + /* Scatter/gather DMA is NOT supported */ + + /* Check if eDMA is busy: if the channel has started transfer, CSR will be + * non-zero. + */ + + regval32 = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + + if (regval32 != 0 && (regval32 & EDMA_CH_CSR_DONE) == 0) + { + return -EBUSY; + } + + /* Configure channel TCD registers to the values specified in config. */ + + imx9_tcd_configure((struct imx9_edmatcd_s *) + (base + IMX9_EDMA_TCD_SADDR_OFFSET), config); + + /* Enable the DONE interrupt when the major iteration count completes. */ + + modifyreg16(base + IMX9_EDMA_TCD_CSR_OFFSET, 0, EDMA_TCD_CSR_INTMAJOR); +#endif + + dmach->state = IMX9_DMA_CONFIGURED; + return OK; +} + +/**************************************************************************** + * Name: imx9_dmach_start + * + * Description: + * Start the DMA transfer. This function should be called after the final + * call to imx9_dmach_xfrsetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the user + * provided function is made: |For "normal" DMAs, this will correspond to + * the DMA DONE interrupt; for scatter gather DMAs, + * this will be generated with the final TCD. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is + * necessary to invalidate the destination memory. That is not done + * automatically by the DMA module. Invalidation of the destination memory + * regions is the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, + void *arg) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + irqstate_t flags; + uint32_t regval; + uint8_t chan; + + DEBUGASSERT(dmach != NULL && dmach->state == IMX9_DMA_CONFIGURED); + chan = dmach->chan; + dmainfo("dmach%u: %p callback: %p arg: %p\n", chan, dmach, callback, arg); + + /* Save the callback info. This will be invoked when the DMA completes */ + + flags = spin_lock_irqsave(&g_edma.lock); + dmach->callback = callback; + dmach->arg = arg; + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Although it is not recommended, it might be possible to call this + * function multiple times while adding TCDs on the fly. + */ + + if (dmach->state != IMX9_DMA_ACTIVE) +#endif + { + dmach->state = IMX9_DMA_ACTIVE; + + regval = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + regval |= EDMA_CH_CSR_ERQ | EDMA_CH_CSR_EEI; + putreg32(regval, base + IMX9_EDMA_CH_CSR_OFFSET); + } + + spin_unlock_irqrestore(&g_edma.lock, flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_dmach_stop + * + * Description: + * Cancel the DMA. After imx9_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and imx9_dmarx/txsetup() must be called + * before imx9_dmach_start() can be called again. + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imx9_dmach_stop(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL); + + imx9_dmaterminate(dmach, -EINTR); +} + +/**************************************************************************** + * Name: imx9_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * + * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int imx9_dmach_getcount(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + unsigned int remaining = 0; + uintptr_t regval32; + uint16_t regval16; + + DEBUGASSERT(dmach != NULL); + + /* If the DMA is done, then the remaining count is zero */ + + regval32 = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + + if ((regval32 & EDMA_CH_CSR_DONE) == 0) + { + /* Calculate the unfinished bytes */ + + regval16 = getreg16(base + IMX9_EDMA_TCD_CITER_OFFSET); + + if ((regval16 & EDMA_TCD_CITER_ELINK) != 0) + { + remaining = (regval16 & EDMA_TCD_CITER_MASK_ELINK) >> + EDMA_TCD_CITER_SHIFT; + } + else + { + remaining = (regval16 & EDMA_TCD_CITER_MASK) >> + EDMA_TCD_CITER_SHIFT; + } + } + + return remaining; +} + +/**************************************************************************** + * Name: imx9_dmach_idle + * + * Description: + * This function checks if the dma is idle + * + * Returned Value: + * 0 - if idle + * !0 - not + * + ****************************************************************************/ + +unsigned int imx9_dmach_idle(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + return dmach->state == IMX9_DMA_IDLE ? 0 : -1; +} + +/**************************************************************************** + * Name: imx9_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by imx9_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + unsigned int chan; + irqstate_t flags; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + DEBUGASSERT(dmach != NULL && regs != NULL); + chan = dmach->chan; + regs->chan = chan; + + /* eDMA Global Registers */ + + flags = spin_lock_irqsave(&g_edma.lock); + + /* REVISIT: eDMA4 does not show INT_HIGH / HRS_HIGH values correctly */ + + regs->cr = getreg32(IMX9_EDMA_CSR(base)); /* Control */ + regs->es = getreg32(IMX9_EDMA_ES(base)); /* Error Status */ + regs->req = getreg32(IMX9_EDMA_INT); /* Interrupt Request */ + regs->hrs = getreg32(IMX9_EDMA_HRS); /* Hardware Request Status */ + + /* eDMA TCD */ + + regs->saddr = getreg32(base + IMX9_EDMA_TCD_SADDR_OFFSET); + regs->soff = getreg16(base + IMX9_EDMA_TCD_SOFF_OFFSET); + regs->attr = getreg16(base + IMX9_EDMA_TCD_ATTR_OFFSET); + regs->nbml = getreg32(base + IMX9_EDMA_TCD_NBYTES_OFFSET); + regs->slast = getreg32(base + IMX9_EDMA_TCD_SLAST_SDA_OFFSET); + regs->daddr = getreg32(base + IMX9_EDMA_TCD_DADDR_OFFSET); + regs->doff = getreg16(base + IMX9_EDMA_TCD_DOFF_OFFSET); + regs->citer = getreg16(base + IMX9_EDMA_TCD_CITER_OFFSET); + regs->dlastsga = getreg32(base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + regs->csr = getreg16(base + IMX9_EDMA_TCD_CSR_OFFSET); + regs->biter = getreg16(base + IMX9_EDMA_TCD_BITER_OFFSET); + + /* DMAMUX registers */ + + if (imx9_edma_tcdhasmux(dmach->base)) + { + regs->dmamux = getreg32(base + IMX9_EDMA_CH_MUX_OFFSET); + } + else + { + regs->dmamux = 0; + } + + spin_unlock_irqrestore(&g_edma.lock, flags); +} +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Name: imx9_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by imx9_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmadump(const struct imx9_dmaregs_s *regs, const char *msg) +{ + unsigned int chan; + + DEBUGASSERT(regs != NULL && msg != NULL); + + chan = regs->chan; + DEBUGASSERT(chan < IMX9_EDMA_NCHANNELS); + + dmainfo("%s\n", msg); + dmainfo(" eDMA Global Registers:\n"); + dmainfo(" CR: %08x\n", (unsigned int)regs->cr); + dmainfo(" ES: %08x\n", (unsigned int)regs->es); + dmainfo(" INT: %08x\n", (unsigned int)regs->req); + dmainfo(" EARS: %08x\n", (unsigned int)regs->hrs); + + /* eDMA Channel registers */ + + dmainfo(" eDMA Channel %u Registers:\n", chan); + dmainfo(" DCHPRI: %02x\n", regs->dchpri); + + /* eDMA TCD */ + + dmainfo(" eDMA Channel %u TCD Registers:\n", chan); + dmainfo(" SADDR: %08x\n", (unsigned int)regs->saddr); + dmainfo(" SOFF: %04x\n", (unsigned int)regs->soff); + dmainfo(" ATTR: %04x\n", (unsigned int)regs->attr); + dmainfo(" NBML: %05x\n", (unsigned int)regs->nbml); + dmainfo(" SLAST: %05x\n", (unsigned int)regs->slast); + dmainfo(" DADDR: %05x\n", (unsigned int)regs->daddr); + dmainfo(" DOFF: %04x\n", (unsigned int)regs->doff); + dmainfo(" CITER: %04x\n", (unsigned int)regs->citer); + dmainfo(" DLASTSGA: %08x\n", (unsigned int)regs->dlastsga); + dmainfo(" CSR: %04x\n", (unsigned int)regs->csr); + dmainfo(" BITER: %04x\n", (unsigned int)regs->biter); + + /* DMAMUX registers */ + + dmainfo(" DMAMUX Channel %u Registers:\n", chan); + dmainfo(" DMAMUX: %08x\n", (unsigned int)regs->dmamux); +} +#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_IMX9_EDMA */ diff --git a/arch/arm/src/imx9/imx9_edma.h b/arch/arm/src/imx9/imx9_edma.h new file mode 100644 index 0000000000000..243d2f8345e09 --- /dev/null +++ b/arch/arm/src/imx9/imx9_edma.h @@ -0,0 +1,478 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_edma.h + * + * SPDX-License-Identifier: BSD-3-Clause + * SPDX-FileCopyrightText: 2024 NXP + * SPDX-FileCopyrightText: 2019, 2021, 2023 Gregory Nutt. + * SPDX-FileCopyrightText: 2022 NXP + * SPDX-FileCopyrightText: 2016-2017 NXP + * SPDX-FileCopyrightText: 2015, Freescale Semiconductor, Inc. + * SPDX-FileContributor: Gregory Nutt + * SPDX-FileContributor: David Sidrane + * SPDX-FileContributor: Peter van der Perk + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H +#define __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H + +/* General Usage: + * + * 1. Allocate a DMA channel + * + * DMACH_HANDLE handle; + * handle = edma_dmach_alloc(dmamux, dchpri); + * + * Where 'dmamux' is the channel DMAMUX configuration register setting and + * 'dchpri' is the channel DCHPRIO priority register setting. + * + * 2. Create the transfer configuration: + * + * struct imx9_edma_xfrconfig_s config; + * config.saddr = ..; + * config.daddr = ..; + * etc. + * + * 3. Setup the transfer in hardware: + * + * int ret; + * ret = imx9_dmach_xfrsetup(handle, &config); + * + * 4. If you are setting up a scatter gather DMA + * (with CONFIG_IMX9_EDMA_NTCD > 0), then repeat steps 2 and 3 for + * each segment of the transfer. + * + * 5. Start the DMA: + * + * ret = imx9_dmach_start(handle, my_callback_func, priv); + * + * Where my_callback_func() is called when the DMA completes or an error + * occurs. 'priv' represents some internal driver state that will be + * provided with the callback. + * + * 6. If you need to stop the DMA and free resources (such as if a timeout + * occurs), then: + * + * i mxrt_dmach_stop(handle); + * + * 7. The callback will be received when the DMA completes (or an error + * occurs). After that, you may free the DMA channel, or re-use it on + * subsequent DMAs. + * + * imx9_dmach_free(handle); + * + * Almost non-invasive debug instrumentation is available. You may call + * imx9_dmasample() to save the current state of the eDMA registers at + * any given point in time. At some later, postmortem analysis, you can + * dump the content of the buffered registers with imx9_dmadump(). + * imx9_dmasample() is also available for monitoring DMA progress. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration flags. + * + * REVISIT: Many missing options that should be represented as flags: + * 1. Bandwidth + * 2. Source/Destination modulo + */ + +#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */ +#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT) +# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */ +# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */ +# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */ + +#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */ +#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT) +# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */ +# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */ +# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */ + +#define EDMA_CONFIG_INTHALF (1 << 4) /* Bits 4: Int on HALF */ +#define EDMA_CONFIG_INTMAJOR (1 << 5) /* Bits 5: Int on all Major completion + * Default is only on last completion + * if using scatter gather + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef void *DMACH_HANDLE; +typedef void (*edma_callback_t)(DMACH_HANDLE handle, + void *arg, bool done, int result); + +/* eDMA transfer type */ + +enum imx9_edma_xfrtype_e +{ + EDMA_MEM2MEM = 0, /* Transfer from memory to memory */ + EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */ + EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */ +}; + +/* eDMA transfer sises */ + +enum imx9_edma_sizes_e +{ + EDMA_8BIT = 0, /* Transfer data size 8 */ + EDMA_16BIT = 1, /* Transfer data size 16 */ + EDMA_32BIT = 2, /* Transfer data size 32 */ + EDMA_64BIT = 3, /* Transfer data size 64 */ + EDMA_16BYTE = 4, /* Transfer data size 16-byte */ + EDMA_32BYTE = 5, /* Transfer data size 32-byte */ + EDMA_64BYTE = 6, /* Transfer data size 64-byte */ +}; + +/* This structure holds the source/destination transfer attribute + * configuration. + */ + +struct imx9_edma_xfrconfig_s +{ + uintptr_t saddr; /* Source data address. */ + uintptr_t daddr; /* Destination data address. */ + int16_t soff; /* Sign-extended offset for current source address. */ + int16_t doff; /* Sign-extended offset for current destination address. */ + uint16_t iter; /* Major loop iteration count. */ + uint8_t flags; /* See EDMA_CONFIG_* definitions */ + uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */ + uint8_t dsize; /* Destination data transfer size. */ +#ifdef CONFIG_IMX9_EDMA_EMLIM + uint16_t nbytes; /* Bytes to transfer in a minor loop */ +#else + uint32_t nbytes; /* Bytes to transfer in a minor loop */ +#endif +#ifdef CONFIG_IMX9_EDMA_MOD + uint8_t smod; + uint8_t dmod; +#endif +#ifdef CONFIG_IMX9_EDMA_BWC + uint8_t bwc; +#endif +#ifdef CONFIG_IMX9_EDMA_ELINK + DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */ +#endif +}; + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ + +#ifdef CONFIG_DEBUG_DMA +struct imx9_dmaregs_s +{ + uint8_t chan; /* Sampled channel */ + + /* eDMA Global Registers */ + + uint32_t cr; /* Control */ + uint32_t es; /* Error Status */ + uint32_t req; /* Interrupt Request */ + uint32_t hrs; /* Hardware Request Status */ + + /* eDMA Channel registers */ + + uint8_t dchpri; /* Channel priority */ + + /* eDMA TCD */ + + uint32_t saddr; /* TCD Source Address */ + uint16_t soff; /* TCD Signed Source Address Offset */ + uint16_t attr; /* TCD Transfer Attributes */ + uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* TCD Last Source Address Adjustment */ + uint32_t daddr; /* TCD Destination Address */ + uint16_t doff; /* TCD Signed Destination Address Offset */ + uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* TCD Control and Status */ + uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */ + + /* DMAMUX registers */ + + uint32_t dmamux; /* Channel configuration */ +}; +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/imx9_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/imx9_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE imx9_dmach_alloc(uint16_t dmamux, uint8_t dchpri); + +/**************************************************************************** + * Name: imx9_dmach_free + * + * Description: + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again + * until imx9_dmach_alloc() is called again to re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_dmach_free(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, imx9_dmach_xfrsetup is called only + * once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_xfrsetup(DMACH_HANDLE handle, + const struct imx9_edma_xfrconfig_s *config); + +/**************************************************************************** + * Name: imx9_dmach_start + * + * Description: + * Start the DMA transfer by enabling the channel DMA request. + * This function should be called after the final call to + * imx9_dmasetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the + * user-provided function is made: |For "normal" DMAs, this will + * correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple + * interrupts will be generated with the final being the DONE interrupt. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: + * On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary + * to invalidate the destination memory. That is not done automatically + * by the DMA module. Invalidation of the destination memory regions is + * the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, + void *arg); + +/**************************************************************************** + * Name: imx9_dmach_stop + * + * Description: + * Cancel the DMA. After imx9_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and imx9_dmarx/txsetup() must be called + * before imx9_dmach_start() can be called again + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imx9_dmach_stop(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int imx9_dmach_getcount(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmach_idle + * + * Description: + * This function checks if the dma is idle + * + * Returned Value: + * 0 - if idle + * !0 - not + * + ****************************************************************************/ + +unsigned int imx9_dmach_idle(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs); +#else +# define imx9_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: imx9_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmadump(const struct imx9_dmaregs_s *regs, const char *msg); +#else +# define imx9_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H */ diff --git a/arch/arm/src/imx9/imx9_flexcan.c b/arch/arm/src/imx9/imx9_flexcan.c new file mode 100644 index 0000000000000..36b51ef0c8b8f --- /dev/null +++ b/arch/arm/src/imx9/imx9_flexcan.c @@ -0,0 +1,2166 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_flexcan.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "imx9_flexcan.h" +#include "imx9_clockconfig.h" +#include "imx9_gpio.h" +#include "imx9_iomuxc.h" +#include "hardware/imx9_flexcan.h" +#include "hardware/imx9_pinmux.h" + +#include + +#include + +#ifdef CONFIG_IMX9_FLEXCAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#define CANWORK LPWORK +#define CANRCVWORK HPWORK + +/* CONFIG_IMX9_FLEXCAN_NETHIFS determines the number of physical + * interfaces that will be supported. + */ + +#define MASKSTDID 0x000007ff +#define MASKEXTID 0x1fffffff +#define FLAGEFF (1 << 31) /* Extended frame format */ +#define FLAGRTR (1 << 30) /* Remote transmission request */ + +#define RXMBCOUNT CONFIG_IMX9_FLEXCAN_RXMB +#define TXMBCOUNT (CONFIG_IMX9_FLEXCAN_TXMB + 1) +#define TOTALMBCOUNT RXMBCOUNT + TXMBCOUNT + +#define IFLAG1_RX ((1 << RXMBCOUNT)-1) +#define IFLAG1_TX (((1 << TXMBCOUNT)-2) << RXMBCOUNT) + +#define CAN_FIFO_NE (1 << 5) +#define CAN_FIFO_OV (1 << 6) +#define CAN_FIFO_WARN (1 << 7) +#define CAN_EFF_FLAG 0x80000000 /* EFF/SFF is set in the MSB */ + +#define POOL_SIZE 1 + +#define MSG_DATA sizeof(struct timeval) + +/* CAN bit timing values */ +#define CLK_FREQ 80000000 +#define PRESDIV_MAX 256 + +#define SEG_MAX 8 +#define SEG_MIN 1 +#define TSEG_MIN 2 +#define TSEG1_MAX 17 +#define TSEG2_MAX 9 +#define NUMTQ_MAX 26 + +#define SEG_FD_MAX 32 +#define SEG_FD_MIN 1 +#define TSEG_FD_MIN 2 +#define TSEG1_FD_MAX 39 +#define TSEG2_FD_MAX 9 +#define NUMTQ_FD_MAX 49 + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + +# if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +# endif + +#define TX_TIMEOUT_WQ +#endif + +#if (CONFIG_IMX9_FLEXCAN_RXMB + CONFIG_IMX9_FLEXCAN_TXMB) > 20 +# error Only 20 MB are allowed to be used +#endif + +/* Interrupt flags for RX fifo */ +#define IFLAG1_RXFIFO (CAN_FIFO_NE | CAN_FIFO_WARN | CAN_FIFO_OV) + +static int peak_tx_mailbox_index_ = 0; + +static uint8_t mb_address[] = + { + 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, + 0x1e, 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, + 0x10, 0x19, 0x22, 0x2b, 0x34, 0x3d, 0x46, + 0x50, 0x59, 0x62, 0x6b, 0x74, 0x7d, 0x86, + 0x90, 0x99, 0xa2, 0xab, 0xb4, 0xbd, 0xc6 + }; + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +union cs_e +{ + volatile uint32_t cs; + struct + { + volatile uint32_t time_stamp : 16; + volatile uint32_t dlc : 4; + volatile uint32_t rtr : 1; + volatile uint32_t ide : 1; + volatile uint32_t srr : 1; + volatile uint32_t res : 1; + volatile uint32_t code : 4; + volatile uint32_t res2 : 1; + volatile uint32_t esi : 1; + volatile uint32_t brs : 1; + volatile uint32_t edl : 1; + }; +}; + +union id_e +{ + volatile uint32_t w; + struct + { + volatile uint32_t ext : 29; + volatile uint32_t resex : 3; + }; + struct + { + volatile uint32_t res : 18; + volatile uint32_t std : 11; + volatile uint32_t resstd : 3; + }; +}; + +union data_e +{ + volatile uint32_t w00; + struct + { + volatile uint32_t b03 : 8; + volatile uint32_t b02 : 8; + volatile uint32_t b01 : 8; + volatile uint32_t b00 : 8; + }; +}; + +struct mb_s +{ + union cs_e cs; + union id_e id; + union data_e data[]; +}; + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +#define TX_ABORT -1 +#define TX_FREE 0 +#define TX_BUSY 1 + +struct txmbstats +{ + struct timeval deadline; + uint32_t pending; /* -1 = abort, 0 = free, 1 = busy */ +}; +#endif + +/* FlexCAN Device hardware configuration */ + +struct flexcan_config_s +{ + iomux_cfg_t tx_pin; /* GPIO configuration for TX */ + iomux_cfg_t rx_pin; /* GPIO configuration for RX */ + uint32_t clk_root; + uint32_t irq; /* Combined interrupt */ +}; + +struct flexcan_timeseg +{ + uint32_t bitrate; + int32_t samplep; + uint8_t propseg; + uint8_t pseg1; + uint8_t pseg2; + uint8_t presdiv; +}; + +/* FlexCAN device structures */ + +#ifdef CONFIG_IMX9_FLEXCAN1 +static const struct flexcan_config_s imx9_flexcan1_config = +{ + .tx_pin = GPIO_FLEXCAN1_TX, + .rx_pin = GPIO_FLEXCAN1_RX, + .clk_root = FLEXCAN1_CLK, + .irq = IMX9_IRQ_CAN1, +}; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 +static const struct flexcan_config_s imx9_flexcan2_config = +{ + .tx_pin = GPIO_FLEXCAN2_TX, + .rx_pin = GPIO_FLEXCAN2_RX, + .clk_root = FLEXCAN2_CLK, + .irq = IMX9_IRQ_CAN2, +}; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN3 +static const struct flexcan_config_s imx9_flexcan3_config = +{ + .tx_pin = GPIO_FLEXCAN3_TX, + .rx_pin = GPIO_FLEXCAN3_RX, + .clk_root = FLEXCAN3_CLK, + .irq = IMX9_IRQ_CAN3, +}; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN4 +static const struct flexcan_config_s imx9_flexcan4_config = +{ + .tx_pin = GPIO_FLEXCAN4_TX, + .rx_pin = GPIO_FLEXCAN4_RX, + .clk_root = FLEXCAN4_CLK, + .irq = IMX9_IRQ_CAN4, +}; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN5 +static const struct flexcan_config_s imx9_flexcan5_config = +{ + .tx_pin = GPIO_FLEXCAN5_TX, + .rx_pin = GPIO_FLEXCAN5_RX, + .clk_root = FLEXCAN5_CLK, + .irq = IMX9_IRQ_CAN5, +}; +#endif + +/* The imx9_driver_s encapsulates all state information for a single + * hardware interface + */ + +struct imx9_driver_s +{ + uint32_t base; /* FLEXCAN base address */ + bool bifup; /* true:ifup false:ifdown */ + bool canfd_capable; + int mb_address_offset; +#ifdef TX_TIMEOUT_WQ + struct wdog_s txtimeout[TXMBCOUNT]; /* TX timeout timer */ +#endif + struct work_s rcvwork; /* For deferring interrupt work to the wq */ + struct work_s irqwork; /* For deferring interrupt work to the wq */ + struct work_s pollwork; /* For deferring poll work to the work wq */ + struct canfd_frame *txdesc_fd; /* A pointer to the list of TX descriptor for FD frames */ + struct canfd_frame *rxdesc_fd; /* A pointer to the list of RX descriptors for FD frames */ + struct can_frame *txdesc; /* A pointer to the list of TX descriptor */ + struct can_frame *rxdesc; /* A pointer to the list of RX descriptors */ + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s dev; /* Interface understood by the network */ + + struct flexcan_timeseg arbi_timing; /* Timing for arbitration phase */ + struct flexcan_timeseg data_timing; /* Timing for data phase */ + + const struct flexcan_config_s *config; + spinlock_t lock; + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + struct txmbstats txmb[TXMBCOUNT]; +#endif +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_IMX9_FLEXCAN1 +static struct imx9_driver_s g_flexcan1; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 +static struct imx9_driver_s g_flexcan2; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN3 +static struct imx9_driver_s g_flexcan3; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN4 +static struct imx9_driver_s g_flexcan4; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN5 +static struct imx9_driver_s g_flexcan5; +#endif + +#ifdef CONFIG_NET_CAN_CANFD +static uint8_t g_tx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE]; +static uint8_t g_rx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE]; +#else +static uint8_t g_tx_pool[sizeof(struct can_frame)*POOL_SIZE]; +static uint8_t g_rx_pool[sizeof(struct can_frame)*POOL_SIZE]; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_lsb + * + * Description: + * Calculate position of lsb that's equal to 1 + * + * Input Parameters: + * value - The value to perform the operation on + * + * Returned Value: + * location of lsb which is equal to 1, returns 32 when value is 0 + * + ****************************************************************************/ + +static inline uint32_t arm_lsb(unsigned int value) +{ + uint32_t ret; + volatile uint32_t rvalue = value; + __asm__ __volatile__ ("rbit %1,%0" : "=r" (rvalue) : "r" (rvalue)); + __asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(rvalue)); + return ret; +} + +/**************************************************************************** + * Name: imx9_bitratetotimeseg + * + * Description: + * Convert bitrate to timeseg + * + * Input Parameters: + * timeseg - structure to store bit timing + * sp_tolerance - allowed difference in sample point from calculated + * bit timings (recommended value: 1) + * can_fd - if set to calculate CAN FD bit timings, otherwise calculate + * classical can timings + * + * Returned Value: + * return 1 on success, return 0 on failure + * + ****************************************************************************/ + +uint32_t imx9_bitratetotimeseg(struct flexcan_timeseg *timeseg, + int32_t sp_tolerance, + uint32_t can_fd) +{ + int32_t tmppresdiv; + int32_t numtq; + int32_t tmpsample; + int32_t tseg1; + int32_t tseg2; + int32_t tmppseg1; + int32_t tmppseg2; + int32_t tmppropseg; + + const int32_t TSEG1MAX = (can_fd ? TSEG1_FD_MAX : TSEG1_MAX); + const int32_t TSEG2MAX = (can_fd ? TSEG2_FD_MAX : TSEG2_MAX); + const int32_t SEGMAX = (can_fd ? SEG_FD_MAX : SEG_MAX); + const int32_t NUMTQMAX = (can_fd ? NUMTQ_FD_MAX : NUMTQ_MAX); + + for (tmppresdiv = 0; tmppresdiv < PRESDIV_MAX; tmppresdiv++) + { + numtq = (CLK_FREQ / ((tmppresdiv + 1) * timeseg->bitrate)); + + if (numtq == 0) + { + continue; + } + + /* The number of time quanta in 1 bit time must be + * lower than the one supported + */ + + if ((CLK_FREQ / ((tmppresdiv + 1) * numtq) == timeseg->bitrate) + && (numtq >= 8) && (numtq < NUMTQMAX)) + { + /* Compute time segments based on the value of the sampling point */ + + tseg1 = (numtq * timeseg->samplep / 100) - 1; + tseg2 = numtq - 1 - tseg1; + + /* Adjust time segment 1 and time segment 2 */ + + while (tseg1 >= TSEG1MAX || tseg2 < TSEG_MIN) + { + tseg2++; + tseg1--; + } + + tmppseg2 = tseg2 - 1; + + /* Start from pseg1 = pseg2 and adjust until propseg is valid */ + + tmppseg1 = tmppseg2; + tmppropseg = tseg1 - tmppseg1 - 2; + + while (tmppropseg <= 0) + { + tmppropseg++; + tmppseg1--; + } + + while (tmppropseg >= SEGMAX) + { + tmppropseg--; + tmppseg1++; + } + + if (((tseg1 >= TSEG1MAX) || (tseg2 >= TSEG2MAX) || + (tseg2 < TSEG_MIN) || (tseg1 < TSEG_MIN)) || + ((tmppropseg >= SEGMAX) || (tmppseg1 >= SEGMAX) || + (tmppseg2 < SEG_MIN) || (tmppseg2 >= SEGMAX))) + { + continue; + } + + tmpsample = ((tseg1 + 1) * 100) / numtq; + + if ((tmpsample - timeseg->samplep) <= sp_tolerance && + (timeseg->samplep - tmpsample) <= sp_tolerance) + { + if (can_fd == 1) + { + timeseg->propseg = tmppropseg + 1; + } + else + { + timeseg->propseg = tmppropseg; + } + timeseg->pseg1 = tmppseg1; + timeseg->pseg2 = tmppseg2; + timeseg->presdiv = tmppresdiv; + timeseg->samplep = tmpsample; + return 1; + } + } + } + + return 0; +} + +/* Common TX logic */ + +static bool imx9_txringfull(struct imx9_driver_s *priv); +static int imx9_transmit(struct imx9_driver_s *priv); +static int imx9_txpoll(struct net_driver_s *dev); + +/* Helper functions */ + +static void imx9_setenable(uint32_t base, uint32_t enable); +static void imx9_setfreeze(uint32_t base, uint32_t freeze); +static uint32_t imx9_waitmcr_change(uint32_t base, + uint32_t mask, + uint32_t target_state); +static struct mb_s *flexcan_get_mb(struct imx9_driver_s *priv, + uint32_t mbi); + +/* Interrupt handling */ + +static void imx9_receive(struct imx9_driver_s *priv, + uint32_t flags); +static void imx9_txdone_work(void *arg); +static void imx9_txdone(struct imx9_driver_s *priv); + +static int imx9_flexcan_interrupt(int irq, void *context, + void *arg); +static void imx9_flexcan_interrupt_work(void *arg); + +/* Watchdog timer expirations */ +#ifdef TX_TIMEOUT_WQ +static void imx9_txtimeout_work(void *arg); +static void imx9_txtimeout_expiry(wdparm_t arg); +#endif + +/* NuttX callback functions */ + +static int imx9_ifup(struct net_driver_s *dev); +static int imx9_ifdown(struct net_driver_s *dev); + +static void imx9_txavail_work(void *arg); +static int imx9_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int imx9_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Initialization */ + +static int imx9_initialize(struct imx9_driver_s *priv); +static void imx9_reset(struct imx9_driver_s *priv); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imx9_txringfull + * + * Description: + * Check if all of the TX descriptors are in use. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * true is the TX ring is full; false if there are free slots at the + * head index. + * + ****************************************************************************/ + +static bool imx9_txringfull(struct imx9_driver_s *priv) +{ + uint32_t mbi = RXMBCOUNT + 1; + struct mb_s *mb; + + while (mbi < TOTALMBCOUNT) + { + mb = flexcan_get_mb(priv, mbi); + if (mb->cs.code != CAN_TXMB_DATAORREMOTE) + { + return 0; + } + + mbi++; + } + + return 1; +} + +/**************************************************************************** + * Function: imx9_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int imx9_transmit(struct imx9_driver_s *priv) +{ + /* Attempt to write frame */ + + uint32_t mbi = 0; + uint32_t mb_bit; + uint32_t regval; +#ifdef CONFIG_NET_CAN_CANFD + uint32_t *frame_data_word; + uint32_t i; +#endif +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + int32_t timeout; + uint32_t txmb = 0; +#endif + + mbi = RXMBCOUNT + 1; + mb_bit = 1 << mbi; + + while (mbi < TOTALMBCOUNT) + { + /* Check whether message buffer is not currently transmitting */ + + struct mb_s *mb = flexcan_get_mb(priv, mbi); + if (mb->cs.code != CAN_TXMB_DATAORREMOTE) + { + putreg32(mb_bit, priv->base + IMX9_CAN_IFLAG1_OFFSET); + break; + } + + mb_bit <<= 1; + mbi++; +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + txmb++; +#endif + } + + if (mbi == TOTALMBCOUNT) + { + nwarn("No TX MB available mbi %" PRIi32 "\n", mbi); + NETDEV_TXERRORS(&priv->dev); + return 0; /* No transmission for you! */ + } + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + struct timespec ts; + clock_systime_timespec(&ts); + + if (priv->dev.d_sndlen > priv->dev.d_len) + { + struct timeval *tv = + (struct timeval *)(priv->dev.d_buf + priv->dev.d_len); + priv->txmb[txmb].deadline = *tv; + timeout = (tv->tv_sec - ts.tv_sec)*CLK_TCK + + ((tv->tv_usec - ts.tv_nsec / 1000)*CLK_TCK) / 1000000; + if (timeout < 0) + { + return 0; /* No transmission for you! */ + } + } + else + { + /* Default TX deadline defined in NET_CAN_RAW_DEFAULT_TX_DEADLINE */ + + if (CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE > 0) + { + timeout = ((CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000) + *CLK_TCK); + priv->txmb[txmb].deadline.tv_sec = ts.tv_sec + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000; + priv->txmb[txmb].deadline.tv_usec = (ts.tv_nsec / 1000) + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE % 1000000; + } + else + { + priv->txmb[txmb].deadline.tv_sec = 0; + priv->txmb[txmb].deadline.tv_usec = 0; + timeout = -1; + } + } +#endif + + peak_tx_mailbox_index_ = + (peak_tx_mailbox_index_ > mbi ? peak_tx_mailbox_index_ : mbi); + + union cs_e cs; + cs.code = CAN_TXMB_DATAORREMOTE; + struct mb_s *mb = flexcan_get_mb(priv, mbi); + mb->cs.code = CAN_TXMB_INACTIVE; + + if (priv->dev.d_len == sizeof(struct can_frame)) + { + struct can_frame *frame = (struct can_frame *)priv->dev.d_buf; + + if (frame->can_id & CAN_EFF_FLAG) + { + cs.ide = 1; + mb->id.ext = frame->can_id & MASKEXTID; + } + else + { + mb->id.std = frame->can_id & MASKSTDID; + } + + cs.rtr = frame->can_id & FLAGRTR ? 1 : 0; + cs.dlc = frame->can_dlc; + + mb->data[0].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[0]); + mb->data[1].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[4]); + } +#ifdef CONFIG_NET_CAN_CANFD + else /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; + + cs.edl = 1; /* CAN FD Frame */ + + if (frame->can_id & CAN_EFF_FLAG) + { + cs.ide = 1; + mb->id.ext = frame->can_id & MASKEXTID; + } + else + { + mb->id.std = frame->can_id & MASKSTDID; + } + + cs.rtr = frame->can_id & FLAGRTR ? 1 : 0; + + cs.dlc = g_len_to_can_dlc[frame->len]; + + frame_data_word = (uint32_t *)&frame->data[0]; + + for (i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + mb->data[i].w00 = __builtin_bswap32(frame_data_word[i]); + } + } +#endif + + mb->cs = cs; /* Go. */ + + /* Errata ER005829 step 8: Write twice into the first TX MB + * Errata mentions writng 0x8 value, but this one couses + * the ESR2_LPTM register to choose the reserved MB for + * transmiting the package, hence we write 0x3 + */ + + struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); + buffer->cs.code = 0x3; + buffer->cs.code = 0x3; + + regval = getreg32(priv->base + IMX9_CAN_IMASK1_OFFSET); + regval |= mb_bit; + putreg32(regval, priv->base + IMX9_CAN_IMASK1_OFFSET); + + /* Increment statistics */ + + NETDEV_TXPACKETS(&priv->dev); + +#ifdef TX_TIMEOUT_WQ + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + if (timeout > 0) + { + wd_start(&priv->txtimeout[txmb], timeout + 1, + imx9_txtimeout_expiry, (wdparm_t)priv); + } +#endif + + return OK; +} + +/**************************************************************************** + * Function: imx9_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int imx9_txpoll(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + irqstate_t flags; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + flags = spin_lock_irqsave(&priv->lock); + sched_lock(); + + if (priv->dev.d_len > 0) + { + imx9_txdone(priv); + + /* Send the packet */ + + imx9_transmit(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (imx9_txringfull(priv)) + { + sched_unlock(); + spin_unlock_irqrestore(&priv->lock, flags); + return -EBUSY; + } + } + + sched_unlock(); + spin_unlock_irqrestore(&priv->lock, flags); + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: imx9_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void imx9_receive(struct imx9_driver_s *priv, + uint32_t flags) +{ + uint32_t mbi; + uint32_t mbj; + struct mb_s *rf; +#ifdef CONFIG_NET_CAN_CANFD + uint32_t *frame_data_word; + uint32_t i; +#endif + uint32_t f; + + while ((f = flags) != 0) + { + mbj = mbi = arm_lsb(f); + rf = flexcan_get_mb(priv, mbi); + uint32_t t = rf->cs.time_stamp; + while ((f &= ~(1 << mbj)) != 0) + { + mbj = arm_lsb(f); + struct mb_s *rf_next = flexcan_get_mb(priv, mbj); + uint16_t t_next = rf_next->cs.time_stamp; + if ((int16_t)(t - t_next) > 0) + { + t = t_next; + mbi = mbj; + } + } + + rf = flexcan_get_mb(priv, mbi); + + /* Read the frame contents */ + +#ifdef CONFIG_NET_CAN_CANFD + if (rf->cs.edl) /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc_fd; + + if (rf->cs.ide) + { + frame->can_id = MASKEXTID & rf->id.ext; + frame->can_id |= FLAGEFF; + } + else + { + frame->can_id = MASKSTDID & rf->id.std; + } + + if (rf->cs.rtr) + { + frame->can_id |= FLAGRTR; + } + + frame->len = g_can_dlc_to_len[rf->cs.dlc]; + + frame_data_word = (uint32_t *)&frame->data[0]; + + for (i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + frame_data_word[i] = __builtin_bswap32(rf->data[i].w00); + } + + /* Clear MB interrupt flag */ + + putreg32(1 << mbi, + priv->base + IMX9_CAN_IFLAG1_OFFSET); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct canfd_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + else /* CAN 2.0 Frame */ +#endif + { + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + + if (rf->cs.ide) + { + frame->can_id = MASKEXTID & rf->id.ext; + frame->can_id |= FLAGEFF; + } + else + { + frame->can_id = MASKSTDID & rf->id.std; + } + + if (rf->cs.rtr) + { + frame->can_id |= FLAGRTR; + } + + frame->can_dlc = rf->cs.dlc; + + *(uint32_t *)&frame->data[0] = __builtin_bswap32(rf->data[0].w00); + *(uint32_t *)&frame->data[4] = __builtin_bswap32(rf->data[1].w00); + + /* Clear MB interrupt flag */ + + putreg32(1 << mbi, + priv->base + IMX9_CAN_IFLAG1_OFFSET); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + + /* Send to socket interface */ + + NETDEV_RXPACKETS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + if (priv->canfd_capable) + { + priv->dev.d_buf = (uint8_t *)priv->txdesc_fd; + } + else + { + priv->dev.d_buf = (uint8_t *)priv->txdesc; + } + + flags &= ~(1 << mbi); + + /* Reread interrupt flags and process them in this loop */ + + if (flags == 0) + { + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + } + } +} + +/**************************************************************************** + * Function: imx9_txdone + * + * Description: + * Check transmit interrupt flags and clear them + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void imx9_txdone(struct imx9_driver_s *priv) +{ + uint32_t flags; + uint32_t mbi; + uint32_t mb_bit; +#ifdef TX_TIMEOUT_WQ + uint32_t txmb; +#endif + + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_TX; + + /* TODO First Process Error aborts */ + + /* Process TX completions */ + + mbi = RXMBCOUNT + 1; + mb_bit = 1 << mbi; +#ifdef TX_TIMEOUT_WQ + txmb = 0; +#endif + + while (mbi < TOTALMBCOUNT) + { + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= ~mb_bit; + NETDEV_TXDONE(&priv->dev); +#ifdef TX_TIMEOUT_WQ + /* We are here because a transmission completed, so the + * corresponding watchdog can be canceled + * mailbox be set to inactive + */ + + wd_cancel(&priv->txtimeout[txmb]); + struct mb_s *mb = flexcan_get_mb(priv, mbi); + mb->cs.code = CAN_TXMB_INACTIVE; +#endif + } + + mb_bit <<= 1; + mbi++; +#ifdef TX_TIMEOUT_WQ + txmb++; +#endif + } +} + +/**************************************************************************** + * Function: imx9_txdone_work + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * We are not in an interrupt context so that we can lock the network. + * + ****************************************************************************/ + +static void imx9_txdone_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + imx9_txdone(priv); + + /* There should be space for a new TX in any event. Poll the network for + * new XMIT data + */ + + net_lock(); + devif_poll(&priv->dev, imx9_txpoll); + net_unlock(); +} + +/**************************************************************************** + * Function: imx9_flexcan_interrupt_work + * + * Description: + * Three interrupt sources will vector this this function: + * 1. CAN MB transmit interrupt handler + * 2. CAN MB receive interrupt handler + * 3. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_flexcan_interrupt_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + uint32_t flags; + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + + net_lock(); + imx9_receive(priv, flags); + net_unlock(); + + /* Mask MB again */ + + modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, 0, IFLAG1_RX); +} + +/**************************************************************************** + * Function: imx9_flexcan_interrupt + * + * Description: + * Three interrupt sources will vector this this function: + * 1. CAN MB transmit interrupt handler + * 2. CAN MB receive interrupt handler + * 3. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_flexcan_interrupt(int irq, void *context, + void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + if (irq == priv->config->irq) + { + uint32_t flags; + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + + if (flags) + { + modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, IFLAG1_RX, 0); + work_queue(CANRCVWORK, &priv->rcvwork, + imx9_flexcan_interrupt_work, priv, 0); + } + + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_TX; + + if (flags) + { + /* Disable further TX MB CAN interrupts. here can be no race + * condition here. + */ + + modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, IFLAG1_TX, 0); + work_queue(CANWORK, &priv->irqwork, imx9_txdone_work, priv, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ +#ifdef TX_TIMEOUT_WQ + +static void imx9_txtimeout_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + uint32_t flags; + uint32_t mbi; + uint32_t mb_bit; + + struct timespec ts; + struct timeval *now = (struct timeval *)&ts; + clock_systime_timespec(&ts); + now->tv_usec = ts.tv_nsec / 1000; /* timespec to timeval conversion */ + + /* The watchdog timed out, yet we still check mailboxes in case the + * transmit function transmitted a new frame + */ + + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + + for (mbi = 0; mbi < TXMBCOUNT; mbi++) + { + if (priv->txmb[mbi].deadline.tv_sec != 0 + && (now->tv_sec > priv->txmb[mbi].deadline.tv_sec + || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) + { + NETDEV_TXTIMEOUTS(&priv->dev); + + mb_bit = 1 << (RXMBCOUNT + mbi); + + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + IMX9_CAN_IFLAG1_OFFSET); + } + + struct mb_s *mb = flexcan_get_mb(priv, mbi + RXMBCOUNT); + mb->cs.code = CAN_TXMB_ABORT; + priv->txmb[mbi].pending = TX_ABORT; + } + } +} + +/**************************************************************************** + * Function: imx9_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void imx9_txtimeout_expiry(wdparm_t arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Schedule to perform the TX timeout processing on the worker thread + */ + + work_queue(CANWORK, &priv->irqwork, imx9_txtimeout_work, priv, 0); +} + +#endif + +static void imx9_setenable(uint32_t base, uint32_t enable) +{ + uint32_t regval; + + if (enable) + { + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_MDIS); + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } + else + { + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_MDIS; + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } + + imx9_waitmcr_change(base, CAN_MCR_LPMACK, 1); +} + +static void imx9_setfreeze(uint32_t base, uint32_t freeze) +{ + uint32_t regval; + if (freeze) + { + /* Enter freeze mode */ + + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval |= (CAN_MCR_HALT | CAN_MCR_FRZ); + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } + else + { + /* Exit freeze mode */ + + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_HALT | CAN_MCR_FRZ); + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } +} + +static uint32_t imx9_waitmcr_change(uint32_t base, uint32_t mask, + uint32_t target_state) +{ + const uint32_t timeout = 1000; + uint32_t wait_ack; + + for (wait_ack = 0; wait_ack < timeout; wait_ack++) + { + const bool state = (getreg32(base + IMX9_CAN_MCR_OFFSET) & mask) + != 0; + if (state == target_state) + { + return true; + } + + up_udelay(10); + } + + return false; +} + +static uint32_t imx9_waitfreezeack_change(uint32_t base, + uint32_t target_state) +{ + return imx9_waitmcr_change(base, CAN_MCR_FRZACK, target_state); +} + +static struct mb_s *flexcan_get_mb(struct imx9_driver_s *priv, + uint32_t mbi) +{ + return (struct mb_s *)(priv->base + + (mb_address[priv->mb_address_offset + mbi] << 3)); +} + +/**************************************************************************** + * Function: imx9_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifup(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + + if (!imx9_initialize(priv)) + { + nerr("initialize failed"); + return -1; + } + + priv->bifup = true; + priv->txdesc = (struct can_frame *)&g_tx_pool; + priv->rxdesc = (struct can_frame *)&g_rx_pool; + if (priv->canfd_capable) + { + priv->txdesc_fd = (struct canfd_frame *)&g_tx_pool; + priv->rxdesc_fd = (struct canfd_frame *)&g_rx_pool; + priv->dev.d_buf = (uint8_t *)priv->txdesc_fd; + } + else + { + priv->dev.d_buf = (uint8_t *)priv->txdesc; + } + + /* Set interrupts */ + + up_enable_irq(priv->config->irq); + + return OK; +} + +/**************************************************************************** + * Function: imx9_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifdown(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + + imx9_reset(priv); + + priv->bifup = false; + return OK; +} + +/**************************************************************************** + * Function: imx9_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void imx9_txavail_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (!imx9_txringfull(priv)) + { + /* No, there is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, imx9_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: imx9_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int imx9_txavail(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + imx9_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int imx9_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + struct flexcan_timeseg data_timing; + int ret; + + switch (cmd) + { +#ifdef CONFIG_NETDEV_CAN_BITRATE_IOCTL + case SIOCGCANBITRATE: /* Get bitrate from a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + req->arbi_bitrate = priv->arbi_timing.bitrate / 1000; /* kbit/s */ + req->arbi_samplep = priv->arbi_timing.samplep; + if (priv->canfd_capable) + { + req->data_bitrate = priv->data_timing.bitrate / 1000; /* kbit/s */ + req->data_samplep = priv->data_timing.samplep; + } + else + { + req->data_bitrate = 0; + req->data_samplep = 0; + } + + ret = OK; + } + break; + + case SIOCSCANBITRATE: /* Set bitrate of a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + + struct flexcan_timeseg arbi_timing; + arbi_timing.bitrate = req->arbi_bitrate * 1000; + arbi_timing.samplep = req->arbi_samplep; + + if (imx9_bitratetotimeseg(&arbi_timing, 10, 0)) + { + ret = OK; + } + else + { + ret = -EINVAL; + } + + if (priv->canfd_capable) + { + data_timing.bitrate = req->data_bitrate * 1000; + data_timing.samplep = req->data_samplep; + + if (ret == OK && imx9_bitratetotimeseg(&data_timing, 10, 1)) + { + ret = OK; + } + else + { + ret = -EINVAL; + } + } + + if (ret == OK) + { + /* Reset CAN controller and start with new timings */ + + priv->arbi_timing = arbi_timing; + if (priv->canfd_capable) + { + priv->data_timing = data_timing; + } + + imx9_ifup(dev); + } + } + break; +#endif + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Function: imx9_init_eccram + * + * Description: + * Initialize FLEXCAN ECC RAM + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_init_eccram(struct imx9_driver_s *priv) +{ + uint32_t i; + uint32_t regval; + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + + regval = getreg32(priv->base + IMX9_CAN_CTRL2_OFFSET); + + /* Set WRMFRZ bit in CTRL2 Register to grant write access to memory */ + + regval |= CAN_CTRL2_WRMFRZ; + + putreg32(regval, priv->base + IMX9_CAN_CTRL2_OFFSET); + + for (i = IMX9_CAN_MB_OFFSET; i < IMX9_CAN_MB_END; i += 4) + { + putreg32(0, priv->base + i); + } + + for (i = IMX9_CAN_MB2_OFFSET; i < IMX9_CAN_MB2_END; i += 4) + { + putreg32(0, priv->base + i); + } + + regval = getreg32(priv->base + IMX9_CAN_CTRL2_OFFSET); + + /* Clear WRMFRZ bit in CTRL2 Register */ + + regval &= ~CAN_CTRL2_WRMFRZ; + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +/**************************************************************************** + * Function: imx9_initalize + * + * Description: + * Initialize FLEXCAN device + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_initialize(struct imx9_driver_s *priv) +{ + uint32_t regval; + uint32_t i; + + /* initialize CAN device */ + + imx9_setenable(priv->base, 1); + + imx9_init_eccram(priv); + + imx9_reset(priv); + + /* Enter freeze mode */ + + imx9_setfreeze(priv->base, 1); + if (!imx9_waitfreezeack_change(priv->base, 1)) + { + nerr("FLEXCAN: freeze fail\n"); + return -1; + } + + if (!priv->canfd_capable) + { + regval = getreg32(priv->base + IMX9_CAN_CTRL1_OFFSET); + regval &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK | + CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_RJW_MASK); + regval |= CAN_CTRL1_PRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */ + CAN_CTRL1_PROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */ + CAN_CTRL1_PSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_CTRL1_PSEG2(priv->arbi_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_CTRL1_RJW(1); /* Resynchronization jump width */ + putreg32(regval, priv->base + IMX9_CAN_CTRL1_OFFSET); + } + else + { + regval = getreg32(priv->base + IMX9_CAN_CBT_OFFSET); + regval &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_EPROPSEG_MASK | + CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_ERJW_MASK); + regval |= CAN_CBT_BTF | /* Enable extended bit timing + * configurations for CAN-FD for setting up + * separately nominal and data phase */ + CAN_CBT_EPRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */ + CAN_CBT_EPROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */ + CAN_CBT_EPSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_CBT_EPSEG2(priv->arbi_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_CBT_ERJW(1); /* Resynchronization jump width */ + putreg32(regval, priv->base + IMX9_CAN_CBT_OFFSET); + + /* Enable CAN FD feature */ + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_FDEN; + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + regval = getreg32(priv->base + IMX9_CAN_FDCBT_OFFSET); + regval &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FPROPSEG_MASK | + CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | + CAN_FDCBT_FRJW_MASK); + regval |= CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */ + CAN_FDCBT_FPROPSEG(priv->data_timing.propseg) | /* Propagation + * segment (only register that doesn't add 1) */ + CAN_FDCBT_FPSEG1(priv->data_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_FDCBT_FPSEG2(priv->data_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_FDCBT_FRJW(priv->data_timing.pseg2); /* Resynchorinzation jump width same as PSEG2 */ + putreg32(regval, priv->base + IMX9_CAN_FDCBT_OFFSET); + + /* Additional CAN-FD configurations */ + + regval = getreg32(priv->base + IMX9_CAN_FDCTRL_OFFSET); + + regval |= CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */ + CAN_FDCTRL_TDCEN | /* Enable transceiver delay compensation */ + CAN_FDCTRL_TDCOFF(5) | /* Setup 5 cycles for data phase sampling delay */ + CAN_FDCTRL_MBDSR0(3) | /* Setup 64 bytes per MB 0-6 */ + CAN_FDCTRL_MBDSR1(3) | /* Setup 64 bytes per MB 7-13 */ + CAN_FDCTRL_MBDSR2(3); /* Setup 64 bytes per MB 14-20 */ + putreg32(regval, priv->base + IMX9_CAN_FDCTRL_OFFSET); + + regval = getreg32(priv->base + IMX9_CAN_CTRL2_OFFSET); + regval |= CAN_CTRL2_ISOCANFDEN; + putreg32(regval, priv->base + IMX9_CAN_CTRL2_OFFSET); + } + + /* Errata ER005829 step 7: Reserve first TX MB + * Errata mentions writng 0x8 value, but this one couses + * the ESR2_LPTM register to choose the reserved MB for + * transmiting the package, hence we write 0x3 + */ + + struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); + buffer->cs.code = 0x3; + + for (i = RXMBCOUNT + 1; i < TOTALMBCOUNT; i++) + { + struct mb_s *rx = flexcan_get_mb(priv, i); + rx->id.w = 0x0; + + /* FIXME sometimes we get a hard fault here */ + } + + putreg32(0x0, priv->base + IMX9_CAN_RXFGMASK_OFFSET); + + for (i = 0; i < TOTALMBCOUNT; i++) + { + putreg32(0, priv->base + IMX9_CAN_RXIMR_OFFSET(i)); + } + + for (i = 0; i < RXMBCOUNT; i++) + { + struct mb_s *rx = flexcan_get_mb(priv, i); + ninfo("Set MB%" PRIi32 " to receive %p\n", i, rx); + rx->cs.edl = 0x1; + rx->cs.brs = 0x1; + rx->cs.esi = 0x0; + rx->cs.code = 4; + rx->cs.srr = 0x0; + rx->cs.ide = 0x1; + rx->cs.rtr = 0x0; + } + + putreg32(IFLAG1_RX, priv->base + IMX9_CAN_IFLAG1_OFFSET); + putreg32(IFLAG1_RX, priv->base + IMX9_CAN_IMASK1_OFFSET); + + /* Exit freeze mode */ + + imx9_setfreeze(priv->base, 0); + if (!imx9_waitfreezeack_change(priv->base, 0)) + { + nerr("FLEXCAN: unfreeze fail\n"); + return -1; + } + + return 1; +} + +/**************************************************************************** + * Function: imx9_reset + * + * Description: + * Put the EMAC in the non-operational, reset state + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_reset(struct imx9_driver_s *priv) +{ + uint32_t regval; + uint32_t i; + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_SOFTRST; + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + if (!imx9_waitmcr_change(priv->base, CAN_MCR_SOFTRST, 0)) + { + nerr("Reset failed"); + return; + } + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_SUPV); + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + /* Initialize all MB rx and tx */ + + for (i = 0; i < TOTALMBCOUNT; i++) + { + struct mb_s *rx = flexcan_get_mb(priv, i); + ninfo("MB %" PRIi32 " %p\n", i, rx); + ninfo("MB %" PRIi32 " %p\n", i, &rx->id.w); + rx->cs.cs = 0x0; + rx->id.w = 0x0; + rx->data[0].w00 = 0x0; + rx->data[1].w00 = 0x0; + } + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_SLFWAK | CAN_MCR_WRNEN | CAN_MCR_SRXDIS | + CAN_MCR_IRMQ | CAN_MCR_AEN | + (((TOTALMBCOUNT - 1) << CAN_MCR_MAXMB_SHIFT) & + CAN_MCR_MAXMB_MASK); + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + regval = CAN_CTRL2_RRS | CAN_CTRL2_EACEN; + putreg32(regval, priv->base + IMX9_CAN_CTRL2_OFFSET); + + for (i = 0; i < TOTALMBCOUNT; i++) + { + putreg32(0, priv->base + IMX9_CAN_RXIMR_OFFSET(i)); + } + + /* Filtering catchall */ + + putreg32(0x3fffffff, priv->base + IMX9_CAN_RX14MASK_OFFSET); + putreg32(0x3fffffff, priv->base + IMX9_CAN_RX15MASK_OFFSET); + putreg32(0x3fffffff, priv->base + IMX9_CAN_RXMGMASK_OFFSET); + putreg32(0x0, priv->base + IMX9_CAN_RXFGMASK_OFFSET); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imx9_caninitialize + * + * Description: + * Initialize the CAN controller and driver + * + * Input Parameters: + * intf - In the case where there are multiple CAN, this value + * identifies which CAN is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int imx9_caninitialize(int intf) +{ + struct imx9_driver_s *priv; + int ret; + + switch (intf) + { +#ifdef CONFIG_IMX9_FLEXCAN1 + case 1: + priv = &g_flexcan1; + memset(priv, 0, sizeof(struct imx9_driver_s)); + priv->base = IMX9_CAN1_BASE; + priv->config = &imx9_flexcan1_config; +# if defined(CONFIG_NET_CAN_CANFD) + priv->canfd_capable = true; + priv->mb_address_offset = 14; +#endif + + /* Default bitrate configuration */ + +# if defined(CONFIG_NET_CAN_CANFD) + priv->arbi_timing.bitrate = CONFIG_FLEXCAN1_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN1_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN1_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN1_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN1_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN1_SAMPLEP; +# endif + break; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 + case 2: + priv = &g_flexcan2; + memset(priv, 0, sizeof(struct imx9_driver_s)); + priv->base = IMX9_CAN2_BASE; + priv->config = &imx9_flexcan2_config; +# if defined(CONFIG_NET_CAN_CANFD) + priv->canfd_capable = true; + priv->mb_address_offset = 14; +# else + priv->canfd_capable = false; + priv->mb_address_offset = 0; +# endif + + /* Default bitrate configuration */ + +# if defined(CONFIG_NET_CAN_CANFD) + priv->arbi_timing.bitrate = CONFIG_FLEXCAN2_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN2_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN2_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN2_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN2_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN2_SAMPLEP; +# endif + break; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN3 + case 3: + priv = &g_flexcan3; + memset(priv, 0, sizeof(struct imx9_driver_s)); + priv->base = IMX9_CAN3_BASE; + priv->config = &imx9_flexcan3_config; +# ifdef CONFIG_NET_CAN_CANFD + priv->canfd_capable = true; + priv->mb_address_offset = 14; +# else + priv->canfd_capable = false; + priv->mb_address_offset = 0; +# endif + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FLEXCAN3_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN3_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN3_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN3_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN3_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN3_SAMPLEP; +# endif + break; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN4 + case 4: + priv = &g_flexcan4; + memset(priv, 0, sizeof(struct imx9_driver_s)); + priv->base = IMX9_CAN4_BASE; + priv->config = &imx9_flexcan4_config; +# ifdef CONFIG_NET_CAN_CANFD + priv->canfd_capable = true; + priv->mb_address_offset = 14; +# else + priv->canfd_capable = false; + priv->mb_address_offset = 0; +# endif + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FLEXCAN4_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN4_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN4_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN4_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN4_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN4_SAMPLEP; +# endif + break; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN5 + case 5: + priv = &g_flexcan5; + memset(priv, 0, sizeof(struct imx9_driver_s)); + priv->base = IMX9_CAN5_BASE; + priv->config = &imx9_flexcan5_config; +# ifdef CONFIG_NET_CAN_CANFD + priv->canfd_capable = true; + priv->mb_address_offset = 14; +# else + priv->canfd_capable = false; + priv->mb_address_offset = 0; +# endif + + /* Default bitrate configuration */ + +# ifdef CONFIG_NET_CAN_CANFD + priv->arbi_timing.bitrate = CONFIG_FLEXCAN5_ARBI_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN5_ARBI_SAMPLEP; + priv->data_timing.bitrate = CONFIG_FLEXCAN5_DATA_BITRATE; + priv->data_timing.samplep = CONFIG_FLEXCAN5_DATA_SAMPLEP; +# else + priv->arbi_timing.bitrate = CONFIG_FLEXCAN5_BITRATE; + priv->arbi_timing.samplep = CONFIG_FLEXCAN5_SAMPLEP; +# endif + break; +#endif + default: + return -ENODEV; + } + + imx9_configure_clock(priv->config->clk_root, true); + + if (!imx9_bitratetotimeseg(&priv->arbi_timing, 1, 0)) + { + nerr("ERROR: Invalid CAN timings please try another sample point " + "or refer to the reference manual\n"); + return -1; + } + + if (priv->canfd_capable) + { + if (!imx9_bitratetotimeseg(&priv->data_timing, 1, 1)) + { + nerr("ERROR: Invalid CAN data phase timings please try another " + "sample point or refer to the reference manual\n"); + return -1; + } + } + + imx9_iomux_configure(priv->config->tx_pin); + imx9_iomux_configure(priv->config->rx_pin); + + if (irq_attach(priv->config->irq, imx9_flexcan_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach CAN bus IRQ\n"); + return -EAGAIN; + } + + /* Initialize the driver structure */ + + priv->dev.d_ifup = imx9_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = imx9_ifdown; /* I/F down callback */ + priv->dev.d_txavail = imx9_txavail; /* New TX data callback */ +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = imx9_ioctl; /* Support CAN ioctl() calls */ +#endif + priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */ + spin_lock_init(&priv->lock); + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling imx9_ifdown(). + */ + + ninfo("callbacks done\n"); + + imx9_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + netdev_register(&priv->dev, NET_LL_CAN); + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Name: arm_caninitialize + * + * Description: + * Initialize the first network interface. If there are more than one + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, Ethernet controllers should + * be initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm_netinitialize(void) +{ +#ifdef CONFIG_IMX9_FLEXCAN1 + imx9_caninitialize(1); +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 + imx9_caninitialize(2); +#endif + +#ifdef CONFIG_IMX9_FLEXCAN3 + imx9_caninitialize(3); +#endif + +#ifdef CONFIG_IMX9_FLEXCAN4 + imx9_caninitialize(4); +#endif + +#ifdef CONFIG_IMX9_FLEXCAN5 + imx9_caninitialize(5); +#endif +} +#endif + +#endif /* CONFIG_IMX9_FLEXCAN */ diff --git a/arch/arm/src/imx9/imx9_flexcan.h b/arch/arm/src/imx9/imx9_flexcan.h new file mode 100644 index 0000000000000..9a183ef312756 --- /dev/null +++ b/arch/arm/src/imx9/imx9_flexcan.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_flexcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H +#define __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/imx9_flexcan.h" + +#ifdef CONFIG_IMX9_FLEXCAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Function: arm_caninitialize + * + * Description: + * Initialize the enabled CAN device interfaces. If there are more + * different network devices in the chip, then board-specific logic will + * have to provide this function to determine which, if any, network + * devices should be initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called very early in the initialization sequence. + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_LATEINIT +int imx9_caninitialize(int intf); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_IMX9_FLEXCAN */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H */ diff --git a/arch/arm/src/imx9/imx9_gpio.c b/arch/arm/src/imx9/imx9_gpio.c new file mode 100644 index 0000000000000..60e20c36e8b27 --- /dev/null +++ b/arch/arm/src/imx9/imx9_gpio.c @@ -0,0 +1,281 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "chip.h" +#include "arm_internal.h" +#include "imx9_iomuxc.h" +#include "imx9_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpio_dirout + ****************************************************************************/ + +static inline void imx9_gpio_dirout(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMX9_GPIO_PDDR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, IMX9_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imx9_gpio_dirin + ****************************************************************************/ + +static inline void imx9_gpio_dirin(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMX9_GPIO_PDDR(port)); + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMX9_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imx9_gpio_setoutput + ****************************************************************************/ + +static void imx9_gpio_setoutput(uint32_t port, uint32_t pin, bool value) +{ + uintptr_t regaddr = IMX9_GPIO_PDOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + if (value) + { + regval |= GPIO_PIN(pin); + } + else + { + regval &= ~GPIO_PIN(pin); + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: imx9_gpio_getpin_status + ****************************************************************************/ + +static inline bool imx9_gpio_get_pinstatus(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMX9_GPIO_PSOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx9_gpio_getinput + ****************************************************************************/ + +static inline bool imx9_gpio_getinput(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMX9_GPIO_PDIR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx9_gpio_configinput + ****************************************************************************/ + +static int imx9_gpio_configinput(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + /* Configure pin as in input */ + + imx9_gpio_dirin(port, pin); + + return OK; +} + +/**************************************************************************** + * Name: imx9_gpio_configoutput + ****************************************************************************/ + +static inline int imx9_gpio_configoutput(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + /* Set the output value */ + + imx9_gpio_setoutput(port, pin, value); + + /* Convert the configured input GPIO to an output */ + + imx9_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imx9_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + int ret; + + /* Configure the pin as an input initially to avoid any spurious outputs */ + + flags = enter_critical_section(); + + /* Configure based upon the pin mode */ + + switch (pinset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + /* Configure the pin as a GPIO input */ + + ret = imx9_gpio_configinput(pinset); + } + break; + + case GPIO_OUTPUT: + { + /* First configure the pin as a GPIO input to avoid output + * glitches. + */ + + ret = imx9_gpio_configinput(pinset); + if (ret >= 0) + { + /* Convert the input to an output */ + + ret = imx9_gpio_configoutput(pinset); + } + } + break; + +#ifdef CONFIG_IMX9_GPIO_IRQ + case GPIO_INTERRUPT: + { + /* Configure the pin as a GPIO input */ + + ret = imx9_gpio_configinput(pinset); + if (ret == OK) + { + ret = imx9_gpioirq_configure(pinset); + } + } + break; +#endif + + default: + ret = -EINVAL; + break; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: imx9_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imx9_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + flags = enter_critical_section(); + imx9_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imx9_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imx9_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + flags = enter_critical_section(); + if ((pinset & (GPIO_OUTPUT)) == (GPIO_OUTPUT)) + { + value = imx9_gpio_get_pinstatus(port, pin); + } + else + { + value = imx9_gpio_getinput(port, pin); + } + + leave_critical_section(flags); + return value; +} diff --git a/arch/arm/src/imx9/imx9_gpio.h b/arch/arm/src/imx9/imx9_gpio.h new file mode 100644 index 0000000000000..e99b1bb2ac568 --- /dev/null +++ b/arch/arm/src/imx9/imx9_gpio.h @@ -0,0 +1,340 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H +#define __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/imx9_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pinset is a 16-bit word used to configure the GPIO settings. The + * encoding is as follows... + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MMVX BEEG GGGP PPPP + * GPIO INPUT 00.. BEEG GGGP PPPP + * INT INPUT 11.. BEEG GGGP PPPP + * GPIO OUTPUT 01V. ...G GGGP PPPP + */ + +/* Input/Output Selection: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MM.. .... .... .... + */ + +#define GPIO_MODE_SHIFT (14) /* Bits 14-15: Pin mode */ +#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */ +# define GPIO_INTERRUPT (2 << GPIO_MODE_SHIFT) /* Interrupt input */ + +/* Initial Output Value: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO OUTPUT 01V. .... .... .... + */ + +#define GPIO_OUTPUT_SHIFT (13) /* Bit 13: Initial output */ +#define GPIO_OUTPUT_MASK (0x1 << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ZERO (0 << GPIO_OUTPUT_SHIFT) /* Bit 29: 0=Initial output is low */ +# define GPIO_OUTPUT_ONE (1 << GPIO_OUTPUT_SHIFT) /* Bit 29: 1=Initial output is high */ + +/* Interrupt on both edges configuration + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * INT INPUT 11.. B... .... .... + */ + +#define GPIO_INTBOTHCFG_SHIFT (11) /* Bit 11: Interrupt both edges configuration */ +#define GPIO_INTBOTHCFG_MASK (1 << GPIO_INTBOTHCFG_SHIFT) +# define GPIO_INTBOTH_EDGES (1 << GPIO_INTBOTHCFG_SHIFT) + +/* Interrupt edge/level configuration + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * INT INPUT 11.. .EE. .... .... + */ + +#define GPIO_INTCFG_SHIFT (9) /* Bits 9-10: Interrupt edge/level configuration */ +#define GPIO_INTCFG_MASK (0x3 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (0 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (1 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (2 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (3 << GPIO_INTCFG_SHIFT) + +/* GPIO Port Number + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO IN/OUT .... ...G GGG. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bits 5-8: GPIO port index */ +#define GPIO_PORT_MASK (0xf << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */ +# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */ +# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */ +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */ +# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */ +# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */ +# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */ +# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */ +# define GPIO_PORT10 (GPIO10 << GPIO_PORT_SHIFT) /* GPIO10 */ +# define GPIO_PORT11 (GPIO11 << GPIO_PORT_SHIFT) /* GPIO11 */ +# define GPIO_PORT12 (GPIO12 << GPIO_PORT_SHIFT) /* GPIO12 */ +# define GPIO_PORT13 (GPIO13 << GPIO_PORT_SHIFT) /* GPIO13 */ + +/* GPIO Pin Number: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO IN/OUT .... .... ...P PPPP + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO pin number */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */ +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */ +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */ +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */ +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */ +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */ +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */ +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */ +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */ +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */ +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */ +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */ +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */ +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */ +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */ +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */ +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */ +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */ +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */ +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */ +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */ +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */ +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */ +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */ +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */ +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */ +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */ +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */ +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */ +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */ +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */ +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */ + +/* Port access via global LUT */ + +#define IMX9_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */ + +#define IMX9_GPIO_VERID(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_VERID_OFFSET) +#define IMX9_GPIO_PARAM(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PARAM_OFFSET) +#define IMX9_GPIO_LOCK(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_LOCK_OFFSET) +#define IMX9_GPIO_PCNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNS_OFFSET) +#define IMX9_GPIO_ICNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNS_OFFSET) +#define IMX9_GPIO_PCNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNP_OFFSET) +#define IMX9_GPIO_ICNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNP_OFFSET) +#define IMX9_GPIO_PDOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDOR_OFFSET) +#define IMX9_GPIO_PSOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PSOR_OFFSET) +#define IMX9_GPIO_PCOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCOR_OFFSET) +#define IMX9_GPIO_PTOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PTOR_OFFSET) +#define IMX9_GPIO_PDIR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDIR_OFFSET) +#define IMX9_GPIO_PDDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDDR_OFFSET) +#define IMX9_GPIO_PIDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PIDR_OFFSET) +#define IMX9_GPIO_GICLR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICLR_OFFSET) +#define IMX9_GPIO_GICHR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICHR_OFFSET) + +/* Interrupt status flags, these have two channels. Channel is selected by + * setting / clearing ICRN.IRQS bit. + */ + +#define IMX9_GPIO_ISFR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR0_OFFSET) +#define IMX9_GPIO_ISFR1(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR1_OFFSET) + +/* GPIO PIN[0...31] and ICR[0...31] */ + +#define IMX9_GPIO_P0DR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_P0DR_OFFSET) +#define IMX9_GPIO_PNDR(n, p) (IMX9_GPIO_P0DR(n) + ((p) * 0x4)) +#define IMX9_GPIO_ICR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICR0_OFFSET) +#define IMX9_GPIO_ICRN(n, p) (IMX9_GPIO_ICR0(n) + ((p) * 0x4)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the GPIO encoding */ + +typedef uint16_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base + * addresses + */ + +EXTERN const uintptr_t g_gpio_base[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +void imx9_gpioirq_initialize(void); +#else +# define imx9_gpioirq_initialize() +#endif + +/**************************************************************************** + * Name: imx9_config_gpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int imx9_config_gpio(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imx9_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imx9_gpio_write(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: imx9_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imx9_gpio_read(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imx9_gpioirq_attach + * + * Description: + * Attach a pin interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg); +#else +#define imx9_gpioirq_attach(pinset, isr, arg) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_configure(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_configure(pinset) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_enable(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_enable(pinset) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_disable(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_disable(pinset) 0 +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H */ diff --git a/arch/arm/src/imx9/imx9_gpiobase.c b/arch/arm/src/imx9/imx9_gpiobase.c new file mode 100644 index 0000000000000..a6a793e2195bb --- /dev/null +++ b/arch/arm/src/imx9/imx9_gpiobase.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_gpiobase.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imx9_gpio.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_IMX93) +/* Base address for the GPIO memory mapped registers */ + +const uintptr_t g_gpio_base[] = +{ + IMX9_GPIO1_BASE, + IMX9_GPIO2_BASE, + IMX9_GPIO3_BASE, + IMX9_GPIO4_BASE, +}; +#elif defined(CONFIG_ARCH_CHIP_IMX9_CORTEX_M) +/* Base address for the GPIO memory mapped registers */ + +const uintptr_t g_gpio_base[] = +{ + IMX9_GPIO1_BASE, + IMX9_GPIO2_BASE, + IMX9_GPIO3_BASE, + IMX9_GPIO4_BASE, +}; +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm/src/imx9/imx9_gpioirq.c b/arch/arm/src/imx9/imx9_gpioirq.c new file mode 100644 index 0000000000000..7a6e9f3de9c40 --- /dev/null +++ b/arch/arm/src/imx9/imx9_gpioirq.c @@ -0,0 +1,309 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_gpioirq.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "imx9_gpio.h" + +#ifdef CONFIG_IMX9_GPIO_IRQ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_portisr_s +{ + struct + { + xcpt_t isr; /* The interrupt service routine */ + void *arg; /* Argument passed to it */ + } + pins[IMX9_GPIO_NPINS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct imx9_portisr_s g_isrtab[IMX9_GPIO_NPORTS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpio_interrupt + * + * Description: + * GPIO interrupt handlers. iMX9 has two interrupt sources for each pin, + * the NuttX driver uses source 0. + * + ****************************************************************************/ + +static int imx9_gpio_interrupt(int irq, void *context, void *arg) +{ + uint32_t port = (uint32_t)((uintptr_t)arg) >> GPIO_PORT_SHIFT; + uint32_t status; + uint32_t pin; + uint32_t regaddr; + + /* Get the pending interrupt indications */ + + regaddr = IMX9_GPIO_ISFR0(port); + status = getreg32(regaddr); + + /* Decode the pending interrupts */ + + for (pin = 0; pin < 32 && status != 0; pin++) + { + /* Is the IRQ associated with this pin pending? */ + + uint32_t mask = (1 << pin); + if ((status & mask) != 0) + { + struct imx9_portisr_s *isrtab; + + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, regaddr); + status &= ~mask; + + /* Get the interrupt table for this port */ + + isrtab = &g_isrtab[port]; + if (isrtab->pins[pin].isr != NULL) + { + /* Run the user handler with the user's argument */ + + isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg); + } + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +void imx9_gpioirq_initialize(void) +{ + /* Do not loop over all GPIOs on IMX95 because some IOs may not be + * accessible depending on the system managers configuration + */ + +#ifndef CONFIG_ARCH_CHIP_IMX95_M7 + uint32_t port; + uint32_t pin; + + /* Disable all GPIO interrupts at the source */ + + for (port = 0; port < IMX9_GPIO_NPORTS; port++) + { + for (pin = 0; pin < IMX9_GPIO_NPINS; pin++) + { + /* Reset the interrupt configuration, disabling the interrupt */ + + putreg32(0, IMX9_GPIO_ICRN(port, pin)); + } + } +#endif /* CONFIG_ARCH_CHIP_IMX95_M7 */ + + /* Disable all GPIO interrupts */ + + up_disable_irq(IMX9_IRQ_GPIO1_0); + up_disable_irq(IMX9_IRQ_GPIO1_1); + + up_disable_irq(IMX9_IRQ_GPIO2_0); + up_disable_irq(IMX9_IRQ_GPIO2_1); + + up_disable_irq(IMX9_IRQ_GPIO3_0); + up_disable_irq(IMX9_IRQ_GPIO3_1); + + up_disable_irq(IMX9_IRQ_GPIO4_0); + up_disable_irq(IMX9_IRQ_GPIO4_1); + + /* Attach the common GPIO interrupt handler and enable the interrupt */ + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO1_0, + imx9_gpio_interrupt, (void *)GPIO_PORT1)); + up_enable_irq(IMX9_IRQ_GPIO1_0); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO2_0, + imx9_gpio_interrupt, (void *)GPIO_PORT2)); + up_enable_irq(IMX9_IRQ_GPIO2_0); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO3_0, + imx9_gpio_interrupt, (void *)GPIO_PORT3)); + up_enable_irq(IMX9_IRQ_GPIO3_0); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO4_0, + imx9_gpio_interrupt, (void *)GPIO_PORT4)); + up_enable_irq(IMX9_IRQ_GPIO4_0); +} + +/**************************************************************************** + * Name: imx9_gpioirq_attach + * + * Description: + * Attach a pin interrupt handler. + * + ****************************************************************************/ + +int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Atomically change the handler */ + + irqstate_t flags = enter_critical_section(); + + g_isrtab[port].pins[pin].isr = isr; + g_isrtab[port].pins[pin].arg = arg; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ****************************************************************************/ + +int imx9_gpioirq_configure(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Nothing much to do here, just reset the IRQ config */ + + putreg32(0, IMX9_GPIO_ICRN(port, pin)); + + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +int imx9_gpioirq_enable(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t both = (pinset & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT; + uint32_t icr = (pinset & GPIO_INTCFG_MASK); + uint32_t regval; + uintptr_t regaddr; + + /* Perform RMW to the specific pin */ + + regaddr = IMX9_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMX9_GPIO_ICRN_MASK; + + if (both) + { + regval |= IMX9_GPIO_ICRN_BOTH; + } + else if (icr == GPIO_INT_LOWLEVEL) + { + regval |= IMX9_GPIO_ICRN_ZERO; + } + else if (icr == GPIO_INT_HIGHLEVEL) + { + regval |= IMX9_GPIO_ICRN_ONE; + } + else if (icr == GPIO_INT_RISINGEDGE) + { + regval |= IMX9_GPIO_ICRN_RISING; + } + else /* GPIO_INT_FALLINGEDGE */ + { + regval |= IMX9_GPIO_ICRN_FALLING; + } + + putreg32(regval, regaddr); + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +int imx9_gpioirq_disable(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t regval; + uintptr_t regaddr; + + /* Perform RMW to the specific pin */ + + regaddr = IMX9_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMX9_GPIO_ICRN_MASK; + + putreg32(regval, regaddr); + return OK; +} + +#endif /* CONFIG_IMX9_GPIO_IRQ */ diff --git a/arch/arm/src/imx9/imx9_idle.c b/arch/arm/src/imx9/imx9_idle.c new file mode 100644 index 0000000000000..f46f73aa4be9f --- /dev/null +++ b/arch/arm/src/imx9/imx9_idle.c @@ -0,0 +1,174 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_idle.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = enter_critical_section(); + + /* Perform board-specific, state-dependent logic here */ + + pwrinfo("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + imx9_pmstop(true); + break; + + case PM_SLEEP: + imx9_pmstandby(); + break; + + default: + break; + } + + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* Sleep until an interrupt occurs to save power. */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} diff --git a/arch/arm/src/imx9/imx9_iomuxc.c b/arch/arm/src/imx9/imx9_iomuxc.c new file mode 100644 index 0000000000000..37c481bd11c8e --- /dev/null +++ b/arch/arm/src/imx9/imx9_iomuxc.c @@ -0,0 +1,207 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_iomuxc.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm_internal.h" +#include "hardware/imx9_memorymap.h" +#include "imx9_iomuxc.h" + +#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI +#include "imx9_scmi.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + * Input Parameters: + * cfg - The IOMUX configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI + +/* Sets the IOMUXC pin mux mode. + */ + +void imx9_sm_iomucx_configure(sm_pinctrl_t *sm_pinctrl) +{ + scmi_pin_config_t configs[4]; + uint32_t num_configs = 0; + uint32_t channel = sm_pinctrl->channel; + uint32_t mux_register = sm_pinctrl->mux_register; + uint32_t mux_mode = sm_pinctrl->mux_mode; + uint32_t input_register = sm_pinctrl->input_register; + uint32_t input_daisy = sm_pinctrl->input_daisy; + uint32_t input_on_field = sm_pinctrl->input_on_field; + uint32_t config_register = sm_pinctrl->config_register; + uint32_t config_value = sm_pinctrl->config_value; + + if (mux_register) + { + configs[num_configs].type = SCMI_PINCTRL_TYPE_MUX; + configs[num_configs].value = SM_PLATFORM_PINCTRL_MUX_MODE(mux_mode) + | SM_PLATFORM_PINCTRL_SION( + input_on_field); + num_configs++; + } + + if (input_register & 0xffff) + { + configs[num_configs].type = SCMI_PINCTRL_TYPE_DAISY_ID; + configs[num_configs].value = + (input_register - SM_PLATFORM_PINCTRL_DAISYREG_OFF) / 4; + num_configs++; + configs[num_configs].type = SCMI_PINCTRL_TYPE_DAISY_CFG; + configs[num_configs].value = input_daisy; + num_configs++; + } + + if (config_register) + { + configs[num_configs].type = SCMI_PINCTRL_TYPE_CONFIG; + configs[num_configs].value = config_value; + num_configs++; + } + + if (mux_register || input_register) + { + uint32_t attributes = SCMI_PINCTRL_SET_ATTR_SELECTOR( + SCMI_PINCTRL_SEL_PIN) + | SCMI_PINCTRL_SET_ATTR_NUM_CONFIGS( + num_configs); + + imx9_scmi_pinctrlconfigset( + channel, (mux_register - SM_PLATFORM_PINCTRL_MUXREG_OFF) / 4, + attributes, configs); + } +} + +#endif + +int imx9_iomux_configure(iomux_cfg_t cfg) +{ +#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI + sm_pinctrl_t sm_pinctrl = + { + 0 + }; + + sm_pinctrl.channel = SM_PLATFORM_A2P; + sm_pinctrl.mux_register = IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff; + sm_pinctrl.mux_mode = cfg.padcfg.mode; + sm_pinctrl.input_register = IMX9_IOMUXC_BASE + cfg.padcfg.dsyregoff; + sm_pinctrl.input_daisy = cfg.padcfg.dsy; + sm_pinctrl.config_register = IMX9_IOMUXC_BASE + cfg.padcfg.padregoff; + sm_pinctrl.config_value = cfg.pad; + sm_pinctrl.input_on_field = cfg.sion; + + imx9_sm_iomucx_configure(&sm_pinctrl); +#else + if (!cfg.padcfg.ctlregoff) + { + return -EINVAL; + } + + putreg32(cfg.padcfg.mode | (cfg.sion << IOMUXC_MUX_SION_SHIFT), + IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff); + + if (cfg.padcfg.dsyregoff) + { + putreg32(cfg.padcfg.dsy, IMX9_IOMUXC_BASE + cfg.padcfg.dsyregoff); + } + + if (cfg.padcfg.padregoff) + { + putreg32(cfg.pad << IOMUXC_PAD_CONFIG_SHIFT, + IMX9_IOMUXC_BASE + cfg.padcfg.padregoff); + } + + return OK; +#endif +} + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This can be used to forcibly set a pad to GPIO mode. This overrides and + * disconnects any peripheral using the pin. + * + * Input Parameters: + * cfg - The IOMUX configuration. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion) +{ + uint32_t reg_sion; + + if (!cfg.padcfg.ctlregoff) + { + return -EINVAL; + } + + /* Set sion if requested to do so */ + + reg_sion = sion ? IOMUXC_MUX_SION_ON : 0; + + /* Based on pad number, either ALT0/ALT5 sets the pad as GPIO */ + + if ((cfg.padcfg.ctlregoff >= IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) + && (cfg.padcfg.ctlregoff <= IOMUXC_MUX_CTL_GPIO_IO37_OFFSET)) + { + putreg32(IOMUXC_MUX_MODE_ALT0 | reg_sion, + IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff); + } + + else + { + putreg32(IOMUXC_MUX_MODE_ALT5 | reg_sion, + IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff); + } + + return OK; +} diff --git a/arch/arm/src/imx9/imx9_iomuxc.h b/arch/arm/src/imx9/imx9_iomuxc.h new file mode 100644 index 0000000000000..8213011f25198 --- /dev/null +++ b/arch/arm/src/imx9/imx9_iomuxc.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_iomuxc.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H +#define __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/imx9_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOMUXC_PAD_CONFIG_SHIFT 1 + +#define IOMUX_PADCFG(_ctlregoff, _mode, _dsyregoff, _dsy, _padregoff) \ + { \ + .ctlregoff = (_ctlregoff), \ + .padregoff = (_padregoff), \ + .dsyregoff = (_dsyregoff), \ + .mode = (_mode), \ + .dsy = (_dsy), \ + } + +#define IOMUX_CFG(_padcfg, _pad, _sion) \ + (iomux_cfg_t) \ + { \ + .padcfg = _padcfg, \ + .pad = (_pad) >> IOMUXC_PAD_CONFIG_SHIFT, \ + .sion = (_sion) >> IOMUXC_MUX_SION_SHIFT, \ + } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Information for the pad alternate function */ + +struct iomux_padcfg_s +{ + /* Register offsets for PAD + * ALT(mode) configuration for ctlreg + * input daisy(dsy) configuration for dsyreg + */ + + uint16_t mode : 3; + uint16_t ctlregoff : 13; + uint16_t padregoff : 16; + uint16_t dsy : 3; + uint16_t dsyregoff : 13; +}; + +struct iomux_cfg_s +{ + struct iomux_padcfg_s padcfg; + + /* Register values */ + + uint32_t pad :31; + uint32_t sion : 1; +}; +typedef struct iomux_cfg_s iomux_cfg_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + * Input Parameters: + * cfg - The IOMUX configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_configure(iomux_cfg_t cfg); + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This can be used to forcibly set a pad to GPIO mode. This overrides and + * disconnects any peripheral using the pin. + * + * Input Parameters: + * cfg - The IOMUX configuration. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H */ diff --git a/arch/arm/src/imx9/imx9_irq.c b/arch/arm/src/imx9/imx9_irq.c new file mode 100644 index 0000000000000..6430c0e036b88 --- /dev/null +++ b/arch/arm/src/imx9/imx9_irq.c @@ -0,0 +1,670 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "nvic.h" +#include "ram_vectors.h" +#include "arm_internal.h" + +#ifdef CONFIG_IMX9_GPIO_IRQ +# include "imx9_gpio.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void imx9_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x " + "SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), + getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), + getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), + getreg32(NVIC_IRQ32_63_ENABLE), + getreg32(NVIC_IRQ64_95_ENABLE), + getreg32(NVIC_IRQ96_127_ENABLE)); +#if IMX9_IRQ_NEXTINT > 128 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ128_159_ENABLE), + getreg32(NVIC_IRQ160_191_ENABLE), + getreg32(NVIC_IRQ192_223_ENABLE), + getreg32(NVIC_IRQ224_239_ENABLE)); +#endif + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), + getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), + getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), + getreg32(NVIC_IRQ12_15_PRIORITY)); +#if IMX9_IRQ_NEXTINT > 16 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), + getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), + getreg32(NVIC_IRQ28_31_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 32 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), + getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), + getreg32(NVIC_IRQ44_47_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 48 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), + getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY), + getreg32(NVIC_IRQ60_63_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 64 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ64_67_PRIORITY), + getreg32(NVIC_IRQ68_71_PRIORITY), + getreg32(NVIC_IRQ72_75_PRIORITY), + getreg32(NVIC_IRQ76_79_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 80 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ80_83_PRIORITY), + getreg32(NVIC_IRQ84_87_PRIORITY), + getreg32(NVIC_IRQ88_91_PRIORITY), + getreg32(NVIC_IRQ92_95_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 96 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ96_99_PRIORITY), + getreg32(NVIC_IRQ100_103_PRIORITY), + getreg32(NVIC_IRQ104_107_PRIORITY), + getreg32(NVIC_IRQ108_111_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 112 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ112_115_PRIORITY), + getreg32(NVIC_IRQ116_119_PRIORITY), + getreg32(NVIC_IRQ120_123_PRIORITY), + getreg32(NVIC_IRQ124_127_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 128 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ128_131_PRIORITY), + getreg32(NVIC_IRQ132_135_PRIORITY), + getreg32(NVIC_IRQ136_139_PRIORITY), + getreg32(NVIC_IRQ140_143_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 144 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ144_147_PRIORITY), + getreg32(NVIC_IRQ148_151_PRIORITY), + getreg32(NVIC_IRQ152_155_PRIORITY), + getreg32(NVIC_IRQ156_159_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 160 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ160_163_PRIORITY), + getreg32(NVIC_IRQ164_167_PRIORITY), + getreg32(NVIC_IRQ168_171_PRIORITY), + getreg32(NVIC_IRQ172_175_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 176 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ176_179_PRIORITY), + getreg32(NVIC_IRQ180_183_PRIORITY), + getreg32(NVIC_IRQ184_187_PRIORITY), + getreg32(NVIC_IRQ188_191_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 192 + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ192_195_PRIORITY), + getreg32(NVIC_IRQ196_199_PRIORITY), + getreg32(NVIC_IRQ200_203_PRIORITY), + getreg32(NVIC_IRQ204_207_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 208 + irqinfo(" %08x %08x %08x\n", + getreg32(NVIC_IRQ208_211_PRIORITY), + getreg32(NVIC_IRQ212_215_PRIORITY), + getreg32(NVIC_IRQ216_219_PRIORITY)); +#endif +#if IMX9_IRQ_NEXTINT > 218 +# warning Missing logic +#endif + + leave_critical_section(flags); +} +#else +# define imx9_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: imx9_nmi, imx9_pendsv, imx9_pendsv, imx9_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int imx9_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int imx9_pendsv(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int imx9_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: imx9_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +static inline void imx9_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} + +/**************************************************************************** + * Name: imx9_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int imx9_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + unsigned int extint = irq - IMX9_IRQ_EXTINT; + + DEBUGASSERT(irq >= IMX9_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= IMX9_IRQ_EXTINT) + { + if (extint < 32) + { + *regaddr = (NVIC_IRQ0_31_ENABLE + offset); + *bit = 1 << extint; + } + else +#if IMX9_IRQ_NEXTINT > 32 + if (extint < 64) + { + *regaddr = (NVIC_IRQ32_63_ENABLE + offset); + *bit = 1 << (extint - 32); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 64 + if (extint < 96) + { + *regaddr = (NVIC_IRQ64_95_ENABLE + offset); + *bit = 1 << (extint - 64); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 96 + if (extint < 128) + { + *regaddr = (NVIC_IRQ96_127_ENABLE + offset); + *bit = 1 << (extint - 96); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 128 + if (extint < 160) + { + *regaddr = (NVIC_IRQ128_159_ENABLE + offset); + *bit = 1 << (extint - 128); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 160 + if (extint < 192) + { + *regaddr = (NVIC_IRQ160_191_ENABLE + offset); + *bit = 1 << (extint - 160); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 192 + if (extint < 219) + { + *regaddr = (NVIC_IRQ192_223_ENABLE + offset); + *bit = 1 << (extint - 192); + } + else +#endif +#if IMX9_IRQ_NEXTINT > 218 +# error Missing logic +#endif + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == IMX9_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == IMX9_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == IMX9_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == IMX9_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uintptr_t regaddr; + int nintlines; + int i; + + /* The NVIC ICTR register (bits 0-4) holds the number of interrupt + * lines that the NVIC supports, defined in groups of 32. That is, + * the total number of interrupt lines is up to (32*(INTLINESNUM+1)). + * + * 0 -> 32 interrupt lines, 1 enable register, 8 priority registers + * 1 -> 64 " " " ", 2 enable registers, 16 priority registers + * 2 -> 96 " " " ", 3 enable registers, 24 priority registers + * ... + */ + + nintlines = (getreg32(NVIC_ICTR) & NVIC_ICTR_INTLINESNUM_MASK) + 1; + + /* Disable all interrupts. There are nintlines interrupt enable + * registers. + */ + + for (i = nintlines, regaddr = NVIC_IRQ0_31_CLEAR; + i > 0; + i--, regaddr += 4) + { + putreg32(0xffffffff, regaddr); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + arm_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* Now set all of the interrupt lines to the default priority. There are + * nintlines * 8 priority registers. + */ + + for (i = (nintlines << 3), regaddr = NVIC_IRQ0_3_PRIORITY; + i > 0; + i--, regaddr += 4) + { + putreg32(DEFPRIORITY32, regaddr); + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(IMX9_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(IMX9_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(IMX9_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + imx9_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(IMX9_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(IMX9_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(IMX9_IRQ_NMI, imx9_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(IMX9_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(IMX9_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(IMX9_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(IMX9_IRQ_PENDSV, imx9_pendsv, NULL); + arm_enable_dbgmonitor(); + irq_attach(IMX9_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(IMX9_IRQ_RESERVED, imx9_reserved, NULL); +#endif + + imx9_dumpnvic("initial", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + */ + +#ifdef CONFIG_IMX9_GPIO_IRQ + imx9_gpioirq_initialize(); +#endif + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (imx9_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= IMX9_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } +#ifdef CONFIG_IMX9_GPIO_IRQ + else + { + /* Maybe it is a (derived) GPIO IRQ */ + + imx9_gpioirq_disable(irq); + } +#endif + +#if 0 /* Might be useful in early bring-up */ + imx9_dumpnvic("disable", irq); +#endif +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (imx9_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= IMX9_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } +#ifdef CONFIG_IMX9_GPIO_IRQ + else + { + /* Maybe it is a (derived) GPIO IRQ */ + + imx9_gpioirq_enable(irq); + } +#endif + +#if 0 /* Might be useful in early bring-up */ + imx9_dumpnvic("enable", irq); +#endif +} + +/**************************************************************************** + * Name: arm_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= IMX9_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < IMX9_IRQ_EXTINT) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= IMX9_IRQ_EXTINT; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + imx9_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/imx9/imx9_lowputc.c b/arch/arm/src/imx9/imx9_lowputc.c new file mode 100644 index 0000000000000..496c33d0b52fc --- /dev/null +++ b/arch/arm/src/imx9/imx9_lowputc.c @@ -0,0 +1,592 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lowputc.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_lpuart.h" + +#include "arm_internal.h" + +#include "imx9_lowputc.h" +#include "imx9_clockconfig.h" +#include "imx9_iomuxc.h" +#include "hardware/imx9_clock.h" +#include "hardware/imx9_pinmux.h" + +#include /* Include last: has dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 0 +# define IMX9_CONSOLE_BASE IMX9_LPUART1_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART1_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART1_2STOP +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 1 +# define IMX9_CONSOLE_BASE IMX9_LPUART2_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART2_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART2_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART2_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART2_2STOP +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 2 +# define IMX9_CONSOLE_BASE IMX9_LPUART3_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART3_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART3_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART3_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART3_2STOP +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 3 +# define IMX9_CONSOLE_BASE IMX9_LPUART4_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART4_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART4_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART4_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART4_2STOP +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 4 +# define IMX9_CONSOLE_BASE IMX9_LPUART5_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART5_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART5_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART5_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART5_2STOP +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 5 +# define IMX9_CONSOLE_BASE IMX9_LPUART6_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART6_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART6_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART6_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART6_2STOP +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 6 +# define IMX9_CONSOLE_BASE IMX9_LPUART7_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART7_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART7_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART7_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART7_2STOP +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 7 +# define IMX9_CONSOLE_BASE IMX9_LPUART8_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART8_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART8_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART8_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART8_2STOP +#endif + +/* Clocking *****************************************************************/ + +/* Functional clocking is provided via the PCC. The PCC clocking must + * be configured by board-specific logic prior to using the LPUART. + */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef IMX9_CONSOLE_BASE +static const struct uart_config_s g_console_config = +{ + .baud = IMX9_CONSOLE_BAUD, /* Configured baud */ + .parity = IMX9_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */ + .bits = IMX9_CONSOLE_BITS, /* Number of bits (5-9) */ + .stopbits2 = IMX9_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imx9_lowsetup(void) +{ +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + +#ifdef CONFIG_IMX9_LPUART1 + /* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART1_RX); + imx9_iomux_configure(MUX_LPUART1_TX); +#ifdef CONFIG_LPUART1_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART1_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART1_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART2 + + /* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART2_RX); + imx9_iomux_configure(MUX_LPUART2_TX); +#ifdef CONFIG_LPUART2_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART2_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART2_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART3 + + /* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART3_RX); + imx9_iomux_configure(MUX_LPUART3_TX); +#ifdef CONFIG_LPUART3_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART3_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART3_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART4 + + /* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART4_RX); + imx9_iomux_configure(MUX_LPUART4_TX); +#ifdef CONFIG_LPUART4_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART4_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART4_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART5 + + /* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART5_RX); + imx9_iomux_configure(MUX_LPUART5_TX); +#ifdef CONFIG_LPUART5_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART5_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART5_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART6 + + /* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART6_RX); + imx9_iomux_configure(MUX_LPUART6_TX); +#ifdef CONFIG_LPUART6_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART6_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART6_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART7 + + /* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART7_RX); + imx9_iomux_configure(MUX_LPUART7_TX); +#ifdef CONFIG_LPUART7_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART7_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART7_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART8 + + /* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART8_RX); + imx9_iomux_configure(MUX_LPUART8_TX); +#ifdef CONFIG_LPUART0_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART8_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART8_RTS); +#endif +#endif + +#ifdef IMX9_CONSOLE_BASE + /* Configure the serial console for initial, non-interrupt driver mode */ + + imx9_lpuart_configure(IMX9_CONSOLE_BASE, IMX9_CONSOLE_DEVNUM, + &g_console_config); +#endif + +#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */ +} + +/**************************************************************************** + * Name: imx9_lpuart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +int imx9_lpuart_configure(uint32_t base, int uartnum, + const struct uart_config_s *config) +{ + uint32_t lpuart_freq; + clock_config_t lpuart_config; + uint16_t sbr; + uint16_t temp_sbr; + uint32_t osr; + uint32_t temp_osr; + int temp_diff; + int configured_baud = config->baud; + int calculated_baud; + int baud_diff; + uint32_t regval; + + switch (base) + { +#ifdef LPUART1_CLK + case IMX9_LPUART1_BASE: + lpuart_config = LPUART1_CLK; + break; +#endif + +#ifdef LPUART2_CLK + case IMX9_LPUART2_BASE: + lpuart_config = LPUART2_CLK; + break; +#endif + +#ifdef LPUART3_CLK + case IMX9_LPUART3_BASE: + lpuart_config = LPUART3_CLK; + break; +#endif + +#ifdef LPUART4_CLK + case IMX9_LPUART4_BASE: + lpuart_config = LPUART4_CLK; + break; +#endif + +#ifdef LPUART5_CLK + case IMX9_LPUART5_BASE: + lpuart_config = LPUART5_CLK; + break; +#endif + +#ifdef LPUART6_CLK + case IMX9_LPUART6_BASE: + lpuart_config = LPUART6_CLK; + break; +#endif + +#ifdef LPUART7_CLK + case IMX9_LPUART7_BASE: + lpuart_config = LPUART7_CLK; + break; +#endif + +#ifdef LPUART8_CLK + case IMX9_LPUART7_BASE: + lpuart_config = LPUART8_CLK; + break; +#endif + + default: + return ERROR; + } + + /* Configure root clock */ + + imx9_configure_clock(lpuart_config, true); + + imx9_get_rootclock(GET_CLOCK_ROOT(lpuart_config), &lpuart_freq); + + /* This LPUART instantiation uses a slightly different baud rate + * calculation. The idea is to use the best OSR (over-sampling rate) + * possible. + * + * NOTE: OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum + * baud_diff iterate through the rest of the supported values of OSR + */ + + baud_diff = configured_baud; + osr = 0; + sbr = 0; + + for (temp_osr = 4; temp_osr <= 32; temp_osr++) + { + /* Calculate the temporary sbr value */ + + temp_sbr = (lpuart_freq / (configured_baud * temp_osr)); + + /* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the + * desired baud rate. + */ + + if (temp_sbr == 0) + { + temp_sbr = 1; + } + + /* Calculate the baud rate based on the temporary OSR and SBR values */ + + calculated_baud = (lpuart_freq / (temp_osr * temp_sbr)); + temp_diff = abs(calculated_baud - configured_baud); + + /* Select the better value between srb and (sbr + 1) */ + + calculated_baud = (lpuart_freq / (temp_osr * (temp_sbr + 1))); + if (temp_diff > + abs(calculated_baud - configured_baud)) + { + temp_diff = abs(calculated_baud - configured_baud); + temp_sbr++; + } + + if (temp_diff <= baud_diff) + { + baud_diff = temp_diff; + osr = temp_osr; + sbr = temp_sbr; + } + } + + if (baud_diff > ((configured_baud * 3) / 100)) + { + /* Unacceptable baud rate difference of more than 3% */ + + return ERROR; + } + + /* Reset all internal logic and registers, except the Global Register */ + + regval = getreg32(base + IMX9_LPUART_GLOBAL_OFFSET); + regval |= LPUART_GLOBAL_RST; + putreg32(regval, base + IMX9_LPUART_GLOBAL_OFFSET); + + regval &= ~LPUART_GLOBAL_RST; + putreg32(regval, base + IMX9_LPUART_GLOBAL_OFFSET); + + /* Enable RX and TX FIFOs */ + + putreg32(LPUART_FIFO_RXFE | LPUART_FIFO_TXFE, + base + IMX9_LPUART_FIFO_OFFSET); + + /* Construct MODIR register */ + + regval = 0; + + if (config->userts) + { + regval |= LPUART_MODIR_RXRTSE; + } + else if (config->users485) + { + /* Both TX and RX side can't control RTS, so this gives + * the RX side precedence. This should have been filtered + * in layers above anyway, but it's just a precaution. + */ + + regval |= LPUART_MODIR_TXRTSE; + } + + if (config->usects) + { + regval |= LPUART_MODIR_TXCTSE; + } + + if (config->invrts) + { + regval |= LPUART_MODIR_TXRTSPOL; + } + + putreg32(regval, base + IMX9_LPUART_MODIR_OFFSET); + + regval = 0; + + if ((osr > 3) && (osr < 8)) + { + regval |= LPUART_BAUD_BOTHEDGE; + } + + if (config->stopbits2) + { + regval |= LPUART_BAUD_SBNS; + } + + regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr); + putreg32(regval, base + IMX9_LPUART_BAUD_OFFSET); + + regval = 0; + if (config->parity == 1) + { + regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD; + } + else if (config->parity == 2) + { + regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN; + } + + if (config->bits == 9 || (config->bits == 8 && config->parity != 0)) + { + regval |= LPUART_CTRL_M; + } + else if ((config->bits == 8)) + { + regval &= ~LPUART_CTRL_M; + } + else + { + /* REVISIT: Here should be added support of other bit modes. */ + + return -ENOSYS; + } + + regval |= LPUART_CTRL_RE | LPUART_CTRL_TE; + putreg32(regval, base + IMX9_LPUART_CTRL_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: arm_earlyprintinit + * + * Description: + * Configure LPUART1 for non-interrupt driven operation + * + ****************************************************************************/ + +void arm_earlyprintinit(char ch) +{ + /* Assume bootloader has already set up the LPUART1 */ +} + +/**************************************************************************** + * Name: arm_lowputc + * + * Description: + * Output a byte with as few system dependencies as possible. This will + * even work BEFORE the console is initialized if we are booting from U- + * Boot (and the same UART is used for the console, of course.) + * + ****************************************************************************/ + +void arm_lowputc(char ch) +{ +#ifdef IMX9_CONSOLE_BASE + while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) & + LPUART_STAT_TDRE) == 0) + { + } + + /* If the character to output is a newline, + * then pre-pend a carriage return + */ + + if (ch == '\n') + { + /* Send the carriage return by writing it into the UART_TXD register. */ + + putreg32((uint32_t)'\r', + IMX9_CONSOLE_BASE + IMX9_LPUART_DATA_OFFSET); + + /* Wait for the transmit register to be emptied. When the TXFE bit is + * non-zero, the TX Buffer FIFO is empty. + */ + + while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) & + LPUART_STAT_TDRE) == 0) + { + } + } + + /* Send the character by writing it into the UART_TXD register. */ + + putreg32((uint32_t)ch, IMX9_CONSOLE_BASE + IMX9_LPUART_DATA_OFFSET); + + /* Wait for the transmit register to be emptied. When the TXFE bit is + * non-zero, the TX Buffer FIFO is empty. + */ + + while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) & + LPUART_STAT_TDRE) == 0) + { + } +#endif +} diff --git a/arch/arm/src/imx9/imx9_lowputc.h b/arch/arm/src/imx9/imx9_lowputc.h new file mode 100644 index 0000000000000..e3ff409b44f97 --- /dev/null +++ b/arch/arm/src/imx9/imx9_lowputc.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lowputc.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H +#define __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + bool userts; /* True: Assert RTS when there are data to be sent */ + bool invrts; /* True: Invert sense of RTS pin (true=active high) */ + bool usects; /* True: Condition transmission on CTS asserted */ + bool users485; /* True: Assert RTS while transmission progresses */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Name: imx9_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imx9_lowsetup(void); + +/**************************************************************************** + * Name: imx9_lpuart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +int imx9_lpuart_configure(uint32_t base, + int uartnum, + const struct uart_config_s *config); + +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H */ diff --git a/arch/arm/src/imx9/imx9_lpi2c.c b/arch/arm/src/imx9/imx9_lpi2c.c new file mode 100644 index 0000000000000..1766b706e86fe --- /dev/null +++ b/arch/arm/src/imx9/imx9_lpi2c.c @@ -0,0 +1,2451 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lpi2c.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "imx9_clockconfig.h" +#include "imx9_gpio.h" +#include "imx9_iomuxc.h" +#include "imx9_lpi2c.h" + +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_lpi2c.h" + +#ifdef CONFIG_IMX9_LPI2C_DMA +# include "chip.h" +# include "imx9_edma.h" +# include "hardware/imx9_dmamux.h" +#endif + +/* At least one I2C peripheral must be enabled */ + +#ifdef CONFIG_IMX9_LPI2C + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_IMX9_LPI2C_TIMEOSEC) && \ + !defined(CONFIG_IMX9_LPI2C_TIMEOMS) +# define CONFIG_IMX9_LPI2C_TIMEOSEC 0 +# define CONFIG_IMX9_LPI2C_TIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_IMX9_LPI2C_TIMEOSEC) +# define CONFIG_IMX9_LPI2C_TIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_IMX9_LPI2C_TIMEOMS) +# define CONFIG_IMX9_LPI2C_TIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_IMX9_LPI2C_TIMEOTICKS +# define CONFIG_IMX9_LPI2C_TIMEOTICKS \ + (SEC2TICK(CONFIG_IMX9_LPI2C_TIMEOSEC) + \ + MSEC2TICK(CONFIG_IMX9_LPI2C_TIMEOMS)) +#endif + +#ifndef CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP +# define CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP \ + TICK2USEC(CONFIG_IMX9_LPI2C_TIMEOTICKS) +#endif + +/* Debug ********************************************************************/ + +/* I2C event trace logic. NOTE: trace uses the internal, non-standard, + * low-level debug interface syslog() but does not require that any other + * debug is enabled. + */ + +#ifndef CONFIG_I2C_TRACE +# define imx9_lpi2c_tracereset(p) +# define imx9_lpi2c_tracenew(p,s) +# define imx9_lpi2c_traceevent(p,e,a) +# define imx9_lpi2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +#ifdef CONFIG_I2C_SLAVE +# error I2C slave logic is not supported yet for IMX9 +#endif + +#define LPI2C_MASTER 1 +#define LPI2C_SLAVE 2 + +#define LPI2C_MSR_LIMITED_ERROR_MASK (LPI2C_MSR_ERROR_MASK & ~(LPI2C_MSR_FEF)) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum imx9_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum imx9_trace_e +{ + I2CEVENT_NONE = 0, /* No events have occurred with this status */ + I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ + I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ + I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ + I2CEVENT_NOSTART, /* BTF on last byte with no restart, param = msgc */ + I2CEVENT_STARTRESTART, /* Last byte sent, re-starting, param = msgc */ + I2CEVENT_STOP, /* Last byte sten, send stop, param = 0 */ + I2CEVENT_ERROR /* Error occurred, param = 0 */ +}; + +/* Trace data */ + +struct imx9_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum imx9_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct imx9_lpi2c_config_s +{ + uint32_t base; /* LPI2C base address */ + uint32_t clk_root; /* LPI2C clock root */ + uint16_t busy_idle; /* LPI2C Bus Idle Timeout */ + uint8_t filtscl; /* Glitch Filter for SCL pin */ + uint8_t filtsda; /* Glitch Filter for SDA pin */ + iomux_cfg_t scl_pin; /* Peripheral configuration for SCL as SCL */ + iomux_cfg_t sda_pin; /* Peripheral configuration for SDA as SDA */ +#if defined(CONFIG_I2C_RESET) + gpio_pinset_t reset_scl_pin; /* GPIO configuration for SCL as GPIO */ + gpio_pinset_t reset_sda_pin; /* GPIO configuration for SDA as GPIO */ +#endif + uint8_t mode; /* Master or Slave mode */ +#ifndef CONFIG_I2C_POLLED + uint32_t irq; /* Event IRQ */ +#endif +#ifdef CONFIG_IMX9_LPI2C_DMA + uint32_t dma_rxreqsrc; /* DMA mux rx source */ + uint32_t dma_txreqsrc; /* DMA mux tx source */ +#endif +}; + +/* I2C Device Private Data */ + +struct imx9_lpi2c_priv_s +{ + /* Standard I2C operations */ + + const struct i2c_ops_s *ops; + + /* Port configuration */ + + const struct imx9_lpi2c_config_s *config; + + int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion mutex */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum imx9_intstate_e) */ + + int8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct imx9_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ + +#ifdef CONFIG_IMX9_LPI2C_DMA + DMACH_HANDLE rxdma; /* rx DMA handle */ + DMACH_HANDLE txdma; /* tx DMA handle */ + uint16_t cmnds[CONFIG_IMX9_LPI2C_DMA_MAXMSG]; /* Commands */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getreg(struct imx9_lpi2c_priv_s *priv, uint16_t offset); +static inline void imx9_lpi2c_putreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t value); +static inline void imx9_lpi2c_modifyreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t clearbits, + uint32_t setbits); + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO +static uint32_t imx9_lpi2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_IMX9_LPI2C_DYNTIMEO */ + +static inline int +imx9_lpi2c_sem_waitdone(struct imx9_lpi2c_priv_s *priv); + +#ifdef CONFIG_I2C_TRACE +static void imx9_lpi2c_tracereset(struct imx9_lpi2c_priv_s *priv); +static void imx9_lpi2c_tracenew(struct imx9_lpi2c_priv_s *priv, + uint32_t status); +static void imx9_lpi2c_traceevent(struct imx9_lpi2c_priv_s *priv, + enum imx9_trace_e event, uint32_t parm); +static void imx9_lpi2c_tracedump(struct imx9_lpi2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ + +static void imx9_lpi2c_setclock(struct imx9_lpi2c_priv_s *priv, + uint32_t frequency); +static inline void imx9_lpi2c_sendstart(struct imx9_lpi2c_priv_s *priv, + uint8_t address); +static inline void imx9_lpi2c_sendstop(struct imx9_lpi2c_priv_s *priv); +static inline uint32_t +imx9_lpi2c_getstatus(struct imx9_lpi2c_priv_s *priv); + +static int imx9_lpi2c_isr_process(struct imx9_lpi2c_priv_s *priv); + +#ifndef CONFIG_I2C_POLLED +static int imx9_lpi2c_isr(int irq, void *context, void *arg); +#endif /* !CONFIG_I2C_POLLED */ + +static void imx9_lpi2c_clock_enable(struct imx9_lpi2c_priv_s *priv); +static void imx9_lpi2c_clock_disable(struct imx9_lpi2c_priv_s *priv); +static int imx9_lpi2c_init(struct imx9_lpi2c_priv_s *priv); +static int imx9_lpi2c_deinit(struct imx9_lpi2c_priv_s *priv); +static int imx9_lpi2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int imx9_lpi2c_reset(struct i2c_master_s *dev); +#endif + +#ifdef CONFIG_IMX9_LPI2C_DMA +static void imx9_rxdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result); +static void imx9_txdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Trace events strings */ + +#ifdef CONFIG_I2C_TRACE +static const char *g_trace_names[] = +{ + "NONE ", + "SENDADDR ", + "SENDBYTE ", + "RCVBYTE ", + "NOSTART ", + "START/RESTART ", + "STOP ", + "ERROR " +}; +#endif + +/* I2C interface */ + +static const struct i2c_ops_s imx9_lpi2c_ops = +{ + .transfer = imx9_lpi2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = imx9_lpi2c_reset, +#endif +}; + +/* I2C device structures */ + +#ifdef CONFIG_IMX9_LPI2C1 +static const struct imx9_lpi2c_config_s imx9_lpi2c1_config = +{ + .base = IMX9_LPI2C1_BASE, + .clk_root = LPI2C1_CLK, + .busy_idle = CONFIG_IMX9_LPI2C1_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C1_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C1_FILTSDA, + .scl_pin = MUX_LPI2C1_SCL, + .sda_pin = MUX_LPI2C1_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C1_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C1_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C1, +#endif +#ifdef CONFIG_IMX9_LPI2C1_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C1RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C1TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c1_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C2 +static const struct imx9_lpi2c_config_s imx9_lpi2c2_config = +{ + .base = IMX9_LPI2C2_BASE, + .clk_root = LPI2C2_CLK, + .busy_idle = CONFIG_IMX9_LPI2C2_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C2_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C2_FILTSDA, + .scl_pin = MUX_LPI2C2_SCL, + .sda_pin = MUX_LPI2C2_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C2_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C2_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C2, +#endif +#ifdef CONFIG_IMX9_LPI2C2_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C2RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C2TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c2_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C3 +static const struct imx9_lpi2c_config_s imx9_lpi2c3_config = +{ + .base = IMX9_LPI2C3_BASE, + .clk_root = LPI2C3_CLK, + .busy_idle = CONFIG_IMX9_LPI2C3_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C3_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C3_FILTSDA, + .scl_pin = MUX_LPI2C3_SCL, + .sda_pin = MUX_LPI2C3_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C3_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C3_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C3, +#endif +#ifdef CONFIG_IMX9_LPI2C3_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C3RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C3TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c3_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C4 +static const struct imx9_lpi2c_config_s imx9_lpi2c4_config = +{ + .base = IMX9_LPI2C4_BASE, + .clk_root = LPI2C4_CLK, + .busy_idle = CONFIG_IMX9_LPI2C4_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C4_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C4_FILTSDA, + .scl_pin = MUX_LPI2C4_SCL, + .sda_pin = MUX_LPI2C4_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C4_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C4_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C4, +#endif +#ifdef CONFIG_IMX9_LPI2C4_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C4RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C4TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c4_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c4_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C5 +static const struct imx9_lpi2c_config_s imx9_lpi2c5_config = +{ + .base = IMX9_LPI2C5_BASE, + .clk_root = LPI2C5_CLK, + .busy_idle = CONFIG_IMX9_LPI2C5_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C5_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C5_FILTSDA, + .scl_pin = MUX_LPI2C5_SCL, + .sda_pin = MUX_LPI2C5_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C5_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C5_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C5, +#endif +#ifdef CONFIG_IMX9_LPI2C5_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C5RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C5TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c5_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c5_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C6 +static const struct imx9_lpi2c_config_s imx9_lpi2c6_config = +{ + .base = IMX9_LPI2C6_BASE, + .clk_root = LPI2C6_CLK, + .busy_idle = CONFIG_IMX9_LPI2C6_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C6_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C6_FILTSDA, + .scl_pin = MUX_LPI2C6_SCL, + .sda_pin = MUX_LPI2C6_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C6_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C6_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C6, +#endif +#ifdef CONFIG_IMX9_LPI2C6_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C6RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C6TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c6_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c6_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C7 +static const struct imx9_lpi2c_config_s imx9_lpi2c7_config = +{ + .base = IMX9_LPI2C7_BASE, + .clk_root = LPI2C7_CLK, + .busy_idle = CONFIG_IMX9_LPI2C7_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C7_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C7_FILTSDA, + .scl_pin = MUX_LPI2C7_SCL, + .sda_pin = MUX_LPI2C7_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C7_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C7_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C7, +#endif +#ifdef CONFIG_IMX9_LPI2C7_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C7RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C7TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c7_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c7_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C8 +static const struct imx9_lpi2c_config_s imx9_lpi2c8_config = +{ + .base = IMX9_LPI2C8_BASE, + .clk_root = LPI2C8_CLK, + .busy_idle = CONFIG_IMX9_LPI2C8_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C8_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C8_FILTSDA, + .scl_pin = MUX_LPI2C8_SCL, + .sda_pin = MUX_LPI2C8_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C8_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C8_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C8, +#endif +#ifdef CONFIG_IMX9_LPI2C8_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C8RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C8TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c8_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c8_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpi2c_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getreg(struct imx9_lpi2c_priv_s *priv, uint16_t offset) +{ + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: imx9_lpi2c_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void imx9_lpi2c_putreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: imx9_lpi2c_modifyreg + * + * Description: + * Modify a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void imx9_lpi2c_modifyreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: imx9_lpi2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO +static uint32_t imx9_lpi2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + int i; + size_t bytecount = 0; + uint32_t tick = 0; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + tick = USEC2TICK(CONFIG_IMX9_LPI2C_DYNTIMEO_USECPERBYTE * bytecount); + if (tick == 0) + { + tick = 1; + } + + return tick; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int +imx9_lpi2c_sem_waitdone(struct imx9_lpi2c_priv_s *priv) +{ + int ret; + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + imx9_lpi2c_toticks(priv->msgc, + priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_IMX9_LPI2C_TIMEOTICKS); +#endif + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + return ret; +} +#else +static inline int +imx9_lpi2c_sem_waitdone(struct imx9_lpi2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO + timeout = imx9_lpi2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_IMX9_LPI2C_TIMEOTICKS; +#endif + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + imx9_lpi2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: imx9_rxdma_callback + * + * Description: + * This function performs the next I2C operation + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static void imx9_rxdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)arg; + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, 0, + LPI2C_MIER_SDIE); + + if (result == OK) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + imx9_lpi2c_sendstop(priv); + } + } + else + { + uint32_t status = imx9_lpi2c_getstatus(priv); + + if ((status & LPI2C_MSR_ERROR_MASK) != 0) + { + i2cerr("ERROR: MSR: status: 0x0%" PRIx32 "\n", status); + + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + } + } +} +#endif + +/**************************************************************************** + * Name: imx9_txdma_callback + * + * Description: + * This function performs the next I2C operation + * + ****************************************************************************/ +#ifdef CONFIG_IMX9_LPI2C_DMA +static void imx9_txdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)arg; + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, 0, + LPI2C_MIER_SDIE); + + if (result == OK) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + imx9_lpi2c_sendstop(priv); + } + } + else + { + uint32_t status = imx9_lpi2c_getstatus(priv); + + if ((status & LPI2C_MSR_ERROR_MASK) != 0) + { + i2cerr("ERROR: MSR: status: 0x0%" PRIx32 "\n", status); + + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + } + } +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void imx9_lpi2c_traceclear(struct imx9_lpi2c_priv_s *priv) +{ + struct imx9_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void imx9_lpi2c_tracereset(struct imx9_lpi2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + imx9_lpi2c_traceclear(priv); +} + +static void imx9_lpi2c_tracenew(struct imx9_lpi2c_priv_s *priv, + uint32_t status) +{ + struct imx9_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index (unless out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + imx9_lpi2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void imx9_lpi2c_traceevent(struct imx9_lpi2c_priv_s *priv, + enum imx9_trace_e event, uint32_t parm) +{ + struct imx9_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + imx9_lpi2c_traceclear(priv); + } +} + +static void imx9_lpi2c_tracedump(struct imx9_lpi2c_priv_s *priv) +{ + struct imx9_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %ld\n", + (long)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08x COUNT: %3d EVENT: %s(%2d) PARM: %08x " + "TIME: %d\n", + i + 1, trace->status, trace->count, + g_trace_names[trace->event], + trace->event, trace->parm, trace->time - priv->start_time); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: imx9_lpi2c_setclock + * + * Description: + * Set the I2C clock + * + ****************************************************************************/ + +static void imx9_lpi2c_setclock(struct imx9_lpi2c_priv_s *priv, + uint32_t frequency) +{ + uint32_t src_freq = 0; + uint32_t regval; + uint32_t men; + uint32_t prescale = 0; + uint32_t best_prescale = 0; + uint32_t best_clk_hi = 0; + uint32_t abs_error = 0; + uint32_t best_error = 0xffffffff; + uint32_t clk_hi_cycle; + uint32_t computed_rate; + uint32_t count; + + /* Has the I2C bus frequency changed? */ + + if (priv->config->mode == LPI2C_MASTER) + { + if (frequency != priv->frequency) + { + /* Disable the selected LPI2C peripheral to configure the new + * clock if it is enabled. + */ + + men = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MCR_OFFSET) & + LPI2C_MCR_MEN; + if (men) + { + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, + LPI2C_MCR_MEN, 0); + } + + /* Get the LPI2C clock source frequency */ + + imx9_get_rootclock(GET_CLOCK_ROOT(priv->config->clk_root), + &src_freq); + + /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) / + * (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale) + * + * Assume CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2 + */ + + for (prescale = 1; + (prescale <= 128) && (best_error != 0); + prescale *= 2) + { + for (clk_hi_cycle = 1; clk_hi_cycle < 32; clk_hi_cycle++) + { + if (clk_hi_cycle == 1) + { + computed_rate = (src_freq / prescale) / + (6 + (2 / prescale)); + } + else + { + computed_rate = (src_freq / prescale) / + ((3 * clk_hi_cycle + 2) + + (2 / prescale)); + } + + if (frequency > computed_rate) + { + abs_error = frequency - computed_rate; + } + else + { + abs_error = computed_rate - frequency; + } + + if (abs_error < best_error) + { + best_prescale = prescale; + best_clk_hi = clk_hi_cycle; + best_error = abs_error; + + if (abs_error == 0) + { + break; + } + } + } + } + + regval = LPI2C_MCCR0_CLKHI(best_clk_hi); + + if (best_clk_hi < 2) + { + regval |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | + LPI2C_MCCR0_DATAVD(1); + } + else + { + regval |= LPI2C_MCCR0_CLKLO(2 * best_clk_hi) | + LPI2C_MCCR0_SETHOLD(best_clk_hi) | + LPI2C_MCCR0_DATAVD(best_clk_hi / 2); + } + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCCR0_OFFSET, regval); + + for (count = 0; count < 8; count++) + { + if (best_prescale == (1 << count)) + { + best_prescale = count; + break; + } + } + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_PRESCALE_MASK, + LPI2C_MCFGR1_PRESCALE(best_prescale)); + + /* Re-enable LPI2C if it was enabled previously */ + + if (men) + { + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_MEN); + } + + /* Save the new LPI2C frequency */ + + priv->frequency = frequency; + } + } +} + +/**************************************************************************** + * Name: imx9_lpi2c_sendstart + * + * Description: + * Send the START conditions/force Master mode + * + ****************************************************************************/ + +static inline void imx9_lpi2c_sendstart(struct imx9_lpi2c_priv_s *priv, + uint8_t address) +{ + uint32_t txcount = 0; + uint32_t status = 0; + uint8_t addr; + + /* Disable AUTOSTOP and turn NAK Ignore off */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP, 0); + + do + { + txcount = (imx9_lpi2c_getreg(priv, IMX9_LPI2C_MFSR_OFFSET) & + LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + txcount = 4 - txcount; + + status = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MSR_OFFSET); + + if (status & LPI2C_MSR_ERROR_MASK) + { + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + status & LPI2C_MSR_ERROR_MASK); + } + } + while (txcount == 0); + + if ((priv->flags & I2C_M_READ) != 0) + { + addr = I2C_READADDR8(address); + } + else + { + addr = I2C_WRITEADDR8(address); + } + + /* Generate START condition and send the address */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + (LPI2C_MTDR_CMD_START | LPI2C_MTDR_DATA(addr))); +} + +/**************************************************************************** + * Name: imx9_lpi2c_sendstop + * + * Description: + * Send the STOP conditions + * + ****************************************************************************/ + +static inline void imx9_lpi2c_sendstop(struct imx9_lpi2c_priv_s *priv) +{ + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, LPI2C_MTDR_CMD_STOP); +} + +/**************************************************************************** + * Name: imx9_lpi2c_getstatus + * + * Description: + * Get 32-bit status + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getstatus(struct imx9_lpi2c_priv_s *priv) +{ + return imx9_lpi2c_getreg(priv, IMX9_LPI2C_MSR_OFFSET); +} + +/**************************************************************************** + * Name: imx9_lpi2c_getenabledints + * + * Description: + * Get 32-bit status + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getenabledints(struct imx9_lpi2c_priv_s *priv) +{ + return imx9_lpi2c_getreg(priv, IMX9_LPI2C_MIER_OFFSET); +} + +/**************************************************************************** + * Name: imx9_lpi2c_start_message + * + * Description: + * Start send or receive a new message in interrupt mode + * + ****************************************************************************/ + +static int imx9_lpi2c_start_message(struct imx9_lpi2c_priv_s *priv) +{ + uint32_t irq_config = (LPI2C_MIER_EPIE | LPI2C_MIER_SDIE | + LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | + LPI2C_MIER_FEIE); + + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + /* Disable ABORT which may be present after errors */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR0_OFFSET, + LPI2C_MCFG0_ABORT, 0); + + /* Send start + address unless M_NOSTART is defined */ + + if ((priv->flags & I2C_M_NOSTART) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, + priv->msgc); + imx9_lpi2c_sendstart(priv, priv->msgv->addr); + } + else + { + imx9_lpi2c_traceevent(priv, I2CEVENT_NOSTART, priv->msgc); + } + + if ((priv->flags & I2C_M_READ) == 0) + { + /* Queue the first byte. NB: if start was sent and NACK received, + * the byte won't be sent out to the bus. + */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + LPI2C_MTDR_CMD_TXD | + LPI2C_MTDR_DATA(*priv->ptr++)); + priv->dcnt--; + + /* Enable TX interrupt */ + + irq_config |= LPI2C_MIER_TDIE; + } + else + { + /* Set LPI2C in read mode */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA((priv->dcnt - 1))); + + /* Enable RX interrupt */ + + irq_config |= LPI2C_MIER_RDIE; + } + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, irq_config); + + return OK; +} + +/**************************************************************************** + * Name: imx9_lpi2c_stop_transfer + * + * Description: + * Stop an ongoing transfer amd signal the waiting thread + * + ****************************************************************************/ + +static int imx9_lpi2c_stop_transfer(struct imx9_lpi2c_priv_s *priv) +{ + /* Mark that there are mo more messages to transfer */ + + priv->ptr = NULL; + priv->msgc = 0; + priv->dcnt = 0; + +#ifndef CONFIG_I2C_POLLED + + /* Disable interrupts */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, + LPI2C_MIER_TDIE | LPI2C_MIER_RDIE | + LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | + LPI2C_MIER_SDIE | LPI2C_MIER_EPIE, 0); + + /* Inform the thread that transfer is complete + * and wake it up + */ + + if (priv->intstate == INTSTATE_WAITING) + { + nxsem_post(&priv->sem_isr); + } +#endif + + priv->intstate = INTSTATE_DONE; + + return OK; +} + +/**************************************************************************** + * Name: imx9_lpi2c_isr_process + * + * Description: + * Common Interrupt Service Routine + * + ****************************************************************************/ + +static int imx9_lpi2c_isr_process(struct imx9_lpi2c_priv_s *priv) +{ + uint32_t status = imx9_lpi2c_getstatus(priv); + +#ifdef CONFIG_IMX9_LPI2C_DMA + uint32_t current_status = status; + + if (priv->rxdma != NULL || priv->txdma != NULL) + { + /* Condition the status with only the enabled interrupts */ + + status &= imx9_lpi2c_getenabledints(priv); + + /* Is there an Error condition */ + + if (current_status & LPI2C_MSR_LIMITED_ERROR_MASK) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + + /* Return the full error status */ + + priv->status = current_status; + } + + /* End of packet or Stop */ + + if ((status & (LPI2C_MSR_SDF | LPI2C_MSR_EPF)) != 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + + /* Acknowledge End of packet or Stop */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, status & + (LPI2C_MSR_SDF | + LPI2C_MSR_EPF)); + + /* Mark that this transaction stopped */ + + priv->msgv = NULL; + priv->msgc = 0; + priv->dcnt = 0; + + if (priv->intstate == INTSTATE_WAITING) + { + /* inform the thread that transfer is complete + * and wake it up + */ + + imx9_dmach_stop(priv->txdma); + imx9_dmach_stop(priv->rxdma); + + priv->intstate = INTSTATE_DONE; + nxsem_post(&priv->sem_isr); + } + } + + /* Clear the error */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + (current_status & (LPI2C_MSR_NDF | + LPI2C_MSR_ALF | + LPI2C_MSR_FEF))); + return OK; + } + +#endif + + /* Check for new trace setup */ + + imx9_lpi2c_tracenew(priv, status); + + /* Check for errors */ + + /* Ignore NACK on RX last byte - this is normal */ + + if ((status & (LPI2C_MSR_RDF | LPI2C_MSR_NDF)) == + (LPI2C_MSR_RDF | LPI2C_MSR_NDF) && priv->dcnt == 1) + { + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, LPI2C_MSR_NDF); + status &= ~LPI2C_MSR_NDF; + } + + /* Handle rest of the errors */ + + if ((status & LPI2C_MSR_ERROR_MASK) != 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + + /* Clear the TX and RX FIFOs */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_RTF | LPI2C_MCR_RRF); + + /* Clear the error */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + status & LPI2C_MSR_ERROR_MASK); + + /* If there is no stop condition on the bus, abort (send stop). + * Otherwise stop the transfer now. + */ + + if ((status & LPI2C_MSR_SDF) == 0) + { + /* Disable RX and TX interrupts */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, + LPI2C_MIER_TDIE | LPI2C_MIER_TDIE, 0); + + /* Abort any ongoing transfer, this also sends stop on the bus */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR0_OFFSET, 0, + LPI2C_MCFG0_ABORT); + } + else + { + imx9_lpi2c_stop_transfer(priv); + } + + /* Mark that there are no more messages to process */ + + priv->status = status; + priv->msgc = 0; + priv->dcnt = 0; + + return OK; + } + + /* Check for end of packet or stop */ + + if (status & (LPI2C_MSR_EPF | LPI2C_MSR_SDF)) + { + /* Reset them both */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + status & (LPI2C_MSR_EPF | LPI2C_MSR_SDF)); + + /* Process more messages or signal the thread */ + + if (priv->msgc > 1) + { + priv->msgc--; + priv->msgv++; + imx9_lpi2c_start_message(priv); + } + else + { + imx9_lpi2c_stop_transfer(priv); + } + + return OK; + } + + /* Check if there are bytes to send */ + + if ((priv->flags & I2C_M_READ) == 0 && (status & LPI2C_MSR_TDF) != 0) + { + if (priv->dcnt > 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + LPI2C_MTDR_CMD_TXD | + LPI2C_MTDR_DATA(*priv->ptr++)); + priv->dcnt--; + } + else if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_sendstop(priv); + } + } + + /* Check if there are received bytes */ + + else if ((status & LPI2C_MSR_RDF) != 0 && priv->dcnt > 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + + /* No interrupts or context switches should occur in the + * following sequence. Otherwise, additional bytes may be + * sent by the device. + */ + +#ifdef CONFIG_I2C_POLLED + irqstate_t flags = enter_critical_section(); +#endif + + /* Receive a byte */ + + *priv->ptr++ = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MRDR_OFFSET) & + LPI2C_MRDR_DATA_MASK; + + priv->dcnt--; + if (priv->dcnt == 0 && (priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_sendstop(priv); + } + +#ifdef CONFIG_I2C_POLLED + leave_critical_section(flags); +#endif + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_lpi2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int imx9_lpi2c_isr(int irq, void *context, void *arg) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return imx9_lpi2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_clock_enable + * + * Description: + * Ungate LPI2C clock + * + ****************************************************************************/ + +static void imx9_lpi2c_clock_enable(struct imx9_lpi2c_priv_s *priv) +{ + imx9_configure_clock(GET_CLOCK_ROOT(priv->config->clk_root), true); +} + +/**************************************************************************** + * Name: imx9_lpi2c_clock_disable + * + * Description: + * Gate LPI2C clock + * + ****************************************************************************/ + +void imx9_lpi2c_clock_disable(struct imx9_lpi2c_priv_s *priv) +{ + imx9_configure_clock(GET_CLOCK_ROOT(priv->config->clk_root), false); +} + +/**************************************************************************** + * Name: imx9_lpi2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int imx9_lpi2c_init(struct imx9_lpi2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Configure pins */ + + imx9_iomux_configure(priv->config->scl_pin); + imx9_iomux_configure(priv->config->sda_pin); + + /* Enable power and reset the peripheral */ + + imx9_lpi2c_clock_enable(priv); + + /* Reset LPI2C before configuring it */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_RST); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, 0); + + /* Disable doze mode (Set DOZEN bit in 1 to disable) */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_DOZEN); + + /* Disable host request */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR0_OFFSET, + LPI2C_MCFG0_HREN | LPI2C_MCFG0_HRSEL, + LPI2C_MCFG0_HRPOL); + + /* Disable AUTOSTOP and turn NAK Ignore off */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP, 0); + + /* Set tx and rx watermarks */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MFCR_OFFSET, + LPI2C_MFCR_TXWATER(0) | LPI2C_MFCR_RXWATER(0)); + + /* Force a frequency update */ + + priv->frequency = 0; + imx9_lpi2c_setclock(priv, 100000); + + /* Set scl, sda glitch filters and busy idle */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCFGR2_OFFSET, + LPI2C_MCFG2_BUSIDLE(priv->config->busy_idle) | + LPI2C_MCFG2_FILTSCL_CYCLES(priv->config->filtscl) | + LPI2C_MCFG2_FILTSDA_CYCLES(priv->config->filtsda)); + + /* Set pin low cycles to 0 (disable) */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCFGR3_OFFSET, + LPI2C_MCFG3_PINLOW_CYCLES(0)); + + /* Attach ISRs */ + +#ifndef CONFIG_I2C_POLLED + irq_attach(priv->config->irq, imx9_lpi2c_isr, priv); + up_enable_irq(priv->config->irq); +#endif + + /* Enable I2C */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, LPI2C_MCR_MEN); + return OK; +} + +/**************************************************************************** + * Name: imx9_lpi2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int imx9_lpi2c_deinit(struct imx9_lpi2c_priv_s *priv) +{ + /* Disable I2C */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_MEN, 0); + + /* Reset LPI2C */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_RST); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, 0); + + /* Disable and detach interrupts */ + +#ifndef CONFIG_I2C_POLLED + up_disable_irq(priv->config->irq); + irq_detach(priv->config->irq); +#endif + + /* Disable clocking */ + + imx9_lpi2c_clock_disable(priv); + + return OK; +} + +/**************************************************************************** + * Device Driver Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpi2c_dma_command_configure + * + * Description: + * Create a command TCD + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_dma_command_configure(struct imx9_lpi2c_priv_s *priv, + uint16_t *ccmd, uint32_t ncmd) +{ + struct imx9_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); + + config.saddr = (uintptr_t) ccmd; + config.daddr = priv->config->base + IMX9_LPI2C_MTDR_OFFSET; + config.soff = sizeof(uint16_t); + config.doff = 0; + config.iter = 1; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_16BIT; + config.dsize = EDMA_16BIT; + config.nbytes = sizeof(uint16_t) * ncmd; + + up_clean_dcache((uintptr_t)config.saddr, + (uintptr_t)config.saddr + config.nbytes); + + return imx9_dmach_xfrsetup(priv->txdma, &config); +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_dma_data_configure + * + * Description: + * Create a data TCD + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_dma_data_configure(struct imx9_lpi2c_priv_s *priv, + struct i2c_msg_s *msg) +{ + DMACH_HANDLE dma; + struct imx9_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); + + config.iter = msg->length; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = sizeof(msg->buffer[0]); + + if (msg->flags & I2C_M_READ) + { + dma = priv->rxdma; + config.saddr = priv->config->base + IMX9_LPI2C_MRDR_OFFSET; + config.daddr = (uintptr_t) msg->buffer; + config.soff = 0; + config.doff = sizeof(msg->buffer[0]); + up_invalidate_dcache((uintptr_t)msg->buffer, + (uintptr_t)msg->buffer + msg->length); + } + else + { + dma = priv->txdma; + config.saddr = (uintptr_t) msg->buffer; + config.daddr = priv->config->base + IMX9_LPI2C_MTDR_OFFSET; + config.soff = sizeof(msg->buffer[0]); + config.doff = 0; + up_clean_dcache((uintptr_t)msg->buffer, + (uintptr_t)msg->buffer + msg->length); + } + + return imx9_dmach_xfrsetup(dma, &config) ? 0 : msg->length; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_form_command_list + * + * Description: + * Form the DMA command list + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_form_command_list(struct imx9_lpi2c_priv_s *priv, + struct i2c_msg_s *msg, int ncmds) +{ + ssize_t length = 0; + + if (priv->flags & I2C_M_NOSTART) + { + if (priv->flags & I2C_M_READ) + { + /* No start read operation */ + + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA(msg->length - 1); + } + } + else + { + /* A start based read or write operation */ + + /* Create bus address with R/W */ + + uint16_t badd = (priv->flags & I2C_M_READ) ? I2C_READADDR8(msg->addr) : + I2C_WRITEADDR8(msg->addr); + + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_START | LPI2C_MTDR_DATA(badd); + + if (badd & I2C_READBIT) + { + length = msg->length; + while (length) + { + if (length > 256u) + { + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA(256u - 1); + length -= 256u; + } + else + { + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA(length - 1); + length = 0; + } + } + } + } + + return ncmds; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_dma_transfer + * + * Description: + * DMA based I2C transfer function + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_dma_transfer(struct imx9_lpi2c_priv_s *priv) +{ + int m; + int ntotcmds = 0; + int ncmds = 0; + uint16_t *ccmnd = NULL; + + /* Disable Interrupts */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, 0); + + /* Disable DMA */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MDER_OFFSET, LPI2C_MDER_TDDE | + LPI2C_MDER_RDDE, 0); + + /* Enable AUTOSTOP and NAK Ignore */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, 0, + LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP); + + /* Form chains of TCDs to process the messages */ + + for (m = 0; m < priv->msgc; m++) + { + ncmds = 0; + priv->flags = priv->msgv[m].flags; + + /* Form a command list */ + + ccmnd = &priv->cmnds[ntotcmds]; + + ncmds = imx9_lpi2c_form_command_list(priv, &priv->msgv[m], ntotcmds); + + /* Have commands for this message ? */ + + if (ncmds != 0) + { + /* Build up a TCD with the command from this message */ + + imx9_lpi2c_dma_command_configure(priv, ccmnd, ncmds - ntotcmds); + + ntotcmds += ncmds; + + DEBUGASSERT(ntotcmds < CONFIG_IMX9_LPI2C_DMA_MAXMSG); + + imx9_lpi2c_dma_data_configure(priv, &priv->msgv[m]); + } + } + + /* Clear the TX and RX FIFOs */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_RTF | LPI2C_MCR_RRF); + + /* Reset the Error bits */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, LPI2C_MSR_NDF | + LPI2C_MSR_ALF | + LPI2C_MSR_FEF); + + /* Enable the Iterrupts */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, + LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | + LPI2C_MIER_PLTIE); + + /* Start The DMA */ + + imx9_dmach_start(priv->rxdma, imx9_rxdma_callback, (void *)priv); + imx9_dmach_start(priv->txdma, imx9_txdma_callback, (void *)priv); + + /* Enable the DMA Request */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MDER_OFFSET, 0, + LPI2C_MDER_TDDE | LPI2C_MDER_RDDE); + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int imx9_lpi2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)dev; + int ret; +#ifdef CONFIG_IMX9_LPI2C_DMA + int m; +#endif + + DEBUGASSERT(count > 0); + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Clear any pending error interrupts */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, 0xffffffff); + + /* Old transfers are done */ + + /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't + * overwrite stale data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + priv->msgv = msgs; + priv->msgc = count; + priv->flags = msgs->flags; + + i2cinfo("Flags %x, len %d\n", msgs->flags, msgs->length); + + /* Reset I2C trace logic */ + + imx9_lpi2c_tracereset(priv); + + /* Set I2C clock frequency */ + + imx9_lpi2c_setclock(priv, msgs->frequency); + + priv->status = 0; + + priv->intstate = INTSTATE_WAITING; + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma || priv->txdma) + { + imx9_lpi2c_dma_transfer(priv); + } + else +#endif + { + imx9_lpi2c_start_message(priv); + } + + if (imx9_lpi2c_sem_waitdone(priv) < 0) + { +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma != NULL) + { + imx9_dmach_stop(priv->rxdma); + } + + if (priv->txdma != NULL) + { + imx9_dmach_stop(priv->txdma); + } + +#endif + ret = -ETIMEDOUT; + i2cerr("ERROR: Timed out: MSR: status: 0x0%" PRIx32 "\n", + priv->status); + + /* Stop the ongoing transfer and clear the FIFOs */ + + imx9_lpi2c_stop_transfer(priv); + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_RTF | LPI2C_MCR_RRF); + + /* Clear any errors */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, LPI2C_MSR_ERROR_MASK); + + /* Reset the semaphore. There is a race between interrupts and + * sem_waitdone, and the semaphore is anyhow posted one extra time in + * imx9_lpi2c_stop_transfer above + */ + + nxsem_reset(&priv->sem_isr, 0); + } + + /* Check for error status conditions */ + + else if ((priv->status & LPI2C_MSR_ERROR_MASK) != 0) + { + /* LPI2C_MSR_ERROR_MASK is the 'OR' of the following individual bits: */ + + if (priv->status & LPI2C_MSR_ALF) + { + /* Arbitration Lost (master mode) */ + + i2cerr("Arbitration lost\n"); + ret = -EAGAIN; + } + else if (priv->status & LPI2C_MSR_NDF) + { + /* Acknowledge Failure */ + + i2cerr("Ack failure\n"); + ret = -ENXIO; + } + else + { + /* FIFO Error */ + + i2cerr("FIFO error\n"); + ret = -EINVAL; + } + } + + /* Dump the trace result */ + + imx9_lpi2c_tracedump(priv); + + /* Ensure that any ISR happening after we finish can't overwrite any user + * data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma) + { + for (m = 0; m < count; m++) + { + if (msgs[m].flags & I2C_M_READ) + { + up_invalidate_dcache((uintptr_t)msgs[m].buffer, + (uintptr_t)msgs[m].buffer + + msgs[m].length); + } + } + } +#endif + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: imx9_lpi2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int imx9_lpi2c_reset(struct i2c_master_s *dev) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)dev; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + imx9_lpi2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + imx9_iomux_gpio(priv->config->scl_pin, true); + imx9_iomux_gpio(priv->config->sda_pin, true); + + scl_gpio = priv->config->reset_scl_pin; + sda_gpio = priv->config->reset_sda_pin; + + imx9_config_gpio(scl_gpio); + imx9_config_gpio(sda_gpio); + + /* Let SDA go high */ + + imx9_gpio_write(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!imx9_gpio_read(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!imx9_gpio_read(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + imx9_gpio_write(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + imx9_gpio_write(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + imx9_gpio_write(sda_gpio, 0); + up_udelay(10); + imx9_gpio_write(scl_gpio, 0); + up_udelay(10); + imx9_gpio_write(scl_gpio, 1); + up_udelay(10); + imx9_gpio_write(sda_gpio, 1); + up_udelay(10); + + /* Re-init the port */ + + imx9_lpi2c_init(priv); + + /* Restore the frequency */ + + imx9_lpi2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for re-use by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *imx9_i2cbus_initialize(int port) +{ + struct imx9_lpi2c_priv_s * priv = NULL; + irqstate_t flags; + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_IMX9_LPI2C1 + case 1: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c1_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C2 + case 2: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c2_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C3 + case 3: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c3_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C4 + case 4: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c4_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C5 + case 5: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c5_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C6 + case 6: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c6_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C7 + case 7: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c7_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C8 + case 8: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c8_priv; + break; +#endif + default: + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ == 0) + { + imx9_lpi2c_init(priv); + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->config->dma_txreqsrc != 0) + { + priv->txdma = imx9_dmach_alloc(priv->config->dma_txreqsrc, 0); + DEBUGASSERT(priv->txdma != NULL); + } + + if (priv->config->dma_rxreqsrc != 0) + { + priv->rxdma = imx9_dmach_alloc(priv->config->dma_rxreqsrc, 0); + DEBUGASSERT(priv->rxdma != NULL); + } +#endif + } + + leave_critical_section(flags); + + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: imx9_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int imx9_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)dev; + irqstate_t flags; + + DEBUGASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs > 0) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + /* Disable power and other HW resource (GPIO's) */ + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma != NULL) + { + imx9_dmach_stop(priv->rxdma); + imx9_dmach_free(priv->rxdma); + priv->rxdma = NULL; + } + + if (priv->txdma != NULL) + { + imx9_dmach_stop(priv->txdma); + imx9_dmach_free(priv->txdma); + priv->txdma = NULL; + } +#endif + + imx9_lpi2c_deinit(priv); + + return OK; +} + +#endif /* CONFIG_IMX9_LPI2C */ diff --git a/arch/arm/src/imx9/imx9_lpi2c.h b/arch/arm/src/imx9/imx9_lpi2c.h new file mode 100644 index 0000000000000..052661e2089b6 --- /dev/null +++ b/arch/arm/src/imx9/imx9_lpi2c.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lpi2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LPI2C_H +#define __ARCH_ARM_SRC_IMX9_IMX9_LPI2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2c_master_s *imx9_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: imx9_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameters: + * Device structure as returned by the imx9_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int imx9_i2cbus_uninitialize(struct i2c_master_s *dev); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LPI2C_H */ diff --git a/arch/arm/src/imx9/imx9_lpspi.c b/arch/arm/src/imx9/imx9_lpspi.c new file mode 100644 index 0000000000000..0fad5fbb85af1 --- /dev/null +++ b/arch/arm/src/imx9/imx9_lpspi.c @@ -0,0 +1,2142 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lpspi.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * The external functions, imx9_lpspi1/2/3/4select and + * imx9_lpspi1/2/3/4status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct imx9_lpspi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including + * imx9_lpspibus_initialize()) are provided by common IMX9 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in imx9_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide imx9_lpspi1/2/3/4select() and imx9_lpspi1/2/3/4status() + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in the way + * your board is configured. + * 3. Add a calls to imx9_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by imx9_lpspibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_lpspislotinitialize(), for example, will bind the SPI + * driver to the SPI MMC/SD driver). + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "imx9_clockconfig.h" +#include "imx9_gpio.h" +#include "imx9_iomuxc.h" +#include "imx9_lpspi.h" + +#include "hardware/imx9_lpspi.h" +#include "hardware/imx9_pinmux.h" + +#ifdef CONFIG_IMX9_LPSPI_DMA +# include "chip.h" +# include "imx9_edma.h" +# include "hardware/imx9_dmamux.h" +#endif + +#ifdef CONFIG_IMX9_LPSPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* SPI interrupts */ + +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS +# error "Interrupt driven SPI not yet supported" +#endif + +/* Can't have both interrupt driven SPI and SPI DMA */ + +#if defined(CONFIG_IMX9_LPSPI_INTERRUPTS) && defined(CONFIG_IMX9_LPSPI_DMA) +# error "Cannot enable both interrupt mode and DMA mode for SPI" +#endif + +#define SPI_SR_CLEAR (LPSPI_SR_WCF | LPSPI_SR_FCF | LPSPI_SR_TCF | \ + LPSPI_SR_TEF | LPSPI_SR_REF | LPSPI_SR_DMF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_lpspidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t spibase; /* SPIn base address */ + uint32_t clk_root; /* SPIn clock root */ +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + uint8_t spiirq; /* SPI IRQ number */ +#endif + mutex_t lock; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + int8_t nbits; /* Width of word in bits */ + uint8_t mode; /* Mode 0,1,2,3 */ +#ifdef CONFIG_IMX9_LPSPI_HWPCS + uint32_t pcs; /* Peripheral Chip Select currently used */ +#endif +#ifdef CONFIG_IMX9_LPSPI_DMA + volatile uint32_t rxresult; /* Result of the RX DMA */ + volatile uint32_t txresult; /* Result of the TX DMA */ + const uint16_t rxch; /* The RX DMA channel number */ + const uint16_t txch; /* The TX DMA channel number */ + DMACH_HANDLE rxdma; /* DMA channel handle for RX transfers */ + DMACH_HANDLE txdma; /* DMA channel handle for TX transfers */ + sem_t rxsem; /* Wait for RX DMA to complete */ + sem_t txsem; /* Wait for TX DMA to complete */ +#endif + int refcount; /* SPIn initialization counter */ +}; + +enum imx9_delay_e +{ + LPSPI_PCS_TO_SCK = 1, /* PCS-to-SCK delay. */ + LPSPI_LAST_SCK_TO_PCS, /* Last SCK edge to PCS delay. */ + LPSPI_BETWEEN_TRANSFER /* Delay between transfers. */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +static inline uint32_t +imx9_lpspi_getreg32(struct imx9_lpspidev_s *priv, uint8_t offset); +static inline void imx9_lpspi_putreg32(struct imx9_lpspidev_s *priv, + uint8_t offset, uint32_t value); +static inline uint32_t imx9_lpspi_readword( + struct imx9_lpspidev_s *priv); +static inline void imx9_lpspi_writeword(struct imx9_lpspidev_s *priv, + uint16_t byte); +static inline bool imx9_lpspi_9to16bitmode( + struct imx9_lpspidev_s *priv); +static inline void imx9_lpspi_master_set_delays(struct imx9_lpspidev_s + *priv, uint32_t delay_ns, + enum imx9_delay_e type); +static inline void imx9_lpspi_master_set_delay_scaler( + struct imx9_lpspidev_s *priv, + uint32_t scaler, + enum imx9_delay_e type); + +/* DMA support */ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static int spi_dmarxwait(struct imx9_lpspidev_s *priv); +static int spi_dmatxwait(struct imx9_lpspidev_s *priv); +static inline void spi_dmarxwakeup(struct imx9_lpspidev_s *priv); +static inline void spi_dmatxwakeup(struct imx9_lpspidev_s *priv); +static void spi_dmarxcallback(DMACH_HANDLE handle, void *arg, + bool done, int result); +static void spi_dmatxcallback(DMACH_HANDLE handle, void *arg, + bool done, int result); +static inline void spi_dmarxstart(struct imx9_lpspidev_s *priv); +static inline void spi_dmatxstart(struct imx9_lpspidev_s *priv); +#endif + +/* SPI methods */ + +static int imx9_lpspi_lock(struct spi_dev_s *dev, bool lock); +static uint32_t imx9_lpspi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency); +static void imx9_lpspi_setmode(struct spi_dev_s *dev, + enum spi_mode_e mode); +static void imx9_lpspi_setbits(struct spi_dev_s *dev, int nbits); +#ifdef CONFIG_SPI_HWFEATURES +static int imx9_lpspi_hwfeatures(struct spi_dev_s *dev, + imx9_lpspi_hwfeatures_t features); +#endif +static uint32_t imx9_lpspi_send(struct spi_dev_s *dev, uint32_t wd); +static void imx9_lpspi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, + size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void imx9_lpspi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, size_t nwords); +static void imx9_lpspi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, + size_t nwords); +#endif + +/* Initialization */ + +static void imx9_lpspi_bus_initialize(struct imx9_lpspidev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct spi_ops_s g_spiops = +{ + .lock = imx9_lpspi_lock, + .select = imx9_lpspi_select, + .setfrequency = imx9_lpspi_setfrequency, + .setmode = imx9_lpspi_setmode, + .setbits = imx9_lpspi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = imx9_lpspi_hwfeatures, +#endif + .status = imx9_lpspi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx9_lpspi_cmddata, +#endif + .send = imx9_lpspi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = imx9_lpspi_exchange, +#else + .sndblock = imx9_lpspi_sndblock, + .recvblock = imx9_lpspi_recvblock, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = imx9_lpspi_register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +#ifdef CONFIG_IMX9_LPSPI1 +static struct imx9_lpspidev_s g_lpspi1dev = +{ + .spidev = + { + .ops = &g_spiops, + }, + .spibase = IMX9_LPSPI1_BASE, + .clk_root = LPSPI1_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI1, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI1_DMA + .rxch = DMA_REQUEST_MUXLPSPI1RX, + .txch = DMA_REQUEST_MUXLPSPI1TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI2 +static struct imx9_lpspidev_s g_lpspi2dev = +{ + .spidev = + { + .ops = &g_spi2ops, + }, + .spibase = IMX9_LPSPI2_BASE, + .clk_root = LPSPI2_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI2, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI2_DMA + .rxch = DMA_REQUEST_MUXLPSPI2RX, + .txch = DMA_REQUEST_MUXLPSPI2TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI3 +static struct imx9_lpspidev_s g_lpspi3dev = +{ + .spidev = + { + .ops = &g_spi3ops, + }, + .spibase = IMX9_LPSPI3_BASE, + .clk_root = LPSPI3_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI3, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI3_DMA + .rxch = DMA_REQUEST_MUXLPSPI3RX, + .txch = DMA_REQUEST_MUXLPSPI3TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI4 +static struct imx9_lpspidev_s g_lpspi4dev = +{ + .spidev = + { + .ops = &g_spiops, + }, + .spibase = IMX9_LPSPI4_BASE, + .clk_root = LPSPI4_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI4, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI4_DMA + .rxch = DMA_REQUEST_MUXLPSPI4RX, + .txch = DMA_REQUEST_MUXLPSPI4TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI5 +static struct imx9_lpspidev_s g_lpspi5dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI5_BASE, + .clk_root = LPSPI5_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI5, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI5_DMA + .rxch = DMA_REQUEST_MUXLPSPI5RX, + .txch = DMA_REQUEST_MUXLPSPI5TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI6 +static struct imx9_lpspidev_s g_lpspi6dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI6_BASE, + .clk_root = LPSPI6_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI6, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI6_DMA + .rxch = DMA_REQUEST_MUXLPSPI6RX, + .txch = DMA_REQUEST_MUXLPSPI6TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI7 +static struct imx9_lpspidev_s g_lpspi7dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI7_BASE, + .clk_root = LPSPI7_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI7, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI7_DMA + .rxch = DMA_REQUEST_MUXLPSPI7RX, + .txch = DMA_REQUEST_MUXLPSPI7TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI8 +static struct imx9_lpspidev_s g_lpspi8dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI8_BASE, + .clk_root = LPSPI8_CLK, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI8, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI6_DMA + .rxch = DMA_REQUEST_MUXLPSPI8RX, + .txch = DMA_REQUEST_MUXLPSPI8TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif + .refcount = 0, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpspi_getreg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpspi_getreg32(struct imx9_lpspidev_s *priv, uint8_t offset) +{ + return getreg32(priv->spibase + offset); +} + +/**************************************************************************** + * Name: imx9_lpspi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 32-bit value to be written + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline void imx9_lpspi_putreg32(struct imx9_lpspidev_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->spibase + offset); +} + +/**************************************************************************** + * Name: imx9_lpspi_readword + * + * Description: + * Read one word from SPI + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * word as read + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpspi_readword(struct imx9_lpspidev_s *priv) +{ + /* Wait until the receive buffer is not empty */ + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET) + & LPSPI_SR_RDF) == 0); + + /* Then return the received byte */ + + return imx9_lpspi_getreg32(priv, IMX9_LPSPI_RDR_OFFSET); +} + +/**************************************************************************** + * Name: imx9_lpspi_writeword + * + * Description: + * Write one word to SPI + * + * Input Parameters: + * priv - Device-specific state data + * word - word to send + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_lpspi_writeword(struct imx9_lpspidev_s *priv, + uint16_t word) +{ + /* Wait until the transmit buffer is empty */ + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET) + & LPSPI_SR_TDF) == 0); + + /* Then send the word */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_TDR_OFFSET, word); +} + +/**************************************************************************** + * Name: imx9_lpspi_9to16bitmode + * + * Description: + * Check if the SPI is operating in more then 8 bit mode + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: >8 bit mode-bit mode, false: <= 8-bit mode + * + ****************************************************************************/ + +static inline bool +imx9_lpspi_9to16bitmode(struct imx9_lpspidev_s *priv) +{ + bool ret; + + if (((imx9_lpspi_getreg32(priv, IMX9_LPSPI_TCR_OFFSET) & + LPSPI_TCR_FRAMESZ_MASK) + 1) < 9) + { + ret = false; + } + else + { + ret = true; + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_lpspi_modifyreg32 + * + * Description: + * Clear and set bits in register + * + * Input Parameters: + * priv - Device-specific state data + * offset - Register offset + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_modifyreg32(struct imx9_lpspidev_s *priv, + uint8_t offset, uint32_t clrbits, + uint32_t setbits) +{ + modifyreg32(priv->spibase + offset, clrbits, setbits); +} + +/**************************************************************************** + * Name: imx9_lpspi_modifyreg32 + * + * Description: + * Clear and set bits TCR register. Need a safe wrapper as TCR expects + * LPSPI is _enabled_ when writing. + * + * Input Parameters: + * priv - Device-specific state data + * offset - Register offset + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_modifytcr(struct imx9_lpspidev_s *priv, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t men; + + /* Enable LPSPI if it was disabled previously */ + + men = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + if (!men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_MEN); + } + + /* Update the register */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_TCR_OFFSET, clrbits, setbits); + + /* Disable LPSPI if it was disabled */ + + if (!men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); + } +} + +/**************************************************************************** + * Name: imx9_lpspi_master_set_delays + * + * Description: + * SET LPSPI Delay times + * + * Input Parameters: + * priv - Device-specific state data + * scaler - scaler value + * type - delay time type + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_lpspi_master_set_delay_scaler( + struct imx9_lpspidev_s *priv, + uint32_t scaler, + enum imx9_delay_e type) +{ + uint32_t ccr1; + uint32_t dbt; + uint32_t sckdiv; + + /* Read from SCKDIV and DTB will always return 0. In order to preserve the + * old values we must calculate them here locally from CCR1 values. + */ + + ccr1 = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CCR1_OFFSET); + dbt = (ccr1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT; + sckdiv = (ccr1 & LPSPI_CCR1_SCKHLD_MASK) >> LPSPI_CCR1_SCKHLD_SHIFT; + sckdiv += (ccr1 & LPSPI_CCR1_SCKSET_MASK) >> LPSPI_CCR1_SCKSET_SHIFT; + + switch (type) + { + case LPSPI_PCS_TO_SCK: + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_PCSSCK_MASK, 0); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_PCSSCK(scaler) | + LPSPI_CCR_SCKDIV(sckdiv)); + break; + + case LPSPI_LAST_SCK_TO_PCS: + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_SCKPCS_MASK, 0); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_PCSSCK(scaler) | + LPSPI_CCR_SCKDIV(sckdiv)); + break; + + case LPSPI_BETWEEN_TRANSFER: + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_DBT_MASK, 0); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_PCSSCK(scaler) | + LPSPI_CCR_SCKDIV(sckdiv)); + break; + } +} + +/**************************************************************************** + * Name: imx9_lpspi_master_set_delays + * + * Description: + * SET LPSPI Delay times + * + * Input Parameters: + * priv - Device-specific state data + * delay_ns - delay time in nano seconds + * type - delay time type + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_lpspi_master_set_delays( + struct imx9_lpspidev_s *priv, + uint32_t delay_ns, + enum imx9_delay_e type) +{ + uint32_t src_freq; + uint64_t real_delay; + uint32_t scaler; + uint32_t best_scaler; + uint32_t diff; + uint32_t min_diff; + uint64_t initial_delay_ns; + uint32_t clock_div_prescaler; + uint32_t additional_scaler; + + imx9_get_rootclock(GET_CLOCK_ROOT(priv->clk_root), &src_freq); + + clock_div_prescaler = src_freq / + (1 << ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_TCR_OFFSET) & + LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT)); + + min_diff = 0xffffffff; + + /* Initialize scaler to max value to generate the max delay */ + + best_scaler = 0xff; + + if (type == LPSPI_BETWEEN_TRANSFER) + { + /* First calculate the initial, default delay, note min delay is 2 + * clock cycles. Due to large size of * calculated values (uint64_t), + * we need to break up the calculation into several steps to ensure + * accurate calculated results + */ + + initial_delay_ns = 1000000000U; + initial_delay_ns *= 2; + initial_delay_ns /= clock_div_prescaler; + + additional_scaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock + * cycle. Due to large size of calculated values (uint64_t), we need to + * break up the calculation into several steps to ensure accurate + * calculated * results. + */ + + initial_delay_ns = 1000000000U; + initial_delay_ns /= clock_div_prescaler; + + additional_scaler = 0; + } + + /* If the initial, default delay is already greater than the desired delay, + * then * set the delay to their initial value (0) and return the delay. In + * other words, * there is no way to decrease the delay value further. + */ + + if (initial_delay_ns >= delay_ns) + { + imx9_lpspi_master_set_delay_scaler(priv, 0, type); + } + else + { + /* If min_diff = 0, the exit for loop */ + + for (scaler = 0; (scaler < 256) && min_diff; scaler++) + { + /* Calculate the real delay value as we cycle through the scaler + * values. Due to large size of calculated values (uint64_t), + * we need to break up the calculation into several steps to + * ensure accurate calculated results + */ + + real_delay = 1000000000U; + real_delay *= (scaler + 1 + additional_scaler); + real_delay /= clock_div_prescaler; + + /* calculate the delay difference based on the conditional + * statement that states that the calculated delay must not be + * less then the desired delay + */ + + if (real_delay >= delay_ns) + { + diff = real_delay - delay_ns; + if (min_diff > diff) + { + /* A better match found */ + + min_diff = diff; + best_scaler = scaler; + } + } + } + + imx9_lpspi_master_set_delay_scaler(priv, best_scaler, type); + } +} + +/**************************************************************************** + * Name: imx9_lpspi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int imx9_lpspi_lock(struct spi_dev_s *dev, bool lock) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + int ret; + + if (lock) + { + ret = nxmutex_lock(&priv->lock); + } + else + { + ret = nxmutex_unlock(&priv->lock); + } + + return ret; +} + +#ifdef CONFIG_IMX9_LPSPI_HWPCS +/**************************************************************************** + * Name: imx9_lpspi_select + * + * Description: + * Change to another SPI chip select (hardware/native, not emulated with + * GPIO) to select another device. The hardware itself controls when + * the chip select is enabled or disabled. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to select + * selected - Ignored, selection is controlled by hardware + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_lpspi_hw_select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + + /* LPSPI on IMX9 supports PCS 0-3 */ + + DEBUGASSERT(SPIDEVID_INDEX(devid) <= 3); + + /* Has the Peripheral Chip Select changed? */ + + if (devid != priv->pcs) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_TCR_OFFSET, + LPSPI_TCR_PCS_MASK, + LPSPI_TCR_PCS(SPIDEVID_INDEX(devid))); + priv->pcs = devid; + } + + if (selected) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_TCR_OFFSET, + 0, + LPSPI_TCR_CONT); + } + else + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_TCR_OFFSET, + LPSPI_TCR_CONT, + 0); + } + + spiinfo("devid: %" PRId32 ", CS: hardware-controlled\n", devid); +} + +void weak_function imx9_lpspi_select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + imx9_lpspi_hw_select(dev, devid, selected); +} + +#endif /* CONFIG_IMX9_LPSPI HWPCS */ + +/**************************************************************************** + * Name: imx9_lpspi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t imx9_lpspi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + + uint32_t men; + uint32_t src_freq = 0; + uint32_t prescaler; + uint32_t best_prescaler; + uint32_t scaler; + uint32_t best_scaler; + uint32_t real_frequency; + uint32_t best_frequency; + uint32_t diff; + uint32_t min_diff; + + /* Has the LPSPI bus frequency changed? */ + + if (frequency != priv->frequency) + { + /* Disable LPSPI if it is enabled */ + + men = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + if (men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); + } + + imx9_get_rootclock(GET_CLOCK_ROOT(priv->clk_root), &src_freq); + + min_diff = 0xffffffff; + best_prescaler = 7; + best_scaler = 255; + best_frequency = 0; + + for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 256) && min_diff; scaler++) + { + real_frequency = src_freq / ((1 << prescaler) * (scaler + 2)); + + /* Calculate the frequency difference based on conditional + * statement that states that the calculated frequency must not + * exceed desired frequency. + */ + + if (frequency >= real_frequency) + { + diff = frequency - real_frequency; + if (min_diff > diff) + { + /* A better match found */ + + min_diff = diff; + best_prescaler = prescaler; + best_scaler = scaler; + best_frequency = real_frequency; + } + } + } + } + + /* Write the best values in the CCR register */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_SCKDIV_MASK, + LPSPI_CCR_SCKDIV(best_scaler)); + + /* Update TCR */ + + imx9_lpspi_modifytcr(priv, LPSPI_TCR_PRESCALE_MASK, + LPSPI_TCR_PRESCALE(best_prescaler)); + + priv->frequency = frequency; + priv->actual = best_frequency; + imx9_lpspi_master_set_delays(priv, 1000000000 / best_frequency, + LPSPI_PCS_TO_SCK); + imx9_lpspi_master_set_delays(priv, 1000000000 / best_frequency, + LPSPI_LAST_SCK_TO_PCS); + imx9_lpspi_master_set_delays(priv, 1000000000 / best_frequency, + LPSPI_BETWEEN_TRANSFER); + + /* Re-enable LPSPI if it was enabled previously */ + + if (men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_MEN); + } + } + + return priv->actual; +} + +/**************************************************************************** + * Name: imx9_lpspi_setmode + * + * Description: + * Set the SPI mode. see enum spi_mode_e mode for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static void imx9_lpspi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + uint32_t setbits; + uint32_t clrbits; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + /* Disable LPSPI if it is enabled */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + setbits = 0; + clrbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + setbits = LPSPI_TCR_CPHA; + clrbits = LPSPI_TCR_CPOL; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + setbits = LPSPI_TCR_CPOL; + clrbits = LPSPI_TCR_CPHA; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + setbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; + clrbits = 0; + break; + + default: + return; + } + + /* Update TCR register */ + + imx9_lpspi_modifytcr(priv, clrbits, setbits); + + /* Reset SPI read FIFO */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_RRF); + + /* Save the mode so that subsequent re-configurations will be faster */ + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: imx9_lpspi_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requested + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + + spiinfo("nbits=%d\n", nbits); + + /* Has the number of bits changed? */ + + if (nbits != priv->nbits) + { + if (nbits < 2 || nbits > 4096) + { + return; + } + + /* Update TCR */ + + imx9_lpspi_modifytcr(priv, LPSPI_TCR_FRAMESZ_MASK, + LPSPI_TCR_FRAMESZ(nbits - 1)); + + /* Save the selection so the subsequent re-configurations + * will be faster. + */ + + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: imx9_lpspi_hwfeatures + * + * Description: + * Set hardware-specific feature flags. + * + * Input Parameters: + * dev - Device-specific state data + * features - H/W feature flags + * + * Returned Value: + * Zero (OK) if the selected H/W features are enabled; A negated errno + * value if any H/W feature is not supportable. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_HWFEATURES +static int imx9_lpspi_hwfeatures(struct spi_dev_s *dev, + imx9_lpspi_hwfeatures_t features) +{ +#ifdef CONFIG_SPI_BITORDER + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + uint32_t setbits; + uint32_t clrbits; + + spiinfo("features=%08x\n", features); + + /* Transfer data LSB first? */ + + if ((features & HWFEAT_LSBFIRST) != 0) + { + setbits = LPSPI_TCR_LSBF; + clrbits = 0; + } + else + { + setbits = 0; + clrbits = LPSPI_TCR_LSBF; + } + + imx9_lpspi_modifytcr(priv, clrbits, setbits); + + /* Other H/W features are not supported */ + + return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS; +#else + return -ENOSYS; +#endif +} +#endif + +/**************************************************************************** + * Name: imx9_lpspi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint32_t imx9_lpspi_send(struct spi_dev_s *dev, uint32_t wd) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + uint32_t regval; + uint32_t ret; + + DEBUGASSERT(priv && priv->spibase); + + imx9_lpspi_writeword(priv, wd); + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET) & + LPSPI_SR_RDF) != LPSPI_SR_RDF); + + ret = imx9_lpspi_readword(priv); + + /* Check and clear any error flags (Reading from the SR clears the error + * flags). + */ + + regval = imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET); + + spiinfo( + "Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", + wd, ret, regval); + + UNUSED(regval); + return ret; +} + +/**************************************************************************** + * Name: imx9_lpspi_exchange (no DMA). aka imx9_lpspi_exchange_nodma + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed + * into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if !defined(CONFIG_IMX9_LPSPI_DMA) +static void imx9_lpspi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, + size_t nwords) +#else +static void imx9_lpspi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, size_t nwords) +#endif +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + DEBUGASSERT(priv && priv->spibase); + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%u\n", txbuffer, rxbuffer, + nwords); + + /* 8- or 16-bit mode? */ + + if (imx9_lpspi_9to16bitmode(priv)) + { + /* 16-bit mode */ + + const uint16_t *src = txbuffer; + uint16_t *dest = rxbuffer; + uint16_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xffff; + } + + /* Exchange one word */ + + word = (uint16_t) imx9_lpspi_send(dev, (uint32_t) word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } + else + { + /* 8-bit mode */ + + const uint8_t *src = txbuffer; + uint8_t *dest = rxbuffer; + uint8_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xff; + } + + /* Exchange one word */ + + word = (uint8_t)imx9_lpspi_send(dev, word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } +} + +/**************************************************************************** + * Name: spi_exchange (with DMA capability) + * + * Description: + * Exchange a block of data on SPI using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits > 8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static void imx9_lpspi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + int ret; + size_t adjust; + ssize_t nbytes; + static uint8_t rxdummy[4] aligned_data(4); + static const uint16_t txdummy = 0xffff; + uint32_t regval; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv && priv->spibase); + spiinfo("txbuffer=%p rxbuffer=%p nwords=%lu\n", txbuffer, rxbuffer, + nwords); + + /* Convert the number of word to a number of bytes */ + + nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; + + /* Invalid DMA channels fall back to non-DMA method. */ + + if (priv->rxdma == NULL || priv->txdma == NULL +#ifdef CONFIG_IMX9_LPSPI_DMATHRESHOLD + /* If this is a small SPI transfer, then let + * imx9_lpspi_exchange_nodma() do the work. + */ + + || nbytes <= CONFIG_IMX9_LPSPI_DMATHRESHOLD +#endif + ) + { + imx9_lpspi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + + /* Disable SPI when we are configuring it */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + + /* ERR050456 workaround: Reset FIFOs using CR[RST] bit */ + + regval = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CFGR1_OFFSET); + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, + LPSPI_CR_RTF | LPSPI_CR_RRF, + LPSPI_CR_RTF | LPSPI_CR_RRF); + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_CFGR1_OFFSET, regval); + + /* Clear all status bits */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_SR_OFFSET, SPI_SR_CLEAR); + + /* disable DMA */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_DER_OFFSET, 0); + + if (txbuffer) + { + up_clean_dcache((uintptr_t)txbuffer, (uintptr_t)txbuffer + nbytes); + } + + /* Set up the DMA */ + + adjust = (priv->nbits > 8) ? 2 : 1; + + struct imx9_edma_xfrconfig_s config; + + config.saddr = priv->spibase + IMX9_LPSPI_RDR_OFFSET; + config.daddr = (uintptr_t) (rxbuffer ? rxbuffer : rxdummy); + config.soff = 0; + config.doff = rxbuffer ? adjust : 0; + config.iter = nwords; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.nbytes = adjust; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = NULL; +#endif + imx9_dmach_xfrsetup(priv->rxdma, &config); + + config.saddr = (uintptr_t) (txbuffer ? txbuffer : &txdummy); + config.daddr = priv->spibase + IMX9_LPSPI_TDR_OFFSET; + config.soff = txbuffer ? adjust : 0; + config.doff = 0; + config.iter = nwords; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.nbytes = adjust; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = NULL; +#endif + imx9_dmach_xfrsetup(priv->txdma, &config); + + /* Start the DMAs */ + + spi_dmarxstart(priv); + spi_dmatxstart(priv); + + /* Enable SPI again */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); + + /* Invoke SPI DMA */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_DER_OFFSET, + 0, LPSPI_DER_TDDE | LPSPI_DER_RDDE); + + /* Then wait for each to complete */ + + ret = spi_dmarxwait(priv); + + if (ret < 0) + { + ret = spi_dmatxwait(priv); + } + + /* Reset any status */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_SR_OFFSET, SPI_SR_CLEAR); + + /* Disable DMA */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_DER_OFFSET, 0); + + if (rxbuffer) + { + up_invalidate_dcache((uintptr_t)rxbuffer, + (uintptr_t)rxbuffer + nbytes); + } +} + +#endif /* CONFIG_IMX9_SPI_DMA */ + +/**************************************************************************** + * Name: imx9_lpspi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of + * words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void imx9_lpspi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%lu\n", txbuffer, nwords); + return imx9_lpspi_exchange(dev, txbuffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: imx9_lpspi_recvblock + * + * Description: + * Receive a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void imx9_lpspi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%lu\n", rxbuffer, nwords); + return imx9_lpspi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: imx9_lpspi_clock_enable + * + * Description: + * Ungate LPSPI clock + * + ****************************************************************************/ + +static void imx9_lpspi_clock_enable(struct imx9_lpspidev_s *priv) +{ + imx9_configure_clock(GET_CLOCK_ROOT(priv->clk_root), true); +} + +/**************************************************************************** + * Name: imx9_lpspi_bus_initialize + * + * Description: + * Initialize the selected SPI bus in its default state + * (Master, 8-bit, mode 0, etc.) + * + * Input Parameters: + * priv - private SPI device structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_bus_initialize(struct imx9_lpspidev_s *priv) +{ + uint32_t reg = 0; + + /* Make sure bus is disabled */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + + /* Enable power and reset the peripheral */ + + imx9_lpspi_clock_enable(priv); + + /* Reset to known status */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, LPSPI_CR_RST); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_RTF | LPSPI_CR_RRF); + imx9_lpspi_putreg32(priv, IMX9_LPSPI_CR_OFFSET, 0x00); + + /* Set LPSPI to master */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CFGR1_OFFSET, 0, + LPSPI_CFGR1_MASTER); + + /* Set specific PCS to active high or low + * TODO: Not needed for now + */ + + /* Set Configuration Register 1 related setting. */ + + reg = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CFGR1_OFFSET); + reg &= ~(LPSPI_CFGR1_OUTCFG | LPSPI_CFGR1_PINCFG_MASK | + LPSPI_CFGR1_NOSTALL); + reg |= LPSPI_CFGR1_OUTCFG_RETAIN | LPSPI_CFGR1_PINCFG_SIN_SOUT; + imx9_lpspi_putreg32(priv, IMX9_LPSPI_CFGR1_OFFSET, reg); + + /* Set frequency and delay times */ + + imx9_lpspi_setfrequency((struct spi_dev_s *)priv, 400000); + + /* Set default watermarks */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_FCR_OFFSET, + LPSPI_FCR_TXWATER(0) | LPSPI_FCR_RXWATER(0)); + + /* Set Transmit Command Register */ + + imx9_lpspi_setbits((struct spi_dev_s *)priv, 8); + + imx9_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0); + + /* Enable LPSPI */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); +} + +/**************************************************************************** + * Name: spi_dmarxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static int spi_dmarxwait(struct imx9_lpspidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed. + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->rxsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->rxresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static int spi_dmatxwait(struct imx9_lpspidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed. + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->txsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->txresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmarxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmarxwakeup(struct imx9_lpspidev_s *priv) +{ + nxsem_post(&priv->rxsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmatxwakeup(struct imx9_lpspidev_s *priv) +{ + nxsem_post(&priv->txsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static void spi_dmarxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)arg; + + priv->rxresult = result | 0x80000000; /* assure non-zero */ + spi_dmarxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static void spi_dmatxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->txresult = result | 0x80000000; /* assure non-zero */ + spi_dmatxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxstart + * + * Description: + * Start RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmarxstart(struct imx9_lpspidev_s *priv) +{ + priv->rxresult = 0; + imx9_dmach_start(priv->rxdma, spi_dmarxcallback, priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxstart + * + * Description: + * Start TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmatxstart(struct imx9_lpspidev_s *priv) +{ + priv->txresult = 0; + imx9_dmach_start(priv->txdma, spi_dmatxcallback, priv); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpspibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *imx9_lpspibus_initialize(int bus) +{ + struct imx9_lpspidev_s *priv = NULL; + + irqstate_t flags = enter_critical_section(); + +#ifdef CONFIG_IMX9_LPSPI1 + if (bus == 1) + { + /* Select SPI1 */ + + priv = &g_lpspi1dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI1 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI1_SCK); + imx9_iomux_configure(MUX_LPSPI1_MISO); + imx9_iomux_configure(MUX_LPSPI1_MOSI); +#ifdef MUX_LPSPI1_CS + imx9_iomux_configure(MUX_LPSPI1_CS); +#endif +#ifdef GPIO_LPSPI1_CS + imx9_config_gpio(GPIO_LPSPI1_CS); +#endif +#if defined(GPIO_LPSPI1_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI1_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI2 + if (bus == 2) + { + /* Select SPI2 */ + + priv = &g_lpspi2dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI2 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI2_SCK); + imx9_iomux_configure(MUX_LPSPI2_MISO); + imx9_iomux_configure(MUX_LPSPI2_MOSI); +#ifdef MUX_LPSPI2_CS + imx9_iomux_configure(MUX_LPSPI2_CS); +#endif +#ifdef GPIO_LPSPI2_CS + imx9_config_gpio(GPIO_LPSPI2_CS); +#endif +#if defined(GPIO_LPSPI2_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI2_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI3 + if (bus == 3) + { + /* Select SPI3 */ + + priv = &g_lpspi3dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI3 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI3_SCK); + imx9_iomux_configure(MUX_LPSPI3_MISO); + imx9_iomux_configure(MUX_LPSPI3_MOSI); +#ifdef MUX_LPSPI3_CS + imx9_iomux_configure(MUX_LPSPI3_CS); +#endif +#ifdef GPIO_LPSPI3_CS + imx9_config_gpio(GPIO_LPSPI3_CS); +#endif +#if defined(GPIO_LPSPI3_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI3_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI4 + if (bus == 4) + { + /* Select SPI4 */ + + priv = &g_lpspi4dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI4 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI4_SCK); + imx9_iomux_configure(MUX_LPSPI4_MISO); + imx9_iomux_configure(MUX_LPSPI4_MOSI); +#ifdef MUX_LPSPI4_CS + imx9_iomux_configure(MUX_LPSPI4_CS); +#endif +#ifdef GPIO_LPSPI4_CS + imx9_config_gpio(GPIO_LPSPI4_CS); +#endif +#ifdef MUX_LPSPI4_CS1 + imx9_iomux_configure(MUX_LPSPI4_CS1); +#endif +#ifdef GPIO_LPSPI4_CS1 + imx9_config_gpio(GPIO_LPSPI4_CS1); +#endif +#if defined(GPIO_LPSPI4_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI4_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI5 + if (bus == 5) + { + /* Select SPI5 */ + + priv = &g_lpspi5dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI5 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI5_SCK); + imx9_iomux_configure(MUX_LPSPI5_MISO); + imx9_iomux_configure(MUX_LPSPI5_MOSI); +#ifdef MUX_LPSPI5_CS + imx9_iomux_configure(MUX_LPSPI5_CS); +#endif +#ifdef GPIO_LPSPI5_CS + imx9_config_gpio(GPIO_LPSPI5_CS); +#endif +#if defined(GPIO_LPSPI5_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI5_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI6 + if (bus == 6) + { + /* Select SPI6 */ + + priv = &g_lpspi6dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI6 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI6_SCK); + imx9_iomux_configure(MUX_LPSPI6_MISO); + imx9_iomux_configure(MUX_LPSPI6_MOSI); +#ifdef MUX_LPSPI6_CS + imx9_iomux_configure(MUX_LPSPI6_CS); +#endif +#ifdef GPIO_LPSPI6_CS + imx9_config_gpio(GPIO_LPSPI6_CS); +#endif +#if defined(GPIO_LPSPI6_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI6_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI7 + if (bus == 7) + { + /* Select SPI7 */ + + priv = &g_lpspi7dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI7 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI7_SCK); + imx9_iomux_configure(MUX_LPSPI7_MISO); + imx9_iomux_configure(MUX_LPSPI7_MOSI); +#ifdef MUX_LPSPI7_CS + imx9_iomux_configure(MUX_LPSPI7_CS); +#endif +#ifdef GPIO_LPSPI7_CS + imx9_config_gpio(GPIO_LPSPI7_CS); +#endif +#if defined(GPIO_LPSPI7_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI7_DC); +#endif + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI8 + if (bus == 8) + { + /* Select SPI8 */ + + priv = &g_lpspi8dev; + + /* Only configure if the bus is not already configured */ + + if (priv->refcount == 0) + { + /* Configure SPI6 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI8_SCK); + imx9_iomux_configure(MUX_LPSPI8_MISO); + imx9_iomux_configure(MUX_LPSPI8_MOSI); +#ifdef MUX_LPSPI8_CS + imx9_iomux_configure(MUX_LPSPI8_CS); +#endif +#ifdef GPIO_LPSPI8_CS + imx9_config_gpio(GPIO_LPSPI8_CS); +#endif +#if defined(GPIO_LPSPI8_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI8_DC); +#endif + } + } + else +#endif + { + leave_critical_section(flags); + spierr("ERROR: Unsupported SPI bus: %d\n", bus); + return NULL; + } + + /* Set up default configuration: Master, 8-bit, etc. */ + + if (priv->refcount == 0) + { + imx9_lpspi_bus_initialize(priv); + } + + priv->refcount++; + +#ifdef CONFIG_IMX9_LPSPI_DMA + if (priv->rxch && priv->txch) + { + if (priv->txdma == NULL && priv->rxdma == NULL) + { + priv->txdma = imx9_dmach_alloc(priv->txch, 0); + priv->rxdma = imx9_dmach_alloc(priv->rxch, 0); + DEBUGASSERT(priv->rxdma && priv->txdma); + } + } + else + { + priv->rxdma = NULL; + priv->txdma = NULL; + } +#endif + + leave_critical_section(flags); + return (struct spi_dev_s *)priv; +} + +/**************************************************************************** + * Name: imx9_lpspibus_uninitialize + * + * Description: + * Unitialize the selected SPI bus + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_lpspi_uninitialize(struct spi_dev_s *dev) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + + if (priv->refcount > 0) + { + priv->refcount--; + if (priv->refcount == 0) + { + imx9_lpspi_modifyreg32(priv, + IMX9_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + } + } +} + +#endif /* CONFIG_IMX9_LPSPI */ diff --git a/arch/arm/src/imx9/imx9_lpspi.h b/arch/arm/src/imx9/imx9_lpspi.h new file mode 100644 index 0000000000000..d1e2f3f617932 --- /dev/null +++ b/arch/arm/src/imx9/imx9_lpspi.h @@ -0,0 +1,162 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lpspi.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LPSPI_H +#define __ARCH_ARM_SRC_IMX9_IMX9_LPSPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "chip.h" +#include "hardware/imx9_lpspi.h" + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +struct spi_dev_s; /* Forward reference */ + +/**************************************************************************** + * Name: imx9_lpspibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * bus number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *imx9_lpspibus_initialize(int bus); + +/**************************************************************************** + * Name: imx9_lpspibus_uninitialize + * + * Description: + * Unitialize the selected SPI bus if refcount is 1 + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_lpspi_uninitialize(struct spi_dev_s *dev); + +/**************************************************************************** + * Name: imx9_lpspi1/2/...select and imx9_lpspi1/2/...status + * + * Description: + * The external functions, imx9_lpspi1/2/...select, + * imx9_lpspi1/2/...status, and imx9_lpspi1/2/...cmddata must be + * provided by board-specific logic. These are implementations of the + * select, status, and cmddata methods of the SPI interface defined by + * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including imx9_lpspibus_initialize()) are provided by common IMX9 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in imx9_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide imx9_lpspi1/2/...select() and imx9_lpspi1/2/...status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, + * then provide imx9_lpspi1/2/...cmddata() functions in your + * board-specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a calls to imx9_lpspibus_initialize() in your low level + * application initialization logic + * 5. The handle returned by imx9_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +void imx9_lpspi_select(struct spi_dev_s *dev, + uint32_t devid, bool selected); +uint8_t imx9_lpspi_status(struct spi_dev_s *dev, uint32_t devid); +int imx9_lpspi_cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd); +#ifdef CONFIG_IMX9_LPSPI_HWPCS +void imx9_lpspi_hw_select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +#endif + +/**************************************************************************** + * Name: imx9_lpspi1/2/...register + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD driver when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The function to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +int imx9_lpspi_register(struct spi_dev_s *dev, + spi_mediachange_t callback, + void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LPSPI_H */ diff --git a/arch/arm/src/imx9/imx9_lpuart.c b/arch/arm/src/imx9/imx9_lpuart.c new file mode 100644 index 0000000000000..3e35c26ccdb7e --- /dev/null +++ b/arch/arm/src/imx9/imx9_lpuart.c @@ -0,0 +1,2674 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_lpuart.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/imx9_lpuart.h" +#include "hardware/imx9_pinmux.h" +#include "imx9_lowputc.h" +#include "imx9_serial.h" + +#if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA) +# include "chip.h" +# include "imx9_edma.h" +# include "hardware/imx9_dmamux.h" +#endif + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called every time + * the FIFO receives half this number of bytes. + * + * This buffer size should be an even multiple of the Cortex-A55 D-Cache line + * size, ARMV8A_DCACHE_LINESIZE, so that it can be individually invalidated. + */ + +# if !defined(ARMV8A_DCACHE_LINESIZE) || ARMV8A_DCACHE_LINESIZE == 0 +# undef ARMV8A_DCACHE_LINESIZE +# define ARMV8A_DCACHE_LINESIZE 64 +# endif + +# if !defined(CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE < ARMV8A_DCACHE_LINESIZE) +# undef CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE ARMV8A_DCACHE_LINESIZE +# endif + +# define RXDMA_BUFFER_MASK (ARMV8A_DCACHE_LINESIZE - 1) +# define RXDMA_BUFFER_SIZE ((CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) + +/* The DMA buffer size when using TX DMA. + * + * This TX buffer size should be an even multiple of the Cortex-A55 D-Cache + * line size, ARMV8A_DCACHE_LINESIZE, so that it can be individually + * invalidated. + */ + +#define TXDMA_BUFFER_MASK (ARMV8A_DCACHE_LINESIZE - 1) +#define TXDMA_BUFFER_SIZE ((CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) + +/* Buffers need to be aligned and multiples of ARMV8A_DCACHE_LINESIZE */ + +#if defined(CONFIG_ARM_DCACHE_DISABLE) +# define TXDMA_BUF_SIZE(b) (b) +# define TXDMA_BUF_ALIGN +#else +# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK) +# define TXDMA_BUF_ALIGN aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#if !defined(CONFIG_LPUART1_TXDMA) +# define LPUART1_TXBUFSIZE_ADJUSTED CONFIG_LPUART1_TXBUFSIZE +# define LPUART1_TXBUFSIZE_ALGN +#else +# define LPUART1_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART1_TXBUFSIZE) +# define LPUART1_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART2_TXDMA) +# define LPUART2_TXBUFSIZE_ADJUSTED CONFIG_LPUART2_TXBUFSIZE +# define LPUART2_TXBUFSIZE_ALGN +#else +# define LPUART2_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART2_TXBUFSIZE) +# define LPUART2_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART3_TXDMA) +# define LPUART3_TXBUFSIZE_ADJUSTED CONFIG_LPUART3_TXBUFSIZE +# define LPUART3_TXBUFSIZE_ALGN +#else +# define LPUART3_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART3_TXBUFSIZE) +# define LPUART3_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART4_TXDMA) +# define LPUART4_TXBUFSIZE_ADJUSTED CONFIG_LPUART4_TXBUFSIZE +# define LPUART4_TXBUFSIZE_ALGN +#else +# define LPUART4_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART4_TXBUFSIZE) +# define LPUART4_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART5_TXDMA) +# define LPUART5_TXBUFSIZE_ADJUSTED CONFIG_LPUART5_TXBUFSIZE +# define LPUART5_TXBUFSIZE_ALGN +#else +# define LPUART5_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART5_TXBUFSIZE) +# define LPUART5_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART6_TXDMA) +# define LPUART6_TXBUFSIZE_ADJUSTED CONFIG_LPUART6_TXBUFSIZE +# define LPUART6_TXBUFSIZE_ALGN +#else +# define LPUART6_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART6_TXBUFSIZE) +# define LPUART6_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART7_TXDMA) +# define LPUART7_TXBUFSIZE_ADJUSTED CONFIG_LPUART7_TXBUFSIZE +# define LPUART7_TXBUFSIZE_ALGN +#else +# define LPUART7_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART7_TXBUFSIZE) +# define LPUART7_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART8_TXDMA) +# define LPUART8_TXBUFSIZE_ADJUSTED CONFIG_LPUART8_TXBUFSIZE +# define LPUART8_TXBUFSIZE_ALGN +#else +# define LPUART8_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART8_TXBUFSIZE) +# define LPUART8_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +/* Which LPUART with be console? */ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart1priv /* LPUART1 is console */ +# if defined(CONFIG_LPUART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart2priv /* LPUART2 is console */ +# if defined(CONFIG_LPUART2_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART2_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart3priv /* LPUART3 is console */ +# if defined(CONFIG_LPUART3_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART3_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart4priv /* LPUART4 is console */ +# if defined(CONFIG_LPUART4_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART4_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart5priv /* LPUART5 is console */ +# if defined(CONFIG_LPUART5_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART5_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart6priv /* LPUART6 is console */ +# if defined(CONFIG_LPUART6_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART6_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart7priv /* LPUART7 is console */ +# if defined(CONFIG_LPUART7_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART7_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart8priv /* LPUART8 is console */ +# if defined(CONFIG_LPUART8_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART8_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#endif + +#if defined(SERIAL_HAVE_CONSOLE_RXDMA) || defined(SERIAL_HAVE_CONSOLE_TXDMA) +# define SERIAL_HAVE_CONSOLE_DMA +#endif + +#ifdef CONFIG_IMX9_LPUART1 +#define TTYS0_DEV g_lpuart1priv /* LPUART1 is ttyS0 */ +#endif + +#ifdef CONFIG_IMX9_LPUART2 +#define TTYS1_DEV g_lpuart2priv /* LPUART2 is ttyS1 */ +#endif + +#ifdef CONFIG_IMX9_LPUART3 +#define TTYS2_DEV g_lpuart3priv /* LPUART3 is ttyS2 */ +#endif + +#ifdef CONFIG_IMX9_LPUART4 +#define TTYS3_DEV g_lpuart4priv /* LPUART4 is ttyS3 */ +#endif + +#ifdef CONFIG_IMX9_LPUART5 +#define TTYS4_DEV g_lpuart5priv /* LPUART5 is ttyS4 */ +#endif + +#ifdef CONFIG_IMX9_LPUART6 +#define TTYS5_DEV g_lpuart6priv /* LPUART6 is ttyS5 */ +#endif + +#ifdef CONFIG_IMX9_LPUART7 +#define TTYS6_DEV g_lpuart7priv /* LPUART7 is ttyS6 */ +#endif + +#ifdef CONFIG_IMX9_LPUART8 +#define TTYS7_DEV g_lpuart8priv /* LPUART8 is ttyS7 */ +#endif + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_IMX9_PM_SERIAL_ACTIVITY) +# define CONFIG_IMX9_PM_SERIAL_ACTIVITY 10 +#endif + +#if defined(CONFIG_PM) +# define PM_IDLE_DOMAIN 0 /* Revisit */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_uart_s +{ + struct uart_dev_s dev; /* Generic UART device */ + + const uint32_t uartbase; /* Base address of UART registers */ + const int uartnum; /* LPUART number 1-8 */ + const bool usects; /* output flow control (CTS) available */ + const bool userts; /* input flow control (RTS) available */ + const bool rs485mode; /* We are in RS485 (RTS on TX) mode */ + const bool inviflow; /* Invert RTS sense */ + spinlock_t lock; /* Spinlock */ + uint32_t baud; /* Configured baud */ + uint32_t ie; /* Saved enabled interrupts */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits vs 1 */ + bool oflow; /* output flow control (CTS) enabled */ + bool iflow; /* input flow control (RTS) enabled */ + + /* TX DMA state */ + +#ifdef SERIAL_HAVE_TXDMA + const unsigned int txch; /* DMAMUX source of TX DMA request */ + DMACH_HANDLE txdma; /* currently-open transmit DMA stream */ +#endif + + /* RX DMA state */ + +#ifdef SERIAL_HAVE_RXDMA + const unsigned int rxch; /* DMAMUX source of RX DMA request */ + DMACH_HANDLE rxdma; /* currently-open receive DMA stream */ + bool rxenable; /* DMA-based reception en/disable */ + uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ +#ifndef CONFIG_ARM_DCACHE_DISABLE + uint32_t rxdmaavail; /* Number of bytes available without need to + * to invalidate the data cache */ +#endif + char *const rxfifo; /* Receive DMA buffer */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t imx9_serialin(struct imx9_uart_s *priv, + uint32_t offset); +static inline void imx9_serialout(struct imx9_uart_s *priv, + uint32_t offset, uint32_t value); +static inline void imx9_disableuartint(struct imx9_uart_s *priv, + uint32_t *ie); +static inline void imx9_restoreuartint(struct imx9_uart_s *priv, + uint32_t ie); + +static int imx9_setup(struct uart_dev_s *dev); +static void imx9_shutdown(struct uart_dev_s *dev); +static int imx9_attach(struct uart_dev_s *dev); +static void imx9_detach(struct uart_dev_s *dev); +static int imx9_interrupt(int irq, void *context, void *arg); +static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg); +#if !defined(SERIAL_HAVE_ONLY_RXDMA) +static int imx9_receive(struct uart_dev_s *dev, unsigned int *status); +static void imx9_rxint(struct uart_dev_s *dev, bool enable); +static bool imx9_rxavailable(struct uart_dev_s *dev); +#endif +#if !defined(SERIAL_HAVE_ONLY_TXDMA) +static void imx9_txint(struct uart_dev_s *dev, bool enable); +#endif + +static void imx9_send(struct uart_dev_s *dev, int ch); + +static bool imx9_txready(struct uart_dev_s *dev); + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_send(struct uart_dev_s *dev); +static void imx9_dma_txint(struct uart_dev_s *dev, bool enable); +static void imx9_dma_txavailable(struct uart_dev_s *dev); +static void imx9_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int imx9_dma_setup(struct uart_dev_s *dev); +static void imx9_dma_shutdown(struct uart_dev_s *dev); +#endif + +#ifdef SERIAL_HAVE_RXDMA +static int imx9_dma_receive(struct uart_dev_s *dev, + unsigned int *status); +#ifdef CONFIG_PM +static void imx9_dma_reenable(struct imx9_uart_s *priv); +#endif +static void imx9_dma_rxint(struct uart_dev_s *dev, bool enable); +static bool imx9_dma_rxavailable(struct uart_dev_s *dev); + +static void imx9_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +static bool imx9_txempty(struct uart_dev_s *dev); + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int dowmin, + enum pm_state_e pmstate); +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Serial driver UART operations */ + +#if !defined(SERIAL_HAVE_ONLY_TXDMA) && !defined(SERIAL_HAVE_ONLY_RXDMA) +static const struct uart_ops_s g_lpuart_ops = +{ + .setup = imx9_setup, + .shutdown = imx9_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_receive, + .rxint = imx9_rxint, + .rxavailable = imx9_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = imx9_send, + .txint = imx9_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, +}; +#endif + +#if defined(SERIAL_HAVE_RXDMA) && defined(SERIAL_HAVE_TXDMA) +static const struct uart_ops_s g_lpuart_rxtxdma_ops = +{ + .setup = imx9_dma_setup, + .shutdown = imx9_dma_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_dma_receive, + .rxint = imx9_dma_rxint, + .rxavailable = imx9_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = imx9_send, + .txint = imx9_dma_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, + .dmatxavail = imx9_dma_txavailable, + .dmasend = imx9_dma_send, +}; +#endif + +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA) +static const struct uart_ops_s g_lpuart_rxdma_ops = +{ + .setup = imx9_dma_setup, + .shutdown = imx9_dma_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_dma_receive, + .rxint = imx9_dma_rxint, + .rxavailable = imx9_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = imx9_send, + .txint = imx9_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, +}; +#endif + +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA) +static const struct uart_ops_s g_lpuart_txdma_ops = +{ + .setup = imx9_dma_setup, + .shutdown = imx9_dma_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_receive, + .rxint = imx9_rxint, + .rxavailable = imx9_rxavailable, + #ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, + #endif + .send = imx9_send, + .txint = imx9_dma_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, + .dmatxavail = imx9_dma_txavailable, + .dmasend = imx9_dma_send, +}; +#endif + +/* Avoid unused warning */ +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA) +const struct uart_ops_s *g_o0 = &g_lpuart_rxdma_ops; +#endif +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA) +const struct uart_ops_s *g_o1 = &g_lpuart_txdma_ops; +#endif + +/* I/O buffers */ + +#ifdef CONFIG_LPUART1_RXDMA +static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +# ifdef CONFIG_LPUART2_RXDMA +static char g_lpuart2rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART3_RXDMA +static char g_lpuart3rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART4_RXDMA +static char g_lpuart4rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART5_RXDMA +static char g_lpuart5rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART6_RXDMA +static char g_lpuart6rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART7_RXDMA +static char g_lpuart7rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART8_RXDMA +static char g_lpuart8rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_IMX9_LPUART1 +static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_lpuart1txbuffer[LPUART1_TXBUFSIZE_ADJUSTED] + LPUART1_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART2 +static char g_lpuart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; +static char g_lpuart2txbuffer[LPUART2_TXBUFSIZE_ADJUSTED] + LPUART2_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART3 +static char g_lpuart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; +static char g_lpuart3txbuffer[LPUART3_TXBUFSIZE_ADJUSTED] + LPUART3_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART4 +static char g_lpuart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE]; +static char g_lpuart4txbuffer[LPUART4_TXBUFSIZE_ADJUSTED] + LPUART4_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART5 +static char g_lpuart5rxbuffer[CONFIG_LPUART5_RXBUFSIZE]; +static char g_lpuart5txbuffer[LPUART5_TXBUFSIZE_ADJUSTED] + LPUART5_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART6 +static char g_lpuart6rxbuffer[CONFIG_LPUART6_RXBUFSIZE]; +static char g_lpuart6txbuffer[LPUART6_TXBUFSIZE_ADJUSTED] + LPUART6_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART7 +static char g_lpuart7rxbuffer[CONFIG_LPUART7_RXBUFSIZE]; +static char g_lpuart7txbuffer[LPUART7_TXBUFSIZE_ADJUSTED] + LPUART7_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART8 +static char g_lpuart8rxbuffer[CONFIG_LPUART8_RXBUFSIZE]; +static char g_lpuart8txbuffer[LPUART8_TXBUFSIZE_ADJUSTED] \ + LPUART8_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART1 +static struct imx9_uart_s g_lpuart1priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_lpuart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_lpuart1txbuffer, + }, +# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART1_BASE, + .uartnum = 1, + .baud = CONFIG_LPUART1_BAUD, + .irq = IMX9_IRQ_LPUART1, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART1_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART1_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART1_TXDMA + .txch = DMA_REQUEST_MUXLPUART1TX, +# endif +# ifdef CONFIG_LPUART1_RXDMA + .rxch = DMA_REQUEST_MUXLPUART1RX, + .rxfifo = g_lpuart1rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART2 +static struct imx9_uart_s g_lpuart2priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART2_RXBUFSIZE, + .buffer = g_lpuart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART2_TXBUFSIZE, + .buffer = g_lpuart2txbuffer, + }, +# if defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART2_RXDMA) && !defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART2_BASE, + .uartnum = 2, + .baud = CONFIG_LPUART2_BAUD, + .irq = IMX9_IRQ_LPUART2, + .parity = CONFIG_LPUART2_PARITY, + .bits = CONFIG_LPUART2_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART2_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART2_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART2_TXDMA + .txch = DMA_REQUEST_MUXLPUART2TX, +# endif +# ifdef CONFIG_LPUART2_RXDMA + .rxch = DMA_REQUEST_MUXLPUART2RX, + .rxfifo = g_lpuart2rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART3 +static struct imx9_uart_s g_lpuart3priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART3_RXBUFSIZE, + .buffer = g_lpuart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART3_TXBUFSIZE, + .buffer = g_lpuart3txbuffer, + }, +# if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART3_BASE, + .uartnum = 3, + .baud = CONFIG_LPUART3_BAUD, + .irq = IMX9_IRQ_LPUART3, + .parity = CONFIG_LPUART3_PARITY, + .bits = CONFIG_LPUART3_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART3_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART3_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART3_TXDMA + .txch = DMA_REQUEST_MUXLPUART3TX, +# endif +# ifdef CONFIG_LPUART3_RXDMA + .rxch = DMA_REQUEST_MUXLPUART3RX, + .rxfifo = g_lpuart3rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART4 +static struct imx9_uart_s g_lpuart4priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART4_RXBUFSIZE, + .buffer = g_lpuart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART4_TXBUFSIZE, + .buffer = g_lpuart4txbuffer, + }, +# if defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART4_RXDMA) && !defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART4_BASE, + .uartnum = 4, + .baud = CONFIG_LPUART4_BAUD, + .irq = IMX9_IRQ_LPUART4, + .parity = CONFIG_LPUART4_PARITY, + .bits = CONFIG_LPUART4_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART4_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART4_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART4_TXDMA + .txch = DMA_REQUEST_MUXLPUART4TX, +# endif +# ifdef CONFIG_LPUART4_RXDMA + .rxch = DMA_REQUEST_MUXLPUART4RX, + .rxfifo = g_lpuart4rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART5 +static struct imx9_uart_s g_lpuart5priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART5_RXBUFSIZE, + .buffer = g_lpuart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART5_TXBUFSIZE, + .buffer = g_lpuart5txbuffer, + }, +# if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART5_BASE, + .uartnum = 5, + .baud = CONFIG_LPUART5_BAUD, + .irq = IMX9_IRQ_LPUART5, + .parity = CONFIG_LPUART5_PARITY, + .bits = CONFIG_LPUART5_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART5_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART5_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART5_TXDMA + .txch = DMA_REQUEST_MUXLPUART5TX, +# endif +# ifdef CONFIG_LPUART5_RXDMA + .rxch = DMA_REQUEST_MUXLPUART5RX, + .rxfifo = g_lpuart5rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART6 +static struct imx9_uart_s g_lpuart6priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART6_RXBUFSIZE, + .buffer = g_lpuart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART6_TXBUFSIZE, + .buffer = g_lpuart6txbuffer, + }, +# if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART6_BASE, + .uartnum = 6, + .baud = CONFIG_LPUART6_BAUD, + .irq = IMX9_IRQ_LPUART6, + .parity = CONFIG_LPUART6_PARITY, + .bits = CONFIG_LPUART6_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART6_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART6_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART6_TXDMA + .txch = DMA_REQUEST_MUXLPUART6TX, +# endif +# ifdef CONFIG_LPUART6_RXDMA + .rxch = DMA_REQUEST_MUXLPUART6RX, + .rxfifo = g_lpuart6rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART7 +static struct imx9_uart_s g_lpuart7priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART7_RXBUFSIZE, + .buffer = g_lpuart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART7_TXBUFSIZE, + .buffer = g_lpuart7txbuffer, + }, +# if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART7_BASE, + .uartnum = 7, + .baud = CONFIG_LPUART7_BAUD, + .irq = IMX9_IRQ_LPUART7, + .parity = CONFIG_LPUART7_PARITY, + .bits = CONFIG_LPUART7_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART7_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART7_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART7_TXDMA + .txch = DMA_REQUEST_MUXLPUART7TX, +# endif +# ifdef CONFIG_LPUART7_RXDMA + .rxch = DMA_REQUEST_MUXLPUART7RX, + .rxfifo = g_lpuart7rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART8 +static struct imx9_uart_s g_lpuart8priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART8_RXBUFSIZE, + .buffer = g_lpuart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART8_TXBUFSIZE, + .buffer = g_lpuart8txbuffer, + }, + #if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + }, + + .uartbase = IMX9_LPUART8_BASE, + .uartnum = 8, + .baud = CONFIG_LPUART8_BAUD, + .irq = IMX9_IRQ_LPUART8, + .parity = CONFIG_LPUART8_PARITY, + .bits = CONFIG_LPUART8_BITS, + .lock = SP_UNLOCKED, + .stopbits2 = CONFIG_LPUART8_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) + .usects = true, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) + .userts = true, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART8_INVERTIFLOWCONTROL) + .inviflow = true, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) + .rs485mode = true, +# endif + +# ifdef CONFIG_LPUART8_TXDMA + .txch = DMA_REQUEST_MUXLPUART8TX, +# endif +# ifdef CONFIG_LPUART8_RXDMA + .rxch = DMA_REQUEST_MUXLPUART8RX, + .rxfifo = g_lpuart8rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_PM +static struct pm_callback_s g_serial_pmcb = +{ + .notify = up_pm_notify, + .prepare = up_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_serialin + ****************************************************************************/ + +static inline uint32_t imx9_serialin(struct imx9_uart_s *priv, + uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imx9_serialout + ****************************************************************************/ + +static inline void imx9_serialout(struct imx9_uart_s *priv, + uint32_t offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imx9_dma_nextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int imx9_dma_nextrx(struct imx9_uart_s *priv) +{ + int dmaresidual = imx9_dmach_getcount(priv->rxdma); + DEBUGASSERT(dmaresidual <= RXDMA_BUFFER_SIZE); + + return (RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE; +} +#endif + +/**************************************************************************** + * Name: imx9_disableuartint + ****************************************************************************/ + +static inline void imx9_disableuartint_nolock(struct imx9_uart_s *priv, + uint32_t *ie) +{ + uint32_t regval; + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + + /* Return the current Rx and Tx interrupt state */ + + if (ie != NULL) + { + *ie = regval & LPUART_ALL_INTS; + } + + regval &= ~LPUART_ALL_INTS; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); +} + +static inline void imx9_disableuartint(struct imx9_uart_s *priv, + uint32_t *ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + imx9_disableuartint_nolock(priv, ie); + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: imx9_restoreuartint + ****************************************************************************/ + +static inline void imx9_restoreuartint_nolock(struct imx9_uart_s *priv, + uint32_t ie) +{ + uint32_t regval; + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); +} + +static inline void imx9_restoreuartint(struct imx9_uart_s *priv, + uint32_t ie) +{ + irqstate_t flags; + + /* Enable/disable any interrupts that are currently disabled but should be + * enabled/disabled. + */ + + flags = spin_lock_irqsave(&priv->lock); + imx9_restoreuartint_nolock(priv, ie); + spin_unlock_irqrestore(&priv->lock, flags); +} + +/**************************************************************************** + * Name: imx9_dma_setup + * + * Description: + * Configure the LPUART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int imx9_dma_setup(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; +#if defined(SERIAL_HAVE_RXDMA) + struct imx9_edma_xfrconfig_s config; +#endif + int result; + + /* Do the basic UART setup first, unless we are the console */ + + if (!dev->isconsole) + { + result = imx9_setup(dev); + if (result != OK) + { + return result; + } + } + +#if defined(SERIAL_HAVE_TXDMA) + /* Acquire the Tx DMA channel. This should always succeed. */ + + if (priv->txch != 0) + { + if (priv->txdma == NULL) + { + priv->txdma = imx9_dmach_alloc(priv->txch, 0); + if (priv->txdma == NULL) + { + return -EBUSY; + } + } + + /* Enable Tx DMA for the UART */ + + modifyreg32(priv->uartbase + IMX9_LPUART_BAUD_OFFSET, + 0, LPUART_BAUD_TDMAE); + } +#endif + +#if defined(SERIAL_HAVE_RXDMA) + /* Acquire the Rx DMA channel. This should always succeed. */ + + if (priv->rxch != 0) + { + if (priv->rxdma == NULL) + { + priv->rxdma = imx9_dmach_alloc(priv->rxch, 0); + + if (priv->rxdma == NULL) + { + return -EBUSY; + } + } + else + { + imx9_dmach_stop(priv->rxdma); + } + + /* Configure for circular DMA reception into the RX FIFO */ + + config.saddr = priv->uartbase + IMX9_LPUART_DATA_OFFSET; + config.daddr = (uintptr_t)priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | + EDMA_CONFIG_LOOPDEST | + EDMA_CONFIG_INTHALF | + EDMA_CONFIG_INTMAJOR; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = 0; +#endif + + imx9_dmach_xfrsetup(priv->rxdma , &config); + + /* Reset our DMA shadow pointer and Rx data availability count to + * match the address just programmed above. + */ + + priv->rxdmanext = 0; + +#ifndef CONFIG_ARM_DCACHE_DISABLE + + /* Make sure the rx buffer area is all invalid or clean */ + + up_invalidate_dcache((uintptr_t)priv->rxfifo, + (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); + priv->rxdmaavail = 0; +#endif + + /* Enable receive Rx DMA for the UART */ + + modifyreg32(priv->uartbase + IMX9_LPUART_BAUD_OFFSET, + 0, LPUART_BAUD_RDMAE); + + /* Enable interrupt on idle and erros */ + + modifyreg32(priv->uartbase + IMX9_LPUART_CTRL_OFFSET, 0, + LPUART_CTRL_PEIE | + LPUART_CTRL_FEIE | + LPUART_CTRL_NEIE | + LPUART_CTRL_ILIE); + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + imx9_dmach_start(priv->rxdma, imx9_dma_rxcallback, (void *)priv); + } +#endif + + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial priv is + * opened. + * + ****************************************************************************/ + +static int imx9_setup(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + struct uart_config_s config; + int ret; + + /* Configure the UART */ + + memset(&config, 0, sizeof(config)); + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + + config.users485 = priv->rs485mode; /* Switch into RS485 mode */ + config.userts = priv->iflow; + config.invrts = priv->inviflow; /* Inversion of outbound flow control */ + config.usects = priv->oflow; + + ret = imx9_lpuart_configure(priv->uartbase, priv->uartnum, &config); + + priv->ie = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET) & \ + LPUART_ALL_INTS; + return ret; + +#else + priv->ie = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET) & \ + LPUART_ALL_INTS; + return OK; +#endif +} + +/**************************************************************************** + * Name: imx9_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * priv is closed + * + ****************************************************************************/ + +static void imx9_shutdown(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Disable the UART */ + + imx9_serialout(priv, IMX9_LPUART_GLOBAL_OFFSET, LPUART_GLOBAL_RST); +} + +/**************************************************************************** + * Name: imx9_dma_shutdown + * + * Description: + * Disable the LPUART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static void imx9_dma_shutdown(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Perform the normal UART shutdown */ + + imx9_shutdown(dev); + +#if defined(SERIAL_HAVE_RXDMA) + /* Stop the RX DMA channel */ + + if (priv->rxch != 0) + { + imx9_dmach_stop(priv->rxdma); + + /* Release the RX DMA channel */ + + imx9_dmach_free(priv->rxdma); + priv->rxdma = NULL; + } +#endif + +#if defined(SERIAL_HAVE_TXDMA) + /* Stop the TX DMA channel */ + + if (priv->txch != 0) + { + imx9_dmach_stop(priv->txdma); + + /* Release the TX DMA channel */ + + imx9_dmach_free(priv->txdma); + priv->txdma = NULL; + } +#endif +} +#endif + +/**************************************************************************** + * Name: imx9_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial priv is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate + * in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supprivs multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int imx9_attach(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, imx9_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial priv is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void imx9_detach(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: imx9_interrupt (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int imx9_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct imx9_uart_s *priv; + uint32_t usr; + uint32_t lsr; + + DEBUGASSERT(dev != NULL && dev != NULL); + priv = (struct imx9_uart_s *)dev; + +#if defined(CONFIG_PM) && CONFIG_IMX9_PM_SERIAL_ACTIVITY > 0 + /* Repriv serial activity to the power management logic */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_IMX9_PM_SERIAL_ACTIVITY); +#endif + + /* Get the current UART status and check for loop + * termination conditions + */ + + usr = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + + /* Removed all W1C from the last sr */ + + lsr = usr & ~(LPUART_STAT_LBKDIF | LPUART_STAT_RXEDGIF | + LPUART_STAT_IDLE | LPUART_STAT_OR | + LPUART_STAT_NF | LPUART_STAT_FE | + LPUART_STAT_PF | LPUART_STAT_MA1F | + LPUART_STAT_MA2F); + + /* Keep what we will service */ + + usr &= (LPUART_STAT_RDRF | LPUART_STAT_TDRE | LPUART_STAT_OR | + LPUART_STAT_FE | LPUART_STAT_NF | LPUART_STAT_PF | + LPUART_STAT_IDLE); + + /* Clear serial overrun, parity and framing errors */ + + if ((usr & LPUART_STAT_OR) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_OR | lsr); + } + + if ((usr & LPUART_STAT_NF) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_NF | lsr); + } + + if ((usr & LPUART_STAT_PF) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_PF | lsr); + } + + if ((usr & LPUART_STAT_FE) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_FE | lsr); + } + + if ((usr & (LPUART_STAT_FE | LPUART_STAT_PF | LPUART_STAT_NF)) != 0) + { + /* Discard data */ + + imx9_serialin(priv, IMX9_LPUART_DATA_OFFSET); + } + +#ifdef SERIAL_HAVE_RXDMA + /* The line going to idle, deliver any fractions of RX data */ + + if ((usr & LPUART_STAT_IDLE) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_IDLE | lsr); + imx9_dma_rxcallback(priv->rxdma, priv, false, LPUART_STAT_IDLE); + } +#endif + + /* Handle incoming, receive bytes */ + + if ((priv->ie & LPUART_CTRL_RIE) != 0 && imx9_rxavailable(&priv->dev)) + { + uart_recvchars(dev); + } + + /* Handle outgoing, transmit bytes */ + + if ((priv->ie & LPUART_CTRL_TIE) != 0) + { + uart_xmitchars(dev); + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || \ + defined(CONFIG_SERIAL_TERMIOS) || \ + defined(CONFIG_IMX9_LPUART_SINGLEWIRE ) || \ + defined(CONFIG_IMX9_LPUART_INVERT ) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct imx9_uart_s *user = (struct imx9_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct imx9_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= priv->stopbits2 ? CSTOPB : 0; + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= (priv->oflow ? CCTS_OFLOW : 0); + +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= (priv->iflow ? CRTS_IFLOW : 0); +#endif + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + +#if defined(CS9) + case 9: + termiosp->c_cflag |= CS9; + break; +#endif + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && !priv->usects) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && !priv->userts) +#endif + ) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + +#if defined(CS9) + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; + + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flags = spin_lock_irqsave(&priv->lock); + imx9_disableuartint_nolock(priv, &ie); + ret = dev->ops->setup(dev); + + /* Restore the interrupt state */ + + imx9_restoreuartint_nolock(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(&priv->lock, flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_IMX9_LPUART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + uint32_t regval; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + flags = spin_lock_irqsave(&priv->lock); + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + regval |= LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC; + } + else + { + regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC); + } + + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + + spin_unlock_irqrestore(&priv->lock, flags); + } + break; +#endif + +#ifdef CONFIG_IMX9_LPUART_INVERT + case TIOCSINVERT: + { + uint32_t ctrl; + uint32_t stat; + uint32_t regval; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + flags = spin_lock_irqsave(&priv->lock); + ctrl = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + stat = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + regval = ctrl; + + /* {R|T}XINV bit field can only be written when the receiver is + * disabled (RE=0). + */ + + regval &= ~LPUART_CTRL_RE; + + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + + /* Enable/disable signal inversion. */ + + if (arg & SER_INVERT_ENABLED_RX) + { + stat |= LPUART_STAT_RXINV; + } + else + { + stat &= ~LPUART_STAT_RXINV; + } + + /* Do not invert TX when in TIOCSSINGLEWIRE */ + + if ((arg & SER_INVERT_ENABLED_TX) && + ((ctrl & LPUART_CTRL_LOOPS) != LPUART_CTRL_LOOPS)) + { + ctrl |= LPUART_CTRL_TXINV; + } + else + { + ctrl &= ~LPUART_CTRL_TXINV; + } + + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, stat); + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, ctrl); + + spin_unlock_irqrestore(&priv->lock, flags); + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_RXDMA +static int imx9_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t rxd; + + rxd = imx9_serialin(priv, IMX9_LPUART_DATA_OFFSET); + *status = rxd >> LPUART_DATA_STATUS_SHIFT; + return (rxd & LPUART_DATA_MASK) >> LPUART_DATA_SHIFT; +} +#endif + +/**************************************************************************** + * Name: imx9_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_RXDMA +static void imx9_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupts for data available at Rx */ + + flags = spin_lock_irqsave(&priv->lock); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE; +#endif + } + else + { + priv->ie &= ~(LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE); + } + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(&priv->lock, flags); +} +#endif + +/**************************************************************************** + * Name: imx9_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_RXDMA +static bool imx9_rxavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t regval; + + /* Return true is data is ready in the Rx FIFO */ + + regval = imx9_serialin(priv, IMX9_LPUART_WATER_OFFSET); + return ((regval & LPUART_WATER_RXCOUNT_MASK) != 0); +} +#endif + +/**************************************************************************** + * Name: imx9_dma_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the LPUART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int imx9_dma_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t nextrx = imx9_dma_nextrx(priv); + int c = 0; + + /* Check if more data is available */ + + if (nextrx != priv->rxdmanext) + { +#ifndef CONFIG_ARM_DCACHE_DISABLE + /* If the data cache is enabled, then we will also need to manage + * cache coherency. Are any bytes available in the currently coherent + * region of the data cache? + */ + + if (priv->rxdmaavail == 0) + { + uint32_t rxdmaavail; + uintptr_t addr; + + /* No.. then we will have to invalidate additional space in the Rx + * DMA buffer. + */ + + if (nextrx > priv->rxdmanext) + { + /* Number of available bytes */ + + rxdmaavail = nextrx - priv->rxdmanext; + } + else + { + /* Number of available bytes up to the end of RXDMA buffer */ + + rxdmaavail = RXDMA_BUFFER_SIZE - priv->rxdmanext; + } + + /* Invalidate the DMA buffer range */ + + addr = (uintptr_t)&priv->rxfifo[priv->rxdmanext]; + up_invalidate_dcache(addr, addr + rxdmaavail); + + /* We don't need to invalidate the data cache for the next + * rxdmaavail number of next bytes. + */ + + priv->rxdmaavail = rxdmaavail; + } + + priv->rxdmaavail--; +#endif + + /* Now read from the DMA buffer */ + + c = priv->rxfifo[priv->rxdmanext]; + + priv->rxdmanext++; + + if (priv->rxdmanext == RXDMA_BUFFER_SIZE) + { + priv->rxdmanext = 0; + } + } + + /* NOTE: If no data is available, then we would return NULL which is, + * of course, valid binary data. The protocol is that the upper half + * driver must call imx9_dma_rxavailable prior to calling this + * function to assure that this never happens. + */ + + return c; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_reenable + * + * Description: + * Call to re-enable RX DMA. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_PM) +static void imx9_dma_reenable(struct imx9_uart_s *priv) +{ + struct imx9_edma_xfrconfig_s config; + + /* Stop an reset the RX DMA */ + + imx9_dmach_stop(priv->rxdma); + + /* Configure for circular DMA reception into the RX FIFO */ + + config.saddr = priv->uartbase + IMX9_LPUART_DATA_OFFSET; + config.daddr = (uint32_t) priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | + EDMA_CONFIG_LOOPDEST | + EDMA_CONFIG_INTHALF | + EDMA_CONFIG_INTMAJOR; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = 0; +#endif + + imx9_dmach_xfrsetup(priv->rxdma, &config); + + /* Reset our DMA shadow pointer and Rx data availability count to match + * the address just programmed above. + */ + + priv->rxdmanext = 0; +#ifndef CONFIG_ARM_DCACHE_DISABLE + priv->rxdmaavail = 0; +#endif + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + imx9_dmach_start(priv->rxdma, imx9_dma_rxcallback, (void *)priv); + + /* Clear DMA suspended flag. */ + + priv->rxdmasusp = false; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void imx9_dma_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Enable/disable DMA reception. + * + * Note that it is not safe to check for available bytes and immediately + * pass them to uart_recvchars as that could potentially recurse back + * to us again. Instead, bytes must wait until the next up_dma_poll or + * DMA event. + */ + + priv->rxenable = enable; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static bool imx9_dma_rxavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Compare our receive pointer to the current DMA pointer, if they + * do not match, then there are bytes to be received. + */ + + return (imx9_dma_nextrx(priv) != priv->rxdmanext); +} +#endif + +/**************************************************************************** + * Name: imx9_dma_txcallback + * + * Description: + * This function clears dma buffer at complete of DMA transfer and wakes up + * threads waiting for space in buffer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)arg; + + /* Update 'nbytes' indicating number of bytes actually transferred by DMA. + * This is important to free TX buffer space by 'uart_xmitchars_done'. + */ + + priv->dev.dmatx.nbytes = priv->dev.dmatx.length; +#if CONFIG_IMX9_EDMA_NTCD > 1 + priv->dev.dmatx.nbytes += priv->dev.dmatx.nlength; +#endif + + /* Adjust the pointers */ + + uart_xmitchars_done(&priv->dev); + + /* Send more data if available */ + + imx9_dma_txavailable(&priv->dev); +} +#endif + +/**************************************************************************** + * Name: imx9_dma_txavailable + * + * Description: + * Informs DMA that Tx data is available and is ready for transfer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_txavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Only send when the DMA is idle */ + + if (imx9_dmach_idle(priv->txdma) == 0) + { + uart_xmitchars_dma(dev); + } +} +#endif + +/**************************************************************************** + * Name: imx9_dma_send + * + * Description: + * Called (usually) from the interrupt level to start DMA transfer. + * (Re-)Configures DMA Stream updating buffer and buffer length. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_send(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + struct imx9_edma_xfrconfig_s config; + + /* We need to stop DMA before reconfiguration */ + + imx9_dmach_stop(priv->txdma); + + /* Reset the number sent */ + + dev->dmatx.nbytes = 0; + + /* Make use of setup function to update buffer and its length for next + * transfer + */ + + config.iter = dev->dmatx.length; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; + config.saddr = (uintptr_t)dev->dmatx.buffer; + config.daddr = priv->uartbase + IMX9_LPUART_DATA_OFFSET; + config.soff = 1; + config.doff = 0; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = 0; +#endif + + /* Flush the contents of the TX buffer into physical memory */ + + up_clean_dcache((uintptr_t)dev->dmatx.buffer, + (uintptr_t)dev->dmatx.buffer + dev->dmatx.length); + + /* Setup first half */ + + imx9_dmach_xfrsetup(priv->txdma, &config); + +#if CONFIG_IMX9_EDMA_NTCD > 1 + /* Is this a split transfer? */ + + if (dev->dmatx.nbuffer) + { + config.iter = priv->dev.dmatx.nlength; + config.saddr = (uintptr_t)priv->dev.dmatx.nbuffer; + + /* Flush the contents of the next TX buffer into physical memory */ + + up_clean_dcache((uintptr_t)dev->dmatx.nbuffer, + (uintptr_t)dev->dmatx.nbuffer + dev->dmatx.nlength); + + imx9_dmach_xfrsetup(priv->txdma, &config); + } +#endif + + /* Start transmission with the callback on DMA completion */ + + imx9_dmach_start(priv->txdma, imx9_dma_txcallback, (void *)priv); +} +#endif + +/**************************************************************************** + * Name: imx9_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void imx9_send(struct uart_dev_s *dev, int ch) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + +#ifdef CONSOLE_DEV + if (dev == &CONSOLE_DEV.dev && !dev->isconsole) + { + return; + } +#endif + + imx9_serialout(priv, IMX9_LPUART_DATA_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: imx9_dma_txint + * + * Description: + * Call to enable or disable TX interrupts from the UART. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_txint(struct uart_dev_s *dev, bool enable) +{ + /* Nothing to do. */ + + /* In case of DMA transfer we do not want to make use of UART interrupts. + * Instead, we use DMA interrupts that are activated once during boot + * sequence. Furthermore we can use imx9_dma_txcallback() to handle + * stuff at half DMA transfer or after transfer completion (depending + * on the configuration). + */ +} +#endif + +/**************************************************************************** + * Name: imx9_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +#if !defined(SERIAL_HAVE_ONLY_TXDMA) +static void imx9_txint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupt for TX complete */ + + flags = spin_lock_irqsave(&priv->lock); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_TIE; +#endif + } + else + { + priv->ie &= ~LPUART_CTRL_TIE; + } + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(&priv->lock, flags); +} +#endif + +/**************************************************************************** + * Name: imx9_txready + * + * Description: + * Return true if the transmit fifo is available to be written to + * + ****************************************************************************/ + +static bool imx9_txready(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t regval; + uint32_t fifo_size; + uint32_t fifo_count; + + /* Read the fifo size and current fill ratio. Return true if fifo is not + * full + */ + + regval = imx9_serialin(priv, IMX9_LPUART_FIFO_OFFSET); + fifo_size = (regval & LPUART_FIFO_TXFIFOSIZE_MASK) >> + LPUART_FIFO_TXFIFOSIZE_SHIFT; + fifo_size = fifo_size == 0 ? 1 : (1 << (fifo_size + 1)); + regval = imx9_serialin(priv, IMX9_LPUART_WATER_OFFSET); + fifo_count = (regval & LPUART_WATER_TXCOUNT_MASK) >> + LPUART_WATER_TXCOUNT_SHIFT; + + return fifo_count < fifo_size; +} + +/**************************************************************************** + * Name: imx9_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool imx9_txempty(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t regval; + + regval = imx9_serialin(priv, IMX9_LPUART_WATER_OFFSET); + return (regval & LPUART_WATER_TXCOUNT_MASK) == 0; +} + +/**************************************************************************** + * Name: imx9_dma_rxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void imx9_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)arg; + uint32_t sr; + + if (priv->rxenable && imx9_dma_rxavailable(&priv->dev)) + { + uart_recvchars(&priv->dev); + } + + /* Get the masked LPUART status word to check and clear error flags. + * + * When wake-up from low power mode was not fast enough, UART is resumed + * too late and sometimes exactly when character was coming over UART, + * resulting to frame error. + * If error flag is not cleared, Rx DMA will be stuck. Clearing errors + * will release Rx DMA. + */ + + sr = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + + if ((sr & (LPUART_STAT_OR | LPUART_STAT_NF | LPUART_STAT_FE)) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + sr & (LPUART_STAT_OR | + LPUART_STAT_NF | + LPUART_STAT_FE)); + } +} +#endif + +/**************************************************************************** + * Name: up_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opprivunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case(PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case(PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case(PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: up_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm_serialinit. + * + ****************************************************************************/ + +void arm_earlyserialinit(void) +{ + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was performed by the + * function imx9_lowsetup() earlier in the boot sequence. + */ + + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.dev.isconsole = true; + imx9_setup(&CONSOLE_DEV.dev); +#endif +} + +/**************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial privs. This assumes + * that imx9_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm_serialinit(void) +{ +#ifdef CONFIG_PM + int ret; + + /* Register to receive power management callbacks */ + + ret = pm_register(&g_serial_pmcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV.dev); +#if defined(SERIAL_HAVE_CONSOLE_DMA) + imx9_dma_setup(&CONSOLE_DEV.dev); +#endif +#endif + + /* Register all UARTs */ + +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV.dev); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV.dev); +#endif +#ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV.dev); +#endif +#ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS3_DEV.dev); +#endif +#ifdef TTYS4_DEV + uart_register("/dev/ttyS4", &TTYS4_DEV.dev); +#endif +#ifdef TTYS5_DEV + uart_register("/dev/ttyS5", &TTYS5_DEV.dev); +#endif +#ifdef TTYS6_DEV + uart_register("/dev/ttyS6", &TTYS6_DEV.dev); +#endif +#ifdef TTYS7_DEV + uart_register("/dev/ttyS7", &TTYS7_DEV.dev); +#endif +} + +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to suppriv OS debug writes + * + ****************************************************************************/ + +void up_putc(int ch) +{ +#ifdef CONSOLE_DEV + struct imx9_uart_s *priv = (struct imx9_uart_s *)&CONSOLE_DEV; + uint32_t ie; + + if (!CONSOLE_DEV.dev.isconsole) + { + return; + } + + imx9_disableuartint(priv, &ie); +#endif + + arm_lowputc(ch); +#ifdef CONSOLE_DEV + imx9_restoreuartint(priv, ie); +#endif +} diff --git a/arch/arm/src/imx9/imx9_mpuinit.c b/arch/arm/src/imx9/imx9_mpuinit.c new file mode 100644 index 0000000000000..94feca18221e7 --- /dev/null +++ b/arch/arm/src/imx9/imx9_mpuinit.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_mpuinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "mpu.h" +#include "barriers.h" + +#include "hardware/imx9_memorymap.h" + +#include "imx9_mpuinit.h" +#include "arm_internal.h" + +#ifdef CONFIG_ARM_MPU + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_ARMV7M_DCACHE + /* With Dcache off: + * Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be off + */ +# undef MPU_RASR_B +# define MPU_RASR_B 0 +# define RASR_B_VALUE 0 +# define RASR_C_VALUE 0 +#else +# ifndef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + /* With Dcache on: + * Cacheable (MPU_RASR_C) and Bufferable (MPU_RASR_B) needs to be on + */ +# define RASR_B_VALUE MPU_RASR_B +# define RASR_C_VALUE MPU_RASR_C + +# else + /* With Dcache in WRITETHROUGH Bufferable (MPU_RASR_B) + * needs to be off, except for FLASH for alignment leniency + */ +# define RASR_B_VALUE 0 +# define RASR_C_VALUE MPU_RASR_C +# endif +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_mpu_initialize + * + * Description: + * Configure the MPU to permit user-space access to only restricted i.MXRT + * resources. + * + ****************************************************************************/ + +void imx9_mpu_initialize(void) +{ + uint32_t regval; + uint32_t region; +#ifdef CONFIG_BUILD_PROTECTED + uintptr_t datastart; + uintptr_t dataend; +#endif + + /* Show MPU information */ + + mpu_showtype(); + + /* Reset MPU if enabled */ + + mpu_reset(); + +#ifdef CONFIG_ARMV7M_DCACHE + /* Memory barrier */ + + ARM_DMB(); +#endif + +#ifdef CONFIG_BUILD_PROTECTED + /* Configure user flash and SRAM space */ + + DEBUGASSERT(USERSPACE->us_textend >= USERSPACE->us_textstart); + + mpu_user_flash(USERSPACE->us_textstart, + USERSPACE->us_textend - USERSPACE->us_textstart); + + datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); + dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); + + DEBUGASSERT(dataend >= datastart); + + mpu_user_intsram(datastart, dataend - datastart); +#else + + region = mpu_allocregion(); + DEBUGASSERT(region == 0); + + /* Select the region */ + + putreg32(region, MPU_RNR); + + /* Select the region base address */ + + putreg32(region | MPU_RBAR_VALID, MPU_RBAR); + + /* The configure the region */ + + regval = MPU_RASR_ENABLE | /* Enable region */ + MPU_RASR_SIZE_LOG2(32) | /* entire memory */ + MPU_RASR_TEX_SO | /* Strongly ordered */ + MPU_RASR_AP_NONO | /* P:None U:None */ + MPU_RASR_XN; /* Execute-never to prevent instruction fetch */ + putreg32(regval, MPU_RASR); + + mpu_configure_region(IMX9_FLEXSPI1_ALIAS_BASE, 32 * 1024 * 1024, + MPU_RASR_AP_RORO | /* P:R0 U:R0 */ + MPU_RASR_TEX_NOR | /* Normal */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B /* Bufferable */ + ); + + mpu_configure_region(IMX9_ITCM_BASE, 512 * 1024, + MPU_RASR_AP_RORO | /* P:R0 U:R0 */ + MPU_RASR_TEX_NOR | /* Normal */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B /* Bufferable */ + ); + + mpu_configure_region(IMX9_DTCM_BASE, 512 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_NOR | /* Normal */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_XN /* Execute-never to prevent instruction fetch */ + ); + + mpu_configure_region(0x20400000, 1 * 1024 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_NOR | /* Normal */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B /* Bufferable */ + ); + + mpu_configure_region(IMX9_FLEXSPI1_BASE, 128 * 1024 * 1024, + MPU_RASR_AP_RORO | /* P:R0 U:R0 */ + MPU_RASR_TEX_NOR | /* Strongly Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B /* Bufferable */ + ); + + /* AIPS1 + AIPS2 */ + + mpu_configure_region(IMX9_AIPS1_BASE, 16 * 1024 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_DEV /* Device */ + ); + + mpu_configure_region(IMX9_AIPS3_BASE, 8 * 1024 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_DEV /* Device */ + ); + + mpu_configure_region(IMX9_AIPS4_BASE, 8 * 1024 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_DEV /* Device */ + ); + + mpu_configure_region(IMX9_GPIO_MEM_BASE, 320 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_DEV /* Device */ + ); + + mpu_configure_region(IMX9_GPIO1_BASE, 64 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_DEV /* Device */ + ); + + /* For RPMSG VRING and RSC table */ + + mpu_configure_region(IMX9_RPMSG_BASE, 4096 * 1024, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_NOR /* Normal */ + ); + + mpu_configure_region(IMX9_DRAM_XIP_BASE, 0x003ff800, + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_TEX_NOR /* Normal */ + ); +#endif + + mpu_control(true, false, true); +} + +/**************************************************************************** + * Name: imx9_mpu_uheap + * + * Description: + * Map the user-heap region. + * + * This logic may need an extension to handle external SDRAM). + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void imx9_mpu_uheap(uintptr_t start, size_t size) +{ + mpu_user_intsram(start, size); +} +#endif + +#endif /* CONFIG_ARM_MPU */ diff --git a/arch/arm/src/imx9/imx9_mpuinit.h b/arch/arm/src/imx9/imx9_mpuinit.h new file mode 100644 index 0000000000000..da44e4671f1e0 --- /dev/null +++ b/arch/arm/src/imx9/imx9_mpuinit.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_mpuinit.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_MPUINIT_H +#define __ARCH_ARM_SRC_IMX9_IMX9_MPUINIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_mpu_initialize + * + * Description: + * Configure the MPU to permit user-space access to only unrestricted + * i.MXRT resources. + * + ****************************************************************************/ + +#ifdef CONFIG_ARM_MPU +void imx9_mpu_initialize(void); +#else +# define imx9_mpu_initialize() +#endif + +/**************************************************************************** + * Name: imx9_mpu_uheap + * + * Description: + * Map the user heap region. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void imx9_mpu_uheap(uintptr_t start, size_t size); +#else +# define imx9_mpu_uheap(start,size) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_MPUINIT_H */ diff --git a/arch/arm/src/imx9/imx9_mu.c b/arch/arm/src/imx9/imx9_mu.c new file mode 100644 index 0000000000000..6ac472a65c017 --- /dev/null +++ b/arch/arm/src/imx9/imx9_mu.c @@ -0,0 +1,287 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_mu.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imx9_mu.h" +#include "arm_internal.h" +#include "hardware/imx95/imx95_memorymap.h" +#include "hardware/imx9_mu.h" +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NR_OF_GPI 4 +#define MSG_INT_MASK ((1 << IMX9_MU_RR_REGARRAY_SIZE) - 1) +#define GPI_INT_MASK ((1 << NR_OF_GPI) - 1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_mudev_s +{ + uint32_t mubase; + uint32_t irq; + imx9_mu_msg_callback_t msg_callback; + imx9_mu_gpi_callback_t gpi_callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_IMX9_MU5 +static struct imx9_mudev_s g_mu5_dev = /* clang-format off */ +{ + .mubase = IMX9_MU5_MUA_BASE, + .irq = IMX9_IRQ_MU5_A +}; /* clang-format on */ +#endif + +#ifdef CONFIG_IMX9_MU7 +static struct imx9_mudev_s g_mu7_dev = /* clang-format off */ +{ + .mubase = IMX9_MU7_MUB_BASE, + .irq = IMX9_IRQ_MU7_B +}; /* clang-format on */ +#endif + +#ifdef CONFIG_IMX9_MU8 +static struct imx9_mudev_s g_mu8_dev = /* clang-format off */ +{ + .mubase = IMX9_MU8_MUB_BASE, + .irq = IMX9_IRQ_MU8_B +}; /* clang-format on */ +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int imx9_mu_interrupt(int irq, void *context, void *args) +{ + struct imx9_mudev_s *dev = args; + + uint32_t sr = getreg32(IMX9_MU_SR(dev->mubase)); + uint32_t rsr = getreg32(IMX9_MU_RSR(dev->mubase)); + uint32_t gsr = getreg32(IMX9_MU_GSR(dev->mubase)); + + ipcinfo("MU irq=%d, SR=0x%04lx, RSR=0x%04lx, GSR=0x%04lx\n", irq, sr, rsr, + gsr); + + if (sr & IMX9_MU_SR_RFP_FLAG) + { + for (int i = 0; i < IMX9_MU_RR_REGARRAY_SIZE; i++) + { + if (rsr & (1 << i)) + { + uint32_t msg = imx95_mu_receive_msg_non_blocking(dev, i); + + if (dev->msg_callback) + { + dev->msg_callback(i, msg, dev); + } + } + } + + for (int i = 0; i < NR_OF_GPI; i++) + { + if (gsr & (1 << i)) + { + putreg32((1 << i), IMX9_MU_GSR(dev->mubase)); + + if (dev->gpi_callback) + { + dev->gpi_callback(i, dev); + } + } + } + } + + /* Unknown interrupt flag which occurs when A55 shuts down */ + + if (sr & 0x80) + { + /* TODO how to clear this flag? A W1C doesn't seem to work.. */ + + putreg32(0x80, IMX9_MU_SR(dev->mubase)); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +struct imx9_mudev_s *imx95_mu_init(int index) +{ + struct imx9_mudev_s *priv; + +#ifdef CONFIG_IMX9_MU5 + if ((index == 5)) + { + priv = &g_mu5_dev; + } + + else +#endif +#ifdef CONFIG_IMX9_MU7 + if ((index == 7)) + { + priv = &g_mu7_dev; + } + + else +#endif +#ifdef CONFIG_IMX9_MU8 + if ((index == 8)) + { + priv = &g_mu8_dev; + } + + else +#endif + { + return NULL; + } + + irq_attach(priv->irq, imx9_mu_interrupt, priv); + up_enable_irq(priv->irq); + + priv->gpi_callback = NULL; + priv->msg_callback = NULL; + + return priv; +} + +void imx95_mu_subscribe_msg(struct imx9_mudev_s *priv, + uint32_t msg_int_bitfield, + imx9_mu_msg_callback_t callback) +{ + priv->msg_callback = callback; + putreg32(msg_int_bitfield & MSG_INT_MASK, IMX9_MU_RCR(priv->mubase)); +} + +void imx95_mu_subscribe_gpi(struct imx9_mudev_s *priv, + uint32_t gpi_int_enable, + imx9_mu_gpi_callback_t callback) +{ + priv->gpi_callback = callback; + putreg32(gpi_int_enable & GPI_INT_MASK, IMX9_MU_GIER(priv->mubase)); +} + +void imx95_mu_deinit(struct imx9_mudev_s *priv) +{ + up_disable_irq(priv->irq); +} + +int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index, uint32_t msg) +{ + assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE); + + ipcinfo("MU send msg nonblocking idx=%ld, msg=%ld\n", reg_index, msg); + + if ((getreg32(IMX9_MU_TSR(priv->mubase)) & (1UL << reg_index)) == 0UL) + { + return -EBUSY; + } + + putreg32(msg, IMX9_MU_TR1(priv->mubase) + (reg_index * sizeof(uint32_t))); + return OK; +} + +void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, + uint32_t msg) +{ + assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE); + + ipcinfo("MU send msg idx=%ld, msg=%ld\n", reg_index, msg); + + /* Wait TX register to be empty. */ + + while ((getreg32(IMX9_MU_TSR(priv->mubase)) & (1UL << reg_index)) == 0UL) + ; + + putreg32(msg, IMX9_MU_TR1(priv->mubase) + (reg_index * sizeof(uint32_t))); +} + +int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index) +{ + if ((getreg32(IMX9_MU_RSR(priv->mubase)) & (1UL << reg_index)) == 0UL) + { + return -ENODATA; + } + + return 0; +} + +uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index) +{ + assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE); + + return getreg32(IMX9_MU_RR1(priv->mubase) + + (reg_index * sizeof(uint32_t))); +} + +uint32_t imx95_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index) +{ + assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE); + + /* Wait RX register to be full. */ + + while (imx95_mu_has_received_msg(priv, reg_index) == -ENODATA); + + return getreg32(IMX9_MU_RR1(priv->mubase) + + (reg_index * sizeof(uint32_t))); +} + +int imx95_mu_trigger_interrupts(struct imx9_mudev_s *priv, + uint32_t interrupts) +{ + int ret = -ECOMM; + uint32_t gcr = getreg32(IMX9_MU_GCR(priv->mubase)); + + /* Only if previous interrupts has been accepted. */ + + if ((gcr & interrupts) == 0) + { + putreg32(gcr | interrupts, IMX9_MU_GCR(priv->mubase)); + ret = OK; + } + + return ret; +} diff --git a/arch/arm/src/imx9/imx9_mu.h b/arch/arm/src/imx9/imx9_mu.h new file mode 100644 index 0000000000000..b929b4f80ad46 --- /dev/null +++ b/arch/arm/src/imx9/imx9_mu.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_mu.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_MU_H +#define __ARCH_ARM_SRC_IMX9_IMX9_MU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +typedef void (*imx9_mu_msg_callback_t)(int id, uint32_t msg, void *arg); +typedef void (*imx9_mu_gpi_callback_t)(int id, void *arg); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct imx9_mudev_s *imx95_mu_init(int index); +void imx95_mu_subscribe_msg(struct imx9_mudev_s *priv, + uint32_t msg_int_bitfield, + imx9_mu_msg_callback_t callback); +void imx95_mu_subscribe_gpi(struct imx9_mudev_s *priv, + uint32_t gpi_int_enable, + imx9_mu_gpi_callback_t callback); + +void imx95_mu_deinit(struct imx9_mudev_s *priv); +int imx95_mu_send_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index, uint32_t msg); +void imx95_mu_send_msg(struct imx9_mudev_s *priv, uint32_t reg_index, + uint32_t msg); +int imx95_mu_has_received_msg(struct imx9_mudev_s *priv, uint32_t reg_index); +uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mudev_s *priv, + uint32_t reg_index); +uint32_t imx95_mu_receive_msg(struct imx9_mudev_s *priv, uint32_t reg_index); +int imx95_mu_trigger_interrupts(struct imx9_mudev_s *priv, + uint32_t interrupts); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_MU_H */ diff --git a/arch/arm/src/imx9/imx9_rptun.c b/arch/arm/src/imx9/imx9_rptun.c new file mode 100644 index 0000000000000..c80093beac3fb --- /dev/null +++ b/arch/arm/src/imx9/imx9_rptun.c @@ -0,0 +1,301 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_rptun.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imx9_rptun.h" +#include "arm_internal.h" +#include "imx9_mu.h" +#include "imx9_rsctable.h" +#include +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define VRING_SHMEM 0x88220000 /* Vring shared memory start */ + +#define RPMSG_MU_CHANNEL 1 +#define MU_INSTANCE 7 + +#define MU_MSG_VQID_BITOFFSET 16 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* IMX9 rptun shared memory */ + +struct imx9_rptun_shmem_s +{ + struct rptun_rsc_s rsc; +}; + +/* IMX9 rptun device */ + +struct imx9_rptun_dev_s +{ + struct rptun_dev_s rptun; + rptun_callback_t callback; + void *mu; + void *arg; + struct imx9_rptun_shmem_s *shmem; + char cpuname[RPMSG_NAME_SIZE + 1]; + char shmemname[RPMSG_NAME_SIZE + 1]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static const char *imx9_rptun_get_cpuname(struct rptun_dev_s *dev); +static const char *imx9_rptun_get_firmware(struct rptun_dev_s *dev); +static const struct rptun_addrenv_s * +imx9_rptun_get_addrenv(struct rptun_dev_s *dev); +static struct rptun_rsc_s *imx9_rptun_get_resource(struct rptun_dev_s *dev); +static bool imx9_rptun_is_autostart(struct rptun_dev_s *dev); +static bool imx9_rptun_is_master(struct rptun_dev_s *dev); +static int imx9_rptun_start(struct rptun_dev_s *dev); +static int imx9_rptun_stop(struct rptun_dev_s *dev); +static int imx9_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid); +static int imx9_rptun_register_callback(struct rptun_dev_s *dev, + rptun_callback_t callback, + void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct rptun_ops_s g_imx9_rptun_ops = +{ + .get_cpuname = imx9_rptun_get_cpuname, + .get_firmware = imx9_rptun_get_firmware, + .get_addrenv = imx9_rptun_get_addrenv, + .get_resource = imx9_rptun_get_resource, + .is_autostart = imx9_rptun_is_autostart, + .is_master = imx9_rptun_is_master, + .start = imx9_rptun_start, + .stop = imx9_rptun_stop, + .notify = imx9_rptun_notify, + .register_callback = imx9_rptun_register_callback, +}; + +struct imx9_rptun_dev_s g_rptun_dev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_rptun_get_cpuname + ****************************************************************************/ + +static const char *imx9_rptun_get_cpuname(struct rptun_dev_s *dev) +{ + struct imx9_rptun_dev_s *priv = + container_of(dev, struct imx9_rptun_dev_s, rptun); + + return priv->cpuname; +} + +/**************************************************************************** + * Name: imx9_rptun_get_firmware + ****************************************************************************/ + +static const char *imx9_rptun_get_firmware(struct rptun_dev_s *dev) +{ + return NULL; +} + +/**************************************************************************** + * Name: imx9_rptun_get_addrenv + ****************************************************************************/ + +static const struct rptun_addrenv_s * +imx9_rptun_get_addrenv(struct rptun_dev_s *dev) +{ + return NULL; +} + +/**************************************************************************** + * Name: imx9_rptun_get_resource + ****************************************************************************/ + +static struct rptun_rsc_s *imx9_rptun_get_resource(struct rptun_dev_s *dev) +{ + struct imx9_rptun_dev_s *priv = + container_of(dev, struct imx9_rptun_dev_s, rptun); + + if (priv->shmem != NULL) + { + return &priv->shmem->rsc; + } + + priv->shmem = (struct imx9_rptun_shmem_s *)VRING_SHMEM; + if (priv->shmem->rsc.rsc_tbl_hdr.offset + != g_imx9_rsc_table.rsc_tbl_hdr.offset) + { + imx9_rsctable_copy(); + } + + return &priv->shmem->rsc; +} + +/**************************************************************************** + * Name: imx9_rptun_is_autostart + ****************************************************************************/ + +static bool imx9_rptun_is_autostart(struct rptun_dev_s *dev) +{ + return true; +} + +/**************************************************************************** + * Name: imx9_rptun_is_master + ****************************************************************************/ + +static bool imx9_rptun_is_master(struct rptun_dev_s *dev) +{ + return false; +} + +/**************************************************************************** + * Name: imx9_rptun_start + ****************************************************************************/ + +static int imx9_rptun_start(struct rptun_dev_s *dev) +{ + return 0; +} + +/**************************************************************************** + * Name: imx9_rptun_stop + ****************************************************************************/ + +static int imx9_rptun_stop(struct rptun_dev_s *dev) +{ + return 0; +} + +/**************************************************************************** + * Name: imx9_rptun_notify + ****************************************************************************/ + +static int imx9_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid) +{ + struct imx9_rptun_dev_s *priv = + container_of(dev, struct imx9_rptun_dev_s, rptun); + + ipcinfo("Rptun notify vqid=%ld\n", vqid); + + imx95_mu_send_msg(priv->mu, RPMSG_MU_CHANNEL, + vqid << MU_MSG_VQID_BITOFFSET); + + return 0; +} + +/**************************************************************************** + * Name: imx9_rptun_register_callback + ****************************************************************************/ + +static int imx9_rptun_register_callback(struct rptun_dev_s *dev, + rptun_callback_t callback, void *arg) +{ + struct imx9_rptun_dev_s *priv = + container_of(dev, struct imx9_rptun_dev_s, rptun); + + priv->callback = callback; + priv->arg = arg; + + return 0; +} + +/**************************************************************************** + * Name: imx9_mu_callback + ****************************************************************************/ + +static void imx9_mu_callback(int id, uint32_t msg, void *arg) +{ + if (id == RPMSG_MU_CHANNEL) + { + struct imx9_rptun_dev_s *dev = &g_rptun_dev; + uint32_t vqid = msg >> MU_MSG_VQID_BITOFFSET; + + ipcinfo("Rptun interrupt id=%d, vqid=%ld\n", id, vqid); + + if (dev->callback != NULL) + { + dev->callback(dev->arg, vqid); + } + } + + else + { + DEBUGASSERT(0); + } + + __asm volatile("dsb 0xF" ::: "memory"); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int imx9_rptun_init(const char *shmemname, const char *cpuname) +{ + struct imx9_rptun_dev_s *dev = &g_rptun_dev; + int ret = OK; + + /* Subscribe to MU */ + + dev->mu = imx95_mu_init(MU_INSTANCE); + if (!dev->mu) + { + ipcerr("ERROR: cannot init mailbox %i!\n", MU_INSTANCE); + return ret; + } + + imx95_mu_subscribe_msg(dev->mu, (1 << RPMSG_MU_CHANNEL), imx9_mu_callback); + + /* Configure device */ + + dev->rptun.ops = &g_imx9_rptun_ops; + strncpy(dev->cpuname, cpuname, RPMSG_NAME_SIZE); + strncpy(dev->shmemname, shmemname, RPMSG_NAME_SIZE); + + ret = rptun_initialize(&dev->rptun); + if (ret < 0) + { + ipcerr("ERROR: rptun_initialize failed %d!\n", ret); + } + + return ret; +} diff --git a/arch/arm/src/common/arm_modifyreg32.c b/arch/arm/src/imx9/imx9_rptun.h similarity index 73% rename from arch/arm/src/common/arm_modifyreg32.c rename to arch/arm/src/imx9/imx9_rptun.h index b98bdc3ae3f55..f170466c4d08d 100644 --- a/arch/arm/src/common/arm_modifyreg32.c +++ b/arch/arm/src/imx9/imx9_rptun.h @@ -1,7 +1,8 @@ /**************************************************************************** - * arch/arm/src/common/arm_modifyreg32.c + * arch/arm/src/imx9/imx9_rptun.h * * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -20,40 +21,27 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_RPTUN_H +#define __ARCH_ARM_SRC_IMX9_IMX9_RPTUN_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include - -#include - -#include "arm_internal.h" +/**************************************************************************** + * Public Data + ****************************************************************************/ /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: modifyreg32 - * - * Description: - * Atomically modify the specified bits in a memory mapped register - * + * Name: imx9_rptun_init ****************************************************************************/ -void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) -{ - irqstate_t flags; - uint32_t regval; - - flags = spin_lock_irqsave(NULL); - regval = getreg32(addr); - regval &= ~clearbits; - regval |= setbits; - putreg32(regval, addr); - spin_unlock_irqrestore(NULL, flags); -} +int imx9_rptun_init(const char *shmemname, const char *cpuname); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_RPTUN_H */ diff --git a/arch/arm/src/imx9/imx9_rsctable.c b/arch/arm/src/imx9/imx9_rsctable.c new file mode 100644 index 0000000000000..70f54caaf1a19 --- /dev/null +++ b/arch/arm/src/imx9/imx9_rsctable.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_rsctable.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "imx9_rsctable.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_VRINGS 0x02 +#define RL_BUFFER_COUNT 0x100 +#define VRING_ALIGN 0x1000 +#define VRING_SIZE 0x8000 +#define VDEV0_VRING_BASE 0x88000000 +#define RESOURCE_TABLE_BASE 0x88220000 + +#define NO_RESOURCE_ENTRIES (1) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ +#define IMX9_RSC_TABLE_VERSION (1) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__ ((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif +const struct rptun_rsc_s g_imx9_rsc_table = +{ + .rsc_tbl_hdr = + { + IMX9_RSC_TABLE_VERSION, + NO_RESOURCE_ENTRIES, + { + 0, 0 + } + }, + + .offset = + { + offsetof(struct rptun_rsc_s, rpmsg_vdev) + }, + + .log_trace = + { + RSC_TRACE, 0, 0 + }, + + .rpmsg_vdev = /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 2, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + { + 0, 0 + } + }, + + .rpmsg_vring0 = + { + VDEV0_VRING_BASE, + VRING_ALIGN, + RL_BUFFER_COUNT, + 0, + 0 + }, + + .rpmsg_vring1 = + { + VDEV0_VRING_BASE + VRING_SIZE, + VRING_ALIGN, + RL_BUFFER_COUNT, + 1, + 0 + }, + + .config = + { + 0 + } +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void imx9_rsctable_copy(void) +{ + memcpy((void *)RESOURCE_TABLE_BASE, (void *)&g_imx9_rsc_table, + sizeof(g_imx9_rsc_table)); +} diff --git a/arch/arm/src/imx9/imx9_rsctable.h b/arch/arm/src/imx9/imx9_rsctable.h new file mode 100644 index 0000000000000..8f45a49a68994 --- /dev/null +++ b/arch/arm/src/imx9/imx9_rsctable.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_rsctable.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_RSCTABLE_H +#define __ARCH_ARM_SRC_IMX9_IMX9_RSCTABLE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern const struct rptun_rsc_s g_imx9_rsc_table; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void imx9_rsctable_copy(void); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_RSCTABLE_H */ diff --git a/arch/arm/src/imx9/imx9_scmi.c b/arch/arm/src/imx9/imx9_scmi.c new file mode 100644 index 0000000000000..e23750a12bef1 --- /dev/null +++ b/arch/arm/src/imx9/imx9_scmi.c @@ -0,0 +1,1046 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_scmi.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" + +#include "hardware/imx95/imx95_memorymap.h" +#include "imx9_mu.h" +#include "imx9_scmi.h" + +#ifdef CONFIG_IMX9_SCMI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SM_PLATFORM_MU_INST 0 +#define SM_PLATFORM_SMA_ADDR 0 +#define SMT_MAX_CHN 3 + +#define SMT_FREE (1UL << 0u) +#define SMT_ERROR (1UL << 1u) +#define SMT_COMP_INT (1UL << 0u) + +#define SMT_BUFFER_SIZE 128u /* SMT buffer size */ +#define SMT_BUFFER_HEADER 24u /* SMT buffer header size */ +#define SMT_BUFFER_PAYLOAD (SMT_BUFFER_SIZE - SMT_BUFFER_HEADER - 4u) +#define SMT_CRC_NONE 0u /* No CRC */ +#define SMT_CRC_XOR 1u /* Simple and fast 32-bit exclusive-OR sum */ +#define SMT_CRC_J1850 2u /* J1850 standard CRC */ +#define SMT_CRC_CRC32 3u /* CRC32 standard CRC */ + +/* SCMI protocol message IDs */ + +#define SCMI_PROTOCOL_BASE 0x10u /* Base protocol */ +#define SCMI_PROTOCOL_POWER 0x11u /* Power domain management protocol */ +#define SCMI_PROTOCOL_SYS 0x12u /* System power management protocol */ +#define SCMI_PROTOCOL_PERF 0x13u /* Performance domain management protocol */ +#define SCMI_PROTOCOL_CLOCK 0x14u /* Clock management protocol */ +#define SCMI_PROTOCOL_SENSOR 0x15u /* Sensor management protocol */ +#define SCMI_PROTOCOL_RESET 0x16u /* Reset domain management protocol */ +#define SCMI_PROTOCOL_VOLTAGE 0x17u /* Voltage domain management protocol */ +#define SCMI_PROTOCOL_PINCTRL 0x19u /* Pin control protocol */ +#define SCMI_PROTOCOL_LMM 0x80u /* LM management protocol */ +#define SCMI_PROTOCOL_BBM 0x81u /* BBM management protocol */ +#define SCMI_PROTOCOL_CPU 0x82u /* CPU management protocol */ +#define SCMI_PROTOCOL_FUSA 0x83u /* FuSa protocol */ +#define SCMI_PROTOCOL_MISC 0x84u /* Misc protocol */ + +/* SCMI clock protocol message IDs */ + +#define SCMI_MSG_CLOCK_ATTRIBUTES 0x3u /* Get clock attributes */ +#define SCMI_MSG_CLOCK_DESCRIBE_RATES 0x4u /* Get clock rate description */ +#define SCMI_MSG_CLOCK_RATE_SET 0x5u /* Set clock rate */ +#define SCMI_MSG_CLOCK_RATE_GET 0x6u /* Get clock rate */ +#define SCMI_MSG_CLOCK_CONFIG_SET 0x7u /* Set clock configuration */ +#define SCMI_MSG_CLOCK_CONFIG_GET 0xbu /* Get clock configuration */ +#define SCMI_MSG_CLOCK_POSSIBLE_PARENTS_GET 0xcu /* Get all possible parents*/ +#define SCMI_MSG_CLOCK_PARENT_SET 0xdu /* Set clock parent */ +#define SCMI_MSG_CLOCK_PARENT_GET 0xeu /* Get clock parent */ +#define SCMI_MSG_CLOCK_GET_PERMISSIONS 0xfu /* Get clock permissions */ + +/* SCMI pinctrl protocol message IDs */ + +#define SCMI_MSG_PINCTRL_ATTRIBUTES 0x3u /* Get pin attributes */ +#define SCMI_MSG_PINCTRL_CONFIG_GET 0x5u /* Get pin configuration */ +#define SCMI_MSG_PINCTRL_CONFIG_SET 0x6u /* Set pin configuration */ +#define SCMI_MSG_PINCTRL_FUNCTION_SELECT 0x7u /* Select a function for a pin \ + */ +#define SCMI_MSG_PINCTRL_REQUEST 0x8u /* Request a pin */ +#define SCMI_MSG_PINCTRL_RELEASE 0x9u /* Release a pin */ + +/* SCMI header creation */ + +#define SCMI_HEADER_MSG(x) (((x) & 0xffu) << 0u) +#define SCMI_HEADER_TYPE(x) (((x) & 0x3u) << 8u) +#define SCMI_HEADER_PROTOCOL(x) (((x) & 0xffu) << 10u) +#define SCMI_HEADER_TOKEN(x) (((x) & 0x3ffu) << 18u) + +/* SCMI header extraction */ + +#define SCMI_HEADER_MSG_EX(x) (((x) & 0xffu) >> 0u) +#define SCMI_HEADER_TYPE_EX(x) (((x) & 0x300u) >> 8u) +#define SCMI_HEADER_PROTOCOL_EX(x) (((x) & 0x3fc00u) >> 10u) +#define SCMI_HEADER_TOKEN_EX(x) (((x) & 0x0ffc0000u) >> 18u) + +/* Max payload length */ + +#define SCMI_PAYLOAD_LEN 100u + +/* Calc number of array elements */ + +#define SCMI_ARRAY(X, Y) ((SCMI_PAYLOAD_LEN - (X)) / sizeof(Y)) + +#define SCMI_PINCTRL_MAX_NAME 16u +#define SCMI_PINCTRL_MAX_CONFIGS SCMI_ARRAY(8u, scmi_pin_config_t) +#define SCMI_PINCTRL_MAX_CONFIGS_T SCMI_ARRAY(8u, scmi_pin_config_t) + +/* Critical section lock callout */ + +#define SCMI_A2P_LOCK(lock) if (getpid()) {nxmutex_lock(&mutex);} + +/* Critical section unlock callout */ + +#define SCMI_A2P_UNLOCK(lock) if (getpid()) {nxmutex_unlock(&mutex);} + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef struct +{ + bool valid; + uint8_t mb_inst; + uint8_t mb_doorbell; + uint32_t shared_memory_address; +} smt_chn_config_t; + +typedef struct +{ + uint32_t header; + int32_t status; +} msg_status_t; + +typedef struct +{ + uint32_t resv; + volatile uint32_t channel_status; + uint32_t impStatus; + uint32_t imp_crc; + uint32_t channel_flags; + uint32_t length; + uint32_t header; + uint32_t payload[SMT_BUFFER_PAYLOAD / 4u]; +} smt_buf_t; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static smt_chn_config_t s_smtconfig[SMT_MAX_CHN]; +static struct imx9_mudev_s *g_mudev; +static mutex_t mutex = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint32_t imx9_crcxor(const uint32_t *addr, uint32_t size) +{ + const uint32_t *a = addr; + uint32_t sz = size; + uint32_t crc = 0u; + + /* Loop over data */ + + while (sz > 0u) + { + /* Update CRC */ + + crc ^= *a; + a++; + sz--; + } + + /* Return CRC */ + + return crc; +} + +static uint32_t imx9_crc32(const uint8_t *addr, uint32_t size) +{ + const uint8_t *a = addr; + uint32_t sz = size; + uint32_t crc = 0u; + + /* Poly table */ + + static uint32_t const crc_table[] = /* clang-format off */ + + { + 0x4dbdf21cu, 0x500ae278u, 0x76d3d2d4u, 0x6b64c2b0u, + 0x3b61b38cu, 0x26d6a3e8u, 0x000f9344u, 0x1db88320u, + 0xa005713cu, 0xbdb26158u, 0x9b6b51f4u, 0x86dc4190u, + 0xd6d930acu, 0xcb6e20c8u, 0xedb71064u, 0xf0000000u + }; /* clang-format on */ + + /* Loop over data */ + + while (sz > 0u) + { + crc = (crc >> 4u) ^ + crc_table[(crc ^ (((uint32_t)(*a)) >> 0u)) & 0x0fu]; + crc = (crc >> 4u) ^ + crc_table[(crc ^ (((uint32_t)(*a)) >> 4u)) & 0x0fu]; + a++; + sz--; + } + + /* Return CRC */ + + return crc; +} + +static smt_buf_t *imx9_smt_smaget(uint32_t smtchannel) +{ + smt_buf_t *rtn = NULL; + + /* Check channel */ + + if ((smtchannel < SMT_MAX_CHN) && (s_smtconfig[smtchannel].valid)) + { + uint8_t db = s_smtconfig[smtchannel].mb_doorbell; + + uint32_t shared_memory_address + = s_smtconfig[smtchannel].shared_memory_address; + + /* Allow use of internal MU SRAM */ + + if (shared_memory_address == 0u) + { + shared_memory_address = IMX9_MU5_MUA_BASE + 0x1000u; + } + + /* Apply channel spacing */ + + shared_memory_address += ((uint32_t)db) * SMT_BUFFER_SIZE; + + /* Set return */ + + rtn = (smt_buf_t *)shared_memory_address; + } + + return rtn; +} + +static bool imx9_smt_channelfree(uint32_t smtchannel) +{ + const smt_buf_t *buf = (const smt_buf_t *)imx9_smt_smaget(smtchannel); + bool free_state = true; + + /* Check for valid buffer */ + + if (buf != NULL) + { + free_state = ((buf->channel_status & SMT_FREE) != 0u); + } + + /* Return state */ + + return free_state; +} + +static int32_t imx9_smt_channelconfig(uint32_t smtchannel, uint8_t mb_inst) +{ + int32_t status = OK; + + if (smtchannel < SMT_MAX_CHN) + { + s_smtconfig[smtchannel].mb_inst = mb_inst; + s_smtconfig[smtchannel].mb_doorbell = smtchannel; + s_smtconfig[smtchannel].shared_memory_address = 0; + s_smtconfig[smtchannel].valid = true; + } + + else + { + status = -EINVAL; + } + + /* Return status */ + + return status; +} + +static void *imx9_smt_hdraddrget(uint32_t channel) +{ + void *rtn = NULL; + smt_buf_t *buf = imx9_smt_smaget(channel); + + /* Get address of header */ + + if (buf != NULL) + { + rtn = (void *)&buf->header; + } + + /* Return address */ + + return rtn; +} + +static int32_t imx9_smt_tx(uint32_t smtchannel, uint32_t len, bool callee, + bool comp_int) +{ + int32_t status = OK; + uint8_t db = s_smtconfig[smtchannel].mb_doorbell; + smt_buf_t *buf = (smt_buf_t *)imx9_smt_smaget(smtchannel); + + /* Check length */ + + if (len > (SMT_BUFFER_SIZE - SMT_BUFFER_HEADER)) + { + status = -EPROTO; + } + + else + { + uint32_t impStatus = buf->impStatus; + + if (callee) + { + /* Wait until channel is busy */ + + while (imx9_smt_channelfree(smtchannel)) + { + ; /* Intentional empty while */ + } + } + + else + { + /* Wait until channel is free */ + + while (!imx9_smt_channelfree(smtchannel)) + { + ; /* Intentional empty while */ + } + } + + /* Fill in reserved */ + + buf->resv = 0u; + + /* Completion interrupt if caller wants */ + + if (!callee) + { + if (comp_int) + { + buf->channel_flags = SMT_COMP_INT; + } + + else + { + buf->channel_flags = 0u; + } + } + + /* Fill in length */ + + buf->length = len; + + /* Calculate CRC */ + + switch (impStatus) + { + case SMT_CRC_XOR: + buf->imp_crc = + imx9_crcxor((const uint32_t *)&buf->header, len / 4u); + break; + case SMT_CRC_CRC32: + buf->imp_crc = imx9_crc32((const uint8_t *)&buf->header, len); + break; + default:; /* Intentional empty while */ + + break; + } + + if (callee) + { + /* Mark as free */ + + buf->channel_status |= SMT_FREE; + } + + else + { + /* Mark as busy */ + + buf->channel_status &= ~SMT_FREE; + } + + /* Trigger GI interrupt */ + + imx95_mu_trigger_interrupts(g_mudev, 1 << db); + } + + /* Return status */ + + return status; +} + +static int32_t imx9_smt_rx(uint32_t smtchannel, uint32_t *len, bool callee) +{ + int32_t status = OK; + const smt_buf_t *buf = (const smt_buf_t *)imx9_smt_smaget(smtchannel); + + /* Check buffer */ + + if (buf == NULL) + { + status = -EINVAL; + } + + else + { + uint32_t impStatus = buf->impStatus; + const void *msgrx = imx9_smt_hdraddrget(smtchannel); + + if (callee) + { + /* Wait until channel is busy */ + + while (imx9_smt_channelfree(smtchannel)) + { + ; /* Intentional empty while */ + } + } + + else + { + /* Wait until channel is free */ + + while (!imx9_smt_channelfree(smtchannel)) + { + ; /* Intentional empty while */ + } + } + + /* Record the length */ + + *len = buf->length; + + /* Check the CRC */ + + switch (impStatus) + { + case SMT_CRC_XOR: + if (buf->imp_crc + != imx9_crcxor((const uint32_t *)msgrx, *len / 4u)) + { + status = -EIO; + } + + break; + case SMT_CRC_CRC32: + if (buf->imp_crc != imx9_crc32((const uint8_t *)msgrx, *len)) + { + status = -EIO; + } + + break; + default:; /* Intentional empty while */ + + break; + } + } + + /* Return status */ + + return status; +} + +/* SCMI generics */ + +static int32_t imx9_scmi_bufinit(uint32_t channel, void **msg) +{ + int32_t status = OK; + + /* Wait until channel is free */ + + while (!imx9_smt_channelfree(channel)) + { + ; /* Intentional empty while */ + } + + /* Get header address */ + + *msg = imx9_smt_hdraddrget(channel); + if (*msg == NULL) + { + status = -EINVAL; + } + + /* Return status */ + + return status; +} + +static int32_t imx9_scmi_a2ptx(uint32_t channel, uint32_t protocol_id, + uint32_t message_id, uint32_t len, + uint32_t *header) +{ + int32_t status; + msg_status_t *msg; + + /* Get transport buffer address */ + + msg = (msg_status_t *)imx9_smt_hdraddrget(channel); + + /* Valid channel and buffer? */ + + if (msg != NULL) + { + static uint32_t s_token = 0u; + + /* Generate header */ + + *header = SCMI_HEADER_MSG(message_id) + | SCMI_HEADER_PROTOCOL(protocol_id) + | SCMI_HEADER_TYPE(0UL) | SCMI_HEADER_TOKEN(s_token); + msg->header = *header; + + /* Increment token */ + + s_token++; + + /* Send message via transport */ + + status = imx9_smt_tx(channel, len, false, false); + } + + else + { + status = -EINVAL; + } + + /* Return status */ + + return status; +} + +static int32_t imx9_scmi_a2prx(uint32_t channel, uint32_t min_len, + uint32_t header) +{ + int32_t status; + const msg_status_t *msg; + uint32_t len; + + /* Get transport buffer address */ + + msg = (msg_status_t *)imx9_smt_hdraddrget(channel); + + /* Valid channel and buffer? */ + + if (msg != NULL) + { + /* Receive message via transport */ + + status = imx9_smt_rx(channel, &len, false); + + /* Check header */ + + if ((status == OK) && (header != msg->header)) + { + status = -EPROTO; + } + + /* Check status */ + + if ((status == OK) && (len >= 8u)) + { + status = msg->status; + } + + /* Check size */ + + if ((status == OK) && (len < min_len)) + { + status = -EPROTO; + } + } + + else + { + status = -EINVAL; + } + + /* Return status */ + + return status; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int32_t imx9_scmi_clockparentget(uint32_t channel, uint32_t clockid, + uint32_t *parentid) +{ + int32_t status; + uint32_t header; + void *msg; + + /* Response message structure */ + + typedef struct + { + uint32_t header; + int32_t status; + uint32_t parentid; + } msg_rclockd14_t; + + /* Acquire lock */ + + SCMI_A2P_LOCK(channel); + + /* Init buffer */ + + status = imx9_scmi_bufinit(channel, &msg); + + /* Send request */ + + if (status == OK) + { + /* Request message structure */ + + typedef struct + { + uint32_t header; + uint32_t clockid; + } msg_tclockd14_t; + + msg_tclockd14_t *msgtx = (msg_tclockd14_t *)msg; + + /* Fill in parameters */ + + msgtx->clockid = clockid; + + /* Send message */ + + status = imx9_scmi_a2ptx(channel, SCMI_PROTOCOL_CLOCK, + SCMI_MSG_CLOCK_PARENT_GET, + sizeof(msg_tclockd14_t), &header); + } + + /* Receive response */ + + if (status == OK) + { + status = imx9_scmi_a2prx(channel, sizeof(msg_rclockd14_t), header); + } + + /* Copy out if no error */ + + if (status == OK) + { + const msg_rclockd14_t *msgrx = (const msg_rclockd14_t *)msg; + + /* Extract parentid */ + + if (parentid != NULL) + { + *parentid = msgrx->parentid; + } + } + + /* Release lock */ + + SCMI_A2P_UNLOCK(channel); + + /* Return status */ + + return status; +} + +int32_t imx9_scmi_clockparentset(uint32_t channel, uint32_t clockid, + uint32_t parentid) +{ + int32_t status; + uint32_t header; + void *msg; + + /* Acquire lock */ + + SCMI_A2P_LOCK(channel); + + /* Init buffer */ + + status = imx9_scmi_bufinit(channel, &msg); + + /* Send request */ + + if (status == OK) + { + /* Request message structure */ + + typedef struct + { + uint32_t header; + uint32_t clockid; + uint32_t parentid; + } msg_tclockd13_t; + + msg_tclockd13_t *msgtx = (msg_tclockd13_t *)msg; + + /* Fill in parameters */ + + msgtx->clockid = clockid; + msgtx->parentid = parentid; + + /* Send message */ + + status = imx9_scmi_a2ptx(channel, SCMI_PROTOCOL_CLOCK, + SCMI_MSG_CLOCK_PARENT_SET, + sizeof(msg_tclockd13_t), &header); + } + + /* Receive response */ + + if (status == OK) + { + status = imx9_scmi_a2prx(channel, sizeof(msg_status_t), header); + } + + /* Release lock */ + + SCMI_A2P_UNLOCK(channel); + + /* Return status */ + + return status; +} + +int32_t imx9_scmi_clockconfigset(uint32_t channel, uint32_t clockid, + uint32_t attributes, + uint32_t oem_config_val) +{ + int32_t status; + uint32_t header; + void *msg; + + /* Acquire lock */ + + SCMI_A2P_LOCK(channel); + + /* Init buffer */ + + status = imx9_scmi_bufinit(channel, &msg); + + /* Send request */ + + if (status == OK) + { + /* Request message structure */ + + typedef struct + { + uint32_t header; + uint32_t clockid; + uint32_t attributes; + uint32_t oem_config_val; + } msg_tclockd7_t; + + msg_tclockd7_t *msgtx = (msg_tclockd7_t *)msg; + + /* Fill in parameters */ + + msgtx->clockid = clockid; + msgtx->attributes = attributes; + msgtx->oem_config_val = oem_config_val; + + /* Send message */ + + status = imx9_scmi_a2ptx(channel, SCMI_PROTOCOL_CLOCK, + SCMI_MSG_CLOCK_CONFIG_SET, + sizeof(msg_tclockd7_t), &header); + } + + /* Receive response */ + + if (status == OK) + { + status = imx9_scmi_a2prx(channel, sizeof(msg_status_t), header); + } + + /* Release lock */ + + SCMI_A2P_UNLOCK(channel); + + /* Return status */ + + return status; +} + +int32_t imx9_scmi_clockrateget(uint32_t channel, uint32_t clockid, + scmi_clock_rate_t *rate) +{ + int32_t status; + uint32_t header; + void *msg; + + /* Response message structure */ + + typedef struct + { + uint32_t header; + int32_t status; + scmi_clock_rate_t rate; + } msg_rclockd6_t; + + /* Acquire lock */ + + SCMI_A2P_LOCK(channel); + + /* Init buffer */ + + status = imx9_scmi_bufinit(channel, &msg); + + /* Send request */ + + if (status == OK) + { + /* Request message structure */ + + typedef struct + { + uint32_t header; + uint32_t clockid; + } msg_tclockd6_t; + + msg_tclockd6_t *msgtx = (msg_tclockd6_t *)msg; + + /* Fill in parameters */ + + msgtx->clockid = clockid; + + /* Send message */ + + status = imx9_scmi_a2ptx(channel, SCMI_PROTOCOL_CLOCK, + SCMI_MSG_CLOCK_RATE_GET, + sizeof(msg_tclockd6_t), + &header); + } + + /* Receive response */ + + if (status == OK) + { + status = imx9_scmi_a2prx(channel, sizeof(msg_rclockd6_t), header); + } + + /* Copy out if no error */ + + if (status == OK) + { + const msg_rclockd6_t *msgrx = (const msg_rclockd6_t *)msg; + + /* Extract rate */ + + if (rate != NULL) + { + *rate = msgrx->rate; + } + } + + /* Release lock */ + + SCMI_A2P_UNLOCK(channel); + + /* Return status */ + + return status; +} + +int32_t imx9_scmi_clockrateset(uint32_t channel, uint32_t clockid, + uint32_t flags, scmi_clock_rate_t rate) +{ + int32_t status; + uint32_t header; + void *msg; + + /* Acquire lock */ + + SCMI_A2P_LOCK(channel); + + /* Init buffer */ + + status = imx9_scmi_bufinit(channel, &msg); + + /* Send request */ + + if (status == OK) + { + /* Request message structure */ + + typedef struct + { + uint32_t header; + uint32_t flags; + uint32_t clockid; + scmi_clock_rate_t rate; + } msg_tclockd5_t; + + msg_tclockd5_t *msgtx = (msg_tclockd5_t *)msg; + + /* Fill in parameters */ + + msgtx->flags = flags; + msgtx->clockid = clockid; + msgtx->rate = rate; + + /* Send message */ + + status = imx9_scmi_a2ptx(channel, SCMI_PROTOCOL_CLOCK, + SCMI_MSG_CLOCK_RATE_SET, + sizeof(msg_tclockd5_t), + &header); + } + + /* Receive response */ + + if (status == OK) + { + status = imx9_scmi_a2prx(channel, sizeof(msg_status_t), header); + } + + /* Release lock */ + + SCMI_A2P_UNLOCK(channel); + + /* Return status */ + + return status; +} + +int32_t imx9_scmi_pinctrlconfigset(uint32_t channel, uint32_t identifier, + uint32_t attributes, + const scmi_pin_config_t *configs) +{ + int32_t status; + uint32_t header; + void *msg; + + /* Acquire lock */ + + SCMI_A2P_LOCK(channel); + + /* Init buffer */ + + status = imx9_scmi_bufinit(channel, &msg); + + /* Send request */ + + if (status == OK) + { + /* Request message structure */ + + typedef struct + { + uint32_t header; + uint32_t identifier; + uint32_t attributes; + scmi_pin_config_t configs[SCMI_PINCTRL_MAX_CONFIGS_T]; + } msg_tpinctrld6_t; + + msg_tpinctrld6_t *msgtx = (msg_tpinctrld6_t *)msg; + + /* Fill in parameters */ + + msgtx->identifier = identifier; + msgtx->attributes = attributes; + + memcpy((uint8_t *)&msgtx->configs, (const uint8_t *)configs, + ((attributes >> 2) * sizeof(scmi_pin_config_t))); + + /* Send message */ + + status = imx9_scmi_a2ptx(channel, SCMI_PROTOCOL_PINCTRL, + SCMI_MSG_PINCTRL_CONFIG_SET, + sizeof(msg_tpinctrld6_t), &header); + } + + /* Receive response */ + + if (status == OK) + { + status = imx9_scmi_a2prx(channel, sizeof(msg_status_t), header); + } + + /* Release lock */ + + SCMI_A2P_UNLOCK(channel); + + /* Return status */ + + return status; +} + +void imx9_scmi_initialize() +{ + /* Configure SMT */ + + imx9_smt_channelconfig(SM_PLATFORM_A2P, SM_PLATFORM_MU_INST); + + /* Configure MU */ + + g_mudev = imx95_mu_init(5); +} + +#endif /* CONFIG_IMX9_SCMI */ diff --git a/arch/arm/src/imx9/imx9_scmi.h b/arch/arm/src/imx9/imx9_scmi.h new file mode 100644 index 0000000000000..15db7e03c9603 --- /dev/null +++ b/arch/arm/src/imx9/imx9_scmi.h @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_scmi.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H +#define __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SM_PLATFORM_A2P 0 /* SCMI Agent -> SCMI Platform */ +#define SM_PLATFORM_NOTIFY 1 /* SCMI Platform -> SCMI Agent */ +#define SM_PLATFORM_PRIORITY 2 + +#define SM_CLOCK_RATE_MASK 0xFFFFFFFFU + +/* SCMI clock round options */ +#define SCMI_CLOCK_ROUND_DOWN 0U /* Round down */ +#define SCMI_CLOCK_ROUND_UP 1U /* Round up */ +#define SCMI_CLOCK_ROUND_AUTO 2U /* Round to nearest */ + +/* SCMI clock rate flags */ + +#define SCMI_CLOCK_RATE_FLAGS_ROUND(x) (((x) & 0x3U) << 2U) /* Round up/down */ +#define SCMI_CLOCK_RATE_FLAGS_NO_RESP(x) (((x) & 0x1U) << 1U) /* Ignore delayed response */ +#define SCMI_CLOCK_RATE_FLAGS_ASYNC(x) (((x) & 0x1U) << 0U) /* Async flag */ + +/* SCMI clock config attributes */ + +#define SCMI_CLOCK_CONFIG_SET_OEM(x) (((x) & 0xFFU) << 16U) /* OEM specified config type */ +#define SCMI_CLOCK_CONFIG_SET_ENABLE(x) (((x) & 0x3U) << 0U) /* Enable/Disable */ + +/* SCMI pin control types */ + +#define SCMI_PINCTRL_SEL_PIN 0U +#define SCMI_PINCTRL_SEL_GROUP 1U +#define SCMI_PINCTRL_TYPE_MUX 192U /* Mux type */ +#define SCMI_PINCTRL_TYPE_CONFIG 193U /* Config type */ +#define SCMI_PINCTRL_TYPE_DAISY_ID 194U /* Daisy ID type */ +#define SCMI_PINCTRL_TYPE_DAISY_CFG 195U /* Daisy config type */ +#define SCMI_PINCTRL_SET_ATTR_NUM_CONFIGS(x) (((x) & 0xFFU) << 2U) +#define SCMI_PINCTRL_SET_ATTR_SELECTOR(x) (((x) & 0x3U) << 0U) + +/* Pinctrl */ +#define SM_PLATFORM_PINCTRL_MUX_MODE_MASK (0x7U) +#define SM_PLATFORM_PINCTRL_MUX_MODE_SHIFT (0U) +#define SM_PLATFORM_PINCTRL_MUX_MODE(x) \ + (((uint32_t)(((uint32_t)(x)) << SM_PLATFORM_PINCTRL_MUX_MODE_SHIFT)) & SM_PLATFORM_PINCTRL_MUX_MODE_MASK) + +#define SM_PLATFORM_PINCTRL_SION_MASK (0x10) +#define SM_PLATFORM_PINCTRL_SION_SHIFT (4U) +#define SM_PLATFORM_PINCTRL_SION(x) \ + (((uint32_t)(((uint32_t)(x)) << SM_PLATFORM_PINCTRL_SION_SHIFT)) & SM_PLATFORM_PINCTRL_SION_MASK) + +#define SM_PLATFORM_PINCTRL_BASE IMX9_IOMUXC_BASE +#define SM_PLATFORM_PINCTRL_MUXREG_OFF (SM_PLATFORM_PINCTRL_BASE) +#define SM_PLATFORM_PINCTRL_CFGREG_OFF (SM_PLATFORM_PINCTRL_BASE + 0x204) /* 0x443c0204 */ +#define SM_PLATFORM_PINCTRL_DAISYREG_OFF (SM_PLATFORM_PINCTRL_BASE + 0x408) /* 0x443c0408 */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef struct +{ + uint32_t channel; /* channel id: SCMI_A2P, SCMI_NOTIRY, SCMI_P2A, */ + uint32_t rateu; + uint32_t ratel; + uint32_t clk_id; /* clock device id */ + uint32_t pclk_id; /* parent clock device id */ + uint32_t div; /* clock divider */ + uint32_t attributes; /* clock attributes */ + uint32_t oem_config_val; + uint32_t flags; +} sm_clock_t; + +typedef struct +{ + uint32_t channel; + uint32_t mux_register; + uint32_t mux_mode; + uint32_t input_register; + uint32_t input_daisy; + uint32_t config_register; + uint32_t config_value; + uint32_t input_on_field; +} sm_pinctrl_t; + +/* SCMI clock rate */ + +typedef struct +{ + uint32_t lower; /* Lower 32 bits of the physical rate in Hz */ + uint32_t upper; /* Upper 32 bits of the physical rate in Hz */ +} scmi_clock_rate_t; + +/* SCMI pin control config */ + +typedef struct +{ + uint32_t type; /* The type of config */ + uint32_t value; /* The configuration value */ +} scmi_pin_config_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_scmi_initialize + * + * Description: + * + ****************************************************************************/ + +void imx9_scmi_initialize(void); + +int32_t imx9_scmi_clockparentget(uint32_t channel, uint32_t clockid, + uint32_t *parentid); +int32_t imx9_scmi_clockparentset(uint32_t channel, uint32_t clockid, + uint32_t parentid); +int32_t imx9_scmi_clockrateget(uint32_t channel, uint32_t clockid, + scmi_clock_rate_t *rate); +int32_t imx9_scmi_clockrateset(uint32_t channel, uint32_t clockid, + uint32_t flags, scmi_clock_rate_t rate); +int32_t imx9_scmi_clockconfigset(uint32_t channel, uint32_t clockid, + uint32_t attributes, uint32_t oem_config_val); +int32_t imx9_scmi_pinctrlconfigset(uint32_t channel, uint32_t identifier, + uint32_t attributes, const scmi_pin_config_t *configs); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H */ diff --git a/arch/arm/src/imx9/imx9_serial.h b/arch/arm/src/imx9/imx9_serial.h new file mode 100644 index 0000000000000..7b3e91de69cf2 --- /dev/null +++ b/arch/arm/src/imx9/imx9_serial.h @@ -0,0 +1,245 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_serial.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_SERIAL_H +#define __ARCH_ARM_SRC_IMX9_IMX9_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_IMX9_LPUART1) || defined(CONFIG_IMX9_LPUART2) || \ + defined(CONFIG_IMX9_LPUART3) || defined(CONFIG_IMX9_LPUART4) || \ + defined(CONFIG_IMX9_LPUART5) || defined(CONFIG_IMX9_LPUART6) || \ + defined(CONFIG_IMX9_LPUART7) || defined(CONFIG_IMX9_LPUART8) +# define HAVE_UART 1 +#endif + +/* Assume DMA is not used on the console UART */ + +#undef SERIAL_HAVE_CONSOLE_RXDMA +#undef SERIAL_HAVE_CONSOLE_TXDMA + +#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +# undef CONFIG_LPUART2_RXDMA +# undef CONFIG_LPUART2_TXDMA +# undef CONFIG_LPUART3_RXDMA +# undef CONFIG_LPUART3_TXDMA +# undef CONFIG_LPUART4_RXDMA +# undef CONFIG_LPUART4_TXDMA +# undef CONFIG_LPUART5_RXDMA +# undef CONFIG_LPUART5_TXDMA +# undef CONFIG_LPUART6_RXDMA +# undef CONFIG_LPUART6_TXDMA +# undef CONFIG_LPUART7_RXDMA +# undef CONFIG_LPUART7_TXDMA +# undef CONFIG_LPUART8_RXDMA +# undef CONFIG_LPUART8_TXDMA +#endif + +/* Disable the DMA configuration on all unused LPUARTs */ + +#ifndef CONFIG_IMX9_LPUART1 +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART2 +# undef CONFIG_LPUART2_RXDMA +# undef CONFIG_LPUART2_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART3 +# undef CONFIG_LPUART3_RXDMA +# undef CONFIG_LPUART3_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART4 +# undef CONFIG_LPUART4_RXDMA +# undef CONFIG_LPUART4_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART5 +# undef CONFIG_LPUART5_RXDMA +# undef CONFIG_LPUART5_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART6 +# undef CONFIG_LPUART6_RXDMA +# undef CONFIG_LPUART6_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART8 +# undef CONFIG_LPUART7_RXDMA +# undef CONFIG_LPUART7_TXDMA +#endif + +/* Is RX DMA available on any (enabled) LPUART? */ + +#undef SERIAL_HAVE_RXDMA +#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_LPUART2_RXDMA) || \ + defined(CONFIG_LPUART3_RXDMA) || defined(CONFIG_LPUART4_RXDMA) || \ + defined(CONFIG_LPUART5_RXDMA) || defined(CONFIG_LPUART6_RXDMA) || \ + defined(CONFIG_LPUART7_RXDMA) || defined(CONFIG_LPUART8_RXDMA) +# define SERIAL_HAVE_RXDMA 1 +#endif + +/* Is TX DMA available on any (enabled) LPUART? */ +#undef SERIAL_HAVE_TXDMA +#if defined(CONFIG_LPUART1_TXDMA) || defined(CONFIG_LPUART2_TXDMA) || \ + defined(CONFIG_LPUART3_TXDMA) || defined(CONFIG_LPUART4_TXDMA) || \ + defined(CONFIG_LPUART5_TXDMA) || defined(CONFIG_LPUART6_TXDMA) || \ + defined(CONFIG_LPUART7_TXDMA) || defined(CONFIG_LPUART8_TXDMA) +# define SERIAL_HAVE_TXDMA 1 +#endif + +/* Is RX DMA used on all (enabled) LPUARTs */ + +#define SERIAL_HAVE_ONLY_RXDMA 1 +#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#endif + +/* Is TX DMA used on all (enabled) LPUARTs */ + +#define SERIAL_HAVE_ONLY_TXDMA 1 +#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#endif + +#undef SERIAL_HAVE_ONLY_DMA +#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA) +#define SERIAL_HAVE_ONLY_DMA +#endif + +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +#if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA) +# ifndef CONFIG_IMX9_EDMA +# error IMXRT LPUART receive or transmit DMA requires CONFIG_IMX9_EDMA +# endif +#endif + +#if defined(SERIAL_HAVE_RXDMA) +/* Currently RS-485 support cannot be enabled when RXDMA is in use due to + * lack of testing. + */ + +# if (defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_RS485)) || \ + (defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_RS485)) || \ + (defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_RS485)) || \ + (defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_RS485)) || \ + (defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_RS485)) || \ + (defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_RS485)) || \ + (defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_RS485)) || \ + (defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_RS485)) +# error "RXDMA and RS-485 cannot be enabled at the same time for the same LPUART" +# endif +#endif /* SERIAL_HAVE_RXDMA */ + +/* Currently RS-485 support cannot be enabled when TXDMA is in use due to + * lack of testing. + */ + +# if (defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_LPUART1_RS485)) || \ + (defined(CONFIG_LPUART2_TXDMA) && defined(CONFIG_LPUART2_RS485)) || \ + (defined(CONFIG_LPUART3_TXDMA) && defined(CONFIG_LPUART3_RS485)) || \ + (defined(CONFIG_LPUART4_TXDMA) && defined(CONFIG_LPUART4_RS485)) || \ + (defined(CONFIG_LPUART5_TXDMA) && defined(CONFIG_LPUART5_RS485)) || \ + (defined(CONFIG_LPUART6_TXDMA) && defined(CONFIG_LPUART6_RS485)) || \ + (defined(CONFIG_LPUART7_TXDMA) && defined(CONFIG_LPUART7_RS485)) || \ + (defined(CONFIG_LPUART8_TXDMA) && defined(CONFIG_LPUART8_RS485)) +# error "TXDMA and RS-485 cannot be enabled at the same time for the same LPUART" +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_SERIAL_H */ diff --git a/arch/arm/src/imx9/imx9_start.c b/arch/arm/src/imx9/imx9_start.c new file mode 100644 index 0000000000000..972d48617cb64 --- /dev/null +++ b/arch/arm/src/imx9/imx9_start.c @@ -0,0 +1,283 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_start.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "barriers.h" +#include "nvic.h" +#include "mpu.h" + +#include "imx9_clockconfig.h" +#include "imx9_mpuinit.h" +#include "imx9_userspace.h" +#include "imx9_lowputc.h" +#include "imx9_serial.h" +#include "imx9_start.h" +#include "imx9_gpio.h" + +#ifdef CONFIG_IMX9_SCMI +#include "imx9_scmi.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IDLE_STACK ((unsigned)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) + +#ifdef CONFIG_DEBUG_FEATURES +#define showprogress(c) arm_lowputc(c) +#else +# define showprogress(c) +#endif + +/* Memory Map ***************************************************************/ + +/* 0x2020:0000 - Start of on-chip RAM (OCRAM) and start of .data (_sdata) + * - End of .data (_edata) and start of .bss (_sbss) + * - End of .bss (_ebss) and bottom of idle stack + * - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack, + * start of heap. NOTE that the ARM uses a decrement before + * store stack so that the correct initial value is the end of + * the stack + 4; + * 0x2027:ffff - End of OCRAM and end of heap (assuming 512Kb OCRAM) + * + * NOTE: This assumes that all internal RAM is configured for OCRAM (vs. + * ITCM or DTCM). The RAM that holds .data and .bss is called the "Primary + * RAM". Many other configurations are possible, including configurations + * where the primary ram is in external memory. Those are not considered + * here. + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_STACKCHECK +/* we need to get r10 set before we can allow instrumentation calls */ + +void __start(void) noinstrument_function; +#endif + +extern const void * const _vectors[]; + +/**************************************************************************** + * Name: imx9_tcmenable + * + * Description: + * Enable/disable tightly coupled memories. Size of tightly coupled + * memory regions is controlled by GPNVM Bits 7-8. + * + ****************************************************************************/ + +static inline void imx9_tcmenable(void) +{ + uint32_t regval; + + ARM_DSB(); + ARM_ISB(); + + /* Enabled/disabled ITCM */ + +#ifdef CONFIG_ARMV7M_ITCM + regval = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN; +#else + regval = getreg32(NVIC_ITCMCR); + regval &= ~NVIC_TCMCR_EN; +#endif + putreg32(regval, NVIC_ITCMCR); + + /* Enabled/disabled DTCM */ + +#ifdef CONFIG_ARMV7M_DTCM + regval = NVIC_TCMCR_EN | NVIC_TCMCR_RMW | NVIC_TCMCR_RETEN; +#else + regval = getreg32(NVIC_DTCMCR); + regval &= ~NVIC_TCMCR_EN; +#endif + putreg32(regval, NVIC_DTCMCR); + + ARM_DSB(); + ARM_ISB(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + register const uint32_t *src; + register uint32_t *dest; + + /* Make sure that interrupts are disabled and set MSP */ + + __asm__ __volatile__ ("CPSID i\n"); + __asm__ __volatile__ ("MSR MSP, %0\n" : : "r" (IDLE_STACK) :); + + /* Make sure that we use MSP from now on */ + + __asm__ __volatile__ ("MSR CONTROL, %0\n" : : "r" (0) :); + __asm__ __volatile__ ("ISB SY\n"); + + /* Make sure VECTAB is set to NuttX vector table + * and not the one from the boot ROM and have consistency + * with debugger that automatically set the VECTAB + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARMV7M_STACKCHECK + /* Set the stack limit before we attempt to call any functions */ + + __asm__ volatile("sub r10, sp, %0" : : + "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); +#endif + + /* If enabled reset the MPU */ + + mpu_early_reset(); + +#if defined(CONFIG_IMX9_INIT_ISRAM) + imx9_init_isram_functions(); +#endif + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in OCRAM. The correct place in OCRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + + /* Copy any necessary code sections from FLASH to RAM. The correct + * destination in OCRAM is given by _sramfuncs and _eramfuncs. The + * temporary location is in flash after the data initialization code + * at _framfuncs. This should be done before imx9_clockconfig() is + * called (in case it has some dependency on initialized C variables). + */ + +#ifdef CONFIG_ARCH_RAMFUNCS + for (src = (const uint32_t *)_framfuncs, + dest = (uint32_t *)_sramfuncs; dest < (uint32_t *)_eramfuncs; + ) + { + *dest++ = *src++; + } +#endif + +#ifdef CONFIG_ARMV7M_STACKCHECK + arm_stack_check_init(); +#endif + +#ifdef CONFIG_IMX9_SCMI + imx9_scmi_initialize(); +#endif + + /* Configure the UART so that we can get debug output as soon as possible */ + + imx9_clockconfig(); + arm_fpuconfig(); + imx9_lowsetup(); + + /* Enable/disable tightly coupled memories */ + + imx9_tcmenable(); + + /* Initialize onboard resources */ + + imx9_boardinitialize(); + +#ifdef CONFIG_ARM_MPU +#ifdef CONFIG_BUILD_PROTECTED + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + + imx9_userspace(); +#endif + + /* Configure the MPU to permit user-space access to its FLASH and RAM (for + * CONFIG_BUILD_PROTECTED) or to manage cache properties in external + * memory regions. + */ + + imx9_mpu_initialize(); +#endif + + /* Enable I- and D-Caches */ + + up_enable_icache(); + up_enable_dcache(); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + arm_earlyserialinit(); +#endif + + /* Then start NuttX */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/imx9/imx9_start.h b/arch/arm/src/imx9/imx9_start.h new file mode 100644 index 0000000000000..c3b68d9147088 --- /dev/null +++ b/arch/arm/src/imx9/imx9_start.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_start.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_START_H +#define __ARCH_ARM_SRC_IMX9_IMX9_START_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FAMILY_IMX9117x +/* Each IMX9117X board must provide the following initialized structure. + * This is needed to establish the initial board clocking. + */ + +extern const struct clock_configuration_s g_initial_clkconfig; +#endif + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imx9_lowsetup(void); + +/**************************************************************************** + * Name: imx9_boardinitialize + * + * Description: + * All i.MXRT architectures must provide the following entry point. This + * entry point is called early in the initialization -- after clocking and + * memory have been configured but before caches have been enabled and + * before any devices have been initialized. + * + ****************************************************************************/ + +void imx9_boardinitialize(void); + +/**************************************************************************** + * Name: imx9_init_isram_functions + * + * Description: + * Called off reset vector to reconfigure the ITCM + * and finish the FLASH to RAM Copy. + * + ****************************************************************************/ + +#ifdef IMX9_INIT_ISRAM +void imx9_init_isram_functions(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_START_H */ diff --git a/arch/arm/src/imx9/imx9_timerisr.c b/arch/arm/src/imx9/imx9_timerisr.c new file mode 100644 index 0000000000000..eeb8def945089 --- /dev/null +++ b/arch/arm/src/imx9/imx9_timerisr.c @@ -0,0 +1,226 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_timerisr.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "arm_internal.h" +#include "chip.h" +#include "hardware/imx9_clock.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select MCU-specific settings + * + * The SysTick timer is driven by the output of the Main Clock (main_clk). + */ + +#define IMX9_SYSTICK_CLOCK BOARD_CPU_FREQUENCY + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + */ + +#define SYSTICK_RELOAD ((IMX9_SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int imx9_timerisr(int irq, uint32_t *regs, void *arg); + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int dowmin, + enum pm_state_e pmstate); +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_timer_pmcb = +{ + .notify = up_pm_notify, + .prepare = up_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imx9_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int imx9_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Name: up_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case(PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case(PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case(PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize the timer + * interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t regval; +#ifdef CONFIG_PM + int ret; +#endif + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + putreg32(0, NVIC_SYSTICK_CURRENT); + + /* Attach the timer interrupt vector */ + + irq_attach(IMX9_IRQ_SYSTICK, (xcpt_t)imx9_timerisr, NULL); + + /* Enable SysTick interrupts */ + + regval = (NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE); + putreg32(regval, NVIC_SYSTICK_CTRL); + +#ifdef CONFIG_PM + /* Register to receive power management callbacks */ + + ret = pm_register(&g_timer_pmcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + + /* And enable the timer interrupt */ + + up_enable_irq(IMX9_IRQ_SYSTICK); +} diff --git a/arch/arm/src/imx9/imx9_userspace.c b/arch/arm/src/imx9/imx9_userspace.c new file mode 100644 index 0000000000000..8c83ae0c1c3dc --- /dev/null +++ b/arch/arm/src/imx9/imx9_userspace.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_userspace.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "imx9_mpuinit.h" +#include "imx9_userspace.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + * Assumptions: + * The D-Cache has not yet been enabled. + * + ****************************************************************************/ + +void imx9_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/common/arm_modifyreg16.c b/arch/arm/src/imx9/imx9_userspace.h similarity index 66% rename from arch/arm/src/common/arm_modifyreg16.c rename to arch/arm/src/imx9/imx9_userspace.h index 53f536f16473a..ef5b028999fb2 100644 --- a/arch/arm/src/common/arm_modifyreg16.c +++ b/arch/arm/src/imx9/imx9_userspace.h @@ -1,7 +1,8 @@ /**************************************************************************** - * arch/arm/src/common/arm_modifyreg16.c + * arch/arm/src/imx9/imx9_userspace.h * * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -20,46 +21,61 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_USERSPACE_H +#define __ARCH_ARM_SRC_IMX9_IMX9_USERSPACE_H + /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include #include -#include - -#include +#include #include "arm_internal.h" +#include "chip.h" /**************************************************************************** - * Private Data + * Public Data ****************************************************************************/ -static spinlock_t g_modifyreg_lock = SP_UNLOCKED; +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif /**************************************************************************** - * Public Functions + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: modifyreg16 + * Name: imx9_userspace * * Description: - * Atomically modify the specified bits in a memory mapped register + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. * ****************************************************************************/ -void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) -{ - irqstate_t flags; - uint16_t regval; +#ifdef CONFIG_BUILD_PROTECTED +void imx9_userspace(void); +#endif - flags = spin_lock_irqsave(&g_modifyreg_lock); - regval = getreg16(addr); - regval &= ~clearbits; - regval |= setbits; - putreg16(regval, addr); - spin_unlock_irqrestore(&g_modifyreg_lock, flags); +#undef EXTERN +#if defined(__cplusplus) } +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_USERSPACE_H */ diff --git a/arch/arm/src/imxrt/imxrt_edma.c b/arch/arm/src/imxrt/imxrt_edma.c index 4fe790a4ac486..1a839ce196c83 100644 --- a/arch/arm/src/imxrt/imxrt_edma.c +++ b/arch/arm/src/imxrt/imxrt_edma.c @@ -158,6 +158,7 @@ static struct imxrt_edma_s g_edma = #if CONFIG_IMXRT_EDMA_NTCD > 0 .dsem = SEM_INITIALIZER(CONFIG_IMXRT_EDMA_NTCD), #endif + .lock = SP_UNLOCKED }; #if CONFIG_IMXRT_EDMA_NTCD > 0 @@ -197,15 +198,15 @@ static struct imxrt_edmatcd_s *imxrt_tcd_alloc(void) * waiting. */ - flags = enter_critical_section(); nxsem_wait_uninterruptible(&g_edma.dsem); /* Now there should be a TCD in the free list reserved just for us */ + flags = spin_lock_irqsave(&g_edma.lock); tcd = (struct imxrt_edmatcd_s *)sq_remfirst(&g_tcd_free); DEBUGASSERT(tcd != NULL); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return tcd; } #endif @@ -219,6 +220,17 @@ static struct imxrt_edmatcd_s *imxrt_tcd_alloc(void) ****************************************************************************/ #if CONFIG_IMXRT_EDMA_NTCD > 0 +static void imxrt_tcd_free_nolock(struct imxrt_edmatcd_s *tcd) +{ + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); +} + static void imxrt_tcd_free(struct imxrt_edmatcd_s *tcd) { irqstate_t flags; @@ -228,10 +240,9 @@ static void imxrt_tcd_free(struct imxrt_edmatcd_s *tcd) * a TCD. */ - flags = spin_lock_irqsave(NULL); - sq_addlast((sq_entry_t *)tcd, &g_tcd_free); - nxsem_post(&g_edma.dsem); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&g_edma.lock); + imxrt_tcd_free_nolock(tcd); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif @@ -436,8 +447,11 @@ static void imxrt_dmaterminate(struct imxrt_dmach_s *dmach, int result) uint8_t regval8; uint8_t chan; edma_callback_t callback; + irqstate_t flags; void *arg; + flags = spin_lock_irqsave(&g_edma.lock); + /* Disable channel ERROR interrupts */ chan = dmach->chan; @@ -469,7 +483,7 @@ static void imxrt_dmaterminate(struct imxrt_dmach_s *dmach, int result) next = dmach->flags & EDMA_CONFIG_LOOPDEST ? NULL : (struct imxrt_edmatcd_s *)tcd->dlastsga; - imxrt_tcd_free(tcd); + imxrt_tcd_free_nolock(tcd); } dmach->head = NULL; @@ -489,6 +503,8 @@ static void imxrt_dmaterminate(struct imxrt_dmach_s *dmach, int result) { callback((DMACH_HANDLE)dmach, arg, true, result); } + + spin_unlock_irqrestore(&g_edma.lock, flags); } /**************************************************************************** @@ -1143,7 +1159,7 @@ int imxrt_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, /* Save the callback info. This will be invoked when the DMA completes */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); dmach->callback = callback; dmach->arg = arg; @@ -1168,7 +1184,7 @@ int imxrt_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, putreg8(regval8, IMXRT_EDMA_SERQ); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return OK; } @@ -1196,9 +1212,7 @@ void imxrt_dmach_stop(DMACH_HANDLE handle) dmainfo("dmach: %p\n", dmach); DEBUGASSERT(dmach != NULL); - flags = spin_lock_irqsave(NULL); imxrt_dmaterminate(dmach, -EINTR); - spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1313,7 +1327,7 @@ void imxrt_dmasample(DMACH_HANDLE handle, struct imxrt_dmaregs_s *regs) /* eDMA Global Registers */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); regs->cr = getreg32(IMXRT_EDMA_CR); /* Control */ regs->es = getreg32(IMXRT_EDMA_ES); /* Error Status */ @@ -1348,7 +1362,7 @@ void imxrt_dmasample(DMACH_HANDLE handle, struct imxrt_dmaregs_s *regs) regaddr = IMXRT_DMAMUX_CHCFG(chan); regs->dmamux = getreg32(regaddr); /* Channel configuration */ - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif /* CONFIG_DEBUG_DMA */ diff --git a/arch/arm/src/imxrt/imxrt_flexcan.c b/arch/arm/src/imxrt/imxrt_flexcan.c index 6f8ce47d88892..32203af9929cb 100644 --- a/arch/arm/src/imxrt/imxrt_flexcan.c +++ b/arch/arm/src/imxrt/imxrt_flexcan.c @@ -267,6 +267,7 @@ struct imxrt_driver_s bool bifup; /* true:ifup false:ifdown */ bool canfd_capable; int mb_address_offset; + spinlock_t lock; #ifdef TX_TIMEOUT_WQ struct wdog_s txtimeout[TXMBCOUNT]; /* TX timeout timer */ #endif @@ -777,7 +778,7 @@ static int imxrt_txpoll(struct net_driver_s *dev) * the field d_len is set to a value > 0. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (priv->dev.d_len > 0) { @@ -793,12 +794,12 @@ static int imxrt_txpoll(struct net_driver_s *dev) if (imxrt_txringfull(priv)) { - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return -EBUSY; } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); /* If zero is returned, the polling will continue until all connections * have been examined. @@ -2032,6 +2033,7 @@ int imxrt_caninitialize(int intf) priv->dev.d_ioctl = imxrt_ioctl; /* Support CAN ioctl() calls */ #endif priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */ + spin_lock_init(&priv->lock); /* Put the interface in the down state. This usually amounts to resetting * the device and/or calling imxrt_ifdown(). diff --git a/arch/arm/src/imxrt/imxrt_hprtc.c b/arch/arm/src/imxrt/imxrt_hprtc.c index 3e9d166b12db7..94a78d5693f4e 100644 --- a/arch/arm/src/imxrt/imxrt_hprtc.c +++ b/arch/arm/src/imxrt/imxrt_hprtc.c @@ -56,6 +56,7 @@ /* Callback to use when the alarm expires */ #if defined(CONFIG_RTC_ALARM) && defined(CONFIG_RTC_DRIVER) +static spinlock_t g_imxrt_hprtc_lock = SP_UNLOCKED; static hprtc_alarm_callback_t g_hprtc_alarmcb; #endif @@ -526,7 +527,7 @@ int imxrt_hprtc_setalarm(struct timespec *ts, hprtc_alarm_callback_t cb) * interrupted or preempted. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_imxrt_hprtc_lock); now = imxrt_hprtc_time(); @@ -539,7 +540,7 @@ int imxrt_hprtc_setalarm(struct timespec *ts, hprtc_alarm_callback_t cb) if ((uint32_t)ts->tv_sec <= now) { rtcwarn("WARNING: time is in the past\n"); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_imxrt_hprtc_lock, flags); return -EINVAL; } @@ -569,7 +570,7 @@ int imxrt_hprtc_setalarm(struct timespec *ts, hprtc_alarm_callback_t cb) /* Unconditionally enable the RTC alarm interrupt */ imxrt_hprtc_alarmenable(); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_imxrt_hprtc_lock, flags); return OK; } #endif diff --git a/arch/arm/src/imxrt/imxrt_wdog.c b/arch/arm/src/imxrt/imxrt_wdog.c index e2fa7b4d33b52..d085c21bcc16d 100644 --- a/arch/arm/src/imxrt/imxrt_wdog.c +++ b/arch/arm/src/imxrt/imxrt_wdog.c @@ -73,6 +73,7 @@ struct imxrt_wdog_lower const struct watchdog_ops_s *ops; /* Lower half operations */ uint32_t timeout; uint32_t enabled; + spinlock_t lock; }; /**************************************************************************** @@ -239,12 +240,14 @@ static int imxrt_wdog_stop(struct watchdog_lowerhalf_s *lower) static int imxrt_wdog_keepalive(struct watchdog_lowerhalf_s *lower) { - irqstate_t flags = spin_lock_irqsave(NULL); + struct imxrt_wdog_lower *priv = (struct imxrt_wdog_lower *)lower; + + irqstate_t flags = spin_lock_irqsave(&priv->lock); putreg16(WDOG_KEEP_ALIVE_KEY1, IMXRT_WDOG1_WSR); putreg16(WDOG_KEEP_ALIVE_KEY2, IMXRT_WDOG1_WSR); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } @@ -314,7 +317,7 @@ static int imxrt_wdog_settimeout(struct watchdog_lowerhalf_s *lower, priv->timeout = timeout; - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); /* write timer value to WCR WT register */ @@ -328,7 +331,7 @@ static int imxrt_wdog_settimeout(struct watchdog_lowerhalf_s *lower, putreg16(WDOG_KEEP_ALIVE_KEY1, IMXRT_WDOG1_WSR); putreg16(WDOG_KEEP_ALIVE_KEY2, IMXRT_WDOG1_WSR); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } @@ -360,14 +363,14 @@ void imxrt_wdog_initialize(void) priv->ops = &g_wdgops; priv->timeout = WDOG_MIN; + spin_lock_init(&g_wdgdev.lock); + /* Register the watchdog driver at the path */ wdinfo("Entry: devpath=%s\n", DEVPATH); watchdog_register(DEVPATH, (struct watchdog_lowerhalf_s *)priv); } -#endif /* CONFIG_WATCHDOG && CONFIG_IMXRT_WDOG */ - /**************************************************************************** * Name: imxrt_wdog_disable * @@ -395,9 +398,11 @@ void imxrt_wdog_disable_all(void) putreg16(reg, IMXRT_WDOG2_WCR); } - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_wdgdev.lock); putreg32(RTWDOG_UPDATE_KEY, IMXRT_RTWDOG_CNT); putreg32(0xffff, IMXRT_RTWDOG_TOVAL); modifyreg32(IMXRT_RTWDOG_CS, RTWDOG_CS_EN, RTWDOG_CS_UPDATE); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_wdgdev.lock, flags); } + +#endif /* CONFIG_WATCHDOG && CONFIG_IMXRT_WDOG */ \ No newline at end of file diff --git a/arch/arm/src/kinetis/kinetis_edma.c b/arch/arm/src/kinetis/kinetis_edma.c index 18c9f3c287321..db5318ff06917 100644 --- a/arch/arm/src/kinetis/kinetis_edma.c +++ b/arch/arm/src/kinetis/kinetis_edma.c @@ -155,6 +155,7 @@ struct kinetis_edma_s static struct kinetis_edma_s g_edma = { .chlock = NXMUTEX_INITIALIZER, + .lock = SP_UNLOCKED, #if CONFIG_KINETIS_EDMA_NTCD > 0 .dsem = SEM_INITIALIZER(CONFIG_KINETIS_EDMA_NTCD), #endif @@ -197,15 +198,16 @@ static struct kinetis_edmatcd_s *kinetis_tcd_alloc(void) * waiting. */ - flags = enter_critical_section(); nxsem_wait_uninterruptible(&g_edma.dsem); + flags = spin_lock_irqsave(&g_edma.lock); + /* Now there should be a TCD in the free list reserved just for us */ tcd = (struct kinetis_edmatcd_s *)sq_remfirst(&g_tcd_free); DEBUGASSERT(tcd != NULL); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return tcd; } #endif @@ -219,7 +221,7 @@ static struct kinetis_edmatcd_s *kinetis_tcd_alloc(void) ****************************************************************************/ #if CONFIG_KINETIS_EDMA_NTCD > 0 -static void kinetis_tcd_free(struct kinetis_edmatcd_s *tcd) +static void kinetis_tcd_free_nolock(struct kinetis_edmatcd_s *tcd) { irqstate_t flags; @@ -228,10 +230,24 @@ static void kinetis_tcd_free(struct kinetis_edmatcd_s *tcd) * a TCD. */ - flags = spin_lock_irqsave(NULL); sq_addlast((sq_entry_t *)tcd, &g_tcd_free); nxsem_post(&g_edma.dsem); - spin_unlock_irqrestore(NULL, flags); +} + +static void kinetis_tcd_free(struct kinetis_edmatcd_s *tcd) +{ + irqstate_t flags; + + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + kinetis_tcd_free_nolock(tcd); + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } #endif @@ -435,9 +451,13 @@ static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result) struct kinetis_edmatcd_s *next; #endif uintptr_t regaddr; + irqstate_t flags; uint8_t regval8; uint8_t chan; + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + /* Disable channel ERROR interrupts */ chan = dmach->chan; @@ -469,7 +489,7 @@ static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result) next = dmach->flags & EDMA_CONFIG_LOOPDEST ? NULL : (struct kinetis_edmatcd_s *)tcd->dlastsga; - kinetis_tcd_free(tcd); + kinetis_tcd_free_nolock(tcd); } dmach->head = NULL; @@ -486,6 +506,9 @@ static void kinetis_dmaterminate(struct kinetis_dmach_s *dmach, int result) dmach->callback = NULL; dmach->arg = NULL; dmach->state = KINETIS_DMA_IDLE; + + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } /**************************************************************************** @@ -1114,7 +1137,7 @@ int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, /* Save the callback info. This will be invoked when the DMA completes */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); dmach->callback = callback; dmach->arg = arg; @@ -1139,7 +1162,7 @@ int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, putreg8(regval8, KINETIS_EDMA_SERQ); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return OK; } @@ -1162,14 +1185,11 @@ int kinetis_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, void kinetis_dmach_stop(DMACH_HANDLE handle) { struct kinetis_dmach_s *dmach = (struct kinetis_dmach_s *)handle; - irqstate_t flags; dmainfo("dmach: %p\n", dmach); DEBUGASSERT(dmach != NULL); - flags = spin_lock_irqsave(NULL); kinetis_dmaterminate(dmach, -EINTR); - spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1267,7 +1287,7 @@ void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs) /* eDMA Global Registers */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); regs->cr = getreg32(KINETIS_EDMA_CR); /* Control */ regs->es = getreg32(KINETIS_EDMA_ES); /* Error Status */ @@ -1302,7 +1322,7 @@ void kinetis_dmasample(DMACH_HANDLE handle, struct kinetis_dmaregs_s *regs) regaddr = KINETIS_DMAMUX_CHCFG(chan); regs->dmamux = getreg32(regaddr); /* Channel configuration */ - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif /* CONFIG_DEBUG_DMA */ diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c index 13bc8de93a4a6..b8274b7f572f8 100644 --- a/arch/arm/src/kinetis/kinetis_lpserial.c +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -273,6 +273,7 @@ struct kinetis_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (8 or 9) */ uint8_t stop2; /* Use 2 stop bits */ + spinlock_t lock; /* Spinlock */ #ifdef CONFIG_SERIAL_IFLOWCONTROL bool iflow; /* input flow control (RTS) enabled */ #endif @@ -428,6 +429,7 @@ static struct kinetis_dev_s g_lpuart0priv = .parity = CONFIG_LPUART0_PARITY, .bits = CONFIG_LPUART0_BITS, .stop2 = CONFIG_LPUART0_2STOP, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART0_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_LPUART0_CTS, @@ -475,6 +477,7 @@ static struct kinetis_dev_s g_lpuart1priv = .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stop2 = CONFIG_LPUART1_2STOP, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_LPUART1_CTS, @@ -522,6 +525,7 @@ static struct kinetis_dev_s g_lpuart2priv = .parity = CONFIG_LPUART2_PARITY, .bits = CONFIG_LPUART2_BITS, .stop2 = CONFIG_LPUART2_2STOP, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_LPUART2_CTS, @@ -569,6 +573,7 @@ static struct kinetis_dev_s g_lpuart3priv = .parity = CONFIG_LPUART3_PARITY, .bits = CONFIG_LPUART3_BITS, .stop2 = CONFIG_LPUART3_2STOP, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_LPUART3_CTS, @@ -616,6 +621,7 @@ static struct kinetis_dev_s g_lpuart4priv = .parity = CONFIG_LPUART4_PARITY, .bits = CONFIG_LPUART4_BITS, .stop2 = CONFIG_LPUART4_2STOP, + .lock = SP_UNLOCKED, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) .oflow = true, .cts_gpio = PIN_LPUART4_CTS, @@ -700,6 +706,17 @@ static void kinetis_setuartint(struct kinetis_dev_s *priv) * Name: kinetis_restoreuartint ****************************************************************************/ +static void kinetis_restoreuartint_nolock(struct kinetis_dev_s *priv, + uint32_t ie) +{ + /* Re-enable/re-disable interrupts corresponding to the state of bits in + * ie + */ + + priv->ie = ie & LPUART_CTRL_ALL_INTS; + kinetis_setuartint(priv); +} + static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie) { irqstate_t flags; @@ -708,10 +725,9 @@ static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie) * ie */ - flags = spin_lock_irqsave(NULL); - priv->ie = ie & LPUART_CTRL_ALL_INTS; - kinetis_setuartint(priv); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + kinetis_restoreuartint_nolock(priv, ie); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -723,14 +739,14 @@ static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { *ie = priv->ie; } - kinetis_restoreuartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + kinetis_restoreuartint_nolock(priv, 0); + spin_unlock_irqrestore(&priv->lock, flags); } #endif diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 6e1c6f24e1d6e..1921a09045a95 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -308,6 +308,7 @@ struct up_dev_s uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ char *const rxfifo; /* Receive DMA buffer */ #endif + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -486,6 +487,7 @@ static struct up_dev_s g_uart0priv = .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART0_RX, .rxfifo = g_uart0rxfifo, # endif + .lock = SP_UNLOCKED }; static uart_dev_t g_uart0port = @@ -536,6 +538,7 @@ static struct up_dev_s g_uart1priv = .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART1_RX, .rxfifo = g_uart1rxfifo, # endif + .lock = SP_UNLOCKED }; static uart_dev_t g_uart1port = @@ -586,6 +589,7 @@ static struct up_dev_s g_uart2priv = .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART2_RX, .rxfifo = g_uart2rxfifo, # endif + .lock = SP_UNLOCKED }; static uart_dev_t g_uart2port = @@ -636,6 +640,7 @@ static struct up_dev_s g_uart3priv = .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART3_RX, .rxfifo = g_uart3rxfifo, # endif + .lock = SP_UNLOCKED }; static uart_dev_t g_uart3port = @@ -686,6 +691,7 @@ static struct up_dev_s g_uart4priv = .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART4_RXTX, .rxfifo = g_uart4rxfifo, # endif + .lock = SP_UNLOCKED }; static uart_dev_t g_uart4port = @@ -736,6 +742,7 @@ static struct up_dev_s g_uart5priv = .rxdma_reqsrc = KINETIS_DMA_REQUEST_SRC_UART5_RX, .rxfifo = g_uart5rxfifo, # endif + .lock = SP_UNLOCKED }; static uart_dev_t g_uart5port = @@ -786,21 +793,27 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, * Name: up_setuartint ****************************************************************************/ -static void up_setuartint(struct up_dev_s *priv) +static void up_setuartint_nolock(struct up_dev_s *priv) { - irqstate_t flags; uint8_t regval; /* Re-enable/re-disable interrupts corresponding to the state of bits in * ie */ - flags = spin_lock_irqsave(NULL); regval = up_serialin(priv, KINETIS_UART_C2_OFFSET); regval &= ~UART_C2_ALLINTS; regval |= priv->ie; up_serialout(priv, KINETIS_UART_C2_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); +} + +static void up_setuartint(struct up_dev_s *priv) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + up_setuartint_nolock(priv); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -815,10 +828,10 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t ie) * ie */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); priv->ie = ie & UART_C2_ALLINTS; - up_setuartint(priv); - spin_unlock_irqrestore(NULL, flags); + up_setuartint_nolock(priv); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -830,14 +843,15 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { *ie = priv->ie; } - up_restoreuartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + priv->ie = 0; + up_setuartint_nolock(priv); + spin_unlock_irqrestore(&priv->lock, flags); } #endif diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index 7da537d257f20..d9c76bd039c9b 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -148,6 +148,7 @@ struct up_dev_s uint8_t ie; /* Interrupts enabled */ uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (8 or 9) */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -216,6 +217,7 @@ static struct up_dev_s g_uart0priv = .irq = KL_IRQ_UART0, .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, + .lock = SP_UNLOCKED }; static uart_dev_t g_uart0port = @@ -246,6 +248,7 @@ static struct up_dev_s g_uart1priv = .irq = KL_IRQ_UART1, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, + .lock = SP_UNLOCKED }; static uart_dev_t g_uart1port = @@ -276,6 +279,7 @@ static struct up_dev_s g_uart2priv = .irq = KL_IRQ_UART2, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, + .lock = SP_UNLOCKED }; static uart_dev_t g_uart2port = @@ -322,27 +326,39 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, * Name: up_setuartint ****************************************************************************/ -static void up_setuartint(struct up_dev_s *priv) +static void up_setuartint_nolock(struct up_dev_s *priv) { - irqstate_t flags; uint8_t regval; /* Re-enable/re-disable interrupts corresponding to the state of bits * in ie. */ - flags = spin_lock_irqsave(NULL); regval = up_serialin(priv, KL_UART_C2_OFFSET); regval &= ~UART_C2_ALLINTS; regval |= priv->ie; up_serialout(priv, KL_UART_C2_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); +} + +static void up_setuartint(struct up_dev_s *priv) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + up_setuartint_nolock(priv); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** * Name: up_restoreuartint ****************************************************************************/ +static void up_restoreuartint_nolock(struct up_dev_s *priv, uint8_t ie) +{ + priv->ie = ie & UART_C2_ALLINTS; + up_setuartint_nolock(priv); +} + static void up_restoreuartint(struct up_dev_s *priv, uint8_t ie) { irqstate_t flags; @@ -351,10 +367,9 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t ie) * in ie. */ - flags = spin_lock_irqsave(NULL); - priv->ie = ie & UART_C2_ALLINTS; - up_setuartint(priv); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + up_restoreuartint_nolock(priv, ie); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -365,14 +380,14 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { *ie = priv->ie; } - up_restoreuartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + up_restoreuartint_nolock(priv, 0); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/lc823450/lc823450_dvfs2.c b/arch/arm/src/lc823450/lc823450_dvfs2.c index 6f70dbaff0ec1..66db5119f320d 100644 --- a/arch/arm/src/lc823450/lc823450_dvfs2.c +++ b/arch/arm/src/lc823450/lc823450_dvfs2.c @@ -68,6 +68,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_dvfs_lock = SP_UNLOCKED; + typedef struct freq_entry { uint16_t freq; @@ -428,7 +430,7 @@ static void lc823450_dvfs_do_auto(uint32_t idle[]) void lc823450_dvfs_get_idletime(uint64_t idletime[]) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_dvfs_lock); /* First, copy g_idle_totaltime to the caller */ @@ -448,7 +450,7 @@ void lc823450_dvfs_get_idletime(uint64_t idletime[]) } #endif - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_dvfs_lock, flags); } /**************************************************************************** @@ -504,7 +506,7 @@ void lc823450_dvfs_tick_callback(void) void lc823450_dvfs_enter_idle(void) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_dvfs_lock); int me = this_cpu(); @@ -544,7 +546,7 @@ void lc823450_dvfs_enter_idle(void) lc823450_dvfs_set_div(_dvfs_cur_idx, 1); exit_with_error: - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_dvfs_lock, flags); } /**************************************************************************** @@ -554,7 +556,7 @@ void lc823450_dvfs_enter_idle(void) void lc823450_dvfs_exit_idle(int irq) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_dvfs_lock); int me = this_cpu(); uint64_t d; @@ -596,7 +598,7 @@ void lc823450_dvfs_exit_idle(int irq) _dvfs_cpu_is_active[me] = 1; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_dvfs_lock, flags); } /**************************************************************************** @@ -628,7 +630,7 @@ int lc823450_dvfs_set_freq(int freq) return -1; } - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_dvfs_lock); switch (freq) { @@ -656,6 +658,6 @@ int lc823450_dvfs_set_freq(int freq) lc823450_dvfs_set_div(idx, 0); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_dvfs_lock, flags); return ret; } diff --git a/arch/arm/src/lc823450/lc823450_gpio.c b/arch/arm/src/lc823450/lc823450_gpio.c index 5c39bbd9fd38d..a82c9d5fdffd2 100644 --- a/arch/arm/src/lc823450/lc823450_gpio.c +++ b/arch/arm/src/lc823450/lc823450_gpio.c @@ -54,6 +54,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_gpio_lock = SP_UNLOCKED; + #ifdef CONFIG_IOEX static struct ioex_dev_s *g_ioex_dev; #endif @@ -229,12 +231,12 @@ int lc823450_gpio_mux(uint16_t gpiocfg) if (port <= (GPIO_PORT5 >> GPIO_PORT_SHIFT)) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_gpio_lock); val = getreg32(PMDCNT0 + (port * 4)); val &= ~(3 << (2 * pin)); val |= (mux << (2 *pin)); putreg32(val, PMDCNT0 + (port * 4)); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_gpio_lock, flags); } else { @@ -277,7 +279,7 @@ int lc823450_gpio_config(uint16_t gpiocfg) /* Handle the GPIO configuration by the basic mode of the pin */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_gpio_lock); /* pull up/down specified */ @@ -302,7 +304,7 @@ int lc823450_gpio_config(uint16_t gpiocfg) break; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_gpio_lock, flags); } #ifdef CONFIG_IOEX else if (port <= (GPIO_PORTEX >> GPIO_PORT_SHIFT)) @@ -390,7 +392,7 @@ void lc823450_gpio_write(uint16_t gpiocfg, bool value) regaddr = lc823450_get_gpio_data(port); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_gpio_lock); /* Write the value (0 or 1). To the data register */ @@ -407,7 +409,7 @@ void lc823450_gpio_write(uint16_t gpiocfg, bool value) putreg32(regval, regaddr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_gpio_lock, flags); } #ifdef CONFIG_IOEX else if (port <= (GPIO_PORTEX >> GPIO_PORT_SHIFT)) diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index 2529cdf089b62..43eba02df09c5 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -97,6 +97,8 @@ const uint32_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = * Private Data ****************************************************************************/ +static spinlock_t g_lc823450_irq_lock = SP_UNLOCKED; + #ifdef CONFIG_LC823450_VIRQ static struct lc823450_irq_ops *virq_ops[LC823450_IRQ_NVIRTUALIRQS]; #endif /* CONFIG_LC823450_VIRQ */ @@ -625,7 +627,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_lc823450_irq_lock); if (irq >= LC823450_IRQ_NIRQS) { @@ -648,7 +650,7 @@ void up_enable_irq(int irq) putreg32(regval, regaddr); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_lc823450_irq_lock, flags); } /* lc823450_dumpnvic("enable", irq); */ @@ -773,7 +775,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype) port = (irq & 0x70) >> 4; gpio = irq & 0xf; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_lc823450_irq_lock); regaddr = INTC_REG(EXTINTCND_BASE, port); regval = getreg32(regaddr); @@ -783,7 +785,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype) putreg32(regval, regaddr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_lc823450_irq_lock, flags); return OK; } diff --git a/arch/arm/src/lc823450/lc823450_syscontrol.c b/arch/arm/src/lc823450/lc823450_syscontrol.c index 318dc4b26b09a..2077051301465 100644 --- a/arch/arm/src/lc823450/lc823450_syscontrol.c +++ b/arch/arm/src/lc823450/lc823450_syscontrol.c @@ -43,6 +43,7 @@ * Private Data ****************************************************************************/ +static spinlock_t g_lc823450_syscontrol_lock = SP_UNLOCKED; static struct clk_st lc823450_clocks[] = LC823450_CLOCKS; /**************************************************************************** @@ -132,7 +133,7 @@ void mod_stby_regs(uint32_t enabits, uint32_t disbits) void up_enable_clk(enum clock_e clk) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_lc823450_syscontrol_lock); DEBUGASSERT(clk < LC823450_CLOCK_NUM); @@ -142,7 +143,7 @@ void up_enable_clk(enum clock_e clk) 0, lc823450_clocks[clk].regmask); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_lc823450_syscontrol_lock, flags); } /**************************************************************************** @@ -152,7 +153,7 @@ void up_enable_clk(enum clock_e clk) void up_disable_clk(enum clock_e clk) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_lc823450_syscontrol_lock); DEBUGASSERT(clk < LC823450_CLOCK_NUM); @@ -169,7 +170,7 @@ void up_disable_clk(enum clock_e clk) lc823450_clocks[clk].count = 0; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_lc823450_syscontrol_lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/lc823450/lc823450_timer.c b/arch/arm/src/lc823450/lc823450_timer.c index d17d049bbbac2..926eeb828f5fb 100644 --- a/arch/arm/src/lc823450/lc823450_timer.c +++ b/arch/arm/src/lc823450/lc823450_timer.c @@ -148,6 +148,8 @@ static void hrt_usleep_add(struct hrt_s *phrt); * Private Data ****************************************************************************/ +static spinlock_t g_hrt_timer_queue_lock = SP_UNLOCKED; + #ifdef CHECK_INTERVAL static bool _timer_val = true; #endif @@ -185,7 +187,7 @@ static void hrt_queue_refresh(void) struct hrt_s *tmp; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_hrt_timer_queue_lock); elapsed = (uint64_t)getreg32(MT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK; for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent)) @@ -204,9 +206,9 @@ static void hrt_queue_refresh(void) if (tmp->usec <= 0) { dq_rem(pent, &hrt_timer_queue); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags); nxsem_post(&tmp->sem); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_hrt_timer_queue_lock); goto cont; } else @@ -215,7 +217,7 @@ static void hrt_queue_refresh(void) } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags); } #endif @@ -230,7 +232,7 @@ static void hrt_usleep_setup(void) struct hrt_s *head; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_hrt_timer_queue_lock); head = container_of(hrt_timer_queue.head, struct hrt_s, ent); if (head == NULL) { @@ -238,7 +240,7 @@ static void hrt_usleep_setup(void) modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0x0); modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0x0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags); return; } @@ -260,7 +262,7 @@ static void hrt_usleep_setup(void) /* Enable MTM2-Ch0 */ putreg32(1, MT2OPR); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags); } #endif @@ -299,7 +301,7 @@ static void hrt_usleep_add(struct hrt_s *phrt) hrt_queue_refresh(); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_hrt_timer_queue_lock); /* add phrt to hrt_timer_queue */ @@ -321,7 +323,7 @@ static void hrt_usleep_add(struct hrt_s *phrt) dq_addlast(&phrt->ent, &hrt_timer_queue); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags); hrt_usleep_setup(); } @@ -699,7 +701,7 @@ int up_rtc_gettime(struct timespec *tp) irqstate_t flags; uint64_t f; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_hrt_timer_queue_lock); /* Get the elapsed time */ @@ -710,7 +712,7 @@ int up_rtc_gettime(struct timespec *tp) f = up_get_timer_fraction(); elapsed += f; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_hrt_timer_queue_lock, flags); tmrinfo("elapsed = %lld\n", elapsed); diff --git a/arch/arm/src/lpc54xx/lpc54_lowputc.c b/arch/arm/src/lpc54xx/lpc54_lowputc.c index a9145c06ada4d..14fb4d004c413 100644 --- a/arch/arm/src/lpc54xx/lpc54_lowputc.c +++ b/arch/arm/src/lpc54xx/lpc54_lowputc.c @@ -244,6 +244,8 @@ ****************************************************************************/ #ifdef HAVE_USART_CONSOLE +static spinlock_t g_console_lock = SP_UNLOCKED; + /* USART console configuration */ static const struct uart_config_s g_console_config = @@ -784,31 +786,17 @@ void arm_lowputc(char ch) #ifdef HAVE_USART_CONSOLE irqstate_t flags; - for (; ; ) - { - /* Wait for the transmit FIFO to be not full */ + /* Wait for the transmit FIFO to be not full */ - while ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) & - USART_FIFOSTAT_TXNOTFULL) == 0) - { - } + flags = spin_lock_irqsave(&g_console_lock); + while ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) & + USART_FIFOSTAT_TXNOTFULL) == 0); - /* Disable interrupts so that the fest test and the transmission are - * atomic. - */ + /* Send the character */ - flags = spin_lock_irqsave(NULL); - if ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) & - USART_FIFOSTAT_TXNOTFULL) != 0) - { - /* Send the character */ + putreg32((uint32_t)ch, CONSOLE_BASE + LPC54_USART_FIFOWR_OFFSET); - putreg32((uint32_t)ch, CONSOLE_BASE + LPC54_USART_FIFOWR_OFFSET); - spin_unlock_irqrestore(NULL, flags); - return; - } + spin_unlock_irqrestore(&g_console_lock, flags); - spin_unlock_irqrestore(NULL, flags); - } #endif } diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c index 7a25b4d642de5..d960821620f70 100644 --- a/arch/arm/src/lpc54xx/lpc54_serial.c +++ b/arch/arm/src/lpc54xx/lpc54_serial.c @@ -378,6 +378,7 @@ struct lpc54_dev_s { uintptr_t uartbase; /* Base address of USART registers */ uint8_t irq; /* IRQ associated with this USART */ + spinlock_t lock; /* Spinlock */ /* USART configuration */ @@ -459,6 +460,7 @@ static struct lpc54_dev_s g_uart0priv = { .uartbase = LPC54_FLEXCOMM0_BASE, .irq = LPC54_IRQ_FLEXCOMM0, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART0_BAUD, @@ -501,6 +503,7 @@ static struct lpc54_dev_s g_uart1priv = { .uartbase = LPC54_FLEXCOMM1_BASE, .irq = LPC54_IRQ_FLEXCOMM1, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART1_BAUD, @@ -543,6 +546,7 @@ static struct lpc54_dev_s g_uart2priv = { .uartbase = LPC54_FLEXCOMM2_BASE, .irq = LPC54_IRQ_FLEXCOMM2, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART2_BAUD, @@ -585,6 +589,7 @@ static struct lpc54_dev_s g_uart3priv = { .uartbase = LPC54_FLEXCOMM3_BASE, .irq = LPC54_IRQ_FLEXCOMM3, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART3_BAUD, @@ -627,6 +632,7 @@ static struct lpc54_dev_s g_uart4priv = { .uartbase = LPC54_FLEXCOMM4_BASE, .irq = LPC54_IRQ_FLEXCOMM4, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART4_BAUD, @@ -669,6 +675,7 @@ static struct lpc54_dev_s g_uart5priv = { .uartbase = LPC54_FLEXCOMM5_BASE, .irq = LPC54_IRQ_FLEXCOMM5, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART5_BAUD, @@ -711,6 +718,7 @@ static struct lpc54_dev_s g_uart6priv = { .uartbase = LPC54_FLEXCOMM6_BASE, .irq = LPC54_IRQ_FLEXCOMM6, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART6_BAUD, @@ -753,6 +761,7 @@ static struct lpc54_dev_s g_uart7priv = { .uartbase = LPC54_FLEXCOMM7_BASE, .irq = LPC54_IRQ_FLEXCOMM7, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART7_BAUD, @@ -795,6 +804,7 @@ static struct lpc54_dev_s g_uart8priv = { .uartbase = LPC54_FLEXCOMM8_BASE, .irq = LPC54_IRQ_FLEXCOMM8, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART8_BAUD, @@ -837,6 +847,7 @@ static struct lpc54_dev_s g_uart9priv = { .uartbase = LPC54_FLEXCOMM9_BASE, .irq = LPC54_IRQ_FLEXCOMM9, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_USART9_BAUD, @@ -925,14 +936,14 @@ static void lpc54_fifoint_disableall(struct lpc54_dev_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (intset) { *intset = lpc54_serialin(priv, LPC54_USART_FIFOINTENCLR_OFFSET); } lpc54_serialout(priv, LPC54_USART_FIFOINTENCLR_OFFSET, USART_FIFOINT_ALL); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/max326xx/max32660/max32660_dma.c b/arch/arm/src/max326xx/max32660/max32660_dma.c index 245742d2b2f80..b1a81b78f00ea 100644 --- a/arch/arm/src/max326xx/max32660/max32660_dma.c +++ b/arch/arm/src/max326xx/max32660/max32660_dma.c @@ -67,6 +67,7 @@ struct max326_dmach_s * Private Data ****************************************************************************/ +static spinlock_t g_max326_dmach_lock = SP_UNLOCKED; struct max326_dmach_s g_max326_dmach[MAX326_DMA_NCHAN]; /**************************************************************************** @@ -267,7 +268,7 @@ DMA_HANDLE max326_dma_channel(void) * allocation. Just check each channel until a free one is found (on not). */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_max326_dmach_lock); for (i = 0; i < 0; i++) { struct max326_dmach_s *dmach = &g_max326_dmach[i]; @@ -279,12 +280,12 @@ DMA_HANDLE max326_dma_channel(void) /* No.. allocate this channel */ dmach->inuse = true; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_max326_dmach_lock, flags); return (DMA_HANDLE)dmach; } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_max326_dmach_lock, flags); return NULL; } diff --git a/arch/arm/src/max326xx/max32660/max32660_gpio.c b/arch/arm/src/max326xx/max32660/max32660_gpio.c index c3efd618c1869..1555c96deeac4 100644 --- a/arch/arm/src/max326xx/max32660/max32660_gpio.c +++ b/arch/arm/src/max326xx/max32660/max32660_gpio.c @@ -64,6 +64,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_max32660_gpio_lock = SP_UNLOCKED; + #ifdef CONFIG_DEBUG_GPIO_INFO static const char *g_afmode[4] = { @@ -242,7 +244,7 @@ int max326_gpio_config(max326_pinset_t pinset) /* Modification of all registers must be atomic */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_max32660_gpio_lock); /* First, force the pin configuration to the default generic input state. * So that we know we are starting from a known state. @@ -403,7 +405,7 @@ int max326_gpio_config(max326_pinset_t pinset) putreg32(regval, MAX326_GPIO0_WAKEEN); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_max32660_gpio_lock, flags); return OK; } @@ -426,7 +428,7 @@ void max326_gpio_write(max326_pinset_t pinset, bool value) /* Modification of registers must be atomic */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_max32660_gpio_lock); regval = getreg32(MAX326_GPIO0_OUT); if (value) { @@ -438,7 +440,7 @@ void max326_gpio_write(max326_pinset_t pinset, bool value) } putreg32(regval, MAX326_GPIO0_OUT); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_max32660_gpio_lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/max326xx/max32660/max32660_lowputc.c b/arch/arm/src/max326xx/max32660/max32660_lowputc.c index d0d8d0f54c527..2041d346f7f20 100644 --- a/arch/arm/src/max326xx/max32660/max32660_lowputc.c +++ b/arch/arm/src/max326xx/max32660/max32660_lowputc.c @@ -88,6 +88,8 @@ ****************************************************************************/ #ifdef HAVE_UART_CONSOLE +static spinlock_t g_max32660_lowputc_lock = SP_UNLOCKED; + /* UART console configuration */ static const struct uart_config_s g_console_config = @@ -429,31 +431,22 @@ void arm_lowputc(char ch) #ifdef HAVE_UART_CONSOLE irqstate_t flags; - for (; ; ) - { - /* Wait for the transmit FIFO to be not full */ + /* Disable interrupts so that the test and the transmission are + * atomic. + */ - while ((getreg32(CONSOLE_BASE + MAX326_UART_STAT_OFFSET) & - UART_STAT_TXFULL) != 0) - { - } + flags = spin_lock_irqsave(&g_max32660_lowputc_lock); - /* Disable interrupts so that the test and the transmission are - * atomic. - */ + /* Wait for the transmit FIFO to be not full */ - flags = spin_lock_irqsave(NULL); - if ((getreg32(CONSOLE_BASE + MAX326_UART_STAT_OFFSET) & - UART_STAT_TXFULL) == 0) - { - /* Send the character */ + while ((getreg32(CONSOLE_BASE + MAX326_UART_STAT_OFFSET) & + UART_STAT_TXFULL) != 0); - putreg32((uint32_t)ch, CONSOLE_BASE + MAX326_UART_FIFO_OFFSET); - spin_unlock_irqrestore(NULL, flags); - return; - } + /* Send the character */ + + putreg32((uint32_t)ch, CONSOLE_BASE + MAX326_UART_FIFO_OFFSET); + + spin_unlock_irqrestore(&g_max32660_lowputc_lock, flags); - spin_unlock_irqrestore(NULL, flags); - } #endif } diff --git a/arch/arm/src/max326xx/max32660/max32660_serial.c b/arch/arm/src/max326xx/max32660/max32660_serial.c index 092c42e82aa5d..8123f999c2e70 100644 --- a/arch/arm/src/max326xx/max32660/max32660_serial.c +++ b/arch/arm/src/max326xx/max32660/max32660_serial.c @@ -129,6 +129,7 @@ struct max326_dev_s { uintptr_t uartbase; /* Base address of UART registers */ uint8_t irq; /* IRQ associated with this UART */ + spinlock_t lock; /* Spinlock */ /* UART configuration */ @@ -194,6 +195,7 @@ static struct max326_dev_s g_uart0priv = { .uartbase = MAX326_UART0_BASE, .irq = MAX326_IRQ_UART0, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_UART0_BAUD, @@ -238,6 +240,7 @@ static struct max326_dev_s g_uart1priv = { .uartbase = MAX326_UART1_BASE, .irq = MAX326_IRQ_UART1, + .lock = SP_UNLOCKED, .config = { .baud = CONFIG_UART1_BAUD, @@ -309,11 +312,11 @@ static inline void max326_int_enable(struct max326_dev_s *priv, irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); regval = max326_serialin(priv, MAX326_UART_INTEN_OFFSET); regval |= intset; max326_serialout(priv, MAX326_UART_INTEN_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -326,11 +329,11 @@ static inline void max326_int_disable(struct max326_dev_s *priv, irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); regval = max326_serialin(priv, MAX326_UART_INTEN_OFFSET); regval &= ~intset; max326_serialout(priv, MAX326_UART_INTEN_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -342,14 +345,14 @@ static void max326_int_disableall(struct max326_dev_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (intset) { *intset = max326_serialin(priv, MAX326_UART_INTEN_OFFSET); } max326_serialout(priv, MAX326_UART_INTEN_OFFSET, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/mx8mp/mx8mp_serial.c b/arch/arm/src/mx8mp/mx8mp_serial.c index 574edb4825baf..c9420266f3880 100644 --- a/arch/arm/src/mx8mp/mx8mp_serial.c +++ b/arch/arm/src/mx8mp/mx8mp_serial.c @@ -163,6 +163,7 @@ struct mx8mp_uart_s uint32_t uartbase; /* Base address of UART registers */ uint32_t baud; /* Configured baud */ uint32_t ie; /* Saved enabled interrupts */ + spinlock_t lock; /* Spinlock */ uint32_t ucr1; /* Saved UCR1 value */ uint8_t irq; /* IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ @@ -258,6 +259,7 @@ static struct mx8mp_uart_s g_uart1priv = .clock = UART1_CLK_ROOT, .uartbase = MX8M_UART1, .baud = CONFIG_UART1_BAUD, + .lock = SP_UNLOCKED, .irq = MX8MP_IRQ_UART1, .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, @@ -287,6 +289,7 @@ static struct mx8mp_uart_s g_uart2priv = .clock = UART2_CLK_ROOT, .uartbase = MX8M_UART2, .baud = CONFIG_UART2_BAUD, + .lock = SP_UNLOCKED, .irq = MX8MP_IRQ_UART2, .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, @@ -316,6 +319,7 @@ static struct mx8mp_uart_s g_uart3priv = .clock = UART3_CLK_ROOT, .uartbase = MX8M_UART3, .baud = CONFIG_UART3_BAUD, + .lock = SP_UNLOCKED, .irq = MX8MP_IRQ_UART3, .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, @@ -345,6 +349,7 @@ static struct mx8mp_uart_s g_uart4priv = .clock = UART4_CLK_ROOT, .uartbase = MX8M_UART4, .baud = CONFIG_UART4_BAUD, + .lock = SP_UNLOCKED, .irq = MX8MP_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, @@ -815,7 +820,7 @@ static int mx8mp_ioctl(struct file *filep, int cmd, unsigned long arg) * implement TCSADRAIN / TCSAFLUSH */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); mx8mp_disableuartint(priv, &ie); ret = mx8mp_setup(dev); @@ -823,7 +828,7 @@ static int mx8mp_ioctl(struct file *filep, int cmd, unsigned long arg) mx8mp_restoreuartint(priv, ie); priv->ie = ie; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } } break; diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c index 2d5f02ae95e29..c650a8ce3bcec 100644 --- a/arch/arm/src/nrf52/nrf52_gpio.c +++ b/arch/arm/src/nrf52/nrf52_gpio.c @@ -38,6 +38,12 @@ #include "hardware/nrf52_gpio.h" #include "nrf52_gpio.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_nrf52_gpio_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -275,7 +281,7 @@ int nrf52_gpio_config(nrf52_pinset_t cfgset) pin = GPIO_PIN_DECODE(cfgset); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_nrf52_gpio_lock); /* First, configure the port as a generic input so that we have a * known starting point and consistent behavior during the re- @@ -310,7 +316,7 @@ int nrf52_gpio_config(nrf52_pinset_t cfgset) ret = -EINVAL; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_nrf52_gpio_lock, flags); } else { diff --git a/arch/arm/src/nrf53/nrf53_gpio.c b/arch/arm/src/nrf53/nrf53_gpio.c index ff9764598d12f..ff4832f3a6f19 100644 --- a/arch/arm/src/nrf53/nrf53_gpio.c +++ b/arch/arm/src/nrf53/nrf53_gpio.c @@ -38,6 +38,12 @@ #include "hardware/nrf53_gpio.h" #include "nrf53_gpio.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_nrf53_gpio_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -330,7 +336,7 @@ int nrf53_gpio_config(nrf53_pinset_t cfgset) pin = GPIO_PIN_DECODE(cfgset); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_nrf53_gpio_lock); /* First, configure the port as a generic input so that we have a * known starting point and consistent behavior during the re- @@ -373,7 +379,7 @@ int nrf53_gpio_config(nrf53_pinset_t cfgset) ret = -EINVAL; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_nrf53_gpio_lock, flags); } else { diff --git a/arch/arm/src/nrf91/nrf91_gpio.c b/arch/arm/src/nrf91/nrf91_gpio.c index 983c6c2fd9a3d..2b165a7b3c731 100644 --- a/arch/arm/src/nrf91/nrf91_gpio.c +++ b/arch/arm/src/nrf91/nrf91_gpio.c @@ -38,6 +38,12 @@ #include "hardware/nrf91_gpio.h" #include "nrf91_gpio.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_nrf91_gpio_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -271,7 +277,7 @@ int nrf91_gpio_config(nrf91_pinset_t cfgset) pin = GPIO_PIN_DECODE(cfgset); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_nrf91_gpio_lock); /* First, configure the port as a generic input so that we have a * known starting point and consistent behavior during the re- @@ -306,7 +312,7 @@ int nrf91_gpio_config(nrf91_pinset_t cfgset) ret = -EINVAL; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_nrf91_gpio_lock, flags); } else { diff --git a/arch/arm/src/rp2040/rp2040_uart.c b/arch/arm/src/rp2040/rp2040_uart.c index 5482a4888ea77..6e67f7c91e6b1 100644 --- a/arch/arm/src/rp2040/rp2040_uart.c +++ b/arch/arm/src/rp2040/rp2040_uart.c @@ -116,6 +116,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_rp2040_uart_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -189,7 +191,7 @@ void rp2040_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud) uint32_t div; uint32_t lcr_h; - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_rp2040_uart_lock); div = basefreq / (16 * baud / 100); ibrd = div / 100; @@ -214,5 +216,5 @@ void rp2040_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud) putreg32(lcr_h, uartbase + RP2040_UART_UARTLCR_H_OFFSET); finish: - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_rp2040_uart_lock, flags); } diff --git a/arch/arm/src/rp2040/rp2040_usbdev.c b/arch/arm/src/rp2040/rp2040_usbdev.c index b1be508c1584f..32a1068bc7954 100644 --- a/arch/arm/src/rp2040/rp2040_usbdev.c +++ b/arch/arm/src/rp2040/rp2040_usbdev.c @@ -267,6 +267,7 @@ struct rp2040_usbdev_s uint16_t next_offset; /* Unused DPSRAM buffer offset */ uint8_t dev_addr; /* USB device address */ + spinlock_t lock; /* USB device address */ enum rp2040_zlp_e zlp_stat; /* Pending EP0 ZLP status */ uint16_t used; /* used epphy */ bool stalled; @@ -496,6 +497,7 @@ static void rp2040_update_buffer_control(struct rp2040_ep_s *privep, static int rp2040_epwrite(struct rp2040_ep_s *privep, uint8_t *buf, uint16_t nbytes) { + struct rp2040_usbdev_s *priv = privep->dev; uint32_t val; irqstate_t flags; @@ -513,9 +515,9 @@ static int rp2040_epwrite(struct rp2040_ep_s *privep, uint8_t *buf, /* Start the transfer */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); rp2040_update_buffer_control(privep, 0, val); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return nbytes; } @@ -530,6 +532,7 @@ static int rp2040_epwrite(struct rp2040_ep_s *privep, uint8_t *buf, static int rp2040_epread(struct rp2040_ep_s *privep, uint16_t nbytes) { + struct rp2040_usbdev_s *priv = privep->dev; uint32_t val; irqstate_t flags; @@ -542,9 +545,9 @@ static int rp2040_epread(struct rp2040_ep_s *privep, uint16_t nbytes) /* Start the transfer */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); rp2040_update_buffer_control(privep, 0, val); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } @@ -1708,15 +1711,12 @@ static int rp2040_epcancel(struct usbdev_ep_s *ep, * ****************************************************************************/ -static int rp2040_epstall_exec(struct usbdev_ep_s *ep) +static int rp2040_epstall_exec_nolock(struct usbdev_ep_s *ep) { struct rp2040_ep_s *privep = (struct rp2040_ep_s *)ep; - irqstate_t flags; usbtrace(TRACE_EPSTALL, privep->epphy); - flags = spin_lock_irqsave(NULL); - if (privep->epphy == 0) { setbits_reg32(privep->in ? @@ -1731,10 +1731,22 @@ static int rp2040_epstall_exec(struct usbdev_ep_s *ep) privep->pending_stall = false; - spin_unlock_irqrestore(NULL, flags); return OK; } +static int rp2040_epstall_exec(struct usbdev_ep_s *ep) +{ + struct rp2040_ep_s *privep = (struct rp2040_ep_s *)ep; + struct rp2040_usbdev_s *priv = privep->dev; + irqstate_t flags; + int ret; + + flags = spin_lock_irqsave(&priv->lock); + ret = rp2040_epstall_exec_nolock(ep); + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + /**************************************************************************** * Name: rp2040_epstall * @@ -1749,7 +1761,7 @@ static int rp2040_epstall(struct usbdev_ep_s *ep, bool resume) struct rp2040_usbdev_s *priv = privep->dev; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (resume) { @@ -1784,13 +1796,13 @@ static int rp2040_epstall(struct usbdev_ep_s *ep, bool resume) { /* Stall immediately */ - rp2040_epstall_exec(ep); + rp2040_epstall_exec_nolock(ep); } priv->zlp_stat = RP2040_ZLP_NONE; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } @@ -2027,6 +2039,7 @@ void arm_usbinitialize(void) g_usbdev.eplist[i].ep.eplog = 0; } + spin_lock_init(&g_usbdev.lock); if (irq_attach(RP2040_USBCTRL_IRQ, rp2040_usbinterrupt, &g_usbdev) != 0) { usbtrace(TRACE_DEVERROR(RP2040_TRACEERR_IRQREGISTRATION), @@ -2139,7 +2152,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) usbtrace(TRACE_DEVUNREGISTER, 0); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); /* Unbind the class driver */ @@ -2157,7 +2170,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) priv->driver = NULL; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } diff --git a/arch/arm/src/rp23xx/rp23xx_uart.c b/arch/arm/src/rp23xx/rp23xx_uart.c index 72efd461fc0b0..1a36e354ed356 100644 --- a/arch/arm/src/rp23xx/rp23xx_uart.c +++ b/arch/arm/src/rp23xx/rp23xx_uart.c @@ -116,6 +116,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_rp23xx_uart_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -189,7 +191,7 @@ void rp23xx_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud) uint32_t div; uint32_t lcr_h; - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_rp23xx_uart_lock); div = basefreq / (16 * baud / 100); ibrd = div / 100; @@ -214,5 +216,5 @@ void rp23xx_setbaud(uintptr_t uartbase, uint32_t basefreq, uint32_t baud) putreg32(lcr_h, uartbase + RP23XX_UART_UARTLCR_H_OFFSET); finish: - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_rp23xx_uart_lock, flags); } diff --git a/arch/arm/src/s32k1xx/s32k1xx_edma.c b/arch/arm/src/s32k1xx/s32k1xx_edma.c index dd7f3708b313f..95ac88ff566f6 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_edma.c +++ b/arch/arm/src/s32k1xx/s32k1xx_edma.c @@ -142,6 +142,7 @@ struct s32k1xx_edma_s /* This array describes each DMA channel */ struct s32k1xx_dmach_s dmach[S32K1XX_EDMA_NCHANNELS]; + spinlock_t lock; }; /**************************************************************************** @@ -156,6 +157,7 @@ static struct s32k1xx_edma_s g_edma = #if CONFIG_S32K1XX_EDMA_NTCD > 0 .dsem = SEM_INITIALIZER(CONFIG_S32K1XX_EDMA_NTCD), #endif + .lock = SP_UNLOCKED }; #if CONFIG_S32K1XX_EDMA_NTCD > 0 @@ -195,15 +197,15 @@ static struct s32k1xx_edmatcd_s *s32k1xx_tcd_alloc(void) * waiting. */ - flags = enter_critical_section(); nxsem_wait_uninterruptible(&g_edma.dsem); /* Now there should be a TCD in the free list reserved just for us */ + flags = spin_lock_irqsave(&g_edma.lock); tcd = (struct s32k1xx_edmatcd_s *)sq_remfirst(&g_tcd_free); DEBUGASSERT(tcd != NULL); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return tcd; } #endif @@ -217,6 +219,17 @@ static struct s32k1xx_edmatcd_s *s32k1xx_tcd_alloc(void) ****************************************************************************/ #if CONFIG_S32K1XX_EDMA_NTCD > 0 +static void s32k1xx_tcd_free_nolock(struct s32k1xx_edmatcd_s *tcd) +{ + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); +} + static void s32k1xx_tcd_free(struct s32k1xx_edmatcd_s *tcd) { irqstate_t flags; @@ -226,10 +239,9 @@ static void s32k1xx_tcd_free(struct s32k1xx_edmatcd_s *tcd) * a TCD. */ - flags = spin_lock_irqsave(NULL); - sq_addlast((sq_entry_t *)tcd, &g_tcd_free); - nxsem_post(&g_edma.dsem); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&g_edma.lock); + s32k1xx_tcd_free_nolock(tcd); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif @@ -432,9 +444,13 @@ static void s32k1xx_dmaterminate(struct s32k1xx_dmach_s *dmach, int result) struct s32k1xx_edmatcd_s *next; #endif uintptr_t regaddr; + irqstate_t flags; uint8_t regval8; uint8_t chan; + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + /* Disable channel ERROR interrupts */ chan = dmach->chan; @@ -465,7 +481,7 @@ static void s32k1xx_dmaterminate(struct s32k1xx_dmach_s *dmach, int result) next = dmach->flags & EDMA_CONFIG_LOOPDEST ? NULL : (struct s32k1xx_edmatcd_s *)tcd->dlastsga; - s32k1xx_tcd_free(tcd); + s32k1xx_tcd_free_nolock(tcd); } dmach->head = NULL; @@ -482,6 +498,8 @@ static void s32k1xx_dmaterminate(struct s32k1xx_dmach_s *dmach, int result) dmach->callback = NULL; dmach->arg = NULL; dmach->state = S32K1XX_DMA_IDLE; + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } /**************************************************************************** @@ -1098,7 +1116,7 @@ int s32k1xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, /* Save the callback info. This will be invoked when the DMA completes */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); dmach->callback = callback; dmach->arg = arg; @@ -1123,7 +1141,7 @@ int s32k1xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, putreg8(regval8, S32K1XX_EDMA_SERQ); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return OK; } @@ -1151,9 +1169,9 @@ void s32k1xx_dmach_stop(DMACH_HANDLE handle) dmainfo("dmach: %p\n", dmach); DEBUGASSERT(dmach != NULL); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); s32k1xx_dmaterminate(dmach, -EINTR); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } /**************************************************************************** @@ -1251,7 +1269,7 @@ void s32k1xx_dmasample(DMACH_HANDLE handle, struct s32k1xx_dmaregs_s *regs) /* eDMA Global Registers */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); regs->cr = getreg32(S32K1XX_EDMA_CR); /* Control */ regs->es = getreg32(S32K1XX_EDMA_ES); /* Error Status */ @@ -1286,7 +1304,7 @@ void s32k1xx_dmasample(DMACH_HANDLE handle, struct s32k1xx_dmaregs_s *regs) regaddr = S32K1XX_DMAMUX_CHCFG(chan); regs->dmamux = getreg32(regaddr); /* Channel configuration */ - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif /* CONFIG_DEBUG_DMA */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_enet.c b/arch/arm/src/s32k1xx/s32k1xx_enet.c index b0a117bf4adf9..6a486a3346f26 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_enet.c +++ b/arch/arm/src/s32k1xx/s32k1xx_enet.c @@ -260,6 +260,7 @@ struct s32k1xx_driver_s struct work_s pollwork; /* For deferring poll work to the work queue */ struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */ struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */ + spinlock_t lock; /* Spinlock */ /* This holds the information visible to the NuttX network */ @@ -541,7 +542,7 @@ static int s32k1xx_transmit(struct s32k1xx_driver_s *priv) /* Make the following operations atomic */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); /* Enable TX interrupts */ @@ -558,7 +559,7 @@ static int s32k1xx_transmit(struct s32k1xx_driver_s *priv) putreg32(ENET_TDAR, S32K1XX_ENET_TDAR); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } @@ -2443,6 +2444,8 @@ int s32k1xx_netinitialize(int intf) #endif priv->dev.d_private = g_enet; /* Used to recover private state from dev */ + spin_lock_init(&priv->lock); + #ifdef CONFIG_NET_ETHERNET /* Determine a semi-unique MAC address from MCU UID * We use UID Low and Mid Low registers to get 64 bits, from which we keep diff --git a/arch/arm/src/s32k3xx/s32k3xx_edma.c b/arch/arm/src/s32k3xx/s32k3xx_edma.c index b0e193b9253bf..36c24219e3a9f 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_edma.c +++ b/arch/arm/src/s32k3xx/s32k3xx_edma.c @@ -206,6 +206,7 @@ static struct s32k3xx_edma_s g_edma = #if CONFIG_S32K3XX_EDMA_NTCD > 0 .dsem = SEM_INITIALIZER(CONFIG_S32K3XX_EDMA_NTCD), #endif + .lock = SP_UNLOCKED }; #if CONFIG_S32K3XX_EDMA_NTCD > 0 @@ -450,15 +451,15 @@ static struct s32k3xx_edmatcd_s *s32k3xx_tcd_alloc(void) * waiting. */ - flags = enter_critical_section(); nxsem_wait_uninterruptible(&g_edma.dsem); /* Now there should be a TCD in the free list reserved just for us */ + flags = spin_lock_irqsave(&g_edma.lock); tcd = (struct s32k3xx_edmatcd_s *)sq_remfirst(&g_tcd_free); DEBUGASSERT(tcd != NULL); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return tcd; } #endif @@ -472,6 +473,17 @@ static struct s32k3xx_edmatcd_s *s32k3xx_tcd_alloc(void) ****************************************************************************/ #if CONFIG_S32K3XX_EDMA_NTCD > 0 +static void s32k3xx_tcd_free_nolock(struct s32k3xx_edmatcd_s *tcd) +{ + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); +} + static void s32k3xx_tcd_free(struct s32k3xx_edmatcd_s *tcd) { irqstate_t flags; @@ -481,10 +493,11 @@ static void s32k3xx_tcd_free(struct s32k3xx_edmatcd_s *tcd) * a TCD. */ - flags = spin_lock_irqsave(NULL); - sq_addlast((sq_entry_t *)tcd, &g_tcd_free); - nxsem_post(&g_edma.dsem); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + s32k3xx_tcd_free_nolock(tcd); + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } #endif @@ -709,8 +722,12 @@ static void s32k3xx_dmaterminate(struct s32k3xx_dmach_s *dmach, int result) #endif uint8_t chan; edma_callback_t callback; + irqstate_t flags; void *arg; + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + chan = dmach->chan; /* Disable channel IRQ requests */ @@ -742,7 +759,7 @@ static void s32k3xx_dmaterminate(struct s32k3xx_dmach_s *dmach, int result) next = dmach->flags & EDMA_CONFIG_LOOPDEST ? NULL : (struct s32k3xx_edmatcd_s *)tcd->dlastsga; - s32k3xx_tcd_free(tcd); + s32k3xx_tcd_free_nolock(tcd); } dmach->head = NULL; @@ -762,6 +779,9 @@ static void s32k3xx_dmaterminate(struct s32k3xx_dmach_s *dmach, int result) { callback((DMACH_HANDLE)dmach, arg, true, result); } + + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } /**************************************************************************** @@ -1377,7 +1397,7 @@ int s32k3xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, /* Save the callback info. This will be invoked when the DMA completes */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); dmach->callback = callback; dmach->arg = arg; @@ -1397,7 +1417,7 @@ int s32k3xx_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, putreg32(regval, S32K3XX_EDMA_TCD[chan] + S32K3XX_EDMA_CH_CSR_OFFSET); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return OK; } @@ -1425,9 +1445,9 @@ void s32k3xx_dmach_stop(DMACH_HANDLE handle) dmainfo("dmach: %p\n", dmach); DEBUGASSERT(dmach != NULL); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); s32k3xx_dmaterminate(dmach, -EINTR); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } /**************************************************************************** @@ -1544,7 +1564,7 @@ void s32k3xx_dmasample(DMACH_HANDLE handle, struct s32k3xx_dmaregs_s *regs) /* eDMA Global Registers */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); regs->cr = getreg32(S32K3XX_EDMA_CSR); /* Control */ regs->es = getreg32(S32K3XX_EDMA_ES); /* Error Status */ @@ -1576,7 +1596,7 @@ void s32k3xx_dmasample(DMACH_HANDLE handle, struct s32k3xx_dmaregs_s *regs) regs->dmamux = getreg32(S32K3XX_DMAMUX1_CHCFG(chan - 16)); /* Channel configuration */ } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif /* CONFIG_DEBUG_DMA */ diff --git a/arch/arm/src/sam34/sam_lowputc.c b/arch/arm/src/sam34/sam_lowputc.c index 8cf2c4a7cc775..67f3ea04bee83 100644 --- a/arch/arm/src/sam34/sam_lowputc.c +++ b/arch/arm/src/sam34/sam_lowputc.c @@ -249,6 +249,10 @@ * Private Data ****************************************************************************/ +#ifdef HAVE_CONSOLE +static spinlock_t g_sam_lowputc_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -270,30 +274,19 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE irqstate_t flags; - for (; ; ) - { + flags = spin_lock_irqsave(&g_sam_lowputc_lock); + /* Wait for the transmitter to be available */ - while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & - UART_INT_TXEMPTY) == 0); + while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & + UART_INT_TXEMPTY) == 0); - /* Disable interrupts so that the test and the transmission are - * atomic. - */ + /* Send the character */ - flags = spin_lock_irqsave(NULL); - if ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & - UART_INT_TXEMPTY) != 0) - { - /* Send the character */ + putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET); - putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET); - spin_unlock_irqrestore(NULL, flags); - return; - } + spin_unlock_irqrestore(&g_sam_lowputc_lock, flags); - spin_unlock_irqrestore(NULL, flags); - } #endif } diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c index c743996e1ac1e..5a69f10fcf77d 100644 --- a/arch/arm/src/sama5/sam_lowputc.c +++ b/arch/arm/src/sama5/sam_lowputc.c @@ -211,6 +211,14 @@ UART_MR_CHMODE_NORMAL) #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) +static spinlock_t g_sam_lowputc_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -228,30 +236,16 @@ void arm_lowputc(char ch) #if defined(SAMA5_HAVE_UART_CONSOLE) || defined(SAMA5_HAVE_USART_CONSOLE) irqstate_t flags; - for (; ; ) - { - /* Wait for the transmitter to be available */ + /* Wait for the transmitter to be available */ - while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & - UART_INT_TXEMPTY) == 0); + flags = spin_lock_irqsave(&g_sam_lowputc_lock); + while ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & + UART_INT_TXEMPTY) == 0); - /* Disable interrupts so that the test and the transmission are - * atomic. - */ - - flags = spin_lock_irqsave(NULL); - if ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & - UART_INT_TXEMPTY) != 0) - { - /* Send the character */ + /* Send the character */ - putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET); - spin_unlock_irqrestore(NULL, flags); - return; - } - - spin_unlock_irqrestore(NULL, flags); - } + putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET); + spin_unlock_irqrestore(&g_sam_lowputc_lock, flags); #elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE) irqstate_t flags; diff --git a/arch/arm/src/samd2l2/sam_serial.c b/arch/arm/src/samd2l2/sam_serial.c index e955139e7238e..60bd704faafac 100644 --- a/arch/arm/src/samd2l2/sam_serial.c +++ b/arch/arm/src/samd2l2/sam_serial.c @@ -260,6 +260,10 @@ static bool sam_txempty(struct uart_dev_s *dev); * Private Data ****************************************************************************/ +#ifdef HAVE_SERIAL_CONSOLE +static spinlock_t g_sam_serial_lock = SP_UNLOCKED; +#endif + static const struct uart_ops_s g_uart_ops = { .setup = sam_setup, @@ -1048,9 +1052,9 @@ void up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_sam_serial_lock); sam_lowputc(ch); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_sam_serial_lock, flags); #endif } diff --git a/arch/arm/src/samd5e5/sam_serial.c b/arch/arm/src/samd5e5/sam_serial.c index ffbc5dedeacf5..e3f0e0f3a8487 100644 --- a/arch/arm/src/samd5e5/sam_serial.c +++ b/arch/arm/src/samd5e5/sam_serial.c @@ -327,6 +327,10 @@ static bool sam_txempty(struct uart_dev_s *dev); * Private Data ****************************************************************************/ +#ifdef HAVE_SERIAL_CONSOLE +static spinlock_t g_sam_serial_lock = SP_UNLOCKED; +#endif + static const struct uart_ops_s g_uart_ops = { .setup = sam_setup, @@ -1107,9 +1111,9 @@ void up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_sam_serial_lock); sam_lowputc(ch); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_sam_serial_lock, flags); #endif } diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c index 75d89efbaf5ea..40708f89f6769 100644 --- a/arch/arm/src/samv7/sam_lowputc.c +++ b/arch/arm/src/samv7/sam_lowputc.c @@ -159,6 +159,14 @@ #endif /* HAVE_SERIAL_CONSOLE */ +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_SERIAL_CONSOLE +static spinlock_t g_sam_lowputc_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -176,30 +184,17 @@ void arm_lowputc(char ch) #ifdef HAVE_SERIAL_CONSOLE irqstate_t flags; - for (; ; ) - { - /* Wait for the transmitter to be available */ - - while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & - UART_INT_TXEMPTY) == 0); + /* Wait for the transmitter to be available */ - /* Disable interrupts so that the test and the transmission are - * atomic. - */ + flags = spin_lock_irqsave(&g_sam_lowputc_lock); + while ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & + UART_INT_TXEMPTY) == 0); - flags = spin_lock_irqsave(NULL); - if ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & - UART_INT_TXEMPTY) != 0) - { - /* Send the character */ + /* Send the character */ - putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET); - spin_unlock_irqrestore(NULL, flags); - return; - } + putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET); - spin_unlock_irqrestore(NULL, flags); - } + spin_unlock_irqrestore(&g_sam_lowputc_lock, flags); #endif } diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/stm32/stm32_hciuart.c index 442e6ad11309b..cc77251341f34 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/stm32/stm32_hciuart.c @@ -283,6 +283,7 @@ struct hciuart_config_s uint32_t rx_gpio; /* U[S]ART RX GPIO pin configuration */ uint32_t cts_gpio; /* U[S]ART CTS GPIO pin configuration */ uint32_t rts_gpio; /* U[S]ART RTS GPIO pin configuration */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -408,6 +409,7 @@ static const struct hciuart_config_s g_hciusart1_config = .rx_gpio = GPIO_USART1_RX, .cts_gpio = GPIO_USART1_CTS, .rts_gpio = GPIO_USART1_RTS, + .lock = SP_UNLOCKED }; #endif @@ -468,6 +470,7 @@ static const struct hciuart_config_s g_hciusart2_config = .rx_gpio = GPIO_USART2_RX, .cts_gpio = GPIO_USART2_CTS, .rts_gpio = GPIO_USART2_RTS, + .lock = SP_UNLOCKED }; #endif @@ -528,6 +531,7 @@ static const struct hciuart_config_s g_hciusart3_config = .rx_gpio = GPIO_USART3_RX, .cts_gpio = GPIO_USART3_CTS, .rts_gpio = GPIO_USART3_RTS, + .lock = SP_UNLOCKED }; #endif @@ -588,6 +592,7 @@ static const struct hciuart_config_s g_hciusart6_config = .rx_gpio = GPIO_USART6_RX, .cts_gpio = GPIO_USART6_CTS, .rts_gpio = GPIO_USART6_RTS, + .lock = SP_UNLOCKED }; #endif @@ -648,6 +653,7 @@ static const struct hciuart_config_s g_hciuart7_config = .rx_gpio = GPIO_UART7_RX, .cts_gpio = GPIO_UART7_CTS, .rts_gpio = GPIO_UART7_RTS, + .lock = SP_UNLOCKED }; #endif @@ -708,6 +714,7 @@ static const struct hciuart_config_s g_hciuart8_config = .rx_gpio = GPIO_UART8_RX, .cts_gpio = GPIO_UART8_CTS, .rts_gpio = GPIO_UART8_RTS, + .lock = SP_UNLOCKED }; #endif @@ -1915,7 +1922,7 @@ static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, /* If the callback is NULL, then we are detaching */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); if (callback == NULL) { uint32_t intset; @@ -1938,7 +1945,7 @@ static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, state->callback = callback; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); } /**************************************************************************** @@ -2003,7 +2010,7 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, * " " USART_SR_ORE Overrun Error Detected */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); if (enable) { /* Receive an interrupt when their is anything in the Rx data @@ -2019,7 +2026,7 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, hciuart_disableints(config, intset); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); } #endif } @@ -2218,9 +2225,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, * USART_CR3_CTSIE USART_SR_CTS CTS flag (not used) */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); hciuart_disableints(config, USART_CR1_TXEIE); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); /* Loop until all of the user data have been moved to the Tx buffer */ @@ -2313,9 +2320,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, if (state->txhead != state->txtail) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); hciuart_enableints(config, USART_CR1_TXEIE); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); } return ntotal; @@ -2394,8 +2401,19 @@ static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status, const struct hciuart_config_s *config = (const struct hciuart_config_s *)arg; struct hciuart_state_s *state; + irqstate_t flags; ssize_t nbytes; + flags = spin_lock_irqsave(&config->lock); + sched_lock(); + + if (config.state->rxdmastream == NULL) + { + spin_unlock_irqrestore(&config->lock, flags); + sched_unlock(); + return; + } + wlinfo("status %u config %p\n", status, config); DEBUGASSERT(config != NULL && config->state != NULL); @@ -2417,6 +2435,9 @@ static void hciuart_dma_rxcallback(DMA_HANDLE handle, uint8_t status, state->callback(config->lower, state->arg); handled = true; } + + spin_unlock_irqrestore(&config->lock, flags); + sched_unlock(); } #endif @@ -2639,59 +2660,35 @@ void hciuart_initialize(void) #ifdef CONFIG_STM32_HCIUART_RXDMA void stm32_serial_dma_poll(void) { - irqstate_t flags; - - flags = spin_lock_irqsave(NULL); - #ifdef CONFIG_STM32_HCIUART1_RXDMA - if (g_hciusart1_config.state->rxdmastream != NULL) - { - hciuart_dma_rxcallback(g_hciusart1_config.state->rxdmastream, 0, - &g_hciusart1_config); - } + hciuart_dma_rxcallback(g_hciusart1_config.state->rxdmastream, 0, + &g_hciusart1_config); #endif #ifdef CONFIG_STM32_HCIUART2_RXDMA - if (g_hciusart2_config.state->rxdmastream != NULL) - { - hciuart_dma_rxcallback(g_hciusart2_config.state->rxdmastream, 0, + hciuart_dma_rxcallback(g_hciusart2_config.state->rxdmastream, 0, &g_hciusart2_config); - } #endif #ifdef CONFIG_STM32_HCIUART3_RXDMA - if (g_hciusart3_config.state->rxdmastream != NULL) - { - hciuart_dma_rxcallback(g_hciusart3_config.state->rxdmastream, 0, - &g_hciusart3_config); - } + hciuart_dma_rxcallback(g_hciusart3_config.state->rxdmastream, 0, + &g_hciusart3_config); #endif #ifdef CONFIG_STM32_HCIUART6_RXDMA - if (g_hciusart6_config.state->rxdmastream != NULL) - { - hciuart_dma_rxcallback(g_hciusart6_config.state->rxdmastream, 0, - &g_hciusart6_config); - } + hciuart_dma_rxcallback(g_hciusart6_config.state->rxdmastream, 0, + &g_hciusart6_config); #endif #ifdef CONFIG_STM32_HCIUART7_RXDMA - if (g_hciuart7_config.state->rxdmastream != NULL) - { - hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream, - 0, - &g_hciuart7_config); - } + hciuart_dma_rxcallback(g_hciuart7_config.state->rxdmastream, + 0, + &g_hciuart7_config); #endif #ifdef CONFIG_STM32_HCIUART8_RXDMA - if (g_hciuart8_config.state->rxdmastream != NULL) - { - hciuart_dma_rxcallback(g_hciuart8.state->rxdmastream, 0, - &g_hciuart8_config); - } + hciuart_dma_rxcallback(g_hciuart8.state->rxdmastream, 0, + &g_hciuart8_config); #endif - - spin_unlock_irqrestore(NULL, flags); } #endif diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 60b83c19b4286..0fe7312039f07 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -322,6 +322,7 @@ struct stm32_lowerhalf_s #ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS volatile int32_t position; /* The current position offset */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -406,6 +407,7 @@ static struct stm32_lowerhalf_s g_tim1lower = .ops = &g_qecallbacks, .config = &g_tim1config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -431,6 +433,7 @@ static struct stm32_lowerhalf_s g_tim2lower = .ops = &g_qecallbacks, .config = &g_tim2config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -456,6 +459,7 @@ static struct stm32_lowerhalf_s g_tim3lower = .ops = &g_qecallbacks, .config = &g_tim3config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -481,6 +485,7 @@ static struct stm32_lowerhalf_s g_tim4lower = .ops = &g_qecallbacks, .config = &g_tim4config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -506,6 +511,7 @@ static struct stm32_lowerhalf_s g_tim5lower = .ops = &g_qecallbacks, .config = &g_tim5config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -531,6 +537,7 @@ static struct stm32_lowerhalf_s g_tim8lower = .ops = &g_qecallbacks, .config = &g_tim8config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -1196,7 +1203,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) /* Loop until we are certain that no interrupt occurred between samples */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); do { position = priv->position; @@ -1204,7 +1211,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) verify = priv->position; } while (position != verify); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); /* Return the position measurement */ diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 529874b1e9f70..adc4bc18bf2ba 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -491,6 +491,7 @@ struct up_dev_s const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR TXEN polarity */ #endif const bool islpuart; /* Is this device a Low Power UART? */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -783,6 +784,7 @@ static struct up_dev_s g_usart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -852,6 +854,7 @@ static struct up_dev_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -921,6 +924,7 @@ static struct up_dev_s g_usart3priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -990,6 +994,7 @@ static struct up_dev_s g_uart4priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1059,6 +1064,7 @@ static struct up_dev_s g_uart5priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1128,6 +1134,7 @@ static struct up_dev_s g_usart6priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1197,6 +1204,7 @@ static struct up_dev_s g_uart7priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1266,6 +1274,7 @@ static struct up_dev_s g_uart8priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1334,6 +1343,7 @@ static struct up_dev_s g_lpuart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1442,11 +1452,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); up_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -1457,7 +1467,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -1498,7 +1508,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index 34ba005712542..209881cf00b7f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -250,6 +250,7 @@ struct stm32_serial_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -445,6 +446,7 @@ static struct stm32_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -506,6 +508,7 @@ static struct stm32_serial_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -567,6 +570,7 @@ static struct stm32_serial_s g_usart3priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -632,6 +636,7 @@ static struct stm32_serial_s g_usart4priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -697,6 +702,7 @@ static struct stm32_serial_s g_usart5priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -806,7 +812,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -850,7 +856,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, stm32serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index 68f14fe934c82..6f439dffbc40c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -158,6 +158,7 @@ struct up_dev_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -285,6 +286,7 @@ static struct up_dev_s g_usart1priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -339,6 +341,7 @@ static struct up_dev_s g_usart2priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -393,6 +396,7 @@ static struct up_dev_s g_usart3priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -447,6 +451,7 @@ static struct up_dev_s g_usart4priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -534,11 +539,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); up_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -549,7 +554,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -593,7 +598,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c index 13add4b14e006..b72fac55558df 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ b/arch/arm/src/stm32f7/stm32_qencoder.c @@ -214,6 +214,7 @@ struct stm32_lowerhalf_s #ifdef HAVE_16BIT_TIMERS volatile int32_t position; /* The current position offset */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -296,6 +297,7 @@ static struct stm32_lowerhalf_s g_tim1lower = .ops = &g_qecallbacks, .config = &g_tim1config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -321,6 +323,7 @@ static struct stm32_lowerhalf_s g_tim2lower = .ops = &g_qecallbacks, .config = &g_tim2config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -346,6 +349,7 @@ static struct stm32_lowerhalf_s g_tim3lower = .ops = &g_qecallbacks, .config = &g_tim3config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -371,6 +375,7 @@ static struct stm32_lowerhalf_s g_tim4lower = .ops = &g_qecallbacks, .config = &g_tim4config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -396,6 +401,7 @@ static struct stm32_lowerhalf_s g_tim5lower = .ops = &g_qecallbacks, .config = &g_tim5config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -421,6 +427,7 @@ static struct stm32_lowerhalf_s g_tim8lower = .ops = &g_qecallbacks, .config = &g_tim8config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -1034,7 +1041,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) /* Loop until we are certain that no interrupt occurred between samples */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); do { position = priv->position; @@ -1042,7 +1049,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) verify = priv->position; } while (position != verify); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); /* Return the position measurement */ diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 458db8f2749a4..aebcd705fbcf3 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -507,6 +507,7 @@ struct up_dev_s const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for * TX enabled */ #endif + spinlock_t lock; }; #ifdef CONFIG_PM @@ -832,6 +833,7 @@ static struct up_dev_s g_usart1priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -900,6 +902,7 @@ static struct up_dev_s g_usart2priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -968,6 +971,7 @@ static struct up_dev_s g_usart3priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1036,6 +1040,7 @@ static struct up_dev_s g_uart4priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1104,6 +1109,7 @@ static struct up_dev_s g_uart5priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1172,6 +1178,7 @@ static struct up_dev_s g_usart6priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1240,6 +1247,7 @@ static struct up_dev_s g_uart7priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1308,6 +1316,7 @@ static struct up_dev_s g_uart8priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1408,11 +1417,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); up_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -1423,7 +1432,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -1467,7 +1476,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index 22ea4e08c120c..13e70f2e56410 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -296,6 +296,7 @@ struct stm32_serial_s const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif const bool islpuart; /* Is this device a Low Power UART? */ + spinlock_t lock; }; /**************************************************************************** @@ -506,6 +507,7 @@ static struct stm32_serial_s g_lpuart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -566,6 +568,7 @@ static struct stm32_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -628,6 +631,7 @@ static struct stm32_serial_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -690,6 +694,7 @@ static struct stm32_serial_s g_usart3priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -752,6 +757,7 @@ static struct stm32_serial_s g_uart4priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -814,6 +820,7 @@ static struct stm32_serial_s g_uart5priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -876,6 +883,7 @@ static struct stm32_serial_s g_usart6priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -938,6 +946,7 @@ static struct stm32_serial_s g_uart7priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1000,6 +1009,7 @@ static struct stm32_serial_s g_uart8priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1062,6 +1072,7 @@ static struct stm32_serial_s g_uart9priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1124,6 +1135,7 @@ static struct stm32_serial_s g_usart10priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1186,6 +1198,7 @@ static struct stm32_serial_s g_usart11priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1248,6 +1261,7 @@ static struct stm32_serial_s g_uart12priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -1375,11 +1389,11 @@ static void stm32serial_restoreusartint(struct stm32_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); stm32serial_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -1391,7 +1405,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -1434,7 +1448,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, stm32serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c index 01d96a5b004f2..70fa3498ba7b0 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ b/arch/arm/src/stm32h7/stm32_qencoder.c @@ -214,6 +214,7 @@ struct stm32_lowerhalf_s #ifdef HAVE_16BIT_TIMERS volatile int32_t position; /* The current position offset */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -296,6 +297,7 @@ static struct stm32_lowerhalf_s g_tim1lower = .ops = &g_qecallbacks, .config = &g_tim1config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -321,6 +323,7 @@ static struct stm32_lowerhalf_s g_tim2lower = .ops = &g_qecallbacks, .config = &g_tim2config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -346,6 +349,7 @@ static struct stm32_lowerhalf_s g_tim3lower = .ops = &g_qecallbacks, .config = &g_tim3config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -371,6 +375,7 @@ static struct stm32_lowerhalf_s g_tim4lower = .ops = &g_qecallbacks, .config = &g_tim4config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -396,6 +401,7 @@ static struct stm32_lowerhalf_s g_tim5lower = .ops = &g_qecallbacks, .config = &g_tim5config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -421,6 +427,7 @@ static struct stm32_lowerhalf_s g_tim8lower = .ops = &g_qecallbacks, .config = &g_tim8config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -1035,7 +1042,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) /* Loop until we are certain that no interrupt occurred between samples */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); do { position = priv->position; @@ -1043,7 +1050,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) verify = priv->position; } while (position != verify); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); /* Return the position measurement */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 97e72854443ce..ee4d1efc37a2c 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -654,6 +654,7 @@ struct up_dev_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; #ifdef CONFIG_PM @@ -981,6 +982,7 @@ static struct up_dev_s g_usart1priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1050,6 +1052,7 @@ static struct up_dev_s g_usart2priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1119,6 +1122,7 @@ static struct up_dev_s g_usart3priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1188,6 +1192,7 @@ static struct up_dev_s g_uart4priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1257,6 +1262,7 @@ static struct up_dev_s g_uart5priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1326,6 +1332,7 @@ static struct up_dev_s g_usart6priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1395,6 +1402,7 @@ static struct up_dev_s g_uart7priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1464,6 +1472,7 @@ static struct up_dev_s g_uart8priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -1569,11 +1578,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); up_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } #endif @@ -1585,7 +1594,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -1629,7 +1638,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 598490f520d4e..0e1ffee9e43a9 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -209,6 +209,7 @@ struct stm32l4_lowerhalf_s #ifdef HAVE_16BIT_TIMERS volatile int32_t position; /* The current position offset */ #endif + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -289,6 +290,7 @@ static struct stm32l4_lowerhalf_s g_tim1lower = .ops = &g_qecallbacks, .config = &g_tim1config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -312,6 +314,7 @@ static struct stm32l4_lowerhalf_s g_tim2lower = .ops = &g_qecallbacks, .config = &g_tim2config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -335,6 +338,7 @@ static struct stm32l4_lowerhalf_s g_tim3lower = .ops = &g_qecallbacks, .config = &g_tim3config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -358,6 +362,7 @@ static struct stm32l4_lowerhalf_s g_tim4lower = .ops = &g_qecallbacks, .config = &g_tim4config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -381,6 +386,7 @@ static struct stm32l4_lowerhalf_s g_tim5lower = .ops = &g_qecallbacks, .config = &g_tim5config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -404,6 +410,7 @@ static struct stm32l4_lowerhalf_s g_tim8lower = .ops = &g_qecallbacks, .config = &g_tim8config, .inuse = false, + .lock = SP_UNLOCKED, }; #endif @@ -1036,7 +1043,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, /* Loop until we are certain that no interrupt occurred between samples */ - spin_lock_irqsave(NULL); + spin_lock_irqsave(&priv->lock); do { position = priv->position; @@ -1044,7 +1051,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, verify = priv->position; } while (position != verify); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); /* Return the position measurement */ diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 69d35bc7f827d..94694d96dedd9 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -287,6 +287,7 @@ struct stm32l4_serial_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -496,6 +497,7 @@ static struct stm32l4_serial_s g_lpuart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -557,6 +559,7 @@ static struct stm32l4_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -618,6 +621,7 @@ static struct stm32l4_serial_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -679,6 +683,7 @@ static struct stm32l4_serial_s g_usart3priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -740,6 +745,7 @@ static struct stm32l4_serial_s g_uart4priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -801,6 +807,7 @@ static struct stm32l4_serial_s g_uart5priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -904,11 +911,11 @@ static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); stm32l4serial_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -920,7 +927,7 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -968,7 +975,7 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, stm32l4serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index 69b43cce859fd..1e7a5e21e6dd4 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -290,6 +290,7 @@ struct stm32l5_serial_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -500,6 +501,7 @@ static struct stm32l5_serial_s g_lpuart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -559,6 +561,7 @@ static struct stm32l5_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -620,6 +623,7 @@ static struct stm32l5_serial_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -681,6 +685,7 @@ static struct stm32l5_serial_s g_usart3priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -742,6 +747,7 @@ static struct stm32l5_serial_s g_uart4priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -803,6 +809,7 @@ static struct stm32l5_serial_s g_uart5priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -909,11 +916,11 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); stm32l5serial_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -925,7 +932,7 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -968,7 +975,7 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, stm32l5serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index d5e864947b554..5d009a3c3b0c9 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -290,6 +290,7 @@ struct stm32_serial_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -500,6 +501,7 @@ static struct stm32_serial_s g_lpuart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = = SP_UNLOCKED, }; #endif @@ -559,6 +561,7 @@ static struct stm32_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = = SP_UNLOCKED, }; #endif @@ -620,6 +623,7 @@ static struct stm32_serial_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = = SP_UNLOCKED, }; #endif @@ -681,6 +685,7 @@ static struct stm32_serial_s g_usart3priv = .rs485_dir_polarity = true, # endif # endif + .lock = = SP_UNLOCKED, }; #endif @@ -742,6 +747,7 @@ static struct stm32_serial_s g_uart4priv = .rs485_dir_polarity = true, # endif # endif + .lock = = SP_UNLOCKED, }; #endif @@ -803,6 +809,7 @@ static struct stm32_serial_s g_uart5priv = .rs485_dir_polarity = true, # endif # endif + .lock = = SP_UNLOCKED, }; #endif @@ -925,7 +932,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -968,7 +975,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, stm32serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 1f6cdc22145e7..60f1700724d36 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -231,6 +231,7 @@ struct stm32wb_serial_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -408,6 +409,7 @@ static struct stm32wb_serial_s g_lpuart1priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -469,6 +471,7 @@ static struct stm32wb_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -559,11 +562,11 @@ static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); stm32wb_serial_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -575,7 +578,7 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -623,7 +626,7 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, stm32wb_serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 434323f9d676a..e9da9162ee94e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -261,6 +261,7 @@ struct stm32wl5_serial_s const uint32_t rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */ const bool rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */ #endif + spinlock_t lock; }; /**************************************************************************** @@ -448,6 +449,7 @@ static struct stm32wl5_serial_s g_lpuart1priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -507,6 +509,7 @@ static struct stm32wl5_serial_s g_usart1priv = .rs485_dir_polarity = true, # endif #endif + .lock = SP_UNLOCKED, }; #endif @@ -568,6 +571,7 @@ static struct stm32wl5_serial_s g_usart2priv = .rs485_dir_polarity = true, # endif # endif + .lock = SP_UNLOCKED, }; #endif @@ -664,11 +668,11 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); stm32wl5serial_setusartint(priv, ie); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -680,7 +684,7 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (ie) { @@ -723,7 +727,7 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, stm32wl5serial_setusartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c b/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c index f933ce4dc6829..31ae914f3763c 100644 --- a/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c +++ b/arch/arm/src/tiva/cc13xx/cc13xx_enablepwr.c @@ -39,6 +39,7 @@ * Private Data ****************************************************************************/ +static spinlock_t g_cc13xx_enablepwr_lock = SP_UNLOCKED; static uint16_t g_domain_usage[2]; /**************************************************************************** @@ -66,13 +67,13 @@ void cc13xx_periph_enablepwr(uint32_t peripheral) /* Remember that this peripheral needs power in this domain */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_cc13xx_enablepwr_lock); g_domain_usage[dndx] |= (1 << pndx); /* Make sure that power is enabled in that domain */ prcm_powerdomain_on(domain); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_cc13xx_enablepwr_lock, flags); /* Wait for the power domain to be ready. REVISIT: This really should be * in the critical section but this could take too long. @@ -100,7 +101,7 @@ void cc13xx_periph_disablepwr(uint32_t peripheral) /* This peripheral no longer needs power in this domain */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_cc13xx_enablepwr_lock); g_domain_usage[dndx] &= ~(1 << pndx); /* If there are no peripherals needing power in this domain, then turn off @@ -113,5 +114,5 @@ void cc13xx_periph_disablepwr(uint32_t peripheral) PRCM_DOMAIN_SERIAL : PRCM_DOMAIN_PERIPH); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_cc13xx_enablepwr_lock, flags); } diff --git a/arch/arm/src/tiva/common/tiva_hciuart.c b/arch/arm/src/tiva/common/tiva_hciuart.c index 25eb0232328aa..e19f15ce47b47 100644 --- a/arch/arm/src/tiva/common/tiva_hciuart.c +++ b/arch/arm/src/tiva/common/tiva_hciuart.c @@ -103,6 +103,7 @@ struct hciuart_config_s { struct btuart_lowerhalf_s lower; /* Generic HCI-UART lower half */ struct hciuart_state_s *state; /* Reference to variable state */ + spinlock_t lock; /* Spinlock */ uint8_t *rxbuffer; /* Rx buffer start */ uint8_t *txbuffer; /* Tx buffer start */ uint16_t rxbufsize; /* Size of the Rx buffer */ @@ -205,6 +206,7 @@ static const struct hciuart_config_s g_hciuart0_config = }, .state = &g_hciuart0_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart0_rxbuffer, .txbuffer = g_uart0_txbuffer, @@ -255,6 +257,7 @@ static const struct hciuart_config_s g_hciuart1_config = }, .state = &g_hciuart1_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart1_rxbuffer, .txbuffer = g_uart1_txbuffer, @@ -305,6 +308,7 @@ static const struct hciuart_config_s g_hciuart2_config = }, .state = &g_hciuart2_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart2_rxbuffer, .txbuffer = g_uart2_txbuffer, @@ -355,6 +359,7 @@ static const struct hciuart_config_s g_hciuart3_config = }, .state = &g_hciuart3_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart3_rxbuffer, .txbuffer = g_uart3_txbuffer, @@ -405,6 +410,7 @@ static const struct hciuart_config_s g_hciuart4_config = }, .state = &g_hciuart4_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart4_rxbuffer, .txbuffer = g_uart4_txbuffer, @@ -455,6 +461,7 @@ static const struct hciuart_config_s g_hciuart5_config = }, .state = &g_hciuart5_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart5_rxbuffer, .txbuffer = g_uart5_txbuffer, @@ -505,6 +512,7 @@ static const struct hciuart_config_s g_hciuart6_config = }, .state = &g_hciuart6_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart6_rxbuffer, .txbuffer = g_uart6_txbuffer, @@ -555,6 +563,7 @@ static const struct hciuart_config_s g_hciuart7_config = }, .state = &g_hciuart7_state, + .lock = SP_UNLOCKED, .rxbuffer = g_uart7_rxbuffer, .txbuffer = g_uart7_txbuffer, @@ -1272,7 +1281,7 @@ static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, /* If the callback is NULL, then we are detaching */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); if (callback == NULL) { uint32_t intset; @@ -1294,7 +1303,7 @@ static void hciuart_rxattach(const struct btuart_lowerhalf_s *lower, state->callback = callback; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); } /**************************************************************************** @@ -1322,7 +1331,7 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, uint32_t intset; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); if (enable) { /* Receive an interrupt when their is anything in the Rx data @@ -1338,7 +1347,7 @@ static void hciuart_rxenable(const struct btuart_lowerhalf_s *lower, hciuart_disableints(config, intset); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); } } @@ -1524,9 +1533,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, /* Make sure that the Tx Interrupts are disabled. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); hciuart_disableints(config, UART_IM_TXIM); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); /* Loop until all of the user data have been moved to the Tx buffer */ @@ -1621,9 +1630,9 @@ static ssize_t hciuart_write(const struct btuart_lowerhalf_s *lower, if (state->txhead != state->txtail) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&config->lock); hciuart_enableints(config, UART_IM_TXIM); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&config->lock, flags); } return ntotal; diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c index 87389035970b0..059e1aee08bdf 100644 --- a/arch/arm/src/tms570/tms570_lowputc.c +++ b/arch/arm/src/tms570/tms570_lowputc.c @@ -82,6 +82,12 @@ # undef HAVE_SERIAL_CONSOLE #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_tms570_lowputc_lock = SP_UNLOCKED; + /**************************************************************************** * Public Data ****************************************************************************/ @@ -187,30 +193,18 @@ void arm_lowputc(char ch) #ifdef HAVE_SERIAL_CONSOLE irqstate_t flags; - for (; ; ) - { - /* Wait for the transmitter to be available */ + /* Wait for the transmitter to be available */ - while ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_FLR_OFFSET) & - SCI_FLR_TXRDY) == 0); + flags = spin_lock_irqsave(&g_tms570_lowputc_lock); - /* Disable interrupts so that the test and the transmission are - * atomic. - */ + while ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_FLR_OFFSET) & + SCI_FLR_TXRDY) == 0); - flags = spin_lock_irqsave(NULL); - if ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_FLR_OFFSET) & - SCI_FLR_TXRDY) != 0) - { - /* Send the character */ + /* Send the character */ - putreg32((uint32_t)ch, TMS570_CONSOLE_BASE + TMS570_SCI_TD_OFFSET); - spin_unlock_irqrestore(NULL, flags); - return; - } + putreg32((uint32_t)ch, TMS570_CONSOLE_BASE + TMS570_SCI_TD_OFFSET); - spin_unlock_irqrestore(NULL, flags); - } + spin_unlock_irqrestore(&g_tms570_lowputc_lock, flags); #endif } diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index 18f6d6922a962..9b1d161601d29 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -238,6 +238,7 @@ struct xmc4_dev_s /* UART configuration */ struct uart_config_s config; + spinlock_t lock; }; /**************************************************************************** @@ -326,7 +327,8 @@ static struct xmc4_dev_s g_uart0priv = .startbufferptr = 0, .txbuffersize = CONFIG_XMC4_USIC0_CHAN0_TX_BUFFER_SIZE, .rxbuffersize = CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE, - } + }, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart0port = @@ -365,7 +367,8 @@ static struct xmc4_dev_s g_uart1priv = + CONFIG_XMC4_USIC0_CHAN0_RX_BUFFER_SIZE, .txbuffersize = CONFIG_XMC4_USIC0_CHAN1_TX_BUFFER_SIZE, .rxbuffersize = CONFIG_XMC4_USIC0_CHAN1_RX_BUFFER_SIZE, - } + }, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart1port = @@ -403,7 +406,8 @@ static struct xmc4_dev_s g_uart2priv = .startbufferptr = 0, .txbuffersize = CONFIG_XMC4_USIC1_CHAN0_TX_BUFFER_SIZE, .rxbuffersize = CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE, - } + }, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart2port = @@ -442,7 +446,8 @@ static struct xmc4_dev_s g_uart3priv = + CONFIG_XMC4_USIC1_CHAN0_RX_BUFFER_SIZE, .txbuffersize = CONFIG_XMC4_USIC1_CHAN1_TX_BUFFER_SIZE, .rxbuffersize = CONFIG_XMC4_USIC1_CHAN1_RX_BUFFER_SIZE, - } + }, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart3port = @@ -480,7 +485,8 @@ static struct xmc4_dev_s g_uart4priv = .startbufferptr = 0, .txbuffersize = CONFIG_XMC4_USIC2_CHAN0_TX_BUFFER_SIZE, .rxbuffersize = CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE, - } + }, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart4port = @@ -519,7 +525,8 @@ static struct xmc4_dev_s g_uart5priv = + CONFIG_XMC4_USIC2_CHAN0_RX_BUFFER_SIZE, .txbuffersize = CONFIG_XMC4_USIC2_CHAN1_TX_BUFFER_SIZE, .rxbuffersize = CONFIG_XMC4_USIC2_CHAN1_RX_BUFFER_SIZE, - } + }, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart5port = @@ -567,22 +574,28 @@ static inline void xmc4_serialout(struct xmc4_dev_s *priv, * Name: xmc4_modifyreg ****************************************************************************/ -static inline void xmc4_modifyreg(struct xmc4_dev_s *priv, unsigned +static inline void xmc4_modifyreg_nolock(struct xmc4_dev_s *priv, unsigned int offset, uint32_t setbits, uint32_t clrbits) { - irqstate_t flags; uintptr_t regaddr = priv->uartbase + offset; uint32_t regval; - flags = spin_lock_irqsave(NULL); - regval = getreg32(regaddr); regval &= ~clrbits; regval |= setbits; putreg32(regval, regaddr); +} - spin_unlock_irqrestore(NULL, flags); +static inline void xmc4_modifyreg(struct xmc4_dev_s *priv, unsigned + int offset, uint32_t setbits, + uint32_t clrbits) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + xmc4_modifyreg_nolock(priv, offset, setbits, clrbits); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -591,15 +604,11 @@ static inline void xmc4_modifyreg(struct xmc4_dev_s *priv, unsigned static void xmc4_setuartint(struct xmc4_dev_s *priv) { - irqstate_t flags; - /* Re-enable/re-disable event interrupts corresponding to the state of * bits in priv->ccr. */ - flags = spin_lock_irqsave(NULL); xmc4_modifyreg(priv, XMC4_USIC_CCR_OFFSET, CCR_ALL_EVENTS, priv->ccr); - spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -614,10 +623,11 @@ static void xmc4_restoreuartint(struct xmc4_dev_s *priv, uint32_t ccr) * in the ccr argument. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); priv->ccr = ccr; - xmc4_setuartint(priv); - spin_unlock_irqrestore(NULL, flags); + xmc4_modifyreg_nolock(priv, XMC4_USIC_CCR_OFFSET, CCR_ALL_EVENTS, + priv->ccr); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -626,16 +636,12 @@ static void xmc4_restoreuartint(struct xmc4_dev_s *priv, uint32_t ccr) static void xmc4_disableuartint(struct xmc4_dev_s *priv, uint32_t *ccr) { - irqstate_t flags; - - flags = spin_lock_irqsave(NULL); if (ccr) { *ccr = priv->ccr; } xmc4_restoreuartint(priv, 0); - spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm64/src/a64/a64_serial.c b/arch/arm64/src/a64/a64_serial.c index d8bac4e6a1666..d2ed531855b0c 100644 --- a/arch/arm64/src/a64/a64_serial.c +++ b/arch/arm64/src/a64/a64_serial.c @@ -269,6 +269,12 @@ struct a64_uart_port_s bool is_console; /* 1 if this UART is console */ }; +/*************************************************************************** + * Private Data + ***************************************************************************/ + +static spinlock_t g_a64_serial_lock = SP_UNLOCKED; + /*************************************************************************** * Private Function Prototypes ***************************************************************************/ @@ -967,7 +973,7 @@ static int a64_uart_init(uint32_t gating, uint32_t rst, pio_pinset_t tx, irqstate_t flags; int ret = OK; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_a64_serial_lock); /* Enable clocking to UART */ @@ -993,7 +999,7 @@ static int a64_uart_init(uint32_t gating, uint32_t rst, pio_pinset_t tx, } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_a64_serial_lock, flags); return ret; }; diff --git a/arch/arm64/src/common/arm64_modifyreg32.c b/arch/arm64/src/common/arm64_modifyreg32.c index 1dd9008c01422..25e5405fea140 100644 --- a/arch/arm64/src/common/arm64_modifyreg32.c +++ b/arch/arm64/src/common/arm64_modifyreg32.c @@ -33,6 +33,12 @@ #include "arm64_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,10 +56,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/arm64/src/common/arm64_modifyreg8.c b/arch/arm64/src/common/arm64_modifyreg8.c index 7ab314b3e3bca..900d6f2af92e2 100644 --- a/arch/arm64/src/common/arm64_modifyreg8.c +++ b/arch/arm64/src/common/arm64_modifyreg8.c @@ -33,6 +33,12 @@ #include "arm64_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,10 +56,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/arm64/src/imx9/imx9_edma.c b/arch/arm64/src/imx9/imx9_edma.c index 1d5f6085454f7..7669f6c35b684 100644 --- a/arch/arm64/src/imx9/imx9_edma.c +++ b/arch/arm64/src/imx9/imx9_edma.c @@ -141,6 +141,7 @@ struct imx9_edma_s /* This array describes each DMA channel */ struct imx9_dmach_s dmach[IMX9_EDMA_NCHANNELS]; + spinlock_t lock; }; /**************************************************************************** @@ -155,6 +156,7 @@ static struct imx9_edma_s g_edma = #if CONFIG_IMX9_EDMA_NTCD > 0 .dsem = SEM_INITIALIZER(CONFIG_IMX9_EDMA_NTCD), #endif + .lock = SP_UNLOCKED }; #if CONFIG_IMX9_EDMA_NTCD > 0 @@ -194,15 +196,15 @@ static struct imx9_edmatcd_s *imx9_tcd_alloc(void) * waiting. */ - flags = enter_critical_section(); nxsem_wait_uninterruptible(&g_edma.dsem); /* Now there should be a TCD in the free list reserved just for us */ + flags = spin_lock_irqsave(&g_edma.lock); tcd = (struct imx9_edmatcd_s *)sq_remfirst(&g_tcd_free); DEBUGASSERT(tcd != NULL); - leave_critical_section(flags); + spin_lock_irqsave(&g_edma.lock, flags); return tcd; } #endif @@ -216,6 +218,17 @@ static struct imx9_edmatcd_s *imx9_tcd_alloc(void) ****************************************************************************/ #if CONFIG_IMX9_EDMA_NTCD > 0 +static void imx9_tcd_free_nolock(struct imx9_edmatcd_s *tcd) +{ + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); +} + static void imx9_tcd_free(struct imx9_edmatcd_s *tcd) { irqstate_t flags; @@ -225,10 +238,11 @@ static void imx9_tcd_free(struct imx9_edmatcd_s *tcd) * a TCD. */ - flags = spin_lock_irqsave(NULL); - sq_addlast((sq_entry_t *)tcd, &g_tcd_free); - nxsem_post(&g_edma.dsem); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + imx9_tcd_free_nolock(tcd); + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } #endif @@ -438,6 +452,11 @@ static void imx9_dmaterminate(struct imx9_dmach_s *dmach, int result) edma_callback_t callback; void *arg; + irqstate_t flags; + + flags = spin_lock_irqsave(&g_edma.lock); + sched_lock(); + /* Disable channel IRQ requests */ putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); @@ -467,7 +486,7 @@ static void imx9_dmaterminate(struct imx9_dmach_s *dmach, int result) next = dmach->flags & EDMA_CONFIG_LOOPDEST ? NULL : (struct imx9_edmatcd_s *)((uintptr_t)tcd->dlastsga); - imx9_tcd_free(tcd); + imx9_tcd_free_nolock(tcd); } dmach->head = NULL; @@ -487,6 +506,9 @@ static void imx9_dmaterminate(struct imx9_dmach_s *dmach, int result) { callback((DMACH_HANDLE)dmach, arg, true, result); } + + spin_unlock_irqrestore(&g_edma.lock, flags); + sched_unlock(); } /**************************************************************************** @@ -1252,7 +1274,7 @@ int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, /* Save the callback info. This will be invoked when the DMA completes */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); dmach->callback = callback; dmach->arg = arg; @@ -1271,7 +1293,7 @@ int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, putreg32(regval, base + IMX9_EDMA_CH_CSR_OFFSET); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); return OK; } @@ -1294,14 +1316,11 @@ int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, void imx9_dmach_stop(DMACH_HANDLE handle) { struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; - irqstate_t flags; dmainfo("dmach: %p\n", dmach); DEBUGASSERT(dmach != NULL); - flags = spin_lock_irqsave(NULL); imx9_dmaterminate(dmach, -EINTR); - spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1416,7 +1435,7 @@ void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs) /* eDMA Global Registers */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_edma.lock); /* REVISIT: eDMA4 does not show INT_HIGH / HRS_HIGH values correctly */ @@ -1450,7 +1469,7 @@ void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs) regs->dmamux = 0; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_edma.lock, flags); } #endif /* CONFIG_DEBUG_DMA */ diff --git a/arch/arm64/src/imx9/imx9_lpuart.c b/arch/arm64/src/imx9/imx9_lpuart.c index c473d241c3830..d8352a56459c3 100644 --- a/arch/arm64/src/imx9/imx9_lpuart.c +++ b/arch/arm64/src/imx9/imx9_lpuart.c @@ -304,6 +304,7 @@ struct imx9_uart_s const bool userts; /* input flow control (RTS) available */ const bool rs485mode; /* We are in RS485 (RTS on TX) mode */ const bool inviflow; /* Invert RTS sense */ + spinlock_t lock; /* Spinlock */ uint32_t baud; /* Configured baud */ uint32_t ie; /* Saved enabled interrupts */ uint8_t irq; /* IRQ associated with this UART */ @@ -626,6 +627,7 @@ static struct imx9_uart_s g_lpuart1priv = .irq = IMX9_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART1_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) .usects = true, @@ -685,6 +687,7 @@ static struct imx9_uart_s g_lpuart2priv = .irq = IMX9_IRQ_LPUART2, .parity = CONFIG_LPUART2_PARITY, .bits = CONFIG_LPUART2_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART2_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) .usects = true, @@ -744,6 +747,7 @@ static struct imx9_uart_s g_lpuart3priv = .irq = IMX9_IRQ_LPUART3, .parity = CONFIG_LPUART3_PARITY, .bits = CONFIG_LPUART3_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART3_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) .usects = true, @@ -803,6 +807,7 @@ static struct imx9_uart_s g_lpuart4priv = .irq = IMX9_IRQ_LPUART4, .parity = CONFIG_LPUART4_PARITY, .bits = CONFIG_LPUART4_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART4_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) .usects = true, @@ -862,6 +867,7 @@ static struct imx9_uart_s g_lpuart5priv = .irq = IMX9_IRQ_LPUART5, .parity = CONFIG_LPUART5_PARITY, .bits = CONFIG_LPUART5_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART5_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) .usects = true, @@ -921,6 +927,7 @@ static struct imx9_uart_s g_lpuart6priv = .irq = IMX9_IRQ_LPUART6, .parity = CONFIG_LPUART6_PARITY, .bits = CONFIG_LPUART6_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART6_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) .usects = true, @@ -980,6 +987,7 @@ static struct imx9_uart_s g_lpuart7priv = .irq = IMX9_IRQ_LPUART7, .parity = CONFIG_LPUART7_PARITY, .bits = CONFIG_LPUART7_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART7_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) .usects = true, @@ -1039,6 +1047,7 @@ static struct imx9_uart_s g_lpuart8priv = .irq = IMX9_IRQ_LPUART8, .parity = CONFIG_LPUART8_PARITY, .bits = CONFIG_LPUART8_BITS, + .lock = SP_UNLOCKED, .stopbits2 = CONFIG_LPUART8_2STOP, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) .usects = true, @@ -1121,13 +1130,11 @@ static int imx9_dma_nextrx(struct imx9_uart_s *priv) * Name: imx9_disableuartint ****************************************************************************/ -static inline void imx9_disableuartint(struct imx9_uart_s *priv, - uint32_t *ie) +static inline void imx9_disableuartint_nolock(struct imx9_uart_s *priv, + uint32_t *ie) { - irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); /* Return the current Rx and Tx interrupt state */ @@ -1139,29 +1146,45 @@ static inline void imx9_disableuartint(struct imx9_uart_s *priv, regval &= ~LPUART_ALL_INTS; imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); +} + +static inline void imx9_disableuartint(struct imx9_uart_s *priv, + uint32_t *ie) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(&priv->lock); + imx9_disableuartint_nolock(priv, ie); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** * Name: imx9_restoreuartint ****************************************************************************/ +static inline void imx9_restoreuartint_nolock(struct imx9_uart_s *priv, + uint32_t ie) +{ + uint32_t regval; + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); +} + static inline void imx9_restoreuartint(struct imx9_uart_s *priv, - uint32_t ie) + uint32_t ie) { irqstate_t flags; - uint32_t regval; /* Enable/disable any interrupts that are currently disabled but should be * enabled/disabled. */ - flags = spin_lock_irqsave(NULL); - regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); - regval &= ~LPUART_ALL_INTS; - regval |= ie; - imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + imx9_restoreuartint_nolock(priv, ie); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -1758,15 +1781,15 @@ static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) * implement TCSADRAIN / TCSAFLUSH */ - flags = spin_lock_irqsave(NULL); - imx9_disableuartint(priv, &ie); + flags = spin_lock_irqsave(&priv->lock); + imx9_disableuartint_nolock(priv, &ie); ret = dev->ops->setup(dev); /* Restore the interrupt state */ - imx9_restoreuartint(priv, ie); + imx9_restoreuartint_nolock(priv, ie); priv->ie = ie; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } } break; @@ -1778,8 +1801,8 @@ static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) uint32_t regval; struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; - flags = spin_lock_irqsave(NULL); - regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + flags = spin_lock_irqsave(&priv->lock); + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1792,7 +1815,7 @@ static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } break; #endif @@ -1805,7 +1828,7 @@ static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) uint32_t regval; struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ctrl = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); stat = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); regval = ctrl; @@ -1844,7 +1867,7 @@ static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, stat); imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, ctrl); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } break; #endif @@ -1898,7 +1921,7 @@ static void imx9_rxint(struct uart_dev_s *dev, bool enable) /* Enable interrupts for data available at Rx */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -1914,7 +1937,7 @@ static void imx9_rxint(struct uart_dev_s *dev, bool enable) regval &= ~LPUART_ALL_INTS; regval |= priv->ie; imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } #endif @@ -2319,7 +2342,7 @@ static void imx9_txint(struct uart_dev_s *dev, bool enable) /* Enable interrupt for TX complete */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (enable) { #ifndef CONFIG_SUPPRESS_SERIAL_INTS @@ -2335,7 +2358,7 @@ static void imx9_txint(struct uart_dev_s *dev, bool enable) regval &= ~LPUART_ALL_INTS; regval |= priv->ie; imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } #endif diff --git a/arch/avr/src/common/avr_modifyreg32.c b/arch/avr/src/common/avr_modifyreg32.c index a4733773b947d..1dd4666639123 100644 --- a/arch/avr/src/common/avr_modifyreg32.c +++ b/arch/avr/src/common/avr_modifyreg32.c @@ -31,6 +31,7 @@ #include #include +#include #include "avr_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/avr/src/common/avr_modifyreg8.c b/arch/avr/src/common/avr_modifyreg8.c index 7419750c03cc0..59bb0fbd79361 100644 --- a/arch/avr/src/common/avr_modifyreg8.c +++ b/arch/avr/src/common/avr_modifyreg8.c @@ -31,6 +31,7 @@ #include #include +#include #include "avr_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/ceva/src/common/ceva_modifyreg32.c b/arch/ceva/src/common/ceva_modifyreg32.c index af64f365f4b52..5fd84ad3e0ae4 100644 --- a/arch/ceva/src/common/ceva_modifyreg32.c +++ b/arch/ceva/src/common/ceva_modifyreg32.c @@ -29,6 +29,12 @@ #include "ceva_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -46,10 +52,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - spin_unlock_irqrestore(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/ceva/src/common/ceva_modifyreg8.c b/arch/ceva/src/common/ceva_modifyreg8.c index c0c1c78beb13a..b91ca92fe20be 100644 --- a/arch/ceva/src/common/ceva_modifyreg8.c +++ b/arch/ceva/src/common/ceva_modifyreg8.c @@ -29,6 +29,12 @@ #include "ceva_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -46,10 +52,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/hc/src/common/hc_modifyreg32.c b/arch/hc/src/common/hc_modifyreg32.c index b10296f720e8d..0ac164a31d0e3 100644 --- a/arch/hc/src/common/hc_modifyreg32.c +++ b/arch/hc/src/common/hc_modifyreg32.c @@ -31,6 +31,7 @@ #include #include +#include #include "hc_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/hc/src/common/hc_modifyreg8.c b/arch/hc/src/common/hc_modifyreg8.c index 05e08e9f1e921..e18263c8eb07b 100644 --- a/arch/hc/src/common/hc_modifyreg8.c +++ b/arch/hc/src/common/hc_modifyreg8.c @@ -31,6 +31,7 @@ #include #include +#include #include "hc_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/mips/src/common/mips_modifyreg32.c b/arch/mips/src/common/mips_modifyreg32.c index a6ea0c1c21085..59364f48ff85b 100644 --- a/arch/mips/src/common/mips_modifyreg32.c +++ b/arch/mips/src/common/mips_modifyreg32.c @@ -31,6 +31,7 @@ #include #include +#include #include "mips_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/mips/src/common/mips_modifyreg8.c b/arch/mips/src/common/mips_modifyreg8.c index 43884a583cebd..fac89d1776d59 100644 --- a/arch/mips/src/common/mips_modifyreg8.c +++ b/arch/mips/src/common/mips_modifyreg8.c @@ -31,6 +31,7 @@ #include #include +#include #include "mips_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/mips/src/pic32mx/pic32mx_serial.c b/arch/mips/src/pic32mx/pic32mx_serial.c index 8bd350b89d925..e2a2a143b3688 100644 --- a/arch/mips/src/pic32mx/pic32mx_serial.c +++ b/arch/mips/src/pic32mx/pic32mx_serial.c @@ -141,6 +141,7 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (5, 6, 7 or 8) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -152,7 +153,9 @@ struct up_dev_s static inline uint32_t up_serialin(struct up_dev_s *priv, int offset); static inline void up_serialout(struct up_dev_s *priv, int offset, uint32_t value); +#ifdef HAVE_SERIAL_CONSOLE static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im); +#endif static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im); /* Serial driver methods */ @@ -220,6 +223,7 @@ static struct up_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart1port = @@ -254,6 +258,7 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart2port = @@ -300,19 +305,27 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, * Name: up_restoreuartint ****************************************************************************/ +static void up_restoreuartint_nolock(struct uart_dev_s *dev, uint8_t im) +{ + up_rxint(dev, RX_ENABLED(im)); + up_txint(dev, TX_ENABLED(im)); +} + +#ifdef HAVE_SERIAL_CONSOLE static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) { + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; /* Re-enable/re-disable interrupts corresponding to the state * of bits in im. */ - flags = spin_lock_irqsave(NULL); - up_rxint(dev, RX_ENABLED(im)); - up_txint(dev, TX_ENABLED(im)); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + up_restoreuartint_nolock(dev, im); + spin_unlock_irqrestore(&priv->lock, flags); } +#endif /**************************************************************************** * Name: up_disableuartint @@ -323,14 +336,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (im) { *im = priv->im; } - up_restoreuartint(dev, 0); - spin_unlock_irqrestore(NULL, flags); + up_restoreuartint_nolock(dev, 0); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/mips/src/pic32mz/pic32mz_serial.c b/arch/mips/src/pic32mz/pic32mz_serial.c index 21d9aa7200d68..0a59fdc09e6ca 100644 --- a/arch/mips/src/pic32mz/pic32mz_serial.c +++ b/arch/mips/src/pic32mz/pic32mz_serial.c @@ -249,6 +249,7 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (5, 6, 7 or 8) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + spinlock_t lock; /* Spinlock */ #ifdef CONFIG_PIC32MZ_UART_BREAKS bool brk; /* true: Line break in progress */ @@ -351,6 +352,7 @@ static struct up_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, + .lock = SP_UNLOCKED, #ifdef CONFIG_PIC32MZ_UART_BREAKS .brk = false, @@ -393,6 +395,7 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, + .lock = SP_UNLOCKED, #ifdef CONFIG_PIC32MZ_UART_BREAKS .brk = false, @@ -435,6 +438,7 @@ static struct up_dev_s g_uart3priv = .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, .stopbits2 = CONFIG_UART3_2STOP, + .lock = SP_UNLOCKED, #ifdef CONFIG_PIC32MZ_UART_BREAKS .brk = false, @@ -477,6 +481,7 @@ static struct up_dev_s g_uart4priv = .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, + .lock = SP_UNLOCKED, #ifdef CONFIG_PIC32MZ_UART_BREAKS .brk = false, @@ -519,6 +524,7 @@ static struct up_dev_s g_uart5priv = .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, + .lock = SP_UNLOCKED, #ifdef CONFIG_PIC32MZ_UART_BREAKS .brk = false, @@ -561,6 +567,7 @@ static struct up_dev_s g_uart6priv = .parity = CONFIG_UART6_PARITY, .bits = CONFIG_UART6_BITS, .stopbits2 = CONFIG_UART6_2STOP, + .lock = SP_UNLOCKED, #ifdef CONFIG_PIC32MZ_UART_BREAKS .brk = false, @@ -617,18 +624,24 @@ static inline void up_serialout(struct up_dev_s *priv, int offset, * Name: up_restoreuartint ****************************************************************************/ +static void up_restoreuartint_nolock(struct uart_dev_s *dev, uint8_t im) +{ + up_rxint(dev, RX_ENABLED(im)); + up_txint(dev, TX_ENABLED(im)); +} + static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) { + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; /* Re-enable/re-disable interrupts corresponding to the state of bits * in im */ - flags = spin_lock_irqsave(NULL); - up_rxint(dev, RX_ENABLED(im)); - up_txint(dev, TX_ENABLED(im)); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + up_restoreuartint_nolock(dev, im); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -640,14 +653,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (im) { *im = priv->im; } - up_restoreuartint(dev, 0); - spin_unlock_irqrestore(NULL, flags); + up_restoreuartint_nolock(dev, 0); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/misoc/src/common/misoc_modifyreg32.c b/arch/misoc/src/common/misoc_modifyreg32.c index 2a5d372efcec3..6d02b36367d61 100644 --- a/arch/misoc/src/common/misoc_modifyreg32.c +++ b/arch/misoc/src/common/misoc_modifyreg32.c @@ -31,9 +31,16 @@ #include #include +#include #include "misoc.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,10 +58,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/misoc/src/common/misoc_modifyreg8.c b/arch/misoc/src/common/misoc_modifyreg8.c index 7eda3878d9995..207d8fe0dcdab 100644 --- a/arch/misoc/src/common/misoc_modifyreg8.c +++ b/arch/misoc/src/common/misoc_modifyreg8.c @@ -31,9 +31,16 @@ #include #include +#include #include "misoc.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -51,10 +58,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/or1k/src/common/or1k_modifyreg32.c b/arch/or1k/src/common/or1k_modifyreg32.c index c079d32323607..7e56c0d308fcf 100644 --- a/arch/or1k/src/common/or1k_modifyreg32.c +++ b/arch/or1k/src/common/or1k_modifyreg32.c @@ -33,6 +33,12 @@ #include "or1k_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,10 +56,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/or1k/src/common/or1k_modifyreg8.c b/arch/or1k/src/common/or1k_modifyreg8.c index c378b542a0329..32783b168c058 100644 --- a/arch/or1k/src/common/or1k_modifyreg8.c +++ b/arch/or1k/src/common/or1k_modifyreg8.c @@ -33,6 +33,12 @@ #include "or1k_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,10 +56,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/or1k/src/mor1kx/mor1kx_serial.c b/arch/or1k/src/mor1kx/mor1kx_serial.c index 9a72027d5f7d4..93fb3af97ff4d 100644 --- a/arch/or1k/src/mor1kx/mor1kx_serial.c +++ b/arch/or1k/src/mor1kx/mor1kx_serial.c @@ -52,6 +52,14 @@ #define OR1K_BAUD (115200) #define OR1K_DIVISOR (OR1K_SYS_CLK / (16*OR1K_BAUD)) +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef HAVE_SERIAL_CONSOLE +static spinlock_t g_serial_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -117,10 +125,10 @@ void up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_serial_lock); /* or1k_lowputc(ch); */ - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_serial_lock, flags); #endif } diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c index fa83aea6450fd..4c8a5da506975 100644 --- a/arch/risc-v/src/bl602/bl602_serial.c +++ b/arch/risc-v/src/bl602/bl602_serial.c @@ -152,6 +152,8 @@ static bool bl602_txempty(struct uart_dev_s *dev); * Private Data ****************************************************************************/ +static spinlock_t g_bl602_serial_lock = SP_UNLOCKED; + static const struct uart_ops_s g_uart_ops = { .setup = bl602_setup, @@ -891,10 +893,10 @@ void riscv_serialinit(void) void up_putc(int ch) { #ifdef HAVE_SERIAL_CONSOLE - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_bl602_serial_lock); riscv_lowputc(ch); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_bl602_serial_lock, flags); #endif } diff --git a/arch/risc-v/src/c906/c906_serial.c b/arch/risc-v/src/c906/c906_serial.c index 51de7e4738ef5..270ddb204b3ab 100644 --- a/arch/risc-v/src/c906/c906_serial.c +++ b/arch/risc-v/src/c906/c906_serial.c @@ -101,6 +101,7 @@ struct up_dev_s uint32_t baud; /* Configured baud */ uint8_t irq; /* IRQ associated with this UART */ uint8_t im; /* Interrupt mask state */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -167,6 +168,7 @@ static struct up_dev_s g_uart0priv = .uartbase = C906_UART0_BASE, .baud = CONFIG_UART0_BAUD, .irq = C906_IRQ_UART0, + .lock = SP_UNLOCKED }; static uart_dev_t g_uart0port = @@ -217,12 +219,12 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); priv->im = im; up_serialout(priv, UART_IE_OFFSET, im); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -231,7 +233,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); /* Return the current interrupt mask value */ @@ -244,7 +246,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IE_OFFSET, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/common/espressif/esp_lowputc.c b/arch/risc-v/src/common/espressif/esp_lowputc.c index b861fb69555c9..29296569cbe68 100644 --- a/arch/risc-v/src/common/espressif/esp_lowputc.c +++ b/arch/risc-v/src/common/espressif/esp_lowputc.c @@ -102,7 +102,8 @@ struct esp_uart_s g_uart0_config = .oflow = false, /* output flow control (CTS) disabled */ #endif #endif - .hal = &g_uart0_hal + .hal = &g_uart0_hal, + .lock = SP_UNLOCKED }; #endif /* CONFIG_ESPRESSIF_UART0 */ @@ -147,7 +148,8 @@ struct esp_uart_s g_uart1_config = .oflow = false, /* output flow control (CTS) disabled */ #endif #endif - .hal = &g_uart1_hal + .hal = &g_uart1_hal, + .lock = SP_UNLOCKED }; #endif /* CONFIG_ESPRESSIF_UART1 */ @@ -210,7 +212,7 @@ void esp_lowputc_disable_all_uart_int(const struct esp_uart_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (current_status != NULL) { @@ -227,7 +229,7 @@ void esp_lowputc_disable_all_uart_int(const struct esp_uart_s *priv, uart_hal_clr_intsts_mask(priv->hal, UINT32_MAX); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/common/espressif/esp_lowputc.h b/arch/risc-v/src/common/espressif/esp_lowputc.h index ebbbe878fc7bc..a0f9cf215b624 100644 --- a/arch/risc-v/src/common/espressif/esp_lowputc.h +++ b/arch/risc-v/src/common/espressif/esp_lowputc.h @@ -39,6 +39,7 @@ #include #include +#include #include "chip.h" #include "esp_irq.h" @@ -76,6 +77,7 @@ struct esp_uart_s bool oflow; /* Output flow control (CTS) enabled */ #endif uart_hal_context_t *hal; /* HAL context */ + spinlock_t lock; /* Spinlock */ }; extern struct esp_uart_s g_uart0_config; diff --git a/arch/risc-v/src/common/espressif/esp_tickless.c b/arch/risc-v/src/common/espressif/esp_tickless.c index b4ce4806a8bf7..18759c937fc8c 100644 --- a/arch/risc-v/src/common/espressif/esp_tickless.c +++ b/arch/risc-v/src/common/espressif/esp_tickless.c @@ -59,6 +59,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_esp_tickless_lock = SP_UNLOCKED; + /* Systimer HAL layer object */ static systimer_hal_context_t systimer_hal; @@ -126,10 +128,10 @@ uint32_t up_get_idletime(void) uint64_t counter; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp_tickless_lock); if (!g_timer_started) { - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp_tickless_lock, flags); return 0; } @@ -147,7 +149,7 @@ uint32_t up_get_idletime(void) us = 0; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp_tickless_lock, flags); return us; } @@ -172,12 +174,12 @@ void up_step_idletime(uint32_t idletime_us) DEBUGASSERT(g_timer_started); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp_tickless_lock); systimer_hal_counter_value_advance(&systimer_hal, SYSTIMER_COUNTER_OS_TICK, idletime_us); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp_tickless_lock, flags); } /**************************************************************************** @@ -216,13 +218,13 @@ void up_step_idletime(uint32_t idletime_us) int IRAM_ATTR up_timer_gettime(struct timespec *ts) { uint64_t time_us; - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_esp_tickless_lock); time_us = systimer_hal_get_time(&systimer_hal, SYSTIMER_COUNTER_OS_TICK); ts->tv_sec = time_us / USEC_PER_SEC; ts->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp_tickless_lock, flags); return OK; } @@ -267,7 +269,7 @@ int IRAM_ATTR up_timer_cancel(struct timespec *ts) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp_tickless_lock); if (ts != NULL) { @@ -314,7 +316,7 @@ int IRAM_ATTR up_timer_cancel(struct timespec *ts) systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp_tickless_lock, flags); return OK; } @@ -350,7 +352,7 @@ int IRAM_ATTR up_timer_start(const struct timespec *ts) uint64_t alarm_ticks; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp_tickless_lock); if (g_timer_started) { @@ -375,7 +377,7 @@ int IRAM_ATTR up_timer_start(const struct timespec *ts) g_timer_started = true; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp_tickless_lock, flags); return OK; } diff --git a/arch/risc-v/src/common/riscv_modifyreg32.c b/arch/risc-v/src/common/riscv_modifyreg32.c index 478351764e96b..93b5d27712a7e 100644 --- a/arch/risc-v/src/common/riscv_modifyreg32.c +++ b/arch/risc-v/src/common/riscv_modifyreg32.c @@ -33,6 +33,12 @@ #include "riscv_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -50,10 +56,10 @@ void modifyreg32(uintreg_t addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c index b3279ee15edde..14bbcab76aba8 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c @@ -76,6 +76,14 @@ #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static spinlock_t g_esp32c3_idle_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -94,7 +102,7 @@ static void up_idlepm(void) irqstate_t flags; #ifdef CONFIG_ESP32C3_AUTO_SLEEP - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp32c3_idle_lock); if (esp32c3_pm_lockstatus() == 0 && (esp32c3_should_skip_light_sleep() == false)) { @@ -138,7 +146,7 @@ static void up_idlepm(void) } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp32c3_idle_lock, flags); #else /* CONFIG_ESP32C3_AUTO_SLEEP */ static enum pm_state_e oldstate = PM_NORMAL; enum pm_state_e newstate; @@ -152,7 +160,7 @@ static void up_idlepm(void) if (newstate != oldstate) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp32c3_idle_lock); /* Perform board-specific, state-dependent logic here */ @@ -174,7 +182,7 @@ static void up_idlepm(void) oldstate = newstate; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp32c3_idle_lock, flags); /* MCU-specific power management logic */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c index 69aae3de8388a..a7cf7f1cb7dcc 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c @@ -79,6 +79,7 @@ struct esp32c3_uart_s g_uart0_config = .txsig = U0TXD_OUT_IDX, .rxpin = CONFIG_ESP32C3_UART0_RXPIN, .rxsig = U0RXD_IN_IDX, + .lock = SP_UNLOCKED, #ifdef CONFIG_SERIAL_IFLOWCONTROL .rtspin = CONFIG_ESP32C3_UART0_RTSPIN, .rtssig = U0RTS_OUT_IDX, @@ -118,6 +119,7 @@ struct esp32c3_uart_s g_uart1_config = .txsig = U1TXD_OUT_IDX, .rxpin = CONFIG_ESP32C3_UART1_RXPIN, .rxsig = U1RXD_IN_IDX, + .lock = SP_UNLOCKED, #ifdef CONFIG_SERIAL_IFLOWCONTROL .rtspin = CONFIG_ESP32C3_UART1_RTSPIN, .rtssig = U1RTS_OUT_IDX, @@ -708,12 +710,12 @@ void esp32c3_lowputc_enable_sysclk(const struct esp32c3_uart_s *priv) * ****************************************************************************/ -void esp32c3_lowputc_disable_all_uart_int(const struct esp32c3_uart_s *priv, +void esp32c3_lowputc_disable_all_uart_int(struct esp32c3_uart_s *priv, uint32_t *current_status) { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (current_status != NULL) { @@ -730,7 +732,7 @@ void esp32c3_lowputc_disable_all_uart_int(const struct esp32c3_uart_s *priv, putreg32(0xffffffff, UART_INT_CLR_REG(priv->id)); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h index e91098072ce53..3fcb612682d11 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -102,6 +103,7 @@ struct esp32c3_uart_s uint8_t txsig; /* TX signal */ uint8_t rxpin; /* RX pin */ uint8_t rxsig; /* RX signal */ + spinlock_t lock; /* Spinlock */ #ifdef CONFIG_SERIAL_IFLOWCONTROL uint8_t rtspin; /* RTS pin number */ uint8_t rtssig; /* RTS signal */ @@ -433,7 +435,7 @@ void esp32c3_lowputc_enable_sysclk(const struct esp32c3_uart_s *priv); * ****************************************************************************/ -void esp32c3_lowputc_disable_all_uart_int(const struct esp32c3_uart_s *priv, +void esp32c3_lowputc_disable_all_uart_int(struct esp32c3_uart_s *priv, uint32_t *current_status); /**************************************************************************** diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c index 643310d551ca4..41d8105c5a3f7 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c @@ -63,6 +63,7 @@ struct esp32c3_lowerhalf_s */ const struct rtc_ops_s *ops; + spinlock_t lock; #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ @@ -118,6 +119,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct esp32c3_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .lock = SP_UNLOCKED, }; /**************************************************************************** @@ -378,6 +380,7 @@ static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { + struct esp32c3_lowerhalf_s *priv = (struct esp32c3_lowerhalf_s *)lower; struct lower_setalarm_s setalarm; time_t seconds; int ret = -EINVAL; @@ -389,7 +392,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, if (alarminfo->reltime > 0) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); seconds = alarminfo->reltime; gmtime_r(&seconds, (struct tm *)&setalarm.time); @@ -401,7 +404,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, setalarm.priv = alarminfo->priv; ret = rtc_lh_setalarm(lower, &setalarm); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } return ret; @@ -468,6 +471,7 @@ static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { + struct esp32c3_lowerhalf_s *priv = (struct esp32c3_lowerhalf_s *)lower; struct timespec ts; int ret; irqstate_t flags; @@ -476,13 +480,13 @@ static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && (alarminfo->id < RTC_ALARM_LAST)); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = up_rtc_rdalarm(&ts, alarminfo->id); localtime_r((const time_t *)&ts.tv_sec, (struct tm *)alarminfo->time); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } diff --git a/arch/risc-v/src/fe310/fe310_gpio.c b/arch/risc-v/src/fe310/fe310_gpio.c index 0e74230294293..089c0bf9b335b 100644 --- a/arch/risc-v/src/fe310/fe310_gpio.c +++ b/arch/risc-v/src/fe310/fe310_gpio.c @@ -38,6 +38,12 @@ #include "fe310_gpio.h" #include "fe310_memorymap.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_fe310_gpio_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -147,7 +153,7 @@ int fe310_gpio_config(uint16_t gpiocfg) uint32_t pin = fe310_gpio_getpin(gpiocfg); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_fe310_gpio_lock); /* Disable IOF for the pin to be used as GPIO */ @@ -182,7 +188,7 @@ int fe310_gpio_config(uint16_t gpiocfg) break; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_fe310_gpio_lock, flags); return ret; } diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c index d8bca3a6a0956..fa74c65ff8337 100644 --- a/arch/risc-v/src/fe310/fe310_serial.c +++ b/arch/risc-v/src/fe310/fe310_serial.c @@ -101,6 +101,7 @@ struct up_dev_s uint32_t baud; /* Configured baud */ uint8_t irq; /* IRQ associated with this UART */ uint8_t im; /* Interrupt mask state */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -167,6 +168,7 @@ static struct up_dev_s g_uart0priv = .uartbase = FE310_UART0_BASE, .baud = CONFIG_UART0_BAUD, .irq = FE310_IRQ_UART0, + .lock = SP_UNLOCKED }; static uart_dev_t g_uart0port = @@ -217,12 +219,12 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); priv->im = im; up_serialout(priv, UART_IE_OFFSET, im); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -231,7 +233,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); /* Return the current interrupt mask value */ @@ -244,7 +246,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IE_OFFSET, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/hpm6750/hpm6750_serial.c b/arch/risc-v/src/hpm6750/hpm6750_serial.c index 0ab37706fb544..7ceb953417c16 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_serial.c +++ b/arch/risc-v/src/hpm6750/hpm6750_serial.c @@ -101,6 +101,7 @@ struct up_dev_s uint32_t uartbase; /* Base address of UART registers */ uint32_t irq; /* IRQ associated with this UART */ uint32_t im; /* Interrupt mask state */ + spinlock_t lock; /* Spinlock */ uart_config_t config; /* Uart config */ }; @@ -158,6 +159,7 @@ static struct up_dev_s g_uart0priv = .uartbase = HPM6750_UART0_BASE, .irq = HPM6750_IRQ_UART0, .im = 0, + .lock = SP_UNLOCKED, .config = { .src_freq_in_hz = 24000000, @@ -236,12 +238,12 @@ static void up_serialmodfiy(struct up_dev_s *priv, int offset, static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); priv->im = im; up_serialout(priv, UART_IER_OFFSET, im); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -250,7 +252,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); /* Return the current interrupt mask value */ @@ -263,7 +265,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IER_OFFSET, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/k210/k210_serial.c b/arch/risc-v/src/k210/k210_serial.c index 4ff4ebb31d411..e229dafb978ef 100644 --- a/arch/risc-v/src/k210/k210_serial.c +++ b/arch/risc-v/src/k210/k210_serial.c @@ -101,6 +101,7 @@ struct up_dev_s uint32_t baud; /* Configured baud */ uint8_t irq; /* IRQ associated with this UART */ uint8_t im; /* Interrupt mask state */ + spinlock_t lock; /* Spinllock */ }; /**************************************************************************** @@ -167,6 +168,7 @@ static struct up_dev_s g_uart0priv = .uartbase = K210_UART0_BASE, .baud = CONFIG_UART0_BAUD, .irq = K210_IRQ_UART0, + .lock = SP_UNLOCKED }; static uart_dev_t g_uart0port = @@ -217,12 +219,12 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); priv->im = im; up_serialout(priv, UART_IE_OFFSET, im); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -231,7 +233,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); /* Return the current interrupt mask value */ @@ -244,7 +246,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IE_OFFSET, 0); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/litex/litex_emac.c b/arch/risc-v/src/litex/litex_emac.c index 6b402057af842..f180556b38738 100644 --- a/arch/risc-v/src/litex/litex_emac.c +++ b/arch/risc-v/src/litex/litex_emac.c @@ -169,6 +169,7 @@ struct litex_emac_s uint8_t phyaddr; /* PHY address (pre-defined by pins on reset) */ uint8_t txslot; + spinlock_t lock; }; /**************************************************************************** @@ -511,7 +512,7 @@ static int litex_transmit(struct litex_emac_s *priv) /* Make the following operations atomic */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); /* Now start transmission */ @@ -528,7 +529,7 @@ static int litex_transmit(struct litex_emac_s *priv) wd_start(&priv->txtimeout, LITEX_TXTIMEOUT, litex_txtimeout_expiry, (wdparm_t)priv); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return OK; } @@ -1524,6 +1525,8 @@ static void litex_ethinitialize(void) return; } + spin_lock_init(&priv->lock); + nerr("ERROR: netdev_register() failed: %d\n", ret); } diff --git a/arch/risc-v/src/mpfs/mpfs_coremmc.c b/arch/risc-v/src/mpfs/mpfs_coremmc.c index 457e614c3ea92..0fe32a282686b 100644 --- a/arch/risc-v/src/mpfs/mpfs_coremmc.c +++ b/arch/risc-v/src/mpfs/mpfs_coremmc.c @@ -214,6 +214,8 @@ static void mpfs_callback(void *arg); * Private Data ****************************************************************************/ +static spinlock_t g_mpfs_modifyreg_lock = SP_UNLOCKED; + struct mpfs_dev_s g_coremmc_dev = { .dev = @@ -282,12 +284,12 @@ static void mpfs_modifyreg8(uintptr_t addr, uint8_t clearbits, irqstate_t flags; uint8_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_mpfs_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_mpfs_modifyreg_lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/mpfs/mpfs_usb.c b/arch/risc-v/src/mpfs/mpfs_usb.c index abd6b30b49996..361f09d8c3cc7 100644 --- a/arch/risc-v/src/mpfs/mpfs_usb.c +++ b/arch/risc-v/src/mpfs/mpfs_usb.c @@ -224,6 +224,8 @@ static void mpfs_epset_reset(struct mpfs_usbdev_s *priv, uint16_t epset); * Private Data ****************************************************************************/ +static spinlock_t g_mpfs_modifyreg_lock = SP_UNLOCKED; + static struct mpfs_usbdev_s g_usbd; static uint8_t g_clkrefs; @@ -297,12 +299,12 @@ static void mpfs_modifyreg16(uintptr_t addr, uint16_t clearbits, DEBUGASSERT((addr >= MPFS_USB_BASE) && addr < (MPFS_USB_BASE + MPFS_USB_REG_MAX)); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_mpfs_modifyreg_lock); regval = getreg16(addr); regval &= ~clearbits; regval |= setbits; putreg16(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_mpfs_modifyreg_lock, flags); } /**************************************************************************** @@ -331,12 +333,12 @@ static void mpfs_modifyreg8(uintptr_t addr, uint8_t clearbits, DEBUGASSERT((addr >= MPFS_USB_BASE) && addr < (MPFS_USB_BASE + MPFS_USB_REG_MAX)); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_mpfs_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_mpfs_modifyreg_lock, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/rv32m1/rv32m1_serial.c b/arch/risc-v/src/rv32m1/rv32m1_serial.c index 9404d2da2f061..62783dd0dd288 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_serial.c +++ b/arch/risc-v/src/rv32m1/rv32m1_serial.c @@ -119,6 +119,7 @@ struct up_dev_s const uintptr_t pcc; /* Address of UART PCC clock gate */ const uint32_t tx_gpio; /* LPUART TX GPIO pin configuration */ const uint32_t rx_gpio; /* LPUART RX GPIO pin configuration */ + spinlock_t lock; /* Spinlock */ uint32_t baud; /* Configured baud */ uint16_t irq; /* IRQ associated with this UART */ }; @@ -188,6 +189,7 @@ static struct up_dev_s g_uart0priv = .pcc = RV32M1_PCC_LPUART0, .tx_gpio = GPIO_LPUART0_TX, .rx_gpio = GPIO_LPUART0_RX, + .lock = SP_UNLOCKED, .baud = CONFIG_LPUART0_BAUD, .irq = RV32M1_IRQ_LPUART0, }; @@ -223,6 +225,7 @@ static struct up_dev_s g_uart1priv = .pcc = RV32M1_PCC_LPUART1, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, + .lock = SP_UNLOCKED, .baud = CONFIG_LPUART1_BAUD, .irq = RV32M1_IRQ_LPUART1, }; @@ -258,6 +261,7 @@ static struct up_dev_s g_uart2priv = .pcc = RV32M1_PCC_LPUART2, .tx_gpio = GPIO_LPUART2_TX, .rx_gpio = GPIO_LPUART2_RX, + .lock = SP_UNLOCKED, .baud = CONFIG_LPUART2_BAUD, .irq = RV32M1_IRQ_LPUART2, }; @@ -293,6 +297,7 @@ static struct up_dev_s g_uart3priv = .pcc = RV32M1_PCC_LPUART3, .tx_gpio = GPIO_LPUART3_TX, .rx_gpio = GPIO_LPUART3_RX, + .lock = SP_UNLOCKED, .baud = CONFIG_LPUART3_BAUD, .irq = RV32M1_IRQ_LPUART3, }; @@ -346,11 +351,11 @@ static void up_putreg(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint32_t im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, im); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -359,7 +364,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint32_t im) static void up_disableuartint(struct up_dev_s *priv, uint32_t *im) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); uint32_t regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); /* Return the current interrupt mask value */ @@ -374,7 +379,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint32_t *im) regval &= ~(LPUART_CTRL_TCIE | LPUART_CTRL_TIE | LPUART_CTRL_RIE); up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/sparc/src/bm3803/bm3803-serial.c b/arch/sparc/src/bm3803/bm3803-serial.c index 53585c4d424cc..cf6f2719ab760 100644 --- a/arch/sparc/src/bm3803/bm3803-serial.c +++ b/arch/sparc/src/bm3803/bm3803-serial.c @@ -156,6 +156,7 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (5, 6, 7 or 8) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -235,6 +236,7 @@ static struct up_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart1port = @@ -265,6 +267,7 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart2port = @@ -295,6 +298,7 @@ static struct up_dev_s g_uart3priv = .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, .stopbits2 = CONFIG_UART3_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart3port = @@ -354,18 +358,24 @@ static inline void up_setuartint(struct up_dev_s *priv) * Name: up_restoreuartint ****************************************************************************/ +static void up_restoreuartint_nolock(struct uart_dev_s *dev, uint8_t im) +{ + up_rxint(dev, RX_ENABLED(im)); + up_txint(dev, TX_ENABLED(im)); +} + static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) { + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; /* Re-enable/re-disable interrupts corresponding to the state of bits * in im */ - flags = spin_lock_irqsave(NULL); - up_rxint(dev, RX_ENABLED(im)); - up_txint(dev, TX_ENABLED(im)); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + up_restoreuartint_nolock(dev, im); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -377,14 +387,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (im) { *im = priv->im; } - up_restoreuartint(dev, 0); - spin_unlock_irqrestore(NULL, flags); + up_restoreuartint_nolock(dev, 0); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/sparc/src/bm3823/bm3823-serial.c b/arch/sparc/src/bm3823/bm3823-serial.c index 5a7f9b008dc65..a7942c4232aea 100644 --- a/arch/sparc/src/bm3823/bm3823-serial.c +++ b/arch/sparc/src/bm3823/bm3823-serial.c @@ -154,6 +154,7 @@ struct up_dev_s uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (5, 6, 7 or 8) */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + spinlock_t lock; /* Spinlock */ }; /**************************************************************************** @@ -232,6 +233,7 @@ static struct up_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart1port = @@ -262,6 +264,7 @@ static struct up_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart2port = @@ -292,6 +295,7 @@ static struct up_dev_s g_uart3priv = .parity = CONFIG_UART3_PARITY, .bits = CONFIG_UART3_BITS, .stopbits2 = CONFIG_UART3_2STOP, + .lock = SP_UNLOCKED, }; static uart_dev_t g_uart3port = @@ -355,18 +359,24 @@ static inline void up_setuartint(struct up_dev_s *priv) * Name: up_restoreuartint ****************************************************************************/ +static void up_restoreuartint_nolock(struct uart_dev_s *dev, uint8_t im) +{ + up_rxint(dev, RX_ENABLED(im)); + up_txint(dev, TX_ENABLED(im)); +} + static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) { + struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; /* Re-enable/re-disable interrupts corresponding to the state of bits in * im */ - flags = spin_lock_irqsave(NULL); - up_rxint(dev, RX_ENABLED(im)); - up_txint(dev, TX_ENABLED(im)); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + up_restoreuartint_nolock(dev, im); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -378,14 +388,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (im) { *im = priv->im; } - up_restoreuartint(dev, 0); - spin_unlock_irqrestore(NULL, flags); + up_restoreuartint_nolock(dev, 0); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/sparc/src/common/sparc_modifyreg32.c b/arch/sparc/src/common/sparc_modifyreg32.c index 899d06670e4a0..9e42428cd8262 100644 --- a/arch/sparc/src/common/sparc_modifyreg32.c +++ b/arch/sparc/src/common/sparc_modifyreg32.c @@ -42,6 +42,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,11 +65,11 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/sparc/src/common/sparc_modifyreg8.c b/arch/sparc/src/common/sparc_modifyreg8.c index 3b5d6b36951a1..a91cd271f8671 100644 --- a/arch/sparc/src/common/sparc_modifyreg8.c +++ b/arch/sparc/src/common/sparc_modifyreg8.c @@ -42,6 +42,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,11 +65,11 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/x86/src/common/x86_modifyreg32.c b/arch/x86/src/common/x86_modifyreg32.c index 2f4f30935c0cb..8b4b61d5a3e19 100644 --- a/arch/x86/src/common/x86_modifyreg32.c +++ b/arch/x86/src/common/x86_modifyreg32.c @@ -31,6 +31,7 @@ #include #include +#include #include "x86_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32((uint16_t)addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, (uint16_t)addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/x86/src/common/x86_modifyreg8.c b/arch/x86/src/common/x86_modifyreg8.c index 03d1169fed421..2145e72e29d68 100644 --- a/arch/x86/src/common/x86_modifyreg8.c +++ b/arch/x86/src/common/x86_modifyreg8.c @@ -31,6 +31,7 @@ #include #include +#include #include "x86_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8((uint16_t)addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, (uint16_t)addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/x86_64/src/common/x86_64_modifyreg32.c b/arch/x86_64/src/common/x86_64_modifyreg32.c index 44427620f1f4f..c1e182a7e522b 100644 --- a/arch/x86_64/src/common/x86_64_modifyreg32.c +++ b/arch/x86_64/src/common/x86_64_modifyreg32.c @@ -31,6 +31,7 @@ #include #include +#include #include "x86_64_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32((uint16_t)addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, (uint16_t)addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/x86_64/src/common/x86_64_modifyreg8.c b/arch/x86_64/src/common/x86_64_modifyreg8.c index 9593752ac6bed..0970eb3f6e22c 100644 --- a/arch/x86_64/src/common/x86_64_modifyreg8.c +++ b/arch/x86_64/src/common/x86_64_modifyreg8.c @@ -31,6 +31,7 @@ #include #include +#include #include "x86_64_internal.h" @@ -42,6 +43,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -63,10 +66,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8((uint16_t)addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, (uint16_t)addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/xtensa/src/common/xtensa_modifyreg32.c b/arch/xtensa/src/common/xtensa_modifyreg32.c index 11028c1c533f2..6ad6b235fe4b5 100644 --- a/arch/xtensa/src/common/xtensa_modifyreg32.c +++ b/arch/xtensa/src/common/xtensa_modifyreg32.c @@ -35,6 +35,12 @@ #include "xtensa.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -52,10 +58,10 @@ void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) irqstate_t flags; uint32_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg32(addr); regval &= ~clearbits; regval |= setbits; putreg32(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/xtensa/src/common/xtensa_modifyreg8.c b/arch/xtensa/src/common/xtensa_modifyreg8.c index 79de96709968b..dd9c0c1df91ea 100644 --- a/arch/xtensa/src/common/xtensa_modifyreg8.c +++ b/arch/xtensa/src/common/xtensa_modifyreg8.c @@ -35,6 +35,12 @@ #include "xtensa.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -52,10 +58,10 @@ void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = getreg8(addr); regval &= ~clearbits; regval |= setbits; putreg8(regval, addr); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/xtensa/src/esp32/esp32_himem.c b/arch/xtensa/src/esp32/esp32_himem.c index 1b2347f8795d2..07590b87b0ed8 100644 --- a/arch/xtensa/src/esp32/esp32_himem.c +++ b/arch/xtensa/src/esp32/esp32_himem.c @@ -126,6 +126,7 @@ typedef struct unsigned int ram_block: 16; } rangeblock_t; +static spinlock_t g_descriptor_lock = SP_UNLOCKED; static ramblock_t *g_ram_descriptor = NULL; static rangeblock_t *g_range_descriptor = NULL; static int g_ramblockcnt = 0; @@ -325,11 +326,11 @@ int esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out) goto nomem; } - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); ok = allocate_blocks(blocks, r->block); - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); if (!ok) { goto nomem; @@ -365,13 +366,13 @@ int esp_himem_free(esp_himem_handle_t handle) /* Mark blocks as free */ - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < handle->block_ct; i++) { g_ram_descriptor[handle->block[i]].is_alloced = false; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); /* Free handle */ @@ -407,7 +408,7 @@ int esp_himem_alloc_map_range(size_t size, r->block_start = -1; start_free = 0; - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < g_rangeblockcnt; i++) { @@ -431,10 +432,11 @@ int esp_himem_alloc_map_range(size_t size, if (r->block_start == -1) { + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); + /* Couldn't find enough free blocks */ kmm_free(r); - spin_unlock_irqrestore(NULL, spinlock_flags); return -ENOMEM; } @@ -445,7 +447,7 @@ int esp_himem_alloc_map_range(size_t size, g_range_descriptor[r->block_start + i].is_alloced = 1; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); /* All done. */ @@ -474,14 +476,14 @@ int esp_himem_free_map_range(esp_himem_rangehandle_t handle) /* We should be good to free this. Mark blocks as free. */ - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < handle->block_ct; i++) { g_range_descriptor[i + handle->block_start].is_alloced = 0; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); kmm_free(handle); return OK; } @@ -537,7 +539,7 @@ int esp_himem_map(esp_himem_handle_t handle, /* Map and mark as mapped */ - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < blockcount; i++) { @@ -548,7 +550,7 @@ int esp_himem_map(esp_himem_handle_t handle, handle->block[i + ram_block]; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); for (i = 0; i < blockcount; i++) { @@ -589,7 +591,7 @@ int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, HIMEM_CHECK(range_block + blockcount > range->block_ct, "range out of bounds for handle", -EINVAL); - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < blockcount; i++) { @@ -602,7 +604,7 @@ int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, } esp_spiram_writeback_cache(); - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); return OK; } diff --git a/arch/xtensa/src/esp32/esp32_idle.c b/arch/xtensa/src/esp32/esp32_idle.c index d5e85f7f430d3..d2e3c1f5a4a07 100644 --- a/arch/xtensa/src/esp32/esp32_idle.c +++ b/arch/xtensa/src/esp32/esp32_idle.c @@ -89,6 +89,13 @@ #define EXPECTED_IDLE_TIME_US (800) #define EARLY_WAKEUP_US (200) +#endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static spinlock_t g_esp32_idle_lock = SP_UNLOCKED; #endif /**************************************************************************** @@ -109,7 +116,7 @@ static void esp32_idlepm(void) irqstate_t flags; #ifdef CONFIG_ESP32_AUTO_SLEEP - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp32_idle_lock); if (esp32_pm_lockstatus() == 0) { uint64_t os_start_us; @@ -155,7 +162,7 @@ static void esp32_idlepm(void) } } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp32_idle_lock, flags); #else /* CONFIG_ESP32_AUTO_SLEEP */ static enum pm_state_e oldstate = PM_NORMAL; enum pm_state_e newstate; @@ -169,7 +176,7 @@ static void esp32_idlepm(void) if (newstate != oldstate) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp32_idle_lock); /* Perform board-specific, state-dependent logic here */ @@ -191,7 +198,7 @@ static void esp32_idlepm(void) oldstate = newstate; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp32_idle_lock, flags); /* MCU-specific power management logic */ diff --git a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c index af07906fea758..cebe6b5a0b8a5 100644 --- a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c @@ -61,6 +61,7 @@ struct esp32_lowerhalf_s */ const struct rtc_ops_s *ops; + spinlock_t lock; #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ @@ -116,6 +117,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct esp32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .lock = SP_UNLOCKED }; /**************************************************************************** @@ -376,6 +378,7 @@ static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { + struct esp32_lowerhalf_s *priv = (struct esp32_lowerhalf_s *)lower; struct lower_setalarm_s setalarm; time_t seconds; int ret = -EINVAL; @@ -387,7 +390,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, if (alarminfo->reltime > 0) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); seconds = alarminfo->reltime; gmtime_r(&seconds, (struct tm *)&setalarm.time); @@ -399,7 +402,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, setalarm.priv = alarminfo->priv; ret = rtc_lh_setalarm(lower, &setalarm); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } return ret; @@ -466,6 +469,7 @@ static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { + struct esp32_lowerhalf_s *priv = (struct esp32_lowerhalf_s *)lower; struct timespec ts; int ret; irqstate_t flags; @@ -474,13 +478,13 @@ static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && (alarminfo->id < RTC_ALARM_LAST)); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = up_rtc_rdalarm(&ts, alarminfo->id); localtime_r((const time_t *)&ts.tv_sec, (struct tm *)alarminfo->time); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } diff --git a/arch/xtensa/src/esp32s2/esp32s2_idle.c b/arch/xtensa/src/esp32s2/esp32s2_idle.c index a37abca02aadb..76b7dce18bbac 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_idle.c +++ b/arch/xtensa/src/esp32s2/esp32s2_idle.c @@ -58,6 +58,14 @@ #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static spinlock_t g_esp32s2_idle_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -86,7 +94,7 @@ static void up_idlepm(void) if (newstate != oldstate) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp32s2_idle_lock); /* Perform board-specific, state-dependent logic here */ @@ -108,7 +116,7 @@ static void up_idlepm(void) oldstate = newstate; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp32s2_idle_lock, flags); /* MCU-specific power management logic */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c index f71acb90b16dc..a9a452e7e5ae6 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c @@ -99,6 +99,7 @@ struct esp32s2_uart_s g_uart0_config = .rs485_dir_polarity = true, #endif #endif + .lock = SP_UNLOCKED }; #endif /* CONFIG_ESP32S2_UART0 */ @@ -146,6 +147,7 @@ struct esp32s2_uart_s g_uart1_config = .rs485_dir_polarity = true, #endif #endif + .lock = SP_UNLOCKED }; #endif /* CONFIG_ESP32S2_UART1 */ @@ -654,7 +656,7 @@ void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, { irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); if (current_status != NULL) { @@ -671,7 +673,7 @@ void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->id)); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.h b/arch/xtensa/src/esp32s2/esp32s2_lowputc.h index 68260f42dc502..c36357196fe0f 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_lowputc.h +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.h @@ -106,6 +106,7 @@ struct esp32s2_uart_s uint8_t rs485_dir_gpio; /* UART RS-485 DIR GPIO pin cfg */ bool rs485_dir_polarity; /* UART RS-485 DIR TXEN polarity */ #endif + spinlock_t lock; /* Spinlock */ }; extern struct esp32s2_uart_s g_uart0_config; diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c index 4faf215408084..03a668ce17546 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c @@ -61,6 +61,7 @@ struct esp32s2_lowerhalf_s */ const struct rtc_ops_s *ops; + spinlock_t lock; #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ @@ -115,6 +116,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct esp32s2_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .lock = SP_UNLOCKED, }; /**************************************************************************** @@ -375,6 +377,7 @@ static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { + struct esp32s2_lowerhalf_s *priv = (struct esp32s2_lowerhalf_s *)lower; struct lower_setalarm_s setalarm; time_t seconds; int ret = -EINVAL; @@ -386,7 +389,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, if (alarminfo->reltime > 0) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); seconds = alarminfo->reltime; gmtime_r(&seconds, (struct tm *)&setalarm.time); @@ -398,7 +401,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, setalarm.priv = alarminfo->priv; ret = rtc_lh_setalarm(lower, &setalarm); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } return ret; @@ -465,6 +468,7 @@ static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { + struct esp32s2_lowerhalf_s *priv = (struct esp32s2_lowerhalf_s *)lower; struct timespec ts; int ret; irqstate_t flags; @@ -473,13 +477,13 @@ static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && (alarminfo->id < RTC_ALARM_LAST)); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = up_rtc_rdalarm(&ts, alarminfo->id); localtime_r((const time_t *)&ts.tv_sec, (struct tm *)alarminfo->time); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } diff --git a/arch/xtensa/src/esp32s3/esp32s3_himem.c b/arch/xtensa/src/esp32s3/esp32s3_himem.c index dbc246dad3f55..7b84890bc5541 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_himem.c +++ b/arch/xtensa/src/esp32s3/esp32s3_himem.c @@ -148,6 +148,7 @@ static int himem_ioctl(struct file *filep, int cmd, * Private Data ****************************************************************************/ +static spinlock_t g_descriptor_lock = SP_UNLOCKED; static ramblock_t *g_ram_descriptor = NULL; static rangeblock_t *g_range_descriptor = NULL; static int g_ramblockcnt = 0; @@ -626,11 +627,11 @@ int esp_himem_alloc(size_t size, esp_himem_handle_t *handle_out) goto nomem; } - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); ok = allocate_blocks(blocks, r->block); - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); if (!ok) { goto nomem; @@ -682,13 +683,13 @@ int esp_himem_free(esp_himem_handle_t handle) /* Mark blocks as free */ - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < handle->block_ct; i++) { g_ram_descriptor[handle->block[i]].is_alloced = false; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); /* Free handle */ @@ -742,7 +743,7 @@ int esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t r->block_start = -1; start_free = 0; - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < g_rangeblockcnt; i++) { @@ -766,10 +767,11 @@ int esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t if (r->block_start == -1) { + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); + /* Couldn't find enough free blocks */ kmm_free(r); - spin_unlock_irqrestore(NULL, spinlock_flags); return -ENOMEM; } @@ -780,7 +782,7 @@ int esp_himem_alloc_map_range(size_t size, esp_himem_rangehandle_t g_range_descriptor[r->block_start + i].is_alloced = 1; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); /* All done. */ @@ -826,14 +828,14 @@ int esp_himem_free_map_range(esp_himem_rangehandle_t handle) /* We should be good to free this. Mark blocks as free. */ - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < handle->block_ct; i++) { g_range_descriptor[i + handle->block_start].is_alloced = 0; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); kmm_free(handle); return OK; } @@ -917,7 +919,7 @@ int esp_himem_map(esp_himem_handle_t handle, /* Map and mark as mapped */ - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < blockcount; i++) { @@ -928,7 +930,7 @@ int esp_himem_map(esp_himem_handle_t handle, handle->block[i + ram_block]; } - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); for (i = 0; i < blockcount; i++) { virt_bank = himem_mmu_start + range->block_start + i + range_block; @@ -983,7 +985,7 @@ int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len) HIMEM_CHECK(range_block + blockcount > range->block_ct, "range out of bounds for handle", -EINVAL); - spinlock_flags = spin_lock_irqsave(NULL); + spinlock_flags = spin_lock_irqsave(&g_descriptor_lock); for (i = 0; i < blockcount; i++) { @@ -996,7 +998,7 @@ int esp_himem_unmap(esp_himem_rangehandle_t range, void *ptr, size_t len) } esp_spiram_writeback_cache(); - spin_unlock_irqrestore(NULL, spinlock_flags); + spin_unlock_irqrestore(&g_descriptor_lock, spinlock_flags); return OK; } diff --git a/arch/xtensa/src/esp32s3/esp32s3_idle.c b/arch/xtensa/src/esp32s3/esp32s3_idle.c index 305dbb31dedbd..8f59ce567a23e 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_idle.c +++ b/arch/xtensa/src/esp32s3/esp32s3_idle.c @@ -63,6 +63,14 @@ #endif +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static spinlock_t g_esp32s3_idle_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -91,7 +99,7 @@ static void up_idlepm(void) if (newstate != oldstate) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_esp32s3_idle_lock); /* Perform board-specific, state-dependent logic here */ @@ -113,7 +121,7 @@ static void up_idlepm(void) oldstate = newstate; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_esp32s3_idle_lock, flags); /* MCU-specific power management logic */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c b/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c index 115b764e2cdf7..483625e492954 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c @@ -61,6 +61,7 @@ struct esp32s3_lowerhalf_s */ const struct rtc_ops_s *ops; + spinlock_t lock; #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ @@ -116,6 +117,7 @@ static const struct rtc_ops_s g_rtc_ops = static struct esp32s3_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, + .lock = SP_UNLOCKED, }; /**************************************************************************** @@ -376,6 +378,7 @@ static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { + struct esp32s3_lowerhalf_s *priv = (struct esp32s3_lowerhalf_s *)lower; struct lower_setalarm_s setalarm; time_t seconds; int ret = -EINVAL; @@ -387,7 +390,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, if (alarminfo->reltime > 0) { - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); seconds = alarminfo->reltime; gmtime_r(&seconds, (struct tm *)&setalarm.time); @@ -399,7 +402,7 @@ static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, setalarm.priv = alarminfo->priv; ret = rtc_lh_setalarm(lower, &setalarm); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } return ret; @@ -466,6 +469,7 @@ static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { + struct esp32s3_lowerhalf_s *priv = (struct esp32s3_lowerhalf_s *)lower; struct timespec ts; int ret; irqstate_t flags; @@ -474,13 +478,13 @@ static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && (alarminfo->id < RTC_ALARM_LAST)); - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = up_rtc_rdalarm(&ts, alarminfo->id); localtime_r((const time_t *)&ts.tv_sec, (struct tm *)alarminfo->time); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index b45ad9dede85b..e432a76bd5e10 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -70,6 +70,7 @@ struct z16f_uart_s uint8_t rxirq; /* RX IRQ associated with this UART */ uint8_t txirq; /* RX IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ + spinlock_t lock; /* */ bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ }; @@ -139,6 +140,7 @@ static struct z16f_uart_s g_uart0priv = Z16F_IRQ_UART0RX, /* rxirq */ Z16F_IRQ_UART0TX, /* txirq */ CONFIG_UART0_PARITY, /* parity */ + SP_UNLOCKED, /* Spinlock */ CONFIG_UART0_2STOP /* stopbits2 */ }; @@ -157,6 +159,7 @@ static struct z16f_uart_s g_uart1priv = Z16F_IRQ_UART1RX, /* rxirq */ Z16F_IRQ_UART1TX, /* txirq */ CONFIG_UART1_PARITY, /* parity */ + SP_UNLOCKED, /* Spinlock */ CONFIG_UART1_2STOP /* stopbits2 */ }; @@ -215,16 +218,16 @@ static uart_dev_t g_uart1port; static uint8_t z16f_disableuartirq(struct uart_dev_s *dev) { struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); uint8_t state = priv->rxenabled ? STATE_RXENABLED : STATE_DISABLED | priv->txenabled ? STATE_TXENABLED : STATE_DISABLED; - z16f_txint(dev, false); - z16f_rxint(dev, false); + z16f_txint_nolock(dev, false); + z16f_rxint_nolock(dev, false); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return state; } @@ -234,12 +237,13 @@ static uint8_t z16f_disableuartirq(struct uart_dev_s *dev) static void z16f_restoreuartirq(struct uart_dev_s *dev, uint8_t state) { - irqstate_t flags = spin_lock_irqsave(NULL); + struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; + irqstate_t flags = spin_lock_irqsave(&priv->lock); - z16f_txint(dev, (state & STATE_TXENABLED) ? true : false); - z16f_rxint(dev, (state & STATE_RXENABLED) ? true : false); + z16f_txint_nolock(dev, (state & STATE_TXENABLED) ? true : false); + z16f_rxint_nolock(dev, (state & STATE_RXENABLED) ? true : false); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -507,10 +511,9 @@ static int z16f_receive(struct uart_dev_s *dev, uint32_t *status) * ****************************************************************************/ -static void z16f_rxint(struct uart_dev_s *dev, bool enable) +static void z16f_rxint_nolock(struct uart_dev_s *dev, bool enable) { - struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; - irqstate_t flags = enter_critical_section(); + struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; if (enable) { @@ -524,7 +527,15 @@ static void z16f_rxint(struct uart_dev_s *dev, bool enable) } priv->rxenabled = enable; - leave_critical_section(flags); +} + +static void z16f_rxint(struct uart_dev_s *dev, bool enable) +{ + struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; + irqstate_t flags = spin_lock_irqsave(&priv->lock); + + z16f_rxint_nolock(dev, enable); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -564,10 +575,9 @@ static void z16f_send(struct uart_dev_s *dev, int ch) * ****************************************************************************/ -static void z16f_txint(struct uart_dev_s *dev, bool enable) +static void z16f_txint_nolock(struct uart_dev_s *dev, bool enable) { - struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; - irqstate_t flags = enter_critical_section(); + struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; if (enable) { @@ -587,7 +597,15 @@ static void z16f_txint(struct uart_dev_s *dev, bool enable) } priv->txenabled = enable; - leave_critical_section(flags); +} + +static void z16f_txint(struct uart_dev_s *dev, bool enable) +{ + struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; + irqstate_t flags = spin_lock_irqsave(&priv->lock); + + z16f_txint_nolock(dev, enable); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/z80/src/z180/z180_modifiyreg8.c b/arch/z80/src/z180/z180_modifiyreg8.c index 282e6592130ba..35a4ca63e780a 100644 --- a/arch/z80/src/z180/z180_modifiyreg8.c +++ b/arch/z80/src/z180/z180_modifiyreg8.c @@ -29,6 +29,7 @@ #include #include +#include #include /**************************************************************************** @@ -39,6 +40,8 @@ * Private Data ****************************************************************************/ +static spinlock_t g_modifyreg_lock = SP_UNLOCKED; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -60,10 +63,10 @@ void modifyreg8(uint16_t addr, uint8_t clearbits, uint8_t setbits) irqstate_t flags; uint8_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_modifyreg_lock); regval = inp(addr); regval &= ~clearbits; regval |= setbits; outp(regval, addr); - leave_critical_section(flags); + spin_unlock_irqrestore(&g_modifyreg_lock, flags); } diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index 09516c209300d..feb63355f43a9 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -70,6 +70,7 @@ struct z8_uart_s uint8_t rxirq; /* RX IRQ associated with this UART */ uint8_t txirq; /* RX IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ + spinlock_t lock; /* Spinlock */ bool stopbits2; /* true: Configure with 2 stop bits * (instead of 1) */ }; @@ -134,6 +135,7 @@ static struct z8_uart_s g_uart0priv = Z8_UART0_RX_IRQ, /* rxirq */ Z8_UART0_TX_IRQ, /* txirq */ CONFIG_UART0_PARITY, /* parity */ + SP_UNLOCKED, /* Spinlock */ CONFIG_UART0_2STOP /* stopbits2 */ }; @@ -179,6 +181,7 @@ static struct z8_uart_s g_uart1priv = Z8_UART1_RX_IRQ, /* rxirq */ Z8_UART1_TX_IRQ, /* txirq */ CONFIG_UART1_PARITY, /* parity */ + SP_UNLOCKED, /* Spinlock */ CONFIG_UART1_2STOP /* stopbits2 */ }; @@ -254,17 +257,17 @@ static inline uint8_t z8_getuart(FAR struct z8_uart_s *priv, uint8_t offset) static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev) { - struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; - irqstate_t flags = spin_lock_irqsave(NULL); - uint8_t state = priv->rxenabled ? - STATE_RXENABLED : STATE_DISABLED | \ - priv->txenabled ? - STATE_TXENABLED : STATE_DISABLED; + struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; + irqstate_t flags = spin_lock_irqsave(&priv->lock); + uint8_t state = priv->rxenabled ? + STATE_RXENABLED : STATE_DISABLED | \ + priv->txenabled ? + STATE_TXENABLED : STATE_DISABLED; - z8_txint(dev, false); - z8_rxint(dev, false); + z8_txint_nolock(dev, false); + z8_rxint_nolock(dev, false); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return state; } @@ -274,12 +277,12 @@ static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev) static void z8_restoreuartirq(FAR struct uart_dev_s *dev, uint8_t state) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&priv->lock); - z8_txint(dev, (state & STATE_TXENABLED) ? true : false); - z8_rxint(dev, (state & STATE_RXENABLED) ? true : false); + z8_txint_nolock(dev, (state & STATE_TXENABLED) ? true : false); + z8_rxint_nolock(dev, (state & STATE_RXENABLED) ? true : false); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -582,10 +585,9 @@ static int z8_receive(FAR struct uart_dev_s *dev, FAR uint32_t *status) * ****************************************************************************/ -static void z8_rxint(FAR struct uart_dev_s *dev, bool enable) +static void z8_rxint_nolock(FAR struct uart_dev_s *dev, bool enable) { - struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; - irqstate_t flags = enter_critical_section(); + struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; if (enable) { @@ -599,7 +601,15 @@ static void z8_rxint(FAR struct uart_dev_s *dev, bool enable) } priv->rxenabled = enable; - leave_critical_section(flags); +} + +static void z8_rxint(FAR struct uart_dev_s *dev, bool enable) +{ + struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; + irqstate_t flags = spin_lock_irqsave(&priv->lock); + + z8_rxint_nolock(dev, enable); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -638,10 +648,9 @@ static void z8_send(FAR struct uart_dev_s *dev, int ch) * ****************************************************************************/ -static void z8_txint(FAR struct uart_dev_s *dev, bool enable) +static void z8_txint_nolock(FAR struct uart_dev_s *dev, bool enable) { - struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; - irqstate_t flags = enter_critical_section(); + struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; if (enable) { @@ -655,7 +664,15 @@ static void z8_txint(FAR struct uart_dev_s *dev, bool enable) } priv->txenabled = enable; - leave_critical_section(flags); +} + +static void z8_txint(FAR struct uart_dev_s *dev, bool enable) +{ + struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; + irqstate_t flags = spin_lock_irqsave(&priv->lock); + + z8_txint_nolock(dev, enable); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/boards/Kconfig b/boards/Kconfig index ccaae55b2fe93..15ed928466d66 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -780,6 +780,16 @@ config ARCH_BOARD_IMXRT1170_EVK This is the board configuration for the port of NuttX to the NXP i.MXRT evaluation kit, MIMXRT1170-EVK. This board features the MIMXRT1176DVMAA MCU. +config ARCH_BOARD_IMX95_EVK + bool "NXP i.MX 95 EVK" + depends on ARCH_CHIP_IMX9_CORTEX_M + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This is the board configuration for the port of NuttX to the NXP i.MXRT + evaluation kit, IMX95-EVK. This board features the IMX95 MCU. + config ARCH_BOARD_LC823450_XGEVK bool "ON Semiconductor LC823450-XGEVK development board" depends on ARCH_CHIP_LC823450 @@ -3345,6 +3355,7 @@ config ARCH_BOARD default "imxrt1060-evk" if ARCH_BOARD_IMXRT1060_EVK default "imxrt1064-evk" if ARCH_BOARD_IMXRT1064_EVK default "imxrt1170-evk" if ARCH_BOARD_IMXRT1170_EVK + default "imx95-evk" if ARCH_BOARD_IMX95_EVK default "kwikstik-k40" if ARCH_BOARD_KWIKSTIK_K40 default "launchxl-cc1310" if ARCH_BOARD_LAUNCHXL_CC1310 default "launchxl-cc1312r1" if ARCH_BOARD_LAUNCHXL_CC1312R1 @@ -3757,6 +3768,9 @@ endif if ARCH_BOARD_IMXRT1170_EVK source "boards/arm/imxrt/imxrt1170-evk/Kconfig" endif +if ARCH_BOARD_IMX95_EVK +source "boards/arm/imx9/imx95-evk/Kconfig" +endif if ARCH_BOARD_TEENSY_4X source "boards/arm/imxrt/teensy-4.x/Kconfig" endif diff --git a/boards/arm/at32/at32f437-mini/src/at32_ethernet.c b/boards/arm/at32/at32f437-mini/src/at32_ethernet.c index 2821c61a4c76e..390598ceb90aa 100644 --- a/boards/arm/at32/at32f437-mini/src/at32_ethernet.c +++ b/boards/arm/at32/at32f437-mini/src/at32_ethernet.c @@ -81,9 +81,8 @@ * Private Data ****************************************************************************/ -static spinlock_t g_ethmac_lock = SP_UNLOCKED; - #ifdef HAVE_NETMONITOR +static spinlock_t g_ethmac_lock = SP_UNLOCKED; static xcpt_t g_ethmac_handler; static void *g_ethmac_arg; #endif diff --git a/boards/arm/imx9/imx95-evk/CMakeLists.txt b/boards/arm/imx9/imx95-evk/CMakeLists.txt new file mode 100644 index 0000000000000..144cb42dffe51 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/CMakeLists.txt @@ -0,0 +1,30 @@ +# ############################################################################## +# boards/arm/imx9/imx95-evk/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) + +if(NOT CONFIG_BUILD_FLAT) + add_subdirectory(kernel) + set_property( + GLOBAL PROPERTY LD_SCRIPT_USER ${CMAKE_CURRENT_LIST_DIR}/scripts/memory.ld + ${CMAKE_CURRENT_LIST_DIR}/scripts/user-space.ld) +endif() diff --git a/boards/arm/imx9/imx95-evk/Kconfig b/boards/arm/imx9/imx95-evk/Kconfig new file mode 100644 index 0000000000000..4d0645a08029d --- /dev/null +++ b/boards/arm/imx9/imx95-evk/Kconfig @@ -0,0 +1,18 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +choice IMX95_CODE_LOCATION + prompt "Code location" + +config IMX95_RUN_FROM_ITCM + bool "Run from Instruction Tightly Coupled Memory (ITCM)" + +config IMX95_RUN_FROM_DDR + bool "Run from SDRAM (DDR)" + +config IMX95_RUN_FROM_FLASH + bool "Run from NOR flash" + +endchoice diff --git a/boards/arm/imx9/imx95-evk/configs/nsh/defconfig b/boards/arm/imx9/imx95-evk/configs/nsh/defconfig new file mode 100644 index 0000000000000..2c4a85e11ab91 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/configs/nsh/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_ARCH_RAMFUNCS is not set +# CONFIG_NDEBUG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="imx95-evk" +CONFIG_ARCH_BOARD_IMX95_EVK=y +CONFIG_ARCH_CHIP="imx9" +CONFIG_ARCH_CHIP_IMX95_M7=y +CONFIG_ARCH_CHIP_IMX9_CORTEX_M=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_ITCM=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=2664 +CONFIG_BUILTIN=y +CONFIG_DEBUG_BUSFAULT=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_HARDFAULT_INFO=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_USAGEFAULT=y +CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_EXAMPLES_CALIB_UDELAY=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_IMX9_LPUART3=y +CONFIG_IMX9_OCRAM_HEAP=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LPUART3_SERIAL_CONSOLE=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_RAM_SIZE=134217728 +CONFIG_RAM_START=0x80000000 +CONFIG_RAW_BINARY=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_NSH=y +CONFIG_TTY_SIGINT=y +CONFIG_TTY_SIGTSTP=y diff --git a/boards/arm/imx9/imx95-evk/configs/rpmsg/defconfig b/boards/arm/imx9/imx95-evk/configs/rpmsg/defconfig new file mode 100644 index 0000000000000..c8bc0374f2bc0 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/configs/rpmsg/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_ARCH_RAMFUNCS is not set +# CONFIG_NDEBUG is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="imx95-evk" +CONFIG_ARCH_BOARD_IMX95_EVK=y +CONFIG_ARCH_CHIP="imx9" +CONFIG_ARCH_CHIP_IMX95_M7=y +CONFIG_ARCH_CHIP_IMX9_CORTEX_M=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARMV7M_ITCM=y +CONFIG_BINFMT_DISABLE=y +CONFIG_BOARD_LOOPSPERMSEC=2664 +CONFIG_BUILTIN=y +CONFIG_DEBUG_BUSFAULT=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_HARDFAULT_ALERT=y +CONFIG_DEBUG_HARDFAULT_INFO=y +CONFIG_DEBUG_IPC=y +CONFIG_DEBUG_IPC_ERROR=y +CONFIG_DEBUG_IPC_WARN=y +CONFIG_DEBUG_RPMSG=y +CONFIG_DEBUG_RPMSG_ERROR=y +CONFIG_DEBUG_RPMSG_WARN=y +CONFIG_DEBUG_SENSORS=y +CONFIG_DEBUG_SENSORS_ERROR=y +CONFIG_DEBUG_SENSORS_INFO=y +CONFIG_DEBUG_SENSORS_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_USAGEFAULT=y +CONFIG_DEBUG_VIRTIO=y +CONFIG_DEBUG_VIRTIO_ERROR=y +CONFIG_DEBUG_VIRTIO_INFO=y +CONFIG_DEBUG_VIRTIO_WARN=y +CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_DEV_RPMSG=y +CONFIG_DEV_SIMPLE_ADDRENV=y +CONFIG_DRIVERS_VIRTIO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_RPMSGFS=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_IMX95_RUN_FROM_DDR=y +CONFIG_IMX9_LPUART3=y +CONFIG_IMX9_MU7=y +CONFIG_IMX9_OCRAM_HEAP=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LPUART3_SERIAL_CONSOLE=y +CONFIG_MM_HEAP_MEMPOOL_THRESHOLD=0 +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_RAM_SIZE=134217728 +CONFIG_RAM_START=0x80000000 +CONFIG_RAW_BINARY=y +CONFIG_RPMSG_LOCAL_CPUNAME="cpuapp" +CONFIG_RPMSG_UART=y +CONFIG_RPTUN=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SENSORS=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=14 +CONFIG_START_MONTH=3 +CONFIG_SYSTEM_CUTERM=y +CONFIG_SYSTEM_CUTERM_DEFAULT_DEVICE="/dev/ttyproxy" +CONFIG_SYSTEM_NSH=y +CONFIG_TTY_SIGINT=y +CONFIG_TTY_SIGTSTP=y diff --git a/boards/arm/imx9/imx95-evk/include/board.h b/boards/arm/imx9/imx95-evk/include/board.h new file mode 100644 index 0000000000000..4b29047bda311 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/include/board.h @@ -0,0 +1,183 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMX9_IMX95_EVK_INCLUDE_BOARD_H +#define __BOARDS_ARM_IMX9_IMX95_EVK_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BOARD_XTAL_FREQUENCY 24000000 + +#define BOARD_CPU_FREQUENCY BOARD_XTAL_FREQUENCY //FIXME + +#define LPUART3_CLK (LPUART3_CLK_ROOT_OSC_24M_CLK | CLOCK_DIV(1)) +#define LPI2C6_CLK (LPI2C6_CLK_ROOT_OSC_24M_CLK | CLOCK_DIV(1)) +#define LPSPI1_CLK (LPSPI1_CLK_ROOT_OSC_24M_CLK | CLOCK_DIV(1)) + +#define FLEXCAN1_CLK (CAN1_CLK_ROOT_SYS_PLL1_DFS1_DIV2_CLK | CLOCK_DIV(5)) + +/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/imxrt_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------------- ------- ------- + * SYMBOL Meaning LED1 LED2 + * GREEN RED + * -------------------- ----------------------------- ------- ------- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt (No change) */ +#define LED_SIGNAL 2 /* In a signal handler (No change) */ +#define LED_ASSERTION 2 /* An assertion failed (No change) */ +#define LED_PANIC 3 /* The system has crashed OFF FLASH */ +#undef LED_IDLE /* Not used (Not used) */ + +/* Default PAD configurations */ + +#define IOMUX_LPI2C_DEFAULT (IOMUXC_PAD_OD_ENABLE | IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6) +#define IOMUX_LPSPI_DEFAULT (IOMUXC_PAD_PU_ON | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6) +#define IOMUX_GPIO_DEFAULT (IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X6) + +/* UART pin muxings */ + +#define MUX_LPUART3_RX IOMUX_CFG(IOMUXC_PAD_GPIO_IO15_LPUART3_RX, 0, IOMUXC_MUX_SION_ON) +#define MUX_LPUART3_TX IOMUX_CFG(IOMUXC_PAD_GPIO_IO14_LPUART3_TX, IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X4, 0) + +/* FLEXIO to PWM pin muxings */ + +/* EVK signals + * GPIO_IO04 -> FLEXIO1_04 + * GPIO_IO05 -> FLEXIO1_05 + * GPIO_IO06 -> FLEXIO1_06 + * GPIO_IO07 -> FLEXIO1_07 + */ + +#define FLEXIO1_PWM0_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) +#define FLEXIO1_PWM1_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) +#define FLEXIO1_PWM2_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) +#define FLEXIO1_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) + +/* LPI2Cs */ + +/* TPM3 ch3 to PWM pin GPIO_IO24 muxing */ + +#define TPM3_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO24_TPM3_CH3, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) + +/* LPI2Cs */ + +#define MUX_LPI2C6_SCL IOMUX_CFG(IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL, IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPI2C6_SDA IOMUX_CFG(IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA, IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON) + +/* I2C reset functionality */ + +#define GPIO_LPI2C1_SCL_RESET (GPIO_PORT1 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) +#define GPIO_LPI2C1_SDA_RESET (GPIO_PORT1 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* LPSPIs */ + +#define MUX_LPSPI1_SCK IOMUX_CFG(IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI1_MOSI IOMUX_CFG(IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI1_MISO IOMUX_CFG(IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) + +/* SPI CS */ + +#define MUX_LPSPI1_CS IOMUX_CFG(IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON) +#define GPIO_LPSPI1_CS (GPIO_PORT1 | GPIO_PIN11 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* FlexCAN */ + +#define GPIO_FLEXCAN1_TX IOMUX_CFG(IOMUXC_PAD_PDM_CLK_CAN1_TX, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON) +#define GPIO_FLEXCAN1_RX IOMUX_CFG(IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON) + +/* Set the PLL clocks as follows: + * + * - OSC24M : 24 MHz + * - ARMPLL_OUT : 1692 MHz + * - DRAMPLL : 933 MHz + * - SYSPLL1 : 4000 MHz + * - SYSPLL_PFD0 : 1000 MHz + * - SYSPLL_PFD1 : 800 MHz + * - SYSPLL_PFD2 : 625 MHz + * - AUDIOPLL_OUT : OFF + * - VIDEOPLL_OUT : OFF + * + * After reset all clock sources (OSCPLL) and root clocks (CLOCK_ROOT) are + * running, but gated (LPCG). + * + * By default, all peripheral root clocks are set to the 24 MHz oscillator. + */ + +#define ARMPLL_CFG PLL_CFG(IMX95_ARMPLL_BASE, false, PLL_PARMS(1, 2, 141, 0, 0)) +#define DRAMPLL_CFG PLL_CFG(IMX95_DRAMPLL_BASE, true, PLL_PARMS(1, 2, 155, 1, 2)) + +#define PLL_CFGS \ + { \ + PLL_CFG(IMX95_SYSPLL_BASE, true, PLL_PARMS(1, 4, 166, 2, 3)), \ + } + +#define PFD_CFGS \ + { \ + PFD_CFG(IMX95_SYSPLL_BASE, 0, PFD_PARMS(4, 0, true)), \ + PFD_CFG(IMX95_SYSPLL_BASE, 1, PFD_PARMS(5, 0, true)), \ + PFD_CFG(IMX95_SYSPLL_BASE, 2, PFD_PARMS(6, 2, true)), \ + } + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_IMX9_IMX95_EVK_INCLUDE_BOARD_H */ diff --git a/boards/arm/imx9/imx95-evk/scripts/Make.defs b/boards/arm/imx9/imx95-evk/scripts/Make.defs new file mode 100644 index 0000000000000..d4591a9eb92a6 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/scripts/Make.defs @@ -0,0 +1,56 @@ +############################################################################ +# boards/arm/imx95/imx95-evk/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileCopyrightText: 2024 NXP +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_IMX95_RUN_FROM_ITCM),y) +LDSCRIPT = itcm.ld +else ifeq ($(CONFIG_IMX95_RUN_FROM_DDR),y) +LDSCRIPT = ddr.ld +else ifeq ($(CONFIG_IMX95_RUN_FROM_FLASH),y) +LDSCRIPT = flash.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) diff --git a/boards/arm/imx9/imx95-evk/scripts/ddr.ld b/boards/arm/imx9/imx95-evk/scripts/ddr.ld new file mode 100644 index 0000000000000..0f77521213ad1 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/scripts/ddr.ld @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/imx95/imx95-evk/scripts/itcm.ld + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* + * Flash controller + * 1) 32 MB of FlexSPI_1 at 0x0200:0000 + * The on-chip SRAM is split in these parts: + * 1) 256Kb of program memory located at 0x0000:0000 + * 2) 256Kb of data memory beginning at the address 0x2000:0000 + * 3) 352Kb of OCRAM beginning at the address 0x2048:0000 + * 4) 4Mb of SDRAM located at 0x9000:0000 + */ + +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x90000000, LENGTH = 0x00000800 + flash (rx) : ORIGIN = 0x90000800, LENGTH = 0x003FF800 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K + ocram (rwx) : ORIGIN = 0x20480000, LENGTH = 352K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.vectors)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) + . = ALIGN(4); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _ram_start = ORIGIN(sram); + _ram_size = LENGTH(sram); + _ram_end = ORIGIN(sram) + LENGTH(sram); + _ocram_start = ORIGIN(ocram); + _ocram_size = LENGTH(ocram); + _ocram_end = ORIGIN(ocram) + LENGTH(ocram); +} diff --git a/boards/arm/imx9/imx95-evk/scripts/flash.ld b/boards/arm/imx9/imx95-evk/scripts/flash.ld new file mode 100644 index 0000000000000..b9e2ca360d8a6 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/scripts/flash.ld @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/imx95/imx95-evk/scripts/itcm.ld + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* + * Flash controller + * 1) 32 MB of FlexSPI_1 at 0x0200:0000 + * The on-chip SRAM is split in these parts: + * 1) 256Kb of program memory located at 0x0000:0000 + * 2) 256Kb of data memory beginning at the address 0x2000:0000 + * 3) 352Kb of OCRAM beginning at the address 0x2048:0000 + * 4) 4Mb of SDRAM located at 0x9000:0000 + */ + +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x02000000, LENGTH = 0x00000800 + flash (rx) : ORIGIN = 0x02000800, LENGTH = 0x01FFF800 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K + ocram (rwx) : ORIGIN = 0x20480000, LENGTH = 352K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.vectors)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) + . = ALIGN(4); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _ram_start = ORIGIN(sram); + _ram_size = LENGTH(sram); + _ram_end = ORIGIN(sram) + LENGTH(sram); + _ocram_start = ORIGIN(ocram); + _ocram_size = LENGTH(ocram); + _ocram_end = ORIGIN(ocram) + LENGTH(ocram); +} diff --git a/boards/arm/imx9/imx95-evk/scripts/itcm.ld b/boards/arm/imx9/imx95-evk/scripts/itcm.ld new file mode 100644 index 0000000000000..d23e5d11a6595 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/scripts/itcm.ld @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/imx95/imx95-evk/scripts/itcm.ld + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* + * Flash controller + * 1) 32 MB of FlexSPI_1 at 0x0200:0000 + * The on-chip SRAM is split in these parts: + * 1) 256Kb of program memory located at 0x0000:0000 + * 2) 256Kb of data memory beginning at the address 0x2000:0000 + * 3) 352Kb of OCRAM beginning at the address 0x2048:0000 + * 4) 4Mb of SDRAM located at 0x9000:0000 + */ + +MEMORY +{ + m_interrupts (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000800 + flash (rx) : ORIGIN = 0x00000800, LENGTH = 0x0003F800 + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K + ocram (rwx) : ORIGIN = 0x20480000, LENGTH = 352K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .interrupts : + { + __VECTOR_TABLE = .; + __Vectors = .; + . = ALIGN(4); + KEEP(*(.vectors)) /* Startup code */ + . = ALIGN(4); + } > m_interrupts + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) + . = ALIGN(4); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + + _ram_start = ORIGIN(sram); + _ram_size = LENGTH(sram); + _ram_end = ORIGIN(sram) + LENGTH(sram); + _ocram_start = ORIGIN(ocram); + _ocram_size = LENGTH(ocram); + _ocram_end = ORIGIN(ocram) + LENGTH(ocram); +} diff --git a/boards/arm/imx9/imx95-evk/src/CMakeLists.txt b/boards/arm/imx9/imx95-evk/src/CMakeLists.txt new file mode 100644 index 0000000000000..470144134ce1c --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/CMakeLists.txt @@ -0,0 +1,49 @@ +# ############################################################################## +# boards/arm/imx9/imx95-evk/src/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS imx95_boardinit.c imx95_bringup.c) + +if(CONFIG_BOARDCTL) + list(APPEND SRCS imx95_appinit.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS imx95_pwm.c) +endif() + +if(CONFIG_IMX9_LPI2C) + list(APPEND SRCS imx95_i2c.c) +endif() + +if(CONFIG_IMX9_LPSPI) + list(APPEND SRCS imx95_spi.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_IMX95_RUN_FROM_ITCM) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/itcm.ld") +elseif(CONFIG_IMX95_RUN_FROM_DDR) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ddr.ld") +elseif(CONFIG_IMX95_RUN_FROM_FLASH) + set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") +endif() diff --git a/boards/arm/imx9/imx95-evk/src/Makefile b/boards/arm/imx9/imx95-evk/src/Makefile new file mode 100644 index 0000000000000..6150390418858 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/Makefile @@ -0,0 +1,44 @@ +############################################################################ +# boards/arm/imx95/imx95-evk/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# SPDX-FileCopyrightText: 2024 NXP +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = imx95_boardinit.c imx95_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += imx95_appinit.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += imx95_pwm.c +endif + +ifeq ($(CONFIG_IMX9_LPI2C),y) +CSRCS += imx95_i2c.c +endif + +ifeq ($(CONFIG_IMX9_LPSPI),y) +CSRCS += imx95_spi.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/imx9/imx95-evk/src/imx95-evk.h b/boards/arm/imx9/imx95-evk/src/imx95-evk.h new file mode 100644 index 0000000000000..b7bcb3e973b51 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/imx95-evk.h @@ -0,0 +1,98 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/src/imx95-evk.h + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_IMX9_IMX95_EVK_SRC_IMX95_EVK_H +#define __BOARDS_ARM_IMX9_IMX95_EVK_SRC_IMX95_EVK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx95_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int imx95_bringup(void); +#endif + +/**************************************************************************** + * Name: imx95_pwm_setup + * + * Description: + * Initialize PWM outputs + * + ****************************************************************************/ + +#if defined(CONFIG_PWM) +int imx95_pwm_setup(void); +#endif + +/**************************************************************************** + * Name: imx95_i2c_setup + * + * Description: + * Initialize I2C devices and driver + * + ****************************************************************************/ + +#if defined(CONFIG_I2C_DRIVER) +int imx95_i2c_initialize(void); +#endif + +/**************************************************************************** + * Name: imx95_spi_setup + * + * Description: + * Initialize SPI devices and driver + * + ****************************************************************************/ + +#if defined(CONFIG_SPI_DRIVER) +int imx95_spi_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_IMX9_IMX95_EVK_SRC_IMX95_EVK_H */ diff --git a/boards/arm/imx9/imx95-evk/src/imx95_appinit.c b/boards/arm/imx9/imx95-evk/src/imx95_appinit.c new file mode 100644 index 0000000000000..207befa8147f1 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/imx95_appinit.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/src/imx95_appinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include "imx95-evk.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + UNUSED(arg); +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return imx95_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/arm/imx9/imx95-evk/src/imx95_boardinit.c b/boards/arm/imx9/imx95-evk/src/imx95_boardinit.c new file mode 100644 index 0000000000000..a08a16edb6070 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/imx95_boardinit.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/src/imx95_boardinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include "imx95-evk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx95_memory_initialize + * + * Description: + * All i.MX8 architectures must provide the following entry point. This + * entry point is called early in the initialization before memory has + * been configured. This board-specific function is responsible for + * configuring any on-board memories. + * + * Logic in imx95_memory_initialize must be careful to avoid using any + * global variables because those will be uninitialized at the time this + * function is called. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx95_memory_initialize(void) +{ + /* SDRAM was initialized by a bootloader in the supported configurations. */ +} + +/**************************************************************************** + * Name: imx95_board_initialize + * + * Description: + * All i.MX8 architectures must provide the following entry point. This + * entry point is called in the initialization phase -- after + * imx_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + imx95_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/imx9/imx95-evk/src/imx95_bringup.c b/boards/arm/imx9/imx95-evk/src/imx95_bringup.c new file mode 100644 index 0000000000000..0888116c2cdc1 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/imx95_bringup.c @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/src/imx95_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include "imx95-evk.h" + +#ifdef CONFIG_RPTUN +# include +#endif + +#ifdef CONFIG_RPMSG_UART +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_RPMSG_UART +void rpmsg_serialinit(void) +{ + uart_rpmsg_init("netcore", "proxy", 4096, true); +} +#endif + +/**************************************************************************** + * Name: imx_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int imx95_bringup(void) +{ + int ret; + +#ifdef CONFIG_RPTUN + imx9_rptun_init("imx9-shmem", "netcore"); +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#if defined(CONFIG_IMX9_LPI2C) + /* Configure I2C peripheral interfaces */ + + ret = imx95_i2c_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize I2C driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_IMX9_LPSPI1) + /* Configure SPI peripheral interfaces */ + + ret = imx95_spi_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SPI driver: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/imx9/imx95-evk/src/imx95_i2c.c b/boards/arm/imx9/imx95-evk/src/imx95_i2c.c new file mode 100644 index 0000000000000..b389923aaa0dc --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/imx95_i2c.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/src/imx95_i2c.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "imx9_lpi2c.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_i2c_init + * + * Description: + * Configure the I2C driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int imx95_i2c_initialize(void) +{ + int ret = OK; + +#ifdef CONFIG_IMX9_LPI2C6 + struct i2c_master_s *i2c; + + i2c = imx9_i2cbus_initialize(6); + if (i2c == NULL) + { + i2cerr("ERROR: Failed to init I2C6 interface\n"); + return -ENODEV; + } + +#ifdef CONFIG_SENSORS_BMM150 + struct bmm150_config_s bmm150_config = { + .i2c = i2c, + .addr = 0x12, + }; + + bmm150_register_uorb(0, &bmm150_config); +#endif + +#ifdef CONFIG_I2C_DRIVER + ret = i2c_register(i2c, 0); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C6 driver: %d\n", ret); + imx9_i2cbus_uninitialize(i2c); + return ret; + } +#endif + +#endif + return OK; +} diff --git a/boards/arm/imx9/imx95-evk/src/imx95_spi.c b/boards/arm/imx9/imx95-evk/src/imx95_spi.c new file mode 100644 index 0000000000000..cf96656948113 --- /dev/null +++ b/boards/arm/imx9/imx95-evk/src/imx95_spi.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/imx9/imx95-evk/src/imx95_spi.c + * + * SPDX-License-Identifier: Apache-2.0 + * SPDX-FileCopyrightText: 2024 NXP + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "imx9_gpio.h" +#include "imx9_lpspi.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI1 +static struct spi_dev_s *g_spi1; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI + +/**************************************************************************** + * Name: imx95_lpspix_select + * + * Description: + * Enable/disable the SPI chip select. The implementation of this method + * must include handshaking: If a device is selected, it must hold off + * all other attempts to select the device until the device is deselected. + * Required. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to select + * selected - true: slave selected, false: slave de-selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_lpspi_select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ +#ifdef CONFIG_IMX9_LPSPI1 + if (dev == g_spi1) + { + imx9_gpio_write(GPIO_LPSPI1_CS, !selected); + } +#endif +} + +/**************************************************************************** + * Name: imx95_lpspix_status + * + * Description: + * Get SPI/MMC status. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to report status on + * + * Returned Value: + * Returns a bitset of status values (see SPI_STATUS_* defines) + * + ****************************************************************************/ + +uint8_t imx9_lpspi_status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +/**************************************************************************** + * Name: imx95_lpspixcmddata + * + * Description: + * Some devices require an additional out-of-band bit to specify if the + * next word sent to the device is a command or data. This is typical, for + * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. + * This function provides selection of command or data. + * + * This "latches" the CMD/DATA state. It does not have to be called before + * every word is transferred; only when the CMD/DATA state changes. This + * method is required if CONFIG_SPI_CMDDATA is selected in the NuttX + * configuration + * + * Input Parameters: + * dev - Device-specific state data + * cmd - TRUE: The following word is a command; FALSE: the following words + * are data. + * + * Returned Value: + * OK unless an error occurs. Then a negated errno value is returned + * + ****************************************************************************/ + +int imx95_lpspi_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: board_spi_initialize + * + * Description: + * Initialize and register SPI driver for the defined SPI ports. + * + ****************************************************************************/ + +int imx95_spi_initialize(void) +{ + int ret = OK; + +#if defined(CONFIG_IMX9_LPSPI1) + /* Initialize SPI device */ + + g_spi1 = imx9_lpspibus_initialize(1); + if (g_spi1 == NULL) + { + spierr("Failed to initialize SPI1\n"); + return -ENODEV; + } + +#ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_spi1, 0); + if (ret < 0) + { + spierr("Failed to register /dev/spi0: %d\n", ret); + } +#endif /* CONFIG_SPI_DRIVER */ + +#endif /* CONFIG_MPFS_SPI0 */ + + return OK; +} diff --git a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_ethernet.c b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_ethernet.c index 9bdd3f07f6b1c..185130095ef8b 100644 --- a/boards/arm/imxrt/imxrt1020-evk/src/imxrt_ethernet.c +++ b/boards/arm/imxrt/imxrt1020-evk/src/imxrt_ethernet.c @@ -76,7 +76,9 @@ * Private Data ****************************************************************************/ +#ifdef GPIO_ENET_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/imxrt/imxrt1050-evk/src/imxrt_ethernet.c b/boards/arm/imxrt/imxrt1050-evk/src/imxrt_ethernet.c index fea90e458b5dd..30e499cf65942 100644 --- a/boards/arm/imxrt/imxrt1050-evk/src/imxrt_ethernet.c +++ b/boards/arm/imxrt/imxrt1050-evk/src/imxrt_ethernet.c @@ -79,7 +79,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ethernet.c b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ethernet.c index 18c6cf7885daa..dc643e48dc3ad 100644 --- a/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ethernet.c +++ b/boards/arm/imxrt/imxrt1060-evk/src/imxrt_ethernet.c @@ -77,7 +77,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ethernet.c b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ethernet.c index 0dcfc4da65660..00d7ad09bb65c 100644 --- a/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ethernet.c +++ b/boards/arm/imxrt/imxrt1064-evk/src/imxrt_ethernet.c @@ -77,7 +77,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/imxrt/teensy-4.x/src/imxrt_ethernet.c b/boards/arm/imxrt/teensy-4.x/src/imxrt_ethernet.c index 6053bcaec9086..d32c21fef98c2 100644 --- a/boards/arm/imxrt/teensy-4.x/src/imxrt_ethernet.c +++ b/boards/arm/imxrt/teensy-4.x/src/imxrt_ethernet.c @@ -77,7 +77,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_IMXRT_GPIO1_0_15_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/max326xx/max32660-evsys/src/max326_button.c b/boards/arm/max326xx/max32660-evsys/src/max326_button.c index 7dee8e905ff65..26f88d1df9915 100644 --- a/boards/arm/max326xx/max32660-evsys/src/max326_button.c +++ b/boards/arm/max326xx/max32660-evsys/src/max326_button.c @@ -43,6 +43,14 @@ #ifdef CONFIG_ARCH_BUTTONS +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_SAMA5_PIOB_IRQ) && defined(CONFIG_ARCH_IRQBUTTONS) +static spinlock_t g_max326_lock = SP_UNLOCKED; +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -108,7 +116,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) * following operations are atomic. */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&g_max326_lock); /* Are we attaching or detaching? */ @@ -127,7 +135,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) irq_detach(BUTTON_IRQ); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_max326_lock, flags); ret = OK; } diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c b/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c index f6424c3ba13e9..e7ebf6e943648 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_ethernet.c @@ -86,7 +86,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_SAMA5_PIOE_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c index e3d32befadf9a..33df048ea704b 100644 --- a/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c +++ b/boards/arm/sama5/sama5d3x-ek/src/sam_ethernet.c @@ -86,7 +86,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_SAMA5_PIOE_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/samv7/same70-xplained/src/sam_ethernet.c b/boards/arm/samv7/same70-xplained/src/sam_ethernet.c index d100c42689169..8f91e63110a3b 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_ethernet.c +++ b/boards/arm/samv7/same70-xplained/src/sam_ethernet.c @@ -82,7 +82,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_SAMV7_GPIOA_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/samv7/samv71-xult/src/sam_ethernet.c b/boards/arm/samv7/samv71-xult/src/sam_ethernet.c index 7bcdb6be69bd8..2bc8cbd708733 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_ethernet.c +++ b/boards/arm/samv7/samv71-xult/src/sam_ethernet.c @@ -82,7 +82,9 @@ * Private Data ****************************************************************************/ +#ifdef CONFIG_SAMV7_GPIOA_IRQ static spinlock_t g_phy_lock = SP_UNLOCKED; +#endif /**************************************************************************** * Private Functions diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c index 45e722039fd18..9a39e6ef612e7 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c @@ -81,9 +81,8 @@ * Private Data ****************************************************************************/ -static spinlock_t g_phy_lock = SP_UNLOCKED; - #ifdef HAVE_NETMONITOR +static spinlock_t g_phy_lock = SP_UNLOCKED; static xcpt_t g_ethmac_handler; static void *g_ethmac_arg; #endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c b/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c index 22113a6f8dae2..a8649863781ae 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c @@ -67,6 +67,8 @@ static void gs2200m_reset(bool); * Private Data ****************************************************************************/ +static spinlock_t g_gs2200m_lock = SP_UNLOCKED; + static const struct gs2200m_lower_s g_wifi_lower = { .attach = gs2200m_irq_attach, @@ -106,12 +108,13 @@ static int gs2200m_irq_attach(xcpt_t handler, void *arg) static void gs2200m_irq_enable(void) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags; uint32_t dready = 0; wlinfo("== ec:%" PRId32 " called=%" PRId32 "\n", _enable_count, _n_called++); + flags = spin_lock_irqsave(&g_gs2200m_lock); if (0 == _enable_count) { /* Check if irq has been asserted */ @@ -126,7 +129,7 @@ static void gs2200m_irq_enable(void) _enable_count++; - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_gs2200m_lock, flags); if (dready) { @@ -143,11 +146,12 @@ static void gs2200m_irq_enable(void) static void gs2200m_irq_disable(void) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags; wlinfo("== ec:%" PRId32 " called=%" PRId32 "\n", _enable_count, _n_called++); + flags = spin_lock_irqsave(&g_gs2200m_lock); _enable_count--; if (0 == _enable_count) @@ -156,7 +160,7 @@ static void gs2200m_irq_disable(void) false, NULL, NULL); } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_gs2200m_lock, flags); } /**************************************************************************** @@ -165,7 +169,7 @@ static void gs2200m_irq_disable(void) static uint32_t gs2200m_dready(int *ec) { - irqstate_t flags = spin_lock_irqsave(NULL); + irqstate_t flags = spin_lock_irqsave(&g_gs2200m_lock); uint32_t r = stm32_gpioread(GPIO_GS2200M_INT); @@ -176,7 +180,7 @@ static uint32_t gs2200m_dready(int *ec) *ec = _enable_count; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&g_gs2200m_lock, flags); return r; } diff --git a/drivers/i2c/i2c_bitbang.c b/drivers/i2c/i2c_bitbang.c index e99c3b3a4ef43..dd9a84f61dd05 100644 --- a/drivers/i2c/i2c_bitbang.c +++ b/drivers/i2c/i2c_bitbang.c @@ -48,6 +48,7 @@ struct i2c_bitbang_dev_s { struct i2c_master_s i2c; struct i2c_bitbang_lower_dev_s *lower; + spinlock_t lock; #ifndef CONFIG_I2C_BITBANG_NO_DELAY int32_t delay; @@ -116,7 +117,7 @@ static int i2c_bitbang_transfer(FAR struct i2c_master_s *dev, /* Lock to enforce timings */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); for (i = 0; i < count; i++) { @@ -245,7 +246,7 @@ static int i2c_bitbang_transfer(FAR struct i2c_master_s *dev, i2c_bitbang_set_scl(priv, true, false); i2c_bitbang_set_sda(priv, true); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); return ret; } @@ -391,6 +392,7 @@ FAR struct i2c_master_s *i2c_bitbang_initialize( dev->i2c.ops = &g_i2c_ops; dev->lower = lower; dev->lower->ops->initialize(dev->lower); + spin_lock_init(&dev->lock); return &dev->i2c; } diff --git a/drivers/power/supply/act8945a.c b/drivers/power/supply/act8945a.c index c8c3a32d346f4..6bf7aada7016e 100644 --- a/drivers/power/supply/act8945a.c +++ b/drivers/power/supply/act8945a.c @@ -298,6 +298,7 @@ struct regulator_act8945a_priv int i2c_freq; FAR const struct regulator_desc_s *regulators; FAR struct regulator_dev_s *rdev; + spinlock_t lock; }; struct act8945a_dev_s @@ -457,9 +458,9 @@ static int act8945a_getreg(FAR struct regulator_act8945a_priv *priv, /* Write the register address */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = i2c_write(priv->i2c, &config, ®addr, sizeof(regaddr)); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); if (ret < 0) { act8945a_err("ERROR: i2c_write failed: %d\n", ret); @@ -468,9 +469,9 @@ static int act8945a_getreg(FAR struct regulator_act8945a_priv *priv, /* Restart and read 8 bits from the register */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = i2c_read(priv->i2c, &config, regval, sizeof(*regval)); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); if (ret < 0) { act8945a_err("ERROR: i2c_read failed: %d\n", ret); @@ -525,9 +526,9 @@ static int act8945a_putreg(FAR struct regulator_act8945a_priv *priv, /* Write the register address followed by the data (no RESTART) */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&priv->lock); ret = i2c_write(priv->i2c, &config, buffer, sizeof(buffer)); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&priv->lock, flags); if (ret < 0) { @@ -1031,6 +1032,8 @@ int act8945a_initialize(FAR struct i2c_master_s *i2c, unsigned int vsel) priv->i2c_addr = ACT8945A_SLAVE_ADDRESS; priv->i2c_freq = ACT8945A_BUS_SPEED; + spin_lock_init(&priv->lock); + /* Early test to see if we can read the ACT8945A. * * We do this by writing a data pattern into the 4 scratch bits of SYS1 diff --git a/drivers/serial/uart_pci_16550.c b/drivers/serial/uart_pci_16550.c index 28f886e2ffa2f..a2a27b421a4a5 100644 --- a/drivers/serial/uart_pci_16550.c +++ b/drivers/serial/uart_pci_16550.c @@ -239,6 +239,7 @@ static struct pci_u16550_priv_s g_pci_u16550_priv0 = .flow = true, #endif .rxtrigger = 2, + .lock = SP_UNLOCKED }, /* PCI specific data */ @@ -287,6 +288,7 @@ static struct pci_u16550_priv_s g_pci_u16550_priv1 = .flow = true, #endif .rxtrigger = 2, + .lock = SP_UNLOCKED }, /* PCI specific data */ @@ -335,6 +337,7 @@ static struct pci_u16550_priv_s g_pci_u16550_priv2 = .flow = true, #endif .rxtrigger = 2, + .lock = SP_UNLOCKED }, /* PCI specific data */ @@ -381,6 +384,7 @@ static struct pci_u16550_priv_s g_pci_u16550_priv3 = .flow = true, #endif .rxtrigger = 2, + .lock = SP_UNLOCKED }, /* PCI specific data */ @@ -755,6 +759,7 @@ static int pci_u16550_probe(FAR struct pci_device_s *dev) #ifdef CONFIG_16550_PCI_CONSOLE void up_putc(int ch) { + FAR struct u16550_s *priv = CONSOLE_DEV.priv; irqstate_t flags; /* Console not initialized yet */ @@ -768,9 +773,9 @@ void up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = spin_lock_irqsave(NULL); - u16550_putc(CONSOLE_DEV.priv, ch); - spin_unlock_irqrestore(NULL, flags); + flags = spin_lock_irqsave(&priv->lock); + u16550_putc(priv, ch); + spin_unlock_irqrestore(&priv->lock, flags); } #endif diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c index 3532584747a87..1da270069920e 100644 --- a/drivers/serial/uart_pl011.c +++ b/drivers/serial/uart_pl011.c @@ -228,6 +228,7 @@ struct pl011_uart_port_s struct pl011_data data; struct pl011_config config; unsigned int irq_num; + spinlock_t lock; }; static int pl011_setup(FAR struct uart_dev_s *dev); @@ -307,6 +308,7 @@ static struct pl011_uart_port_s g_uart0priv = }, .irq_num = CONFIG_UART0_IRQ, + .lock = SP_UNLOCKED, }; /* I/O buffers */ @@ -350,6 +352,7 @@ static struct pl011_uart_port_s g_uart1priv = }, .irq_num = CONFIG_UART1_IRQ, + .lock = SP_UNLOCKED, }; /* I/O buffers */ @@ -393,6 +396,7 @@ static struct pl011_uart_port_s g_uart2priv = }, .irq_num = CONFIG_UART2_IRQ, + .lock = SP_UNLOCKED, }; /* I/O buffers */ @@ -436,6 +440,7 @@ static struct pl011_uart_port_s g_uart3priv = }, .irq_num = CONFIG_UART3_IRQ, + .lock = SP_UNLOCKED, }; /* I/O buffers */ @@ -670,12 +675,13 @@ static void pl011_send(FAR struct uart_dev_s *dev, int ch) static void pl011_putc(struct uart_dev_s *dev, int ch) { + FAR struct pl011_uart_port_s *sport = dev->priv; irqstate_t flags; - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&sport->lock); while (!pl011_txempty(dev)); pl011_send(dev, ch); - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&sport->lock, flags); } /*************************************************************************** @@ -737,24 +743,20 @@ static void pl011_txint(FAR struct uart_dev_s *dev, bool enable) FAR struct pl011_uart_port_s *sport = dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&sport->lock); if (enable) { pl011_irq_tx_enable(sport); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ + spin_unlock_irqrestore(&sport->lock, flags); uart_xmitchars(dev); } else { pl011_irq_tx_disable(sport); + spin_unlock_irqrestore(&sport->lock, flags); } - - leave_critical_section(flags); } /*************************************************************************** diff --git a/drivers/wireless/bluetooth/bt_uart_shim.c b/drivers/wireless/bluetooth/bt_uart_shim.c index 73c07c69c5427..f91e73b24eac2 100644 --- a/drivers/wireless/bluetooth/bt_uart_shim.c +++ b/drivers/wireless/bluetooth/bt_uart_shim.c @@ -59,6 +59,7 @@ struct hciuart_state_s struct file f; /* File structure */ struct pollfd p; /* Poll structure */ + spinlock_t lock; /* Spinlock */ }; struct hciuart_config_s @@ -120,7 +121,7 @@ hciuart_rxattach(FAR const struct btuart_lowerhalf_s *lower, /* If the callback is NULL, then we are detaching */ - flags = spin_lock_irqsave(NULL); + flags = spin_lock_irqsave(&state->lock); if (callback == NULL) { /* Disable Rx callbacks and detach the Rx callback */ @@ -137,7 +138,7 @@ hciuart_rxattach(FAR const struct btuart_lowerhalf_s *lower, state->callback = callback; } - spin_unlock_irqrestore(NULL, flags); + spin_unlock_irqrestore(&state->lock, flags); } /**************************************************************************** @@ -373,6 +374,7 @@ FAR struct btuart_lowerhalf_s *btuart_shim_getdevice(FAR const char *path) s->p.events = POLLIN; s->p.arg = n; s->p.cb = hciuart_rxpollcb; + spin_lock_init(&s->lock); /* Hook the routines in */ diff --git a/include/nuttx/serial/uart_16550.h b/include/nuttx/serial/uart_16550.h index ad77ca391bb42..9acd75a87a0c5 100644 --- a/include/nuttx/serial/uart_16550.h +++ b/include/nuttx/serial/uart_16550.h @@ -30,6 +30,7 @@ #include #include +#include #ifdef CONFIG_16550_UART @@ -376,6 +377,7 @@ struct u16550_s #endif #endif uart_datawidth_t rxtrigger; /* RX trigger level */ + spinlock_t lock; /* Spinlock */ }; /****************************************************************************