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| 1 | +# Copyright (c) 2024 Seb Holzapfel <[email protected]> |
| 2 | +# |
| 3 | +# SPDX-License-Identifier: BSD--3-Clause |
| 4 | + |
| 5 | +from amaranth import * |
| 6 | +from amaranth.lib.fifo import AsyncFIFO |
| 7 | + |
| 8 | +class AudioToChannels(Elaboratable): |
| 9 | + |
| 10 | + """ |
| 11 | + Domain crossing logic to move samples from `eurorack-pmod` logic in the audio domain |
| 12 | + to `channels_to_usb_stream` and `usb_stream_to_channels` logic in the USB domain. |
| 13 | + """ |
| 14 | + |
| 15 | + def __init__(self, eurorack_pmod, to_usb_stream, from_usb_stream): |
| 16 | + |
| 17 | + self.to_usb = to_usb_stream |
| 18 | + self.from_usb = from_usb_stream |
| 19 | + self.eurorack_pmod = eurorack_pmod |
| 20 | + |
| 21 | + def elaborate(self, platform) -> Module: |
| 22 | + |
| 23 | + m = Module() |
| 24 | + |
| 25 | + eurorack_pmod = self.eurorack_pmod |
| 26 | + |
| 27 | + # Sample widths |
| 28 | + SW = eurorack_pmod.width # Sample width used in underlying I2S driver. |
| 29 | + SW_USB = self.to_usb.payload.width # Sample width used for USB transfers. |
| 30 | + N_ZFILL = SW_USB - SW # Zero padding if SW < SW_USB |
| 31 | + |
| 32 | + assert(N_ZFILL >= 0) |
| 33 | + |
| 34 | + # |
| 35 | + # INPUT SIDE |
| 36 | + # eurorack-pmod calibrated INPUT samples -> USB Channel stream -> HOST |
| 37 | + # |
| 38 | + |
| 39 | + m.submodules.adc_fifo = adc_fifo = AsyncFIFO(width=SW*4, depth=64, w_domain="audio", r_domain="usb") |
| 40 | + |
| 41 | + # (audio domain) on every sample strobe, latch and write all channels concatenated into one entry |
| 42 | + # of adc_fifo. |
| 43 | + |
| 44 | + m.d.audio += [ |
| 45 | + # FIXME: ignoring rdy in write domain. Should be fine as write domain |
| 46 | + # will always be slower than the read domain, but should be fixed. |
| 47 | + adc_fifo.w_en.eq(eurorack_pmod.fs_strobe), |
| 48 | + adc_fifo.w_data[ :SW*1].eq(eurorack_pmod.cal_in0), |
| 49 | + adc_fifo.w_data[SW*1:SW*2].eq(eurorack_pmod.cal_in1), |
| 50 | + adc_fifo.w_data[SW*2:SW*3].eq(eurorack_pmod.cal_in2), |
| 51 | + adc_fifo.w_data[SW*3:SW*4].eq(eurorack_pmod.cal_in3), |
| 52 | + ] |
| 53 | + |
| 54 | + # (usb domain) unpack samples from the adc_fifo (one big concatenated |
| 55 | + # entry with samples for all channels once per sample strobe) and feed them |
| 56 | + # into ChannelsToUSBStream with one entry per channel, i.e 1 -> 4 entries |
| 57 | + # per sample strobe in the audio domain. |
| 58 | + |
| 59 | + # Storage for samples in the USB domain as we send them to the channel stream. |
| 60 | + adc_latched = Signal(SW*4) |
| 61 | + |
| 62 | + with m.FSM(domain="usb") as fsm: |
| 63 | + |
| 64 | + with m.State('WAIT'): |
| 65 | + m.d.usb += self.to_usb.valid.eq(0), |
| 66 | + with m.If(adc_fifo.r_rdy): |
| 67 | + m.d.usb += adc_fifo.r_en.eq(1) |
| 68 | + m.next = 'LATCH' |
| 69 | + |
| 70 | + with m.State('LATCH'): |
| 71 | + m.d.usb += [ |
| 72 | + adc_fifo.r_en.eq(0), |
| 73 | + adc_latched.eq(adc_fifo.r_data) |
| 74 | + ] |
| 75 | + m.next = 'CH0' |
| 76 | + |
| 77 | + def generate_channel_states(channel, next_state_name): |
| 78 | + with m.State(f'CH{channel}'): |
| 79 | + m.d.usb += [ |
| 80 | + # FIXME: currently filling bottom bits with zeroes for SW bit -> SW_USB bit |
| 81 | + # sample conversion. Better to just switch native rate of I2S driver. |
| 82 | + self.to_usb.payload.eq( |
| 83 | + Cat(Const(0, N_ZFILL), adc_latched[channel*SW:(channel+1)*SW])), |
| 84 | + self.to_usb.channel_no.eq(channel), |
| 85 | + self.to_usb.valid.eq(1), |
| 86 | + ] |
| 87 | + m.next = f'CH{channel}-SEND' |
| 88 | + with m.State(f'CH{channel}-SEND'): |
| 89 | + with m.If(self.to_usb.ready): |
| 90 | + m.d.usb += self.to_usb.valid.eq(0) |
| 91 | + m.next = next_state_name |
| 92 | + |
| 93 | + generate_channel_states(0, 'CH1') |
| 94 | + generate_channel_states(1, 'CH2') |
| 95 | + generate_channel_states(2, 'CH3') |
| 96 | + generate_channel_states(3, 'WAIT') |
| 97 | + |
| 98 | + # |
| 99 | + # OUTPUT SIDE |
| 100 | + # HOST -> USB Channel stream -> eurorack-pmod calibrated OUTPUT samples. |
| 101 | + # |
| 102 | + |
| 103 | + for n, output in zip(range(4), [eurorack_pmod.cal_out0, eurorack_pmod.cal_out1, |
| 104 | + eurorack_pmod.cal_out2, eurorack_pmod.cal_out3]): |
| 105 | + |
| 106 | + # FIXME: we shouldn't need one FIFO per channel |
| 107 | + fifo = AsyncFIFO(width=SW, depth=64, w_domain="usb", r_domain="audio") |
| 108 | + setattr(m.submodules, f'dac_fifo{n}', fifo) |
| 109 | + |
| 110 | + # (usb domain) if the channel_no matches, demux it into the correct channel FIFO |
| 111 | + m.d.comb += [ |
| 112 | + fifo.w_data.eq(self.from_usb.payload[N_ZFILL:]), |
| 113 | + fifo.w_en.eq((self.from_usb.channel_no == n) & |
| 114 | + self.from_usb.valid), |
| 115 | + ] |
| 116 | + |
| 117 | + # (audio domain) once fs_strobe hits, write the next pending sample to eurorack_pmod. |
| 118 | + with m.FSM(domain="audio") as fsm: |
| 119 | + with m.State('READ'): |
| 120 | + with m.If(eurorack_pmod.fs_strobe & fifo.r_rdy): |
| 121 | + m.d.audio += fifo.r_en.eq(1) |
| 122 | + m.next = 'SEND' |
| 123 | + with m.State('SEND'): |
| 124 | + m.d.audio += [ |
| 125 | + fifo.r_en.eq(0), |
| 126 | + output.eq(fifo.r_data), |
| 127 | + ] |
| 128 | + m.next = 'READ' |
| 129 | + |
| 130 | + # FIXME: make this less lenient |
| 131 | + m.d.comb += self.from_usb.ready.eq( |
| 132 | + m.submodules.dac_fifo0.w_rdy | m.submodules.dac_fifo1.w_rdy | |
| 133 | + m.submodules.dac_fifo2.w_rdy | m.submodules.dac_fifo3.w_rdy) |
| 134 | + |
| 135 | + return m |
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