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Rename classes whose names start with 'SIMD'
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‎README.md‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -95,15 +95,15 @@ import simuhw as hw
9595
- [`LeadingZeroCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.LeadingZeroCounter)
9696
- [`TrailingZeroCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.TrailingZeroCounter)
9797
- [`BitReverser`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.BitReverser)
98-
- [`SIMDLeftShifter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDLeftShifter)
99-
- [`SIMDRightShifter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDRightShifter)
100-
- [`SIMDArithmeticRightShifter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDArithmeticRightShifter)
101-
- [`SIMDLeftRotator`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDLeftRotator)
102-
- [`SIMDRightRotator`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDRightRotator)
103-
- [`SIMDPopulationCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDPopulationCounter)
104-
- [`SIMDLeadingZeroCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDLeadingZeroCounter)
105-
- [`SIMDTrailingZeroCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDTrailingZeroCounter)
106-
- [`SIMDBitReverser`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDBitReverser)
98+
- [`SIMD_LeftShifter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_LeftShifter)
99+
- [`SIMD_RightShifter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_RightShifter)
100+
- [`SIMD_ArithmeticRightShifter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_ArithmeticRightShifter)
101+
- [`SIMD_LeftRotator`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_LeftRotator)
102+
- [`SIMD_RightRotator`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_RightRotator)
103+
- [`SIMD_PopulationCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_PopulationCounter)
104+
- [`SIMD_LeadingZeroCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_LeadingZeroCounter)
105+
- [`SIMD_TrailingZeroCounter`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_TrailingZeroCounter)
106+
- [`SIMD_BitReverser`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_BitReverser)
107107
- Integer Arithmetic
108108
- [`Adder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.Adder)
109109
- [`HalfAdder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.HalfAdder)
@@ -117,14 +117,14 @@ import simuhw as hw
117117
- [`SignedDivider`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SignedDivider)
118118
- [`Remainder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.Remainder)
119119
- [`SignedRemainder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SignedRemainder)
120-
- [`SIMDAdder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDAdder)
121-
- [`SIMDSubtractor`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDSubtractor)
122-
- [`SIMDMultiplier`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDMultiplier)
123-
- [`SIMDSignedMultiplier`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDSignedMultiplier)
124-
- [`SIMDDivider`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDDivider)
125-
- [`SIMDSignedDivider`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDSignedDivider)
126-
- [`SIMDRemainder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDRemainder)
127-
- [`SIMDSignedRemainder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMDSignedRemainder)
120+
- [`SIMD_Adder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_Adder)
121+
- [`SIMD_Subtractor`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_Subtractor)
122+
- [`SIMD_Multiplier`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_Multiplier)
123+
- [`SIMD_SignedMultiplier`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_SignedMultiplier)
124+
- [`SIMD_Divider`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_Divider)
125+
- [`SIMD_SignedDivider`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_SignedDivider)
126+
- [`SIMD_Remainder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_Remainder)
127+
- [`SIMD_SignedRemainder`](https://arithy.github.io/simuhw/apidoc/simuhw.html#simuhw.SIMD_SignedRemainder)
128128
- Memory
129129
- [`LevelTriggeredMemory`](https://arithy.github.io/simuhw/apidoc/simuhw.memory.html#simuhw.memory.LevelTriggeredMemory)
130130
- [`EdgeTriggeredMemory`](https://arithy.github.io/simuhw/apidoc/simuhw.memory.html#simuhw.memory.EdgeTriggeredMemory)

‎python/src/simuhw/__init__.py‎

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -35,14 +35,14 @@
3535
'DLatch',
3636
'DFlipFlop',
3737
'Shifter', 'LeftShifter', 'RightShifter', 'ArithmeticRightShifter', 'LeftRotator', 'RightRotator',
38-
'SIMDShifter', 'SIMDLeftShifter', 'SIMDRightShifter', 'SIMDArithmeticRightShifter', 'SIMDLeftRotator', 'SIMDRightRotator',
38+
'SIMD_Shifter', 'SIMD_LeftShifter', 'SIMD_RightShifter', 'SIMD_ArithmeticRightShifter', 'SIMD_LeftRotator', 'SIMD_RightRotator',
3939
'BitOperator', 'PopulationCounter', 'LeadingZeroCounter', 'TrailingZeroCounter', 'BitReverser',
40-
'SIMDBitOperator', 'SIMDPopulationCounter', 'SIMDLeadingZeroCounter', 'SIMDTrailingZeroCounter', 'SIMDBitReverser',
41-
'Adder', 'HalfAdder', 'FullAdder', 'SIMDAdder',
42-
'Subtractor', 'HalfSubtractor', 'FullSubtractor', 'SIMDSubtractor',
43-
'Multiplier', 'SignedMultiplier', 'SIMDMultiplier', 'SIMDSignedMultiplier',
44-
'Divider', 'SignedDivider', 'SIMDDivider', 'SIMDSignedDivider',
45-
'Remainder', 'SignedRemainder', 'SIMDRemainder', 'SIMDSignedRemainder'
40+
'SIMD_BitOperator', 'SIMD_PopulationCounter', 'SIMD_LeadingZeroCounter', 'SIMD_TrailingZeroCounter', 'SIMD_BitReverser',
41+
'Adder', 'HalfAdder', 'FullAdder', 'SIMD_Adder',
42+
'Subtractor', 'HalfSubtractor', 'FullSubtractor', 'SIMD_Subtractor',
43+
'Multiplier', 'SignedMultiplier', 'SIMD_Multiplier', 'SIMD_SignedMultiplier',
44+
'Divider', 'SignedDivider', 'SIMD_Divider', 'SIMD_SignedDivider',
45+
'Remainder', 'SignedRemainder', 'SIMD_Remainder', 'SIMD_SignedRemainder'
4646
]
4747

4848
from ._version import __version__ # noqa:F401
@@ -60,14 +60,14 @@
6060
from ._flipflop import DFlipFlop
6161
from ._shifter import (
6262
Shifter, LeftShifter, RightShifter, ArithmeticRightShifter, LeftRotator, RightRotator,
63-
SIMDShifter, SIMDLeftShifter, SIMDRightShifter, SIMDArithmeticRightShifter, SIMDLeftRotator, SIMDRightRotator
63+
SIMD_Shifter, SIMD_LeftShifter, SIMD_RightShifter, SIMD_ArithmeticRightShifter, SIMD_LeftRotator, SIMD_RightRotator
6464
)
6565
from ._bit_op import (
6666
BitOperator, PopulationCounter, LeadingZeroCounter, TrailingZeroCounter, BitReverser,
67-
SIMDBitOperator, SIMDPopulationCounter, SIMDLeadingZeroCounter, SIMDTrailingZeroCounter, SIMDBitReverser
67+
SIMD_BitOperator, SIMD_PopulationCounter, SIMD_LeadingZeroCounter, SIMD_TrailingZeroCounter, SIMD_BitReverser
6868
)
69-
from ._adder import Adder, HalfAdder, FullAdder, SIMDAdder
70-
from ._subtractor import Subtractor, HalfSubtractor, FullSubtractor, SIMDSubtractor
71-
from ._multiplier import Multiplier, SignedMultiplier, SIMDMultiplier, SIMDSignedMultiplier
72-
from ._divider import Divider, SignedDivider, SIMDDivider, SIMDSignedDivider
73-
from ._remainder import Remainder, SignedRemainder, SIMDRemainder, SIMDSignedRemainder
69+
from ._adder import Adder, HalfAdder, FullAdder, SIMD_Adder
70+
from ._subtractor import Subtractor, HalfSubtractor, FullSubtractor, SIMD_Subtractor
71+
from ._multiplier import Multiplier, SignedMultiplier, SIMD_Multiplier, SIMD_SignedMultiplier
72+
from ._divider import Divider, SignedDivider, SIMD_Divider, SIMD_SignedDivider
73+
from ._remainder import Remainder, SignedRemainder, SIMD_Remainder, SIMD_SignedRemainder

‎python/src/simuhw/_adder.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
180180
return (ports_i, None)
181181

182182

183-
class SIMDAdder(BinaryGate):
183+
class SIMD_Adder(BinaryGate):
184184
"""A SIMD adder.
185185
186186
This device calculates respective additions of multiple pairs of binary integers simultaneously.

‎python/src/simuhw/_bit_op.py‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -181,7 +181,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
181181
return (list(self._ports_i), None)
182182

183183

184-
class SIMDBitOperator(UnaryGate, metaclass=ABCMeta):
184+
class SIMD_BitOperator(UnaryGate, metaclass=ABCMeta):
185185
"""The super class for all SIMD bit operators."""
186186

187187
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -219,7 +219,7 @@ def reset(self) -> None:
219219
self._port_s.reset()
220220

221221

222-
class SIMDPopulationCounter(SIMDBitOperator):
222+
class SIMD_PopulationCounter(SIMD_BitOperator):
223223
"""A SIMD bit population counter."""
224224

225225
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -263,7 +263,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
263263
return (ports_i, None)
264264

265265

266-
class SIMDLeadingZeroCounter(SIMDBitOperator):
266+
class SIMD_LeadingZeroCounter(SIMD_BitOperator):
267267
"""A SIMD leading bit-0 counter."""
268268

269269
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -307,7 +307,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
307307
return (ports_i, None)
308308

309309

310-
class SIMDTrailingZeroCounter(SIMDBitOperator):
310+
class SIMD_TrailingZeroCounter(SIMD_BitOperator):
311311
"""A SIMD trailing bit-0 counter."""
312312

313313
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -351,7 +351,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
351351
return (ports_i, None)
352352

353353

354-
class SIMDBitReverser(SIMDBitOperator):
354+
class SIMD_BitReverser(SIMD_BitOperator):
355355
"""A SIMD bit reverser."""
356356

357357
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:

‎python/src/simuhw/_divider.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
134134
return (ports_i, None)
135135

136136

137-
class SIMDDivider(BinaryGate):
137+
class SIMD_Divider(BinaryGate):
138138
"""A SIMD divider.
139139
140140
This device calculates respective divisions of multiple pairs of unsigned binary integers simultaneously.
@@ -226,7 +226,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
226226
return (ports_i, None)
227227

228228

229-
class SIMDSignedDivider(SIMDDivider):
229+
class SIMD_SignedDivider(SIMD_Divider):
230230
"""A SIMD signed divider.
231231
232232
This device calculates respective divisions of multiple pairs of signed binary integers simultaneously.

‎python/src/simuhw/_multiplier.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
126126
return (ports_i, None)
127127

128128

129-
class SIMDMultiplier(BinaryGate):
129+
class SIMD_Multiplier(BinaryGate):
130130
"""A SIMD multiplier.
131131
132132
This device calculates respective multiplications of multiple pairs of unsigned binary integers simultaneously.
@@ -213,7 +213,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
213213
return (ports_i, None)
214214

215215

216-
class SIMDSignedMultiplier(SIMDMultiplier):
216+
class SIMD_SignedMultiplier(SIMD_Multiplier):
217217
"""A SIMD signed multiplier.
218218
219219
This device calculates respective multiplications of multiple pairs of signed binary integers simultaneously.

‎python/src/simuhw/_remainder.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
134134
return (ports_i, None)
135135

136136

137-
class SIMDRemainder(BinaryGate):
137+
class SIMD_Remainder(BinaryGate):
138138
"""A SIMD remainder calculator.
139139
140140
This device calculates respective remainders of multiple pairs of unsigned binary integers simultaneously.
@@ -226,7 +226,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
226226
return (ports_i, None)
227227

228228

229-
class SIMDSignedRemainder(SIMDRemainder):
229+
class SIMD_SignedRemainder(SIMD_Remainder):
230230
"""A SIMD signed remainder calculator.
231231
232232
This device calculates respective remainders of multiple pairs of signed binary integers simultaneously.

‎python/src/simuhw/_shifter.py‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
221221
return (ports_i, None)
222222

223223

224-
class SIMDShifter(BinaryGate, metaclass=ABCMeta):
224+
class SIMD_Shifter(BinaryGate, metaclass=ABCMeta):
225225
"""The super class for all SIMD barrel shifters."""
226226

227227
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -259,7 +259,7 @@ def reset(self) -> None:
259259
self._port_s.reset()
260260

261261

262-
class SIMDLeftShifter(SIMDShifter):
262+
class SIMD_LeftShifter(SIMD_Shifter):
263263
"""A SIMD left barrel shifter."""
264264

265265
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -304,7 +304,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
304304
return (ports_i, None)
305305

306306

307-
class SIMDRightShifter(SIMDShifter):
307+
class SIMD_RightShifter(SIMD_Shifter):
308308
"""A SIMD right barrel shifter."""
309309

310310
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -349,7 +349,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
349349
return (ports_i, None)
350350

351351

352-
class SIMDArithmeticRightShifter(SIMDShifter):
352+
class SIMD_ArithmeticRightShifter(SIMD_Shifter):
353353
"""A SIMD arithmetic right barrel shifter."""
354354

355355
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -395,7 +395,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
395395
return (ports_i, None)
396396

397397

398-
class SIMDLeftRotator(SIMDShifter):
398+
class SIMD_LeftRotator(SIMD_Shifter):
399399
"""A SIMD left barrel rotator."""
400400

401401
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:
@@ -441,7 +441,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
441441
return (ports_i, None)
442442

443443

444-
class SIMDRightRotator(SIMDShifter):
444+
class SIMD_RightRotator(SIMD_Shifter):
445445
"""A SIMD right barrel rotator."""
446446

447447
def __init__(self, width: int, dsize: int | Iterable[int]) -> None:

‎python/src/simuhw/_subtractor.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ def work(self, time: float | None) -> tuple[list[InputPort], float | None]:
180180
return (ports_i, None)
181181

182182

183-
class SIMDSubtractor(BinaryGate):
183+
class SIMD_Subtractor(BinaryGate):
184184
"""A SIMD subtractor.
185185
186186
This device calculates respective subtractions of multiple pairs of binary integers simultaneously.

‎python/tests/simuhw/test_adder.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
# SOFTWARE.
2222

2323
from simuhw import (
24-
Source, Drain, Adder, HalfAdder, FullAdder, SIMDAdder,
24+
Source, Drain, Adder, HalfAdder, FullAdder, SIMD_Adder,
2525
ChannelProbe, Simulator
2626
)
2727

@@ -198,7 +198,7 @@ def test_FullAdder() -> None:
198198
assert abs(o[1] - q[1]) <= _EPS
199199

200200

201-
def test_SIMDAdder() -> None:
201+
def test_SIMD_Adder() -> None:
202202
test_data: list[tuple[list[int], list[int], list[list[tuple[bytes | None, float]]], list[tuple[bytes | None, float]]]] = [
203203
(
204204
[32, 2],
@@ -226,7 +226,7 @@ def test_SIMDAdder() -> None:
226226
po: ChannelProbe = ChannelProbe('out', w)
227227
ti: list[Source] = [Source(u, d) for u, d in zip([w, w, s], t[2])]
228228
to: Drain = Drain(w)
229-
dev: SIMDAdder = SIMDAdder(w, t[1])
229+
dev: SIMD_Adder = SIMD_Adder(w, t[1])
230230
dev.port_o.connect(to.port_i)
231231
ti[0].port_o.connect(dev.ports_i[0])
232232
ti[1].port_o.connect(dev.ports_i[1])

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