Skip to content

Commit 1dcf8c6

Browse files
HackingGateHackingGate
committed
board: photonicat2: add kernel patches in rk35xx-current
1 parent 4d3683d commit 1dcf8c6

File tree

109 files changed

+35037
-0
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

109 files changed

+35037
-0
lines changed

‎config/sources/families/rk35xx.conf‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,15 @@ case $BRANCH in
4040
KERNELBRANCH='branch:rk-6.1-rkr5.1'
4141
KERNELPATCHDIR='rk35xx-vendor-6.1'
4242
;;
43+
44+
current)
45+
BOOTDIR='u-boot-rockchip64'
46+
declare -g KERNEL_MAJOR_MINOR="6.12" # Major and minor versions of this kernel.
47+
declare -g -i KERNEL_GIT_CACHE_TTL=120 # 2 minutes; this is a high-traffic repo
48+
KERNELSOURCE='https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git'
49+
KERNELBRANCH='tag:v6.12.41' # Pin to working version from standalone repo
50+
KERNELPATCHDIR='rk35xx-current'
51+
;;
4352
esac
4453

4554
prepare_boot_configuration

‎patch/kernel/rk35xx-current/032-06-v6.13-phy-rockchip-inno-usb2-convert-clock-management-to-bulk.patch‎

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
1+
From 86e2ed4e9a9680013ec9ab7c0428c9b8c5108efe Mon Sep 17 00:00:00 2001
2+
From: Frank Wang <[email protected]>
3+
Date: Wed, 16 Oct 2024 15:37:10 +0800
4+
Subject: [PATCH] phy: rockchip: inno-usb2: convert clock management to bulk
5+
6+
Since some Rockchip SoCs (e.g RK3576) have more than one clock,
7+
this converts the clock management from single to bulk method to
8+
make the driver more flexible.
9+
10+
Signed-off-by: Frank Wang <[email protected]>
11+
Reviewed-by: Heiko Stuebner <[email protected]>
12+
Link: https://lore.kernel.org/r/[email protected]
13+
Signed-off-by: Vinod Koul <[email protected]>
14+
---
15+
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 45 +++++++++++++++----
16+
1 file changed, 37 insertions(+), 8 deletions(-)
17+
18+
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
19+
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
20+
@@ -225,9 +225,10 @@ struct rockchip_usb2phy_port {
21+
* @dev: pointer to device.
22+
* @grf: General Register Files regmap.
23+
* @usbgrf: USB General Register Files regmap.
24+
- * @clk: clock struct of phy input clk.
25+
+ * @clks: array of phy input clocks.
26+
* @clk480m: clock struct of phy output clk.
27+
* @clk480m_hw: clock struct of phy output clk management.
28+
+ * @num_clks: number of phy input clocks.
29+
* @phy_reset: phy reset control.
30+
* @chg_state: states involved in USB charger detection.
31+
* @chg_type: USB charger types.
32+
@@ -242,9 +243,10 @@ struct rockchip_usb2phy {
33+
struct device *dev;
34+
struct regmap *grf;
35+
struct regmap *usbgrf;
36+
- struct clk *clk;
37+
+ struct clk_bulk_data *clks;
38+
struct clk *clk480m;
39+
struct clk_hw clk480m_hw;
40+
+ int num_clks;
41+
struct reset_control *phy_reset;
42+
enum usb_chg_state chg_state;
43+
enum power_supply_type chg_type;
44+
@@ -306,6 +308,13 @@ static int rockchip_usb2phy_reset(struct
45+
return 0;
46+
}
47+
48+
+static void rockchip_usb2phy_clk_bulk_disable(void *data)
49+
+{
50+
+ struct rockchip_usb2phy *rphy = data;
51+
+
52+
+ clk_bulk_disable_unprepare(rphy->num_clks, rphy->clks);
53+
+}
54+
+
55+
static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
56+
{
57+
struct rockchip_usb2phy *rphy =
58+
@@ -372,7 +381,9 @@ rockchip_usb2phy_clk480m_register(struct
59+
{
60+
struct device_node *node = rphy->dev->of_node;
61+
struct clk_init_data init;
62+
+ struct clk *refclk = NULL;
63+
const char *clk_name;
64+
+ int i;
65+
int ret = 0;
66+
67+
init.flags = 0;
68+
@@ -382,8 +393,15 @@ rockchip_usb2phy_clk480m_register(struct
69+
/* optional override of the clockname */
70+
of_property_read_string(node, "clock-output-names", &init.name);
71+
72+
- if (rphy->clk) {
73+
- clk_name = __clk_get_name(rphy->clk);
74+
+ for (i = 0; i < rphy->num_clks; i++) {
75+
+ if (!strncmp(rphy->clks[i].id, "phyclk", 6)) {
76+
+ refclk = rphy->clks[i].clk;
77+
+ break;
78+
+ }
79+
+ }
80+
+
81+
+ if (!IS_ERR(refclk)) {
82+
+ clk_name = __clk_get_name(refclk);
83+
init.parent_names = &clk_name;
84+
init.num_parents = 1;
85+
} else {
86+
@@ -1385,11 +1403,13 @@ static int rockchip_usb2phy_probe(struct
87+
if (IS_ERR(rphy->phy_reset))
88+
return PTR_ERR(rphy->phy_reset);
89+
90+
- rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk");
91+
- if (IS_ERR(rphy->clk)) {
92+
- return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk),
93+
- "failed to get phyclk\n");
94+
- }
95+
+ ret = devm_clk_bulk_get_all(dev, &rphy->clks);
96+
+ if (ret == -EPROBE_DEFER)
97+
+ return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
98+
+ "failed to get phy clock\n");
99+
+
100+
+ /* Clocks are optional */
101+
+ rphy->num_clks = ret < 0 ? 0 : ret;
102+
103+
ret = rockchip_usb2phy_clk480m_register(rphy);
104+
if (ret) {
105+
@@ -1397,6 +1417,14 @@ static int rockchip_usb2phy_probe(struct
106+
return ret;
107+
}
108+
109+
+ ret = clk_bulk_prepare_enable(rphy->num_clks, rphy->clks);
110+
+ if (ret)
111+
+ return dev_err_probe(dev, ret, "failed to enable phy clock\n");
112+
+
113+
+ ret = devm_add_action_or_reset(dev, rockchip_usb2phy_clk_bulk_disable, rphy);
114+
+ if (ret)
115+
+ return ret;
116+
+
117+
if (rphy->phy_cfg->phy_tuning) {
118+
ret = rphy->phy_cfg->phy_tuning(rphy);
119+
if (ret)

‎patch/kernel/rk35xx-current/032-07-v6.13-phy-rockchip-inno-usb2-Add-usb2-phys-support-for-rk3576.patch‎

Lines changed: 143 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,143 @@
1+
From 3d7de6e870ece5a32153382df9df6fb87613335e Mon Sep 17 00:00:00 2001
2+
From: William Wu <[email protected]>
3+
Date: Wed, 16 Oct 2024 15:37:13 +0800
4+
Subject: [PATCH] phy: rockchip: inno-usb2: Add usb2 phys support for rk3576
5+
6+
The RK3576 SoC has two independent USB2.0 PHYs, and each PHY has
7+
one port. This adds device specific data for it.
8+
9+
Signed-off-by: William Wu <[email protected]>
10+
Signed-off-by: Frank Wang <[email protected]>
11+
Reviewed-by: Heiko Stuebner <[email protected]>
12+
Link: https://lore.kernel.org/r/[email protected]
13+
Signed-off-by: Vinod Koul <[email protected]>
14+
---
15+
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 103 ++++++++++++++++++
16+
1 file changed, 103 insertions(+)
17+
18+
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
19+
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
20+
@@ -1494,6 +1494,30 @@ put_child:
21+
return ret;
22+
}
23+
24+
+static int rk3576_usb2phy_tuning(struct rockchip_usb2phy *rphy)
25+
+{
26+
+ int ret;
27+
+ u32 reg = rphy->phy_cfg->reg;
28+
+
29+
+ /* Deassert SIDDQ to power on analog block */
30+
+ ret = regmap_write(rphy->grf, reg + 0x0010, GENMASK(29, 29) | 0x0000);
31+
+ if (ret)
32+
+ return ret;
33+
+
34+
+ /* Do reset after exit IDDQ mode */
35+
+ ret = rockchip_usb2phy_reset(rphy);
36+
+ if (ret)
37+
+ return ret;
38+
+
39+
+ /* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
40+
+ ret |= regmap_write(rphy->grf, reg + 0x000c, GENMASK(27, 24) | 0x0900);
41+
+
42+
+ /* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
43+
+ ret |= regmap_write(rphy->grf, reg + 0x0010, GENMASK(20, 19) | 0x0010);
44+
+
45+
+ return ret;
46+
+}
47+
+
48+
static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
49+
{
50+
int ret;
51+
@@ -1856,6 +1880,84 @@ static const struct rockchip_usb2phy_cfg
52+
{ /* sentinel */ }
53+
};
54+
55+
+static const struct rockchip_usb2phy_cfg rk3576_phy_cfgs[] = {
56+
+ {
57+
+ .reg = 0x0,
58+
+ .num_ports = 1,
59+
+ .phy_tuning = rk3576_usb2phy_tuning,
60+
+ .clkout_ctl = { 0x0008, 0, 0, 1, 0 },
61+
+ .port_cfgs = {
62+
+ [USB2PHY_PORT_OTG] = {
63+
+ .phy_sus = { 0x0000, 8, 0, 0, 0x1d1 },
64+
+ .bvalid_det_en = { 0x00c0, 1, 1, 0, 1 },
65+
+ .bvalid_det_st = { 0x00c4, 1, 1, 0, 1 },
66+
+ .bvalid_det_clr = { 0x00c8, 1, 1, 0, 1 },
67+
+ .ls_det_en = { 0x00c0, 0, 0, 0, 1 },
68+
+ .ls_det_st = { 0x00c4, 0, 0, 0, 1 },
69+
+ .ls_det_clr = { 0x00c8, 0, 0, 0, 1 },
70+
+ .disfall_en = { 0x00c0, 6, 6, 0, 1 },
71+
+ .disfall_st = { 0x00c4, 6, 6, 0, 1 },
72+
+ .disfall_clr = { 0x00c8, 6, 6, 0, 1 },
73+
+ .disrise_en = { 0x00c0, 5, 5, 0, 1 },
74+
+ .disrise_st = { 0x00c4, 5, 5, 0, 1 },
75+
+ .disrise_clr = { 0x00c8, 5, 5, 0, 1 },
76+
+ .utmi_avalid = { 0x0080, 1, 1, 0, 1 },
77+
+ .utmi_bvalid = { 0x0080, 0, 0, 0, 1 },
78+
+ .utmi_ls = { 0x0080, 5, 4, 0, 1 },
79+
+ }
80+
+ },
81+
+ .chg_det = {
82+
+ .cp_det = { 0x0080, 8, 8, 0, 1 },
83+
+ .dcp_det = { 0x0080, 8, 8, 0, 1 },
84+
+ .dp_det = { 0x0080, 9, 9, 1, 0 },
85+
+ .idm_sink_en = { 0x0010, 5, 5, 1, 0 },
86+
+ .idp_sink_en = { 0x0010, 5, 5, 0, 1 },
87+
+ .idp_src_en = { 0x0010, 14, 14, 0, 1 },
88+
+ .rdm_pdwn_en = { 0x0010, 14, 14, 0, 1 },
89+
+ .vdm_src_en = { 0x0010, 7, 6, 0, 3 },
90+
+ .vdp_src_en = { 0x0010, 7, 6, 0, 3 },
91+
+ },
92+
+ },
93+
+ {
94+
+ .reg = 0x2000,
95+
+ .num_ports = 1,
96+
+ .phy_tuning = rk3576_usb2phy_tuning,
97+
+ .clkout_ctl = { 0x2008, 0, 0, 1, 0 },
98+
+ .port_cfgs = {
99+
+ [USB2PHY_PORT_OTG] = {
100+
+ .phy_sus = { 0x2000, 8, 0, 0, 0x1d1 },
101+
+ .bvalid_det_en = { 0x20c0, 1, 1, 0, 1 },
102+
+ .bvalid_det_st = { 0x20c4, 1, 1, 0, 1 },
103+
+ .bvalid_det_clr = { 0x20c8, 1, 1, 0, 1 },
104+
+ .ls_det_en = { 0x20c0, 0, 0, 0, 1 },
105+
+ .ls_det_st = { 0x20c4, 0, 0, 0, 1 },
106+
+ .ls_det_clr = { 0x20c8, 0, 0, 0, 1 },
107+
+ .disfall_en = { 0x20c0, 6, 6, 0, 1 },
108+
+ .disfall_st = { 0x20c4, 6, 6, 0, 1 },
109+
+ .disfall_clr = { 0x20c8, 6, 6, 0, 1 },
110+
+ .disrise_en = { 0x20c0, 5, 5, 0, 1 },
111+
+ .disrise_st = { 0x20c4, 5, 5, 0, 1 },
112+
+ .disrise_clr = { 0x20c8, 5, 5, 0, 1 },
113+
+ .utmi_avalid = { 0x2080, 1, 1, 0, 1 },
114+
+ .utmi_bvalid = { 0x2080, 0, 0, 0, 1 },
115+
+ .utmi_ls = { 0x2080, 5, 4, 0, 1 },
116+
+ }
117+
+ },
118+
+ .chg_det = {
119+
+ .cp_det = { 0x2080, 8, 8, 0, 1 },
120+
+ .dcp_det = { 0x2080, 8, 8, 0, 1 },
121+
+ .dp_det = { 0x2080, 9, 9, 1, 0 },
122+
+ .idm_sink_en = { 0x2010, 5, 5, 1, 0 },
123+
+ .idp_sink_en = { 0x2010, 5, 5, 0, 1 },
124+
+ .idp_src_en = { 0x2010, 14, 14, 0, 1 },
125+
+ .rdm_pdwn_en = { 0x2010, 14, 14, 0, 1 },
126+
+ .vdm_src_en = { 0x2010, 7, 6, 0, 3 },
127+
+ .vdp_src_en = { 0x2010, 7, 6, 0, 3 },
128+
+ },
129+
+ },
130+
+ { /* sentinel */ }
131+
+};
132+
+
133+
static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
134+
{
135+
.reg = 0x0000,
136+
@@ -2026,6 +2128,7 @@ static const struct of_device_id rockchi
137+
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
138+
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
139+
{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
140+
+ { .compatible = "rockchip,rk3576-usb2phy", .data = &rk3576_phy_cfgs },
141+
{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
142+
{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
143+
{}

‎patch/kernel/rk35xx-current/032-08-v6.13-phy-rockchip-usbdp-add-rk3576-device-match-data.patch‎

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
From a76de028c619dd18f89786805bcc7bb4d379ea9f Mon Sep 17 00:00:00 2001
2+
From: Frank Wang <[email protected]>
3+
Date: Mon, 14 Oct 2024 10:03:42 +0800
4+
Subject: [PATCH] phy: rockchip: usbdp: add rk3576 device match data
5+
6+
This adds RK3576 device match data support.
7+
8+
Signed-off-by: Frank Wang <[email protected]>
9+
Acked-by: Dragan Simic <[email protected]>
10+
Reviewed-by: Heiko Stuebner <[email protected]>
11+
Link: https://lore.kernel.org/r/[email protected]
12+
Signed-off-by: Vinod Koul <[email protected]>
13+
---
14+
drivers/phy/rockchip/phy-rockchip-usbdp.c | 41 +++++++++++++++++++++++
15+
1 file changed, 41 insertions(+)
16+
17+
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
18+
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
19+
@@ -1538,6 +1538,43 @@ static const char * const rk_udphy_rst_l
20+
"init", "cmn", "lane", "pcs_apb", "pma_apb"
21+
};
22+
23+
+static const struct rk_udphy_cfg rk3576_udphy_cfgs = {
24+
+ .num_phys = 1,
25+
+ .phy_ids = { 0x2b010000 },
26+
+ .num_rsts = ARRAY_SIZE(rk_udphy_rst_list),
27+
+ .rst_list = rk_udphy_rst_list,
28+
+ .grfcfg = {
29+
+ /* u2phy-grf */
30+
+ .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0010, 1, 0, 0x2, 0x3),
31+
+ .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0000, 15, 14, 0x1, 0x3),
32+
+
33+
+ /* usb-grf */
34+
+ .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x0030, 15, 0, 0x1100, 0x0188),
35+
+
36+
+ /* usbdpphy-grf */
37+
+ .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1),
38+
+ .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1),
39+
+ },
40+
+ .vogrfcfg = {
41+
+ {
42+
+ .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
43+
+ .dp_lane_reg = 0x0000,
44+
+ },
45+
+ },
46+
+ .dp_tx_ctrl_cfg = {
47+
+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
48+
+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
49+
+ rk3588_dp_tx_drv_ctrl_hbr2,
50+
+ rk3588_dp_tx_drv_ctrl_hbr3,
51+
+ },
52+
+ .dp_tx_ctrl_cfg_typec = {
53+
+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
54+
+ rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
55+
+ rk3588_dp_tx_drv_ctrl_hbr2,
56+
+ rk3588_dp_tx_drv_ctrl_hbr3,
57+
+ },
58+
+};
59+
+
60+
static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
61+
.num_phys = 2,
62+
.phy_ids = {
63+
@@ -1585,6 +1622,10 @@ static const struct rk_udphy_cfg rk3588_
64+
65+
static const struct of_device_id rk_udphy_dt_match[] = {
66+
{
67+
+ .compatible = "rockchip,rk3576-usbdp-phy",
68+
+ .data = &rk3576_udphy_cfgs
69+
+ },
70+
+ {
71+
.compatible = "rockchip,rk3588-usbdp-phy",
72+
.data = &rk3588_udphy_cfgs
73+
},

‎patch/kernel/rk35xx-current/033-01-v6.13-gpio-rockchip-explan-the-format-of-the-GPIO-version-ID.patch‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
From 591ae6bed250e4067db926313ff7279d23a1c7d1 Mon Sep 17 00:00:00 2001
2+
From: Ye Zhang <[email protected]>
3+
Date: Tue, 12 Nov 2024 09:54:05 +0800
4+
Subject: [PATCH] gpio: rockchip: explan the format of the GPIO version ID
5+
6+
Remove redundant comments and provide a detailed explanation of the
7+
GPIO version ID.
8+
9+
Signed-off-by: Ye Zhang <[email protected]>
10+
Reviewed-by: Andy Shevchenko <[email protected]>
11+
Reviewed-by: Sebastian Reichel <[email protected]>
12+
Link: https://lore.kernel.org/r/[email protected]
13+
Signed-off-by: Bartosz Golaszewski <[email protected]>
14+
---
15+
drivers/gpio/gpio-rockchip.c | 10 ++++++++--
16+
1 file changed, 8 insertions(+), 2 deletions(-)
17+
18+
--- a/drivers/gpio/gpio-rockchip.c
19+
+++ b/drivers/gpio/gpio-rockchip.c
20+
@@ -26,9 +26,15 @@
21+
#include "../pinctrl/core.h"
22+
#include "../pinctrl/pinctrl-rockchip.h"
23+
24+
+/*
25+
+ * Version ID Register
26+
+ * Bits [31:24] - Major Version
27+
+ * Bits [23:16] - Minor Version
28+
+ * Bits [15:0] - Revision Number
29+
+ */
30+
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
31+
-#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
32+
-#define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
33+
+#define GPIO_TYPE_V2 (0x01000C2B)
34+
+#define GPIO_TYPE_V2_1 (0x0101157C)
35+
36+
static const struct rockchip_gpio_regs gpio_regs_v1 = {
37+
.port_dr = 0x00,

0 commit comments

Comments
 (0)