|
| 1 | +From 5d001456be3aab35acc9399512743ad276301b28 Mon Sep 17 00:00:00 2001 |
| 2 | +From: HackingGate < [email protected]> |
| 3 | +Date: Sat, 27 Sep 2025 17:52:20 +0900 |
| 4 | +Subject: [PATCH] arm64: dts: rockchip: rk3576: add PWM device nodes for |
| 5 | + Photonicat2 |
| 6 | + |
| 7 | +Add two PWM device nodes required by the Photonicat2 board. These nodes |
| 8 | +expose the SoC PWM controllers used by the Photonicat2 daughterboard so |
| 9 | +userspace (and board DT overlays) can enable and use PWM outputs. |
| 10 | +--- |
| 11 | + arch/arm64/boot/dts/rockchip/rk3576.dtsi | 26 ++++++++++++++++++++++++ |
| 12 | + 1 file changed, 26 insertions(+) |
| 13 | + |
| 14 | +diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi |
| 15 | +index c3cdae8a5494..71545b606430 100644 |
| 16 | +--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi |
| 17 | ++++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi |
| 18 | +@@ -2291,6 +2291,32 @@ uart9: serial@2adc0000 { |
| 19 | + status = "disabled"; |
| 20 | + }; |
| 21 | + |
| 22 | ++ pwm1_6ch_0: pwm@2add0000 { |
| 23 | ++ compatible = "rockchip,rk3576-pwm"; |
| 24 | ++ reg = <0x0 0x2add0000 0x0 0x1000>; |
| 25 | ++ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>, |
| 26 | ++ <&cru CLK_OSC_PWM1>, <&cru CLK_RC_PWM1>; |
| 27 | ++ clock-names = "pwm", "pclk", "osc", "rc"; |
| 28 | ++ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| 29 | ++ pinctrl-names = "default"; |
| 30 | ++ pinctrl-0 = <&pwm1m0_ch0>; |
| 31 | ++ #pwm-cells = <3>; |
| 32 | ++ status = "disabled"; |
| 33 | ++ }; |
| 34 | ++ |
| 35 | ++ pwm2_8ch_2: pwm@2ade2000 { |
| 36 | ++ compatible = "rockchip,rk3576-pwm"; |
| 37 | ++ reg = <0x0 0x2ade2000 0x0 0x1000>; |
| 38 | ++ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>, |
| 39 | ++ <&cru CLK_OSC_PWM2>, <&cru CLK_RC_PWM2>; |
| 40 | ++ clock-names = "pwm", "pclk", "osc", "rc"; |
| 41 | ++ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 42 | ++ pinctrl-names = "default"; |
| 43 | ++ pinctrl-0 = <&pwm2m0_ch2>; |
| 44 | ++ #pwm-cells = <3>; |
| 45 | ++ status = "disabled"; |
| 46 | ++ }; |
| 47 | ++ |
| 48 | + saradc: adc@2ae00000 { |
| 49 | + compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; |
| 50 | + reg = <0x0 0x2ae00000 0x0 0x10000>; |
| 51 | +-- |
| 52 | +2.47.3 |
| 53 | + |
0 commit comments