vdivs.ato

import Resistor from "resistors.ato"
import Capacitor from "capacitors.ato"
import Power from "interfaces.ato"
import Pair from "interfaces.ato"

module VDiv from _VDiv:
    v_in: voltage
    v_out: voltage
    i_q: current

    i_q = 100uA to 10mA

    assert v_in * r_bottom.value / (r_top.value + r_bottom.value) within v_out
    assert v_in / (r_bottom.value + r_top.value) within i_q


module _VDiv:
    signal top
    signal out
    signal bottom

    output = new Pair
    output.io ~ out
    output.gnd ~ bottom

    in = new Power # legacy
    power = new Power
    in ~ power
    power.vcc ~ top
    power.gnd ~ bottom

    r_top = new Resistor
    r_bottom = new Resistor
    r_top.package = "0402"
    r_bottom.package = "0402"

    top ~ r_top.1; r_top.2 ~ r_bottom.1; r_bottom.2 ~ bottom
    r_top.2 ~ out

module VDivLowPassFilter from VDiv:
    cap = new Capacitor
    cap.package = "0402"
    cutoff_frequency: frequency

    out ~ cap.1; cap.2 ~ bottom
    cap.value = 100nF +/- 10%

    cutoff_frequency: frequency

    assert 1 / (2 * 3.14 * r_top.value * cap.value) within cutoff_frequency