@@ -3364,6 +3364,7 @@ void Capstone2LlvmIrTranslatorX86_impl::translateShiftX(cs_insn* i, cs_x86* xi,
33643364 case X86_INS_SHR: return llvm::Instruction::BinaryOps::LShr;
33653365 case X86_INS_SAR: return llvm::Instruction::BinaryOps::AShr;
33663366 case X86_INS_SHL: return llvm::Instruction::BinaryOps::Shl;
3367+ default : assert (false );
33673368 }
33683369 }();
33693370
@@ -5444,5 +5445,28 @@ void Capstone2LlvmIrTranslatorX86_impl::translateRdtscp(cs_insn* i, cs_x86* xi,
54445445 storeRegister (X86_REG_ECX, irb.CreateExtractValue (c, {2 }), irb);
54455446}
54465447
5448+ void Capstone2LlvmIrTranslatorX86_impl::translateTzcntOrLzcnt (cs_insn* i, cs_x86* xi, llvm::IRBuilder<>& irb)
5449+ {
5450+ EXPECT_IS_BINARY (i, xi, irb);
5451+
5452+ std::tie (op0, op1) = loadOpBinary (xi, irb);
5453+
5454+ storeRegister (X86_REG_CF, generateZeroFlag (op1, irb), irb);
5455+
5456+ op0 = irb.CreateIntrinsic (
5457+ i->id == X86_INS_LZCNT ? llvm::Intrinsic::ctlz : llvm::Intrinsic::cttz,
5458+ {op1->getType ()},
5459+ {op1, irb.getFalse ()});
5460+
5461+ storeRegister (X86_REG_OF, irb.getFalse (), irb); // undef
5462+ storeRegister (X86_REG_SF, irb.getFalse (), irb); // undef
5463+ storeRegister (X86_REG_PF, irb.getFalse (), irb); // undef
5464+ storeRegister (X86_REG_AF, irb.getFalse (), irb); // undef
5465+
5466+ storeRegister (X86_REG_ZF, generateZeroFlag (op0, irb), irb);
5467+
5468+ storeOp (xi->operands [0 ], op0, irb);
5469+ }
5470+
54475471} // namespace capstone2llvmir
54485472} // namespace retdec
0 commit comments