diff --git a/src/devdescr.cc b/src/devdescr.cc
index 41b49cd..6f76f0e 100644
--- a/src/devdescr.cc
+++ b/src/devdescr.cc
@@ -783,9 +783,71 @@ jtag_device_def_type deviceDefinitions[] = {
 	    fill_b2(0x1F),	// EECRAddress
 	},
 	{ 0 },			// Xmega device descr.
-    },
-    // DEV_ATMEGA644
-    {
+	},
+	// DEV_ATMEGA324PB
+	{
+	"atmega324pb",
+	0x9517,
+	128, 256,	// 32768 bytes flash
+	4, 256,	// 1024 bytes EEPROM
+	0x60,		// First flash address which is not an interrupt vector
+	DEVFL_NONE,
+	atmega324pb_io_registers,
+	false,
+	0x07, 0x8000, // fuses
+	0x66, // osccal
+	3, // OCD revision
+	{
+		0	// no mkI support
+	},
+	{
+		CMND_SET_DEVICE_DESCRIPTOR,
+		{ 0xFF,0x0F,0xE0,0xF8,0xFF,0x3D,0xB9,0xE8 }, // ucReadIO
+		{ 0X00,0X00,0X00,0X00,0X01,0X00,0X00,0X00 }, // ucReadIOShadow
+		{ 0xB6,0x0D,0x00,0xE0,0xFF,0x1D,0xB8,0xE8 }, // ucWriteIO
+		{ 0X00,0X00,0X00,0X00,0X01,0X00,0X00,0X00 }, // ucWriteIOShadow
+		{ 0x53,0xFB,0x09,0xDF,0xF3,0x0F,0x00,0x00,
+		  0x00,0x00,0x5F,0x3F,0x37,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00 }, // ucReadExtIO
+		{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00 }, // ucReadIOExtShadow
+		{ 0x51,0xFB,0x09,0xD8,0xF3,0x0F,0x00,0x00,
+		  0x00,0x00,0x5F,0x2F,0x36,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00 }, // ucWriteExtIO
+		{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00 }, // ucWriteIOExtShadow
+		0x31,	// ucIDRAddress
+		0x37,	// ucSPMCRAddress
+		0x3B,	// ucRAMPZAddress
+		fill_b2(128),	// uiFlashPageSize
+		4,	// ucEepromPageSize
+		fill_b4(0x3f00),	// ulBootAddress
+		fill_b2(0x00C6),	// uiUpperExtIOLoc
+		fill_b4(32768),	// ulFlashSize
+		{ 0x00 },	// ucEepromInst
+		{ 0x00 },	// ucFlashInst
+		0x3E,	// ucSPHaddr
+		0x3D,	// ucSPLaddr
+		fill_b2(32768 / 128),	// uiFlashpages
+		0x00,	// ucDWDRAddress
+		0x00,	// ucDWBasePC
+		0x00,	// ucAllowFullPageBitstream
+		fill_b2(0x00),	// uiStartSmallestBootLoaderSection
+		1,	// EnablePageProgramming
+		0,	// ucCacheType
+		fill_b2(0x100),	// uiSramStartAddr
+		0,	// ucResetType
+		0,	// ucPCMaskExtended
+		0,	// ucPCMaskHigh
+		0,	// ucEindAddress
+		fill_b2(0x1F),	// EECRAddress
+	},
+	{ 0 },			// Xmega device descr.
+	},
+	// DEV_ATMEGA644
+	{
 	"atmega644",
 	0x9609,
 	256, 256,    // 64K flash
@@ -3012,9 +3074,69 @@ jtag_device_def_type deviceDefinitions[] = {
 	    fill_b2(0x1C),	// EECRAddress
 	},
 	{ 0 },			// Xmega device descr.
-    },
-    // DEV_ATTINY461
-    {
+	},
+	// DEV_ATTINY402
+	{
+		"attiny402",
+		0x9227,
+		64, 64,	// flash
+		32, 4,	// EEPROM
+		(31 + 1) * 2,	// First flash address which is not an interrupt vector
+		DEVFL_NONE,
+		attiny402_io_registers,
+		false,
+		0x5E7, 0, // fuses
+		0, // osccal
+		0, // OCD revision
+		{
+			0	// no mkI support
+		},
+		{
+			0   // no mkII JTAG support
+		},
+		{
+			0   // no Xmega support
+		},
+		{
+			fill_b2(0x8000),	// Start address of Program memory
+			64,					// Page size of flash in bytes
+			32,					// Page size of EEPROM
+			fill_b2(0x1000),	// Address of NVMCTRL module
+			fill_b2(0x0F80),	// Address of OCD module
+		},
+	},
+	// DEV_ATTINY412
+	{
+		"attiny412",
+		0x9223,
+		64, 64,	// flash
+		32, 4,	// EEPROM
+		(26 + 1) * 2,	// First flash address which is not an interrupt vector
+		DEVFL_NONE,
+		attiny412_io_registers,
+		false,
+		0x5F7, 0, // fuses
+		0, // osccal
+		0, // OCD revision
+		{
+			0	// no mkI support
+		},
+		{
+			0   // no mkII JTAG support
+		},
+		{
+			0   // no Xmega support
+		},
+		{
+			fill_b2(0x8000),	// Start address of Program memory
+			64,					// Page size of flash in bytes
+			32,					// Page size of EEPROM
+			fill_b2(0x1000),	// Address of NVMCTRL module
+			fill_b2(0x0F80),	// Address of OCD module
+		},
+	},
+	// DEV_ATTINY461
+	{
 	"attiny461",
 	0x9208,
 	64, 64,	// 4096 bytes flash
@@ -3076,9 +3198,39 @@ jtag_device_def_type deviceDefinitions[] = {
 	    fill_b2(0x1C),	// EECRAddress
 	},
 	{ 0 },			// Xmega device descr.
-    },
-    // DEV_ATTINY861
-    {
+	},
+	// DEV_ATTINY814
+	{
+		"attiny814",
+		0x9322,
+		64, 128,	// flash
+		32, 4,	// EEPROM
+		26 * 2,	// interrupt vectors
+		DEVFL_NONE,
+		attiny814_io_registers,
+		false,
+		0x5F7, 0, // fuses
+		0, // osccal
+		0, // OCD revision
+		{
+			0	// no mkI support
+		},
+		{
+			0   // no mkII JTAG support
+		},
+		{
+			0   // no Xmega support
+		},
+		{
+			fill_b2(0x8000),	// Start address of Program memory
+			64,					// Page size of flash in bytes
+			32,					// Page size of EEPROM
+			fill_b2(0x1000),	// Address of NVMCTRL module
+			fill_b2(0x0F80),	// Address of OCD module
+		},
+	},
+	// DEV_ATTINY861
+	{
 	"attiny861",
 	0x930D,
 	64, 128,	// 8192 bytes flash
@@ -5319,9 +5471,92 @@ jtag_device_def_type deviceDefinitions[] = {
 	    fill_b2(0x1c0),	// IO space base address of NVM controller
 	    fill_b2(0x90),	// IO space address of MCU control
 	},
-    },
-    // DEV_ATXMEGA128A3
-    {
+	},
+	// DEV_ATXMEGA16A4U
+	{
+	"atxmega16a4u",
+	0x9441,
+	256, 80,	// 20480 bytes flash
+	32, 32, 	// 1024 bytes EEPROM
+	94 * 4, 	// 94 interrupt vectors?
+	DEVFL_MKII_ONLY,
+	atxmega16a4u_io_registers,	// registers
+	true,
+	0x37, 0x0000, // fuses
+	0, // osccal
+	0, // OCD revision
+	{
+		0	// no mkI support
+	},
+	{
+		CMND_SET_DEVICE_DESCRIPTOR,
+		{ 0xFF,0xFF,0xFF,0xF9,0xFF,0x3D,0xB9,0xF8 }, // ucReadIO
+		{ 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 }, // ucReadIOShadow
+		{ 0xFF,0xFF,0x1F,0xE0,0xFF,0x1D,0xA9,0xF8 }, // ucWriteIO
+		{ 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 }, // ucWriteIOShadow
+		{ 0x73,0xFF,0x3F,0xFF,0xF7,0x3F,0xF7,0x3F,
+		  0xF7,0x3F,0x5F,0x3F,0x37,0x37,0x36,0x00,
+		  0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,
+		  0xF7,0x3F,0x36,0x00 }, // ucReadExtIO
+		{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00 }, // ucReadIOExtShadow
+		{ 0x73,0xFF,0x3F,0xF8,0xF7,0x3F,0xF7,0x3F,
+		  0xF7,0x3F,0x5F,0x2F,0x36,0x36,0x36,0x00,
+		  0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00,
+		  0xF7,0x3F,0x36,0x00 }, // ucWriteExtIO
+		{ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+		  0x00,0x00,0x00,0x00 }, // ucWriteIOExtShadow
+		0x31,	// ucIDRAddress
+		0x57,	// ucSPMCRAddress
+		0,	// ucRAMPZAddress
+		fill_b2(256),	// uiFlashPageSize
+		32,	// ucEepromPageSize
+		fill_b4(0x4000),	// ulBootAddress -- byte address
+		fill_b2(0x136),	// uiUpperExtIOLoc
+		fill_b4(256 * 80),	// ulFlashSize (page size * pages)
+		{ 0x00 },	// ucEepromInst
+		{ 0x00 },	// ucFlashInst
+		0x3E,	// ucSPHaddr
+		0x3D,	// ucSPLaddr
+		fill_b2(80),	// uiFlashpages (64 application + 16 boot)
+		0x00,	// ucDWDRAddress
+		0x00,	// ucDWBasePC
+		0x00,	// ucAllowFullPageBitstream
+		fill_b2(0x00),	// uiStartSmallestBootLoaderSection
+		1,	// EnablePageProgramming
+		0x02,	// ucCacheType
+		fill_b2(8192),	// uiSramStartAddr
+		0,	// ucResetType
+		0,	// ucPCMaskExtended
+		0,	// ucPCMaskHigh
+		0,	// ucEindAddress
+		fill_b2(0),	// EECRAddress
+	},
+	{
+		CMND_SET_XMEGA_PARAMS, // cmd
+		fill_b2(2),		// whatever
+		47,			// length of following data
+		fill_b4(0x800000),	// NVM offset for application flash
+		fill_b4(0x804000),	// NVM offset for boot flash
+		fill_b4(0x8c0000),	// NVM offset for EEPROM
+		fill_b4(0x8f0020),	// NVM offset for fuses
+		fill_b4(0x8f0027),	// NVM offset for lock bits
+		fill_b4(0x8e0400),	// NVM offset for user signature row
+		fill_b4(0x8e0200),	// NVM offset for production sig. row
+		fill_b4(0x1000000), // NVM offset for data memory
+		fill_b4(20480),	// size of application flash
+		fill_b2(4096),	// size of boot flash
+		fill_b2(256),	// flash page size
+		fill_b2(1024),	// size of EEPROM
+		32,			// EEPROM page size
+		fill_b2(0x1c0),	// IO space base address of NVM controller
+		fill_b2(0x90),	// IO space address of MCU control
+	},
+	},
+	// DEV_ATXMEGA128A3
+	{
 	"atxmega128a3",
 	0x9742,
 	512, 272,	// 139264 bytes flash
@@ -6308,8 +6543,98 @@ jtag_device_def_type deviceDefinitions[] = {
             fill_b2(0x90),      // IO space address of MCU control
         },
     },
-    // DEV_ATXMEGA64A3
-    {
+	// DEV_ATMEGA3208
+	{
+		"atmega3208",
+		0x9552,
+		128, 256,	   // 32768 bytes flash (page size. # pages)
+		64, 4, // 256 bytes EEPROM
+		0x50,		// First flash address which is not an interrupt vector
+		DEVFL_NONE,
+		atmega3208_io_registers,
+		false,
+		0x5E7, 0, // fuses
+		0, // osccal
+		0, // OCD revision
+		{
+			0   // no mkI support
+		},
+		{
+			0   // no mkII JTAG support
+		},
+		{
+			0   // no Xmega support
+		},
+		{
+			fill_b2(0x4000),	// Start address of Program memory
+			128,				// Page size of flash in bytes
+			64,					// Page size of EEPROM
+			fill_b2(0x1000),	// Address of NVMCTRL module
+			fill_b2(0x0F80),	// Address of OCD module
+		},
+	},
+	// DEV_ATMEGA4808
+	{
+		"atmega4808",
+		0x9650,
+		128, 384,	   // 49152 bytes flash (page size. # pages)
+		64, 4, // 256 bytes EEPROM
+		0x50,		// First flash address which is not an interrupt vector
+		DEVFL_NONE,
+		atmega4808_io_registers,
+		false,
+		0x5E7, 0, // fuses
+		0, // osccal
+		0, // OCD revision
+		{
+			0   // no mkI support
+		},
+		{
+			0   // no mkII JTAG support
+		},
+		{
+			0   // no Xmega support
+		},
+		{
+			fill_b2(0x4000),	// Start address of Program memory
+			128,				// Page size of flash in bytes
+			64,					// Page size of EEPROM
+			fill_b2(0x1000),	// Address of NVMCTRL module
+			fill_b2(0x0F80),	// Address of OCD module
+		},
+	},
+	// DEV_ATMEGA4809
+	{
+		"atmega4809",
+		0x9651,
+		128, 384,	   // 49152 bytes flash (page size. # pages)
+		64, 4, // 256 bytes EEPROM
+		0x50,		// First flash address which is not an interrupt vector
+		DEVFL_NONE,
+		atmega4809_io_registers,
+		false,
+		0x5E7, 0, // fuses
+		0, // osccal
+		0, // OCD revision
+		{
+			0   // no mkI support
+		},
+		{
+			0   // no mkII JTAG support
+		},
+		{
+			0   // no Xmega support
+		},
+		{
+			fill_b2(0x4000),	// Start address of Program memory
+			128,				// Page size of flash in bytes
+			64,					// Page size of EEPROM
+			fill_b2(0x1000),	// Address of NVMCTRL module
+			fill_b2(0x0F80),	// Address of OCD module
+		},
+	},
+	// DEV_ATXMEGA64A3
+	{
 	"atxmega64a3",
 	0x9642,
         256, 272,       // 69,632 bytes flash (page size. # pages)
diff --git a/src/ioreg.cc b/src/ioreg.cc
index c21bb93..f4e3786 100644
--- a/src/ioreg.cc
+++ b/src/ioreg.cc
@@ -1015,6 +1015,159 @@ gdb_io_reg_def_type atmega324p_io_registers[] =
 };
 
 
+gdb_io_reg_def_type atmega324pb_io_registers[] =
+{
+    { "PINA", 0x20, 0x00 },
+    { "DDRA", 0x21, 0x00 },
+    { "PORTA", 0x22, 0x00 },
+    { "PINB", 0x23, 0x00 },
+    { "DDRB", 0x24, 0x00 },
+    { "PORTB", 0x25, 0x00 },
+    { "PINC", 0x26, 0x00 },
+    { "DDRC", 0x27, 0x00 },
+    { "PORTC", 0x28, 0x00 },
+    { "PIND", 0x29, 0x00 },
+    { "DDRD", 0x2a, 0x00 },
+    { "PORTD", 0x2b, 0x00 },
+    { "TIFR0", 0x35, 0x00 },
+    { "TIFR1", 0x36, 0x00 },
+    { "TIFR2", 0x37, 0x00 },
+    { "TIFR3", 0x38, 0x00 },
+    { "TIFR4", 0x39, 0x00 },
+    { "PCIFR", 0x3b, 0x00 },
+    { "EIFR", 0x3c, 0x00 },
+    { "EIMSK", 0x3d, 0x00 },
+    { "GPIOR0", 0x3e, 0x00 },
+    { "EECR", 0x3f, 0x00 },
+    { "EEDR", 0x40, 0x00 },
+    { "EEARL", 0x41, 0x00 },
+    { "EEARH", 0x42, 0x00 },
+    { "GTCCR", 0x43, 0x00 },
+    { "TCCR0A", 0x44, 0x00 },
+    { "TCCR0B", 0x45, 0x00 },
+    { "TCNT0", 0x46, 0x00 },
+    { "OCR0A", 0x47, 0x00 },
+    { "OCR0B", 0x48, 0x00 },
+    { "GPIOR1", 0x4a, 0x00 },
+    { "GPIOR2", 0x4b, 0x00 },
+    { "SPCR", 0x4c, 0x00 },
+    { "SPSR", 0x4d, 0x00 },
+    { "SPDR", 0x4e, 0x00 },
+    { "ACSRB", 0x4f, 0x00 },
+    { "ACSR", 0x50, 0x00 },
+    { "OCDR", 0x51, 0x00 },
+    { "SMCR", 0x53, 0x00 },
+    { "MCUSR", 0x54, 0x00 },
+    { "MCUCR", 0x55, 0x00 },
+    { "SPMCSR", 0x57, 0x00 },
+    { "SPL", 0x5d, 0x00 },
+    { "SPH", 0x5e, 0x00 },
+    { "SREG", 0x5f, 0x00 },
+    { "WDTCSR", 0x60, 0x00 },
+    { "CLKPR", 0x61, 0x00 },
+    { "XFDCSR", 0x62, 0x00 },
+    { "PRR2", 0x63, 0x00 },
+    { "PRR -- PRR0", 0x64, 0x00 },
+    { "PRR1", 0x65, 0x00 },
+    { "OSCCAL", 0x66, 0x00 },
+    { "PCICR", 0x68, 0x00 },
+    { "EICRA", 0x69, 0x00 },
+    { "PCMSK0", 0x6b, 0x00 },
+    { "PCMSK1", 0x6c, 0x00 },
+    { "PCMSK2", 0x6d, 0x00 },
+    { "TIMSK0", 0x6e, 0x00 },
+    { "TIMSK1", 0x6f, 0x00 },
+    { "TIMSK2", 0x70, 0x00 },
+    { "TIMSK3", 0x71, 0x00 },
+    { "TIMSK4", 0x72, 0x00 },
+    { "PCMSK3", 0x73, 0x00 },
+    { "PCMSK4", 0x74, 0x00 },
+    { "ADCL", 0x78, IO_REG_RSE },
+    { "ADCH", 0x79, IO_REG_RSE },
+    { "ADCSRA", 0x7a, 0x00 },
+    { "ADCSRB", 0x7b, 0x00 },
+    { "ADMUX", 0x7c, 0x00 },
+    { "DIDR0", 0x7e, 0x00 },
+    { "DIDR1", 0x7f, 0x00 },
+    { "TCCR1A", 0x80, 0x00 },
+    { "TCCR1B", 0x81, 0x00 },
+    { "TCCR1C", 0x82, 0x00 },
+    { "TCNT1L", 0x84, 0x00 },
+    { "TCNT1H", 0x85, 0x00 },
+    { "ICR1L", 0x86, 0x00 },
+    { "ICR1H", 0x87, 0x00 },
+    { "OCR1AL", 0x88, 0x00 },
+    { "OCR1AH", 0x89, 0x00 },
+    { "OCR1BL", 0x8a, 0x00 },
+    { "OCR1BH", 0x8b, 0x00 },
+    { "TCCR3A", 0x90, 0x00 },
+    { "TCCR3B", 0x91, 0x00 },
+    { "TCCR3C", 0x92, 0x00 },
+    { "TCNT3L", 0x94, 0x00 },
+    { "TCNT3H", 0x95, 0x00 },
+    { "ICR3L", 0x96, 0x00 },
+    { "ICR3H", 0x97, 0x00 },
+    { "OCR3AL", 0x98, 0x00 },
+    { "OCR3AH", 0x99, 0x00 },
+    { "OCR3BL", 0x9a, 0x00 },
+    { "OCR3BH", 0x9b, 0x00 },
+    { "TCCR4A", 0xa0, 0x00 },
+    { "TCCR4B", 0xa1, 0x00 },
+    { "TCCR4C", 0xa2, 0x00 },
+    { "TCNT4L", 0xa4, 0x00 },
+    { "TCNT4H", 0xa5, 0x00 },
+    { "ICR4L", 0xa6, 0x00 },
+    { "ICR4H", 0xa7, 0x00 },
+    { "OCR4AL", 0xa8, 0x00 },
+    { "OCR4AH", 0xa9, 0x00 },
+    { "OCR4BL", 0xaa, 0x00 },
+    { "OCR4BH", 0xab, 0x00 },
+    { "SPCR1", 0xac, 0x00 },
+    { "SPSR1", 0xad, 0x00 },
+    { "SPDR1", 0xae, 0x00 },
+    { "TCCR2A", 0xb0, 0x00 },
+    { "TCCR2B", 0xb1, 0x00 },
+    { "TCNT2", 0xb2, 0x00 },
+    { "OCR2A", 0xb3, 0x00 },
+    { "OCR2B", 0xb4, 0x00 },
+    { "ASSR", 0xb6, 0x00 },
+    { "TWBR0", 0xb8, 0x00 },
+    { "TWSR0", 0xb9, 0x00 },
+    { "TWAR0", 0xba, 0x00 },
+    { "TWDR0", 0xbb, 0x00 },
+    { "TWCR0", 0xbc, 0x00 },
+    { "TWAMR0", 0xbd, 0x00 },
+    { "UCSR0A", 0xc0, 0x00 },
+    { "UCSR0B", 0xc1, 0x00 },
+    { "UCSR0C", 0xc2, 0x00 },
+    { "UCSR0D", 0xc3, 0x00 },
+    { "UBRR0L", 0xc4, 0x00 },
+    { "UBRR0H", 0xc5, 0x00 },
+    { "UDR0", 0xc6, IO_REG_RSE },
+    { "UCSR1A", 0xc8, 0x00 },
+    { "UCSR1B", 0xc9, 0x00 },
+    { "UCSR1C", 0xca, 0x00 },
+    { "UCSR1D", 0xcb, 0x00 },
+    { "UBRR1L", 0xcc, 0x00 },
+    { "UBRR1H", 0xcd, 0x00 },
+    { "UDR1", 0xce, IO_REG_RSE },
+    { "UCSR2A", 0xd0, 0x00 },
+    { "UCSR2B", 0xd1, 0x00 },
+    { "UCSR2C", 0xd2, 0x00 },
+    { "UCSR2D", 0xd3, 0x00 },
+    { "UBRR2L", 0xd4, 0x00 },
+    { "UBRR2H", 0xd5, 0x00 },
+    { "UDR2", 0xd6, IO_REG_RSE },
+    { "TWBR1", 0xd8, 0x00 },
+    { "TWSR1", 0xd9, 0x00 },
+    { "TWAR1", 0xda, 0x00 },
+    { "TWDR1", 0xdb, 0x00 },
+    { "TWCR1", 0xdc, 0x00 },
+    { "TWAMR1", 0xdd, 0x00 },
+    { 0, 0, 0 }
+};
+
+
 gdb_io_reg_def_type atmega644_io_registers[] =
 {
     { "PINA", 0x20, 0x00 },
@@ -4306,6 +4459,628 @@ gdb_io_reg_def_type attiny261_io_registers[] =
 };
 
 
+gdb_io_reg_def_type attiny402_io_registers[] =
+{
+    { "VPORTA_DIR", 0x0, 0x00 },
+    { "VPORTA_OUT", 0x1, 0x00 },
+    { "VPORTA_IN" , 0x2, 0x00 },
+    { "VPORTA_INTFLAGS", 0x3, 0x00 },
+    { "VPORTB_DIR", 0x4, 0x00 },
+    { "VPORTB_OUT", 0x5, 0x00 },
+    { "VPORTB_IN" , 0x6, 0x00 },
+    { "VPORTB_INTFLAGS", 0x7, 0x00 },
+    { "VPORTC_DIR", 0x8, 0x00 },
+    { "VPORTC_OUT", 0x9, 0x00 },
+    { "VPORTC_IN" , 0xA, 0x00 },
+    { "VPORTC_INTFLAGS", 0xB, 0x00 },
+    { "GPIO_GPIOR0", 0x1C, 0x00 },
+    { "GPIO_GPIOR1", 0x1D, 0x00 },
+    { "GPIO_GPIOR2", 0x1E, 0x00 },
+    { "GPIO_GPIOR3", 0x1F, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "RSTCTRL_RSTFR", 0x40, 0x00 },
+    { "RSTCTRL_SWRR", 0x41, 0x00 },
+    { "SLPCTRL_CTRLA", 0x50, 0x00 },
+    { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 },
+    { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 },
+    { "CLKCTRL_MCLKLOCK", 0x62, 0x00 },
+    { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 },
+    { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 },
+    { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 },
+    { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 },
+    { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 },
+    { "BOD_CTRLA" , 0x80, 0x00 },
+    { "BOD_CTRLB" , 0x81, 0x00 },
+    { "BOD_VLMCTRLA", 0x88, 0x00 },
+    { "BOD_INTCTRL", 0x89, 0x00 },
+    { "BOD_INTFLAGS", 0x8A, 0x00 },
+    { "BOD_STATUS", 0x8B, 0x00 },
+    { "VREF_CTRLA", 0xA0, 0x00 },
+    { "VREF_CTRLB", 0xA1, 0x00 },
+    { "WDT_CTRLA" , 0x100, 0x00 },
+    { "WDT_STATUS", 0x101, 0x00 },
+    { "CPUINT_CTRLA", 0x110, 0x00 },
+    { "CPUINT_STATUS", 0x111, 0x00 },
+    { "CPUINT_LVL0PRI", 0x112, 0x00 },
+    { "CPUINT_LVL1VEC", 0x113, 0x00 },
+    { "CRCSCAN_CTRLA", 0x120, 0x00 },
+    { "CRCSCAN_CTRLB", 0x121, 0x00 },
+    { "CRCSCAN_STATUS", 0x122, 0x00 },
+    { "RTC_CTRLA" , 0x140, 0x00 },
+    { "RTC_STATUS", 0x141, 0x00 },
+    { "RTC_INTCTRL", 0x142, 0x00 },
+    { "RTC_INTFLAGS", 0x143, 0x00 },
+    { "RTC_TEMP"  , 0x144, 0x00 },
+    { "RTC_DBGCTRL", 0x145, 0x00 },
+    { "RTC_CLKSEL", 0x147, 0x00 },
+    { "RTC_CNTL"  , 0x148, 0x00 },
+    { "RTC_CNTH"  , 0x149, 0x00 },
+    { "RTC_PERL"  , 0x14A, 0x00 },
+    { "RTC_PERH"  , 0x14B, 0x00 },
+    { "RTC_CMPL"  , 0x14C, 0x00 },
+    { "RTC_CMPH"  , 0x14D, 0x00 },
+    { "RTC_PITCTRLA", 0x150, 0x00 },
+    { "RTC_PITSTATUS", 0x151, 0x00 },
+    { "RTC_PITINTCTRL", 0x152, 0x00 },
+    { "RTC_PITINTFLAGS", 0x153, 0x00 },
+    { "RTC_PITDBGCTRL", 0x155, 0x00 },
+    { "EVSYS_ASYNCSTROBE", 0x180, 0x00 },
+    { "EVSYS_SYNCSTROBE", 0x181, 0x00 },
+    { "EVSYS_ASYNCCH0", 0x182, 0x00 },
+    { "EVSYS_ASYNCCH1", 0x183, 0x00 },
+    { "EVSYS_SYNCCH0", 0x18A, 0x00 },
+    { "EVSYS_SYNCCH1", 0x18B, 0x00 },
+    { "EVSYS_ASYNCUSER0", 0x192, 0x00 },
+    { "EVSYS_ASYNCUSER1", 0x193, 0x00 },
+    { "EVSYS_ASYNCUSER2", 0x194, 0x00 },
+    { "EVSYS_ASYNCUSER3", 0x195, 0x00 },
+    { "EVSYS_ASYNCUSER4", 0x196, 0x00 },
+    { "EVSYS_ASYNCUSER5", 0x197, 0x00 },
+    { "EVSYS_ASYNCUSER6", 0x198, 0x00 },
+    { "EVSYS_ASYNCUSER7", 0x199, 0x00 },
+    { "EVSYS_ASYNCUSER8", 0x19A, 0x00 },
+    { "EVSYS_ASYNCUSER9", 0x19B, 0x00 },
+    { "EVSYS_ASYNCUSER10", 0x19C, 0x00 },
+    { "EVSYS_SYNCUSER0", 0x1A2, 0x00 },
+    { "CCL_CTRLA" , 0x1C0, 0x00 },
+    { "CCL_SEQCTRL0", 0x1C1, 0x00 },
+    { "CCL_LUT0CTRLA", 0x1C5, 0x00 },
+    { "CCL_LUT0CTRLB", 0x1C6, 0x00 },
+    { "CCL_LUT0CTRLC", 0x1C7, 0x00 },
+    { "CCL_TRUTH0", 0x1C8, 0x00 },
+    { "CCL_LUT1CTRLA", 0x1C9, 0x00 },
+    { "CCL_LUT1CTRLB", 0x1CA, 0x00 },
+    { "CCL_LUT1CTRLC", 0x1CB, 0x00 },
+    { "CCL_TRUTH1", 0x1CC, 0x00 },
+    { "PORTMUX_CTRLA", 0x200, 0x00 },
+    { "PORTMUX_CTRLB", 0x201, 0x00 },
+    { "PORTMUX_CTRLC", 0x202, 0x00 },
+    { "PORTMUX_CTRLD", 0x203, 0x00 },
+    { "PORTA_DIR" , 0x400, 0x00 },
+    { "PORTA_DIRSET", 0x401, 0x00 },
+    { "PORTA_DIRCLR", 0x402, 0x00 },
+    { "PORTA_DIRTGL", 0x403, 0x00 },
+    { "PORTA_OUT" , 0x404, 0x00 },
+    { "PORTA_OUTSET", 0x405, 0x00 },
+    { "PORTA_OUTCLR", 0x406, 0x00 },
+    { "PORTA_OUTTGL", 0x407, 0x00 },
+    { "PORTA_IN"  , 0x408, 0x00 },
+    { "PORTA_INTFLAGS", 0x409, 0x00 },
+    { "PORTA_PIN0CTRL", 0x410, 0x00 },
+    { "PORTA_PIN1CTRL", 0x411, 0x00 },
+    { "PORTA_PIN2CTRL", 0x412, 0x00 },
+    { "PORTA_PIN3CTRL", 0x413, 0x00 },
+    { "PORTA_PIN4CTRL", 0x414, 0x00 },
+    { "PORTA_PIN5CTRL", 0x415, 0x00 },
+    { "PORTA_PIN6CTRL", 0x416, 0x00 },
+    { "PORTA_PIN7CTRL", 0x417, 0x00 },
+    { "ADC0_CTRLA", 0x600, 0x00 },
+    { "ADC0_CTRLB", 0x601, 0x00 },
+    { "ADC0_CTRLC", 0x602, 0x00 },
+    { "ADC0_CTRLD", 0x603, 0x00 },
+    { "ADC0_CTRLE", 0x604, 0x00 },
+    { "ADC0_SAMPCTRL", 0x605, 0x00 },
+    { "ADC0_MUXPOS", 0x606, 0x00 },
+    { "ADC0_COMMAND", 0x608, 0x00 },
+    { "ADC0_EVCTRL", 0x609, 0x00 },
+    { "ADC0_INTCTRL", 0x60A, 0x00 },
+    { "ADC0_INTFLAGS", 0x60B, 0x00 },
+    { "ADC0_DBGCTRL", 0x60C, 0x00 },
+    { "ADC0_TEMP" , 0x60D, 0x00 },
+    { "ADC0_RESL" , 0x610, 0x00 },
+    { "ADC0_RESH" , 0x611, 0x00 },
+    { "ADC0_WINLTL", 0x612, 0x00 },
+    { "ADC0_WINLTH", 0x613, 0x00 },
+    { "ADC0_WINHTL", 0x614, 0x00 },
+    { "ADC0_WINHTH", 0x615, 0x00 },
+    { "ADC0_CALIB", 0x616, 0x00 },
+    { "AC0_CTRLA" , 0x670, 0x00 },
+    { "AC0_MUXCTRLA", 0x672, 0x00 },
+    { "AC0_INTCTRL", 0x676, 0x00 },
+    { "AC0_STATUS", 0x677, 0x00 },
+    { "USART0_RXDATAL", 0x800, 0x00 },
+    { "USART0_RXDATAH", 0x801, 0x00 },
+    { "USART0_TXDATAL", 0x802, 0x00 },
+    { "USART0_TXDATAH", 0x803, 0x00 },
+    { "USART0_STATUS", 0x804, 0x00 },
+    { "USART0_CTRLA", 0x805, 0x00 },
+    { "USART0_CTRLB", 0x806, 0x00 },
+    { "USART0_CTRLC", 0x807, 0x00 },
+    { "USART0_BAUDL", 0x808, 0x00 },
+    { "USART0_BAUDH", 0x809, 0x00 },
+    { "USART0_DBGCTRL", 0x80B, 0x00 },
+    { "USART0_EVCTRL", 0x80C, 0x00 },
+    { "USART0_TXPLCTRL", 0x80D, 0x00 },
+    { "USART0_RXPLCTRL", 0x80E, 0x00 },
+    { "TWI0_CTRLA", 0x810, 0x00 },
+    { "TWI0_DBGCTRL", 0x812, 0x00 },
+    { "TWI0_MCTRLA", 0x813, 0x00 },
+    { "TWI0_MCTRLB", 0x814, 0x00 },
+    { "TWI0_MSTATUS", 0x815, 0x00 },
+    { "TWI0_MBAUD", 0x816, 0x00 },
+    { "TWI0_MADDR", 0x817, 0x00 },
+    { "TWI0_MDATA", 0x818, 0x00 },
+    { "TWI0_SCTRLA", 0x819, 0x00 },
+    { "TWI0_SCTRLB", 0x81A, 0x00 },
+    { "TWI0_SSTATUS", 0x81B, 0x00 },
+    { "TWI0_SADDR", 0x81C, 0x00 },
+    { "TWI0_SDATA", 0x81D, 0x00 },
+    { "TWI0_SADDRMASK", 0x81E, 0x00 },
+    { "SPI0_CTRLA", 0x820, 0x00 },
+    { "SPI0_CTRLB", 0x821, 0x00 },
+    { "SPI0_INTCTRL", 0x822, 0x00 },
+    { "SPI0_INTFLAGS", 0x823, 0x00 },
+    { "SPI0_DATA" , 0x824, 0x00 },
+    { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 },
+    { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 },
+    { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 },
+    { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 },
+    { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 },
+    { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 },
+    { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 },
+    { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 },
+    { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 },
+    { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 },
+    { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 },
+    { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 },
+    { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 },
+    { "TCA0_SPLIT_LCNT", 0xA20, 0x00 },
+    { "TCA0_SPLIT_HCNT", 0xA21, 0x00 },
+    { "TCA0_SPLIT_LPER", 0xA26, 0x00 },
+    { "TCA0_SPLIT_HPER", 0xA27, 0x00 },
+    { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 },
+    { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 },
+    { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 },
+    { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 },
+    { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 },
+    { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 },
+    { "TCA0_SINGLE_PERBUFL", 0xA36, 0x00 },
+    { "TCA0_SINGLE_PERBUFH", 0xA37, 0x00 },
+    { "TCA0_SINGLE_CMP0BUFL", 0xA38, 0x00 },
+    { "TCA0_SINGLE_CMP0BUFH", 0xA39, 0x00 },
+    { "TCA0_SINGLE_CMP1BUFL", 0xA3A, 0x00 },
+    { "TCA0_SINGLE_CMP1BUFH", 0xA3B, 0x00 },
+    { "TCA0_SINGLE_CMP2BUFL", 0xA3C, 0x00 },
+    { "TCA0_SINGLE_CMP2BUFH", 0xA3D, 0x00 },
+    { "TCB0_CTRLA", 0xA40, 0x00 },
+    { "TCB0_CTRLB", 0xA41, 0x00 },
+    { "TCB0_EVCTRL", 0xA44, 0x00 },
+    { "TCB0_INTCTRL", 0xA45, 0x00 },
+    { "TCB0_INTFLAGS", 0xA46, 0x00 },
+    { "TCB0_STATUS", 0xA47, 0x00 },
+    { "TCB0_DBGCTRL", 0xA48, 0x00 },
+    { "TCB0_TEMP" , 0xA49, 0x00 },
+    { "TCB0_CNTL" , 0xA4A, 0x00 },
+    { "TCB0_CNTH" , 0xA4B, 0x00 },
+    { "TCB0_CCMPL", 0xA4C, 0x00 },
+    { "TCB0_CCMPH", 0xA4D, 0x00 },
+    { "SYSCFG_REVID", 0xF01, 0x00 },
+    { "SYSCFG_EXTBRK", 0xF02, 0x00 },
+    { "NVMCTRL_CTRLA", 0x1000, 0x00 },
+    { "NVMCTRL_CTRLB", 0x1001, 0x00 },
+    { "NVMCTRL_STATUS", 0x1002, 0x00 },
+    { "NVMCTRL_INTCTRL", 0x1003, 0x00 },
+    { "NVMCTRL_INTFLAGS", 0x1004, 0x00 },
+    { "NVMCTRL_DATAL", 0x1006, 0x00 },
+    { "NVMCTRL_DATAH", 0x1007, 0x00 },
+    { "NVMCTRL_ADDRL", 0x1008, 0x00 },
+    { "NVMCTRL_ADDRH", 0x1009, 0x00 },
+    { "SIGROW_DEVICEID0", 0x1100, 0x00 },
+    { "SIGROW_DEVICEID1", 0x1101, 0x00 },
+    { "SIGROW_DEVICEID2", 0x1102, 0x00 },
+    { "SIGROW_SERNUM0", 0x1103, 0x00 },
+    { "SIGROW_SERNUM1", 0x1104, 0x00 },
+    { "SIGROW_SERNUM2", 0x1105, 0x00 },
+    { "SIGROW_SERNUM3", 0x1106, 0x00 },
+    { "SIGROW_SERNUM4", 0x1107, 0x00 },
+    { "SIGROW_SERNUM5", 0x1108, 0x00 },
+    { "SIGROW_SERNUM6", 0x1109, 0x00 },
+    { "SIGROW_SERNUM7", 0x110A, 0x00 },
+    { "SIGROW_SERNUM8", 0x110B, 0x00 },
+    { "SIGROW_SERNUM9", 0x110C, 0x00 },
+    { "SIGROW_TEMPSENSE0", 0x1120, 0x00 },
+    { "SIGROW_TEMPSENSE1", 0x1121, 0x00 },
+    { "SIGROW_OSC16ERR3V", 0x1122, 0x00 },
+    { "SIGROW_OSC16ERR5V", 0x1123, 0x00 },
+    { "SIGROW_OSC20ERR3V", 0x1124, 0x00 },
+    { "SIGROW_OSC20ERR5V", 0x1125, 0x00 },
+    { "FUSE_WDTCFG", 0x1280, 0x00 },
+    { "FUSE_BODCFG", 0x1281, 0x00 },
+    { "FUSE_OSCCFG", 0x1282, 0x00 },
+    { "FUSE_TCD0CFG", 0x1284, 0x00 },
+    { "FUSE_SYSCFG0", 0x1285, 0x00 },
+    { "FUSE_SYSCFG1", 0x1286, 0x00 },
+    { "FUSE_APPEND", 0x1287, 0x00 },
+    { "FUSE_BOOTEND", 0x1288, 0x00 },
+    { "LOCKBIT_LOCKBIT", 0x128A, 0x00 },
+    { "USERROW_USERROW0", 0x1300, 0x00 },
+    { "USERROW_USERROW1", 0x1301, 0x00 },
+    { "USERROW_USERROW2", 0x1302, 0x00 },
+    { "USERROW_USERROW3", 0x1303, 0x00 },
+    { "USERROW_USERROW4", 0x1304, 0x00 },
+    { "USERROW_USERROW5", 0x1305, 0x00 },
+    { "USERROW_USERROW6", 0x1306, 0x00 },
+    { "USERROW_USERROW7", 0x1307, 0x00 },
+    { "USERROW_USERROW8", 0x1308, 0x00 },
+    { "USERROW_USERROW9", 0x1309, 0x00 },
+    { "USERROW_USERROW10", 0x130A, 0x00 },
+    { "USERROW_USERROW11", 0x130B, 0x00 },
+    { "USERROW_USERROW12", 0x130C, 0x00 },
+    { "USERROW_USERROW13", 0x130D, 0x00 },
+    { "USERROW_USERROW14", 0x130E, 0x00 },
+    { "USERROW_USERROW15", 0x130F, 0x00 },
+    { "USERROW_USERROW16", 0x1310, 0x00 },
+    { "USERROW_USERROW17", 0x1311, 0x00 },
+    { "USERROW_USERROW18", 0x1312, 0x00 },
+    { "USERROW_USERROW19", 0x1313, 0x00 },
+    { "USERROW_USERROW20", 0x1314, 0x00 },
+    { "USERROW_USERROW21", 0x1315, 0x00 },
+    { "USERROW_USERROW22", 0x1316, 0x00 },
+    { "USERROW_USERROW23", 0x1317, 0x00 },
+    { "USERROW_USERROW24", 0x1318, 0x00 },
+    { "USERROW_USERROW25", 0x1319, 0x00 },
+    { "USERROW_USERROW26", 0x131A, 0x00 },
+    { "USERROW_USERROW27", 0x131B, 0x00 },
+    { "USERROW_USERROW28", 0x131C, 0x00 },
+    { "USERROW_USERROW29", 0x131D, 0x00 },
+    { "USERROW_USERROW30", 0x131E, 0x00 },
+    { "USERROW_USERROW31", 0x131F, 0x00 },
+    { 0, 0, 0}
+};
+
+
+gdb_io_reg_def_type attiny412_io_registers[] =
+{
+    { "VPORTA_DIR", 0x0, 0x00 },
+    { "VPORTA_OUT", 0x1, 0x00 },
+    { "VPORTA_IN" , 0x2, 0x00 },
+    { "VPORTA_INTFLAGS", 0x3, 0x00 },
+    { "VPORTB_DIR", 0x4, 0x00 },
+    { "VPORTB_OUT", 0x5, 0x00 },
+    { "VPORTB_IN" , 0x6, 0x00 },
+    { "VPORTB_INTFLAGS", 0x7, 0x00 },
+    { "VPORTC_DIR", 0x8, 0x00 },
+    { "VPORTC_OUT", 0x9, 0x00 },
+    { "VPORTC_IN" , 0xA, 0x00 },
+    { "VPORTC_INTFLAGS", 0xB, 0x00 },
+    { "GPIO_GPIOR0", 0x1C, 0x00 },
+    { "GPIO_GPIOR1", 0x1D, 0x00 },
+    { "GPIO_GPIOR2", 0x1E, 0x00 },
+    { "GPIO_GPIOR3", 0x1F, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "RSTCTRL_RSTFR", 0x40, 0x00 },
+    { "RSTCTRL_SWRR", 0x41, 0x00 },
+    { "SLPCTRL_CTRLA", 0x50, 0x00 },
+    { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 },
+    { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 },
+    { "CLKCTRL_MCLKLOCK", 0x62, 0x00 },
+    { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 },
+    { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 },
+    { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 },
+    { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 },
+    { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 },
+    { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 },
+    { "BOD_CTRLA" , 0x80, 0x00 },
+    { "BOD_CTRLB" , 0x81, 0x00 },
+    { "BOD_VLMCTRLA", 0x88, 0x00 },
+    { "BOD_INTCTRL", 0x89, 0x00 },
+    { "BOD_INTFLAGS", 0x8A, 0x00 },
+    { "BOD_STATUS", 0x8B, 0x00 },
+    { "VREF_CTRLA", 0xA0, 0x00 },
+    { "VREF_CTRLB", 0xA1, 0x00 },
+    { "WDT_CTRLA" , 0x100, 0x00 },
+    { "WDT_STATUS", 0x101, 0x00 },
+    { "CPUINT_CTRLA", 0x110, 0x00 },
+    { "CPUINT_STATUS", 0x111, 0x00 },
+    { "CPUINT_LVL0PRI", 0x112, 0x00 },
+    { "CPUINT_LVL1VEC", 0x113, 0x00 },
+    { "CRCSCAN_CTRLA", 0x120, 0x00 },
+    { "CRCSCAN_CTRLB", 0x121, 0x00 },
+    { "CRCSCAN_STATUS", 0x122, 0x00 },
+    { "RTC_CTRLA" , 0x140, 0x00 },
+    { "RTC_STATUS", 0x141, 0x00 },
+    { "RTC_INTCTRL", 0x142, 0x00 },
+    { "RTC_INTFLAGS", 0x143, 0x00 },
+    { "RTC_TEMP"  , 0x144, 0x00 },
+    { "RTC_DBGCTRL", 0x145, 0x00 },
+    { "RTC_CLKSEL", 0x147, 0x00 },
+    { "RTC_CNTL"  , 0x148, 0x00 },
+    { "RTC_CNTH"  , 0x149, 0x00 },
+    { "RTC_PERL"  , 0x14A, 0x00 },
+    { "RTC_PERH"  , 0x14B, 0x00 },
+    { "RTC_CMPL"  , 0x14C, 0x00 },
+    { "RTC_CMPH"  , 0x14D, 0x00 },
+    { "RTC_PITCTRLA", 0x150, 0x00 },
+    { "RTC_PITSTATUS", 0x151, 0x00 },
+    { "RTC_PITINTCTRL", 0x152, 0x00 },
+    { "RTC_PITINTFLAGS", 0x153, 0x00 },
+    { "RTC_PITDBGCTRL", 0x155, 0x00 },
+    { "EVSYS_ASYNCSTROBE", 0x180, 0x00 },
+    { "EVSYS_SYNCSTROBE", 0x181, 0x00 },
+    { "EVSYS_ASYNCCH0", 0x182, 0x00 },
+    { "EVSYS_ASYNCCH1", 0x183, 0x00 },
+    { "EVSYS_ASYNCCH2", 0x184, 0x00 },
+    { "EVSYS_ASYNCCH3", 0x185, 0x00 },
+    { "EVSYS_SYNCCH0", 0x18A, 0x00 },
+    { "EVSYS_SYNCCH1", 0x18B, 0x00 },
+    { "EVSYS_ASYNCUSER0", 0x192, 0x00 },
+    { "EVSYS_ASYNCUSER1", 0x193, 0x00 },
+    { "EVSYS_ASYNCUSER2", 0x194, 0x00 },
+    { "EVSYS_ASYNCUSER3", 0x195, 0x00 },
+    { "EVSYS_ASYNCUSER4", 0x196, 0x00 },
+    { "EVSYS_ASYNCUSER5", 0x197, 0x00 },
+    { "EVSYS_ASYNCUSER6", 0x198, 0x00 },
+    { "EVSYS_ASYNCUSER7", 0x199, 0x00 },
+    { "EVSYS_ASYNCUSER8", 0x19A, 0x00 },
+    { "EVSYS_ASYNCUSER9", 0x19B, 0x00 },
+    { "EVSYS_ASYNCUSER10", 0x19C, 0x00 },
+    { "EVSYS_SYNCUSER0", 0x1A2, 0x00 },
+    { "EVSYS_SYNCUSER1", 0x1A3, 0x00 },
+    { "CCL_CTRLA" , 0x1C0, 0x00 },
+    { "CCL_SEQCTRL0", 0x1C1, 0x00 },
+    { "CCL_LUT0CTRLA", 0x1C5, 0x00 },
+    { "CCL_LUT0CTRLB", 0x1C6, 0x00 },
+    { "CCL_LUT0CTRLC", 0x1C7, 0x00 },
+    { "CCL_TRUTH0", 0x1C8, 0x00 },
+    { "CCL_LUT1CTRLA", 0x1C9, 0x00 },
+    { "CCL_LUT1CTRLB", 0x1CA, 0x00 },
+    { "CCL_LUT1CTRLC", 0x1CB, 0x00 },
+    { "CCL_TRUTH1", 0x1CC, 0x00 },
+    { "PORTMUX_CTRLA", 0x200, 0x00 },
+    { "PORTMUX_CTRLB", 0x201, 0x00 },
+    { "PORTMUX_CTRLC", 0x202, 0x00 },
+    { "PORTMUX_CTRLD", 0x203, 0x00 },
+    { "PORTA_DIR" , 0x400, 0x00 },
+    { "PORTA_DIRSET", 0x401, 0x00 },
+    { "PORTA_DIRCLR", 0x402, 0x00 },
+    { "PORTA_DIRTGL", 0x403, 0x00 },
+    { "PORTA_OUT" , 0x404, 0x00 },
+    { "PORTA_OUTSET", 0x405, 0x00 },
+    { "PORTA_OUTCLR", 0x406, 0x00 },
+    { "PORTA_OUTTGL", 0x407, 0x00 },
+    { "PORTA_IN"  , 0x408, 0x00 },
+    { "PORTA_INTFLAGS", 0x409, 0x00 },
+    { "PORTA_PIN0CTRL", 0x410, 0x00 },
+    { "PORTA_PIN1CTRL", 0x411, 0x00 },
+    { "PORTA_PIN2CTRL", 0x412, 0x00 },
+    { "PORTA_PIN3CTRL", 0x413, 0x00 },
+    { "PORTA_PIN4CTRL", 0x414, 0x00 },
+    { "PORTA_PIN5CTRL", 0x415, 0x00 },
+    { "PORTA_PIN6CTRL", 0x416, 0x00 },
+    { "PORTA_PIN7CTRL", 0x417, 0x00 },
+    { "ADC0_CTRLA", 0x600, 0x00 },
+    { "ADC0_CTRLB", 0x601, 0x00 },
+    { "ADC0_CTRLC", 0x602, 0x00 },
+    { "ADC0_CTRLD", 0x603, 0x00 },
+    { "ADC0_CTRLE", 0x604, 0x00 },
+    { "ADC0_SAMPCTRL", 0x605, 0x00 },
+    { "ADC0_MUXPOS", 0x606, 0x00 },
+    { "ADC0_COMMAND", 0x608, 0x00 },
+    { "ADC0_EVCTRL", 0x609, 0x00 },
+    { "ADC0_INTCTRL", 0x60A, 0x00 },
+    { "ADC0_INTFLAGS", 0x60B, 0x00 },
+    { "ADC0_DBGCTRL", 0x60C, 0x00 },
+    { "ADC0_TEMP" , 0x60D, 0x00 },
+    { "ADC0_RESL" , 0x610, 0x00 },
+    { "ADC0_RESH" , 0x611, 0x00 },
+    { "ADC0_WINLTL", 0x612, 0x00 },
+    { "ADC0_WINLTH", 0x613, 0x00 },
+    { "ADC0_WINHTL", 0x614, 0x00 },
+    { "ADC0_WINHTH", 0x615, 0x00 },
+    { "ADC0_CALIB", 0x616, 0x00 },
+    { "AC0_CTRLA" , 0x670, 0x00 },
+    { "AC0_MUXCTRLA", 0x672, 0x00 },
+    { "AC0_INTCTRL", 0x676, 0x00 },
+    { "AC0_STATUS", 0x677, 0x00 },
+    { "DAC0_CTRLA", 0x680, 0x00 },
+    { "DAC0_DATA" , 0x681, 0x00 },
+    { "USART0_RXDATAL", 0x800, 0x00 },
+    { "USART0_RXDATAH", 0x801, 0x00 },
+    { "USART0_TXDATAL", 0x802, 0x00 },
+    { "USART0_TXDATAH", 0x803, 0x00 },
+    { "USART0_STATUS", 0x804, 0x00 },
+    { "USART0_CTRLA", 0x805, 0x00 },
+    { "USART0_CTRLB", 0x806, 0x00 },
+    { "USART0_CTRLC", 0x807, 0x00 },
+    { "USART0_BAUDL", 0x808, 0x00 },
+    { "USART0_BAUDH", 0x809, 0x00 },
+    { "USART0_DBGCTRL", 0x80B, 0x00 },
+    { "USART0_EVCTRL", 0x80C, 0x00 },
+    { "USART0_TXPLCTRL", 0x80D, 0x00 },
+    { "USART0_RXPLCTRL", 0x80E, 0x00 },
+    { "TWI0_CTRLA", 0x810, 0x00 },
+    { "TWI0_DBGCTRL", 0x812, 0x00 },
+    { "TWI0_MCTRLA", 0x813, 0x00 },
+    { "TWI0_MCTRLB", 0x814, 0x00 },
+    { "TWI0_MSTATUS", 0x815, 0x00 },
+    { "TWI0_MBAUD", 0x816, 0x00 },
+    { "TWI0_MADDR", 0x817, 0x00 },
+    { "TWI0_MDATA", 0x818, 0x00 },
+    { "TWI0_SCTRLA", 0x819, 0x00 },
+    { "TWI0_SCTRLB", 0x81A, 0x00 },
+    { "TWI0_SSTATUS", 0x81B, 0x00 },
+    { "TWI0_SADDR", 0x81C, 0x00 },
+    { "TWI0_SDATA", 0x81D, 0x00 },
+    { "TWI0_SADDRMASK", 0x81E, 0x00 },
+    { "SPI0_CTRLA", 0x820, 0x00 },
+    { "SPI0_CTRLB", 0x821, 0x00 },
+    { "SPI0_INTCTRL", 0x822, 0x00 },
+    { "SPI0_INTFLAGS", 0x823, 0x00 },
+    { "SPI0_DATA" , 0x824, 0x00 },
+    { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 },
+    { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 },
+    { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 },
+    { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 },
+    { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 },
+    { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 },
+    { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 },
+    { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 },
+    { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 },
+    { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 },
+    { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 },
+    { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 },
+    { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 },
+    { "TCA0_SPLIT_LCNT", 0xA20, 0x00 },
+    { "TCA0_SPLIT_HCNT", 0xA21, 0x00 },
+    { "TCA0_SPLIT_LPER", 0xA26, 0x00 },
+    { "TCA0_SPLIT_HPER", 0xA27, 0x00 },
+    { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 },
+    { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 },
+    { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 },
+    { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 },
+    { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 },
+    { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 },
+    { "TCA0_SINGLE_PERBUFL", 0xA36, 0x00 },
+    { "TCA0_SINGLE_PERBUFH", 0xA37, 0x00 },
+    { "TCA0_SINGLE_CMP0BUFL", 0xA38, 0x00 },
+    { "TCA0_SINGLE_CMP0BUFH", 0xA39, 0x00 },
+    { "TCA0_SINGLE_CMP1BUFL", 0xA3A, 0x00 },
+    { "TCA0_SINGLE_CMP1BUFH", 0xA3B, 0x00 },
+    { "TCA0_SINGLE_CMP2BUFL", 0xA3C, 0x00 },
+    { "TCA0_SINGLE_CMP2BUFH", 0xA3D, 0x00 },
+    { "TCB0_CTRLA", 0xA40, 0x00 },
+    { "TCB0_CTRLB", 0xA41, 0x00 },
+    { "TCB0_EVCTRL", 0xA44, 0x00 },
+    { "TCB0_INTCTRL", 0xA45, 0x00 },
+    { "TCB0_INTFLAGS", 0xA46, 0x00 },
+    { "TCB0_STATUS", 0xA47, 0x00 },
+    { "TCB0_DBGCTRL", 0xA48, 0x00 },
+    { "TCB0_TEMP" , 0xA49, 0x00 },
+    { "TCB0_CNTL" , 0xA4A, 0x00 },
+    { "TCB0_CNTH" , 0xA4B, 0x00 },
+    { "TCB0_CCMPL", 0xA4C, 0x00 },
+    { "TCB0_CCMPH", 0xA4D, 0x00 },
+    { "TCD0_CTRLA", 0xA80, 0x00 },
+    { "TCD0_CTRLB", 0xA81, 0x00 },
+    { "TCD0_CTRLC", 0xA82, 0x00 },
+    { "TCD0_CTRLD", 0xA83, 0x00 },
+    { "TCD0_CTRLE", 0xA84, 0x00 },
+    { "TCD0_EVCTRLA", 0xA88, 0x00 },
+    { "TCD0_EVCTRLB", 0xA89, 0x00 },
+    { "TCD0_INTCTRL", 0xA8C, 0x00 },
+    { "TCD0_INTFLAGS", 0xA8D, 0x00 },
+    { "TCD0_STATUS", 0xA8E, 0x00 },
+    { "TCD0_INPUTCTRLA", 0xA90, 0x00 },
+    { "TCD0_INPUTCTRLB", 0xA91, 0x00 },
+    { "TCD0_FAULTCTRL", 0xA92, 0x00 },
+    { "TCD0_DLYCTRL", 0xA94, 0x00 },
+    { "TCD0_DLYVAL", 0xA95, 0x00 },
+    { "TCD0_DITCTRL", 0xA98, 0x00 },
+    { "TCD0_DITVAL", 0xA99, 0x00 },
+    { "TCD0_DBGCTRL", 0xA9E, 0x00 },
+    { "TCD0_CAPTUREAL", 0xAA2, 0x00 },
+    { "TCD0_CAPTUREAH", 0xAA3, 0x00 },
+    { "TCD0_CAPTUREBL", 0xAA4, 0x00 },
+    { "TCD0_CAPTUREBH", 0xAA5, 0x00 },
+    { "TCD0_CMPASETL", 0xAA8, 0x00 },
+    { "TCD0_CMPASETH", 0xAA9, 0x00 },
+    { "TCD0_CMPACLRL", 0xAAA, 0x00 },
+    { "TCD0_CMPACLRH", 0xAAB, 0x00 },
+    { "TCD0_CMPBSETL", 0xAAC, 0x00 },
+    { "TCD0_CMPBSETH", 0xAAD, 0x00 },
+    { "TCD0_CMPBCLRL", 0xAAE, 0x00 },
+    { "TCD0_CMPBCLRH", 0xAAF, 0x00 },
+    { "SYSCFG_REVID", 0xF01, 0x00 },
+    { "SYSCFG_EXTBRK", 0xF02, 0x00 },
+    { "NVMCTRL_CTRLA", 0x1000, 0x00 },
+    { "NVMCTRL_CTRLB", 0x1001, 0x00 },
+    { "NVMCTRL_STATUS", 0x1002, 0x00 },
+    { "NVMCTRL_INTCTRL", 0x1003, 0x00 },
+    { "NVMCTRL_INTFLAGS", 0x1004, 0x00 },
+    { "NVMCTRL_DATAL", 0x1006, 0x00 },
+    { "NVMCTRL_DATAH", 0x1007, 0x00 },
+    { "NVMCTRL_ADDRL", 0x1008, 0x00 },
+    { "NVMCTRL_ADDRH", 0x1009, 0x00 },
+    { "SIGROW_DEVICEID0", 0x1100, 0x00 },
+    { "SIGROW_DEVICEID1", 0x1101, 0x00 },
+    { "SIGROW_DEVICEID2", 0x1102, 0x00 },
+    { "SIGROW_SERNUM0", 0x1103, 0x00 },
+    { "SIGROW_SERNUM1", 0x1104, 0x00 },
+    { "SIGROW_SERNUM2", 0x1105, 0x00 },
+    { "SIGROW_SERNUM3", 0x1106, 0x00 },
+    { "SIGROW_SERNUM4", 0x1107, 0x00 },
+    { "SIGROW_SERNUM5", 0x1108, 0x00 },
+    { "SIGROW_SERNUM6", 0x1109, 0x00 },
+    { "SIGROW_SERNUM7", 0x110A, 0x00 },
+    { "SIGROW_SERNUM8", 0x110B, 0x00 },
+    { "SIGROW_SERNUM9", 0x110C, 0x00 },
+    { "SIGROW_TEMPSENSE0", 0x1120, 0x00 },
+    { "SIGROW_TEMPSENSE1", 0x1121, 0x00 },
+    { "SIGROW_OSC16ERR3V", 0x1122, 0x00 },
+    { "SIGROW_OSC16ERR5V", 0x1123, 0x00 },
+    { "SIGROW_OSC20ERR3V", 0x1124, 0x00 },
+    { "SIGROW_OSC20ERR5V", 0x1125, 0x00 },
+    { "FUSE_WDTCFG", 0x1280, 0x00 },
+    { "FUSE_BODCFG", 0x1281, 0x00 },
+    { "FUSE_OSCCFG", 0x1282, 0x00 },
+    { "FUSE_TCD0CFG", 0x1284, 0x00 },
+    { "FUSE_SYSCFG0", 0x1285, 0x00 },
+    { "FUSE_SYSCFG1", 0x1286, 0x00 },
+    { "FUSE_APPEND", 0x1287, 0x00 },
+    { "FUSE_BOOTEND", 0x1288, 0x00 },
+    { "LOCKBIT_LOCKBIT", 0x128A, 0x00 },
+    { "USERROW_USERROW0", 0x1300, 0x00 },
+    { "USERROW_USERROW1", 0x1301, 0x00 },
+    { "USERROW_USERROW2", 0x1302, 0x00 },
+    { "USERROW_USERROW3", 0x1303, 0x00 },
+    { "USERROW_USERROW4", 0x1304, 0x00 },
+    { "USERROW_USERROW5", 0x1305, 0x00 },
+    { "USERROW_USERROW6", 0x1306, 0x00 },
+    { "USERROW_USERROW7", 0x1307, 0x00 },
+    { "USERROW_USERROW8", 0x1308, 0x00 },
+    { "USERROW_USERROW9", 0x1309, 0x00 },
+    { "USERROW_USERROW10", 0x130A, 0x00 },
+    { "USERROW_USERROW11", 0x130B, 0x00 },
+    { "USERROW_USERROW12", 0x130C, 0x00 },
+    { "USERROW_USERROW13", 0x130D, 0x00 },
+    { "USERROW_USERROW14", 0x130E, 0x00 },
+    { "USERROW_USERROW15", 0x130F, 0x00 },
+    { "USERROW_USERROW16", 0x1310, 0x00 },
+    { "USERROW_USERROW17", 0x1311, 0x00 },
+    { "USERROW_USERROW18", 0x1312, 0x00 },
+    { "USERROW_USERROW19", 0x1313, 0x00 },
+    { "USERROW_USERROW20", 0x1314, 0x00 },
+    { "USERROW_USERROW21", 0x1315, 0x00 },
+    { "USERROW_USERROW22", 0x1316, 0x00 },
+    { "USERROW_USERROW23", 0x1317, 0x00 },
+    { "USERROW_USERROW24", 0x1318, 0x00 },
+    { "USERROW_USERROW25", 0x1319, 0x00 },
+    { "USERROW_USERROW26", 0x131A, 0x00 },
+    { "USERROW_USERROW27", 0x131B, 0x00 },
+    { "USERROW_USERROW28", 0x131C, 0x00 },
+    { "USERROW_USERROW29", 0x131D, 0x00 },
+    { "USERROW_USERROW30", 0x131E, 0x00 },
+    { "USERROW_USERROW31", 0x131F, 0x00 },
+    { 0, 0, 0}
+};
+
+
 gdb_io_reg_def_type attiny461_io_registers[] =
 {
     { "TCCR1E", 0x20, 0x00 },
@@ -4375,6 +5150,345 @@ gdb_io_reg_def_type attiny461_io_registers[] =
 };
 
 
+gdb_io_reg_def_type attiny814_io_registers[] =
+{
+    { "VPORTA_DIR", 0x0, 0x00 },
+    { "VPORTA_OUT", 0x1, 0x00 },
+    { "VPORTA_IN" , 0x2, 0x00 },
+    { "VPORTA_INTFLAGS", 0x3, 0x00 },
+    { "VPORTB_DIR", 0x4, 0x00 },
+    { "VPORTB_OUT", 0x5, 0x00 },
+    { "VPORTB_IN" , 0x6, 0x00 },
+    { "VPORTB_INTFLAGS", 0x7, 0x00 },
+    { "VPORTC_DIR", 0x8, 0x00 },
+    { "VPORTC_OUT", 0x9, 0x00 },
+    { "VPORTC_IN" , 0xA, 0x00 },
+    { "VPORTC_INTFLAGS", 0xB, 0x00 },
+    { "GPIO_GPIO0", 0x1C, 0x00 },
+    { "GPIO_GPIO1", 0x1D, 0x00 },
+    { "GPIO_GPIO2", 0x1E, 0x00 },
+    { "GPIO_GPIO3", 0x1F, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "RSTCTRL_RSTFR", 0x40, 0x00 },
+    { "RSTCTRL_SWRR", 0x41, 0x00 },
+    { "SLPCTRL_CTRLA", 0x50, 0x00 },
+    { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 },
+    { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 },
+    { "CLKCTRL_MCLKLOCK", 0x62, 0x00 },
+    { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 },
+    { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 },
+    { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 },
+    { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 },
+    { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 },
+    { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 },
+    { "BOD_CTRLA" , 0x80, 0x00 },
+    { "BOD_CTRLB" , 0x81, 0x00 },
+    { "BOD_VLMCTRLA", 0x88, 0x00 },
+    { "BOD_INTCTRL", 0x89, 0x00 },
+    { "BOD_INTFLAGS", 0x8A, 0x00 },
+    { "BOD_STATUS", 0x8B, 0x00 },
+    { "VREF_CTRLA", 0xA0, 0x00 },
+    { "VREF_CTRLB", 0xA1, 0x00 },
+    { "WDT_CTRLA" , 0x100, 0x00 },
+    { "WDT_STATUS", 0x101, 0x00 },
+    { "CPUINT_CTRLA", 0x110, 0x00 },
+    { "CPUINT_STATUS", 0x111, 0x00 },
+    { "CPUINT_LVL0PRI", 0x112, 0x00 },
+    { "CPUINT_LVL1VEC", 0x113, 0x00 },
+    { "CRCSCAN_CTRLA", 0x120, 0x00 },
+    { "CRCSCAN_CTRLB", 0x121, 0x00 },
+    { "CRCSCAN_STATUS", 0x122, 0x00 },
+    { "RTC_CTRLA" , 0x140, 0x00 },
+    { "RTC_STATUS", 0x141, 0x00 },
+    { "RTC_INTCTRL", 0x142, 0x00 },
+    { "RTC_INTFLAGS", 0x143, 0x00 },
+    { "RTC_TEMP"  , 0x144, 0x00 },
+    { "RTC_DBGCTRL", 0x145, 0x00 },
+    { "RTC_CLKSEL", 0x147, 0x00 },
+    { "RTC_CNTL"  , 0x148, 0x00 },
+    { "RTC_CNTH"  , 0x149, 0x00 },
+    { "RTC_PERL"  , 0x14A, 0x00 },
+    { "RTC_PERH"  , 0x14B, 0x00 },
+    { "RTC_CMPL"  , 0x14C, 0x00 },
+    { "RTC_CMPH"  , 0x14D, 0x00 },
+    { "RTC_PITCTRLA", 0x150, 0x00 },
+    { "RTC_PITSTATUS", 0x151, 0x00 },
+    { "RTC_PITINTCTRL", 0x152, 0x00 },
+    { "RTC_PITINTFLAGS", 0x153, 0x00 },
+    { "RTC_PITDBGCTRL", 0x155, 0x00 },
+    { "EVSYS_ASYNCSTROBE", 0x180, 0x00 },
+    { "EVSYS_SYNCSTROBE", 0x181, 0x00 },
+    { "EVSYS_ASYNCCH0", 0x182, 0x00 },
+    { "EVSYS_ASYNCCH1", 0x183, 0x00 },
+    { "EVSYS_ASYNCCH2", 0x184, 0x00 },
+    { "EVSYS_ASYNCCH3", 0x185, 0x00 },
+    { "EVSYS_SYNCCH0", 0x18A, 0x00 },
+    { "EVSYS_SYNCCH1", 0x18B, 0x00 },
+    { "EVSYS_ASYNCUSER0", 0x192, 0x00 },
+    { "EVSYS_ASYNCUSER1", 0x193, 0x00 },
+    { "EVSYS_ASYNCUSER2", 0x194, 0x00 },
+    { "EVSYS_ASYNCUSER3", 0x195, 0x00 },
+    { "EVSYS_ASYNCUSER4", 0x196, 0x00 },
+    { "EVSYS_ASYNCUSER5", 0x197, 0x00 },
+    { "EVSYS_ASYNCUSER6", 0x198, 0x00 },
+    { "EVSYS_ASYNCUSER7", 0x199, 0x00 },
+    { "EVSYS_ASYNCUSER8", 0x19A, 0x00 },
+    { "EVSYS_ASYNCUSER9", 0x19B, 0x00 },
+    { "EVSYS_ASYNCUSER10", 0x19C, 0x00 },
+    { "EVSYS_SYNCUSER0", 0x1A2, 0x00 },
+    { "EVSYS_SYNCUSER1", 0x1A3, 0x00 },
+    { "CCL_CTRLA" , 0x1C0, 0x00 },
+    { "CCL_SEQCTRL0", 0x1C1, 0x00 },
+    { "CCL_LUT0CTRLA", 0x1C5, 0x00 },
+    { "CCL_LUT0CTRLB", 0x1C6, 0x00 },
+    { "CCL_LUT0CTRLC", 0x1C7, 0x00 },
+    { "CCL_TRUTH0", 0x1C8, 0x00 },
+    { "CCL_LUT1CTRLA", 0x1C9, 0x00 },
+    { "CCL_LUT1CTRLB", 0x1CA, 0x00 },
+    { "CCL_LUT1CTRLC", 0x1CB, 0x00 },
+    { "CCL_TRUTH1", 0x1CC, 0x00 },
+    { "PORTMUX_CTRLA", 0x200, 0x00 },
+    { "PORTMUX_CTRLB", 0x201, 0x00 },
+    { "PORTMUX_CTRLC", 0x202, 0x00 },
+    { "PORTMUX_CTRLD", 0x203, 0x00 },
+    { "PORTA_DIR" , 0x400, 0x00 },
+    { "PORTA_DIRSET", 0x401, 0x00 },
+    { "PORTA_DIRCLR", 0x402, 0x00 },
+    { "PORTA_DIRTGL", 0x403, 0x00 },
+    { "PORTA_OUT" , 0x404, 0x00 },
+    { "PORTA_OUTSET", 0x405, 0x00 },
+    { "PORTA_OUTCLR", 0x406, 0x00 },
+    { "PORTA_OUTTGL", 0x407, 0x00 },
+    { "PORTA_IN"  , 0x408, 0x00 },
+    { "PORTA_INTFLAGS", 0x409, 0x00 },
+    { "PORTA_PIN0CTRL", 0x410, 0x00 },
+    { "PORTA_PIN1CTRL", 0x411, 0x00 },
+    { "PORTA_PIN2CTRL", 0x412, 0x00 },
+    { "PORTA_PIN3CTRL", 0x413, 0x00 },
+    { "PORTA_PIN4CTRL", 0x414, 0x00 },
+    { "PORTA_PIN5CTRL", 0x415, 0x00 },
+    { "PORTA_PIN6CTRL", 0x416, 0x00 },
+    { "PORTA_PIN7CTRL", 0x417, 0x00 },
+    { "PORTB_DIR" , 0x420, 0x00 },
+    { "PORTB_DIRSET", 0x421, 0x00 },
+    { "PORTB_DIRCLR", 0x422, 0x00 },
+    { "PORTB_DIRTGL", 0x423, 0x00 },
+    { "PORTB_OUT" , 0x424, 0x00 },
+    { "PORTB_OUTSET", 0x425, 0x00 },
+    { "PORTB_OUTCLR", 0x426, 0x00 },
+    { "PORTB_OUTTGL", 0x427, 0x00 },
+    { "PORTB_IN"  , 0x428, 0x00 },
+    { "PORTB_INTFLAGS", 0x429, 0x00 },
+    { "PORTB_PIN0CTRL", 0x430, 0x00 },
+    { "PORTB_PIN1CTRL", 0x431, 0x00 },
+    { "PORTB_PIN2CTRL", 0x432, 0x00 },
+    { "PORTB_PIN3CTRL", 0x433, 0x00 },
+    { "PORTB_PIN4CTRL", 0x434, 0x00 },
+    { "PORTB_PIN5CTRL", 0x435, 0x00 },
+    { "PORTB_PIN6CTRL", 0x436, 0x00 },
+    { "PORTB_PIN7CTRL", 0x437, 0x00 },
+    { "ADC0_CTRLA", 0x600, 0x00 },
+    { "ADC0_CTRLB", 0x601, 0x00 },
+    { "ADC0_CTRLC", 0x602, 0x00 },
+    { "ADC0_CTRLD", 0x603, 0x00 },
+    { "ADC0_CTRLE", 0x604, 0x00 },
+    { "ADC0_SAMPCTRL", 0x605, 0x00 },
+    { "ADC0_MUXPOS", 0x606, 0x00 },
+    { "ADC0_COMMAND", 0x608, 0x00 },
+    { "ADC0_EVCTRL", 0x609, 0x00 },
+    { "ADC0_INTCTRL", 0x60A, 0x00 },
+    { "ADC0_INTFLAGS", 0x60B, 0x00 },
+    { "ADC0_DBGCTRL", 0x60C, 0x00 },
+    { "ADC0_TEMP" , 0x60D, 0x00 },
+    { "ADC0_RESL" , 0x610, 0x00 },
+    { "ADC0_RESH" , 0x611, 0x00 },
+    { "ADC0_WINLTL", 0x612, 0x00 },
+    { "ADC0_WINLTH", 0x613, 0x00 },
+    { "ADC0_WINHTL", 0x614, 0x00 },
+    { "ADC0_WINHTH", 0x615, 0x00 },
+    { "ADC0_CALIB", 0x616, 0x00 },
+    { "AC0_CTRLA" , 0x670, 0x00 },
+    { "AC0_MUXCTRLA", 0x672, 0x00 },
+    { "AC0_INTCTRL", 0x676, 0x00 },
+    { "AC0_STATUS", 0x677, 0x00 },
+    { "DAC0_CTRLA", 0x680, 0x00 },
+    { "DAC0_DATA" , 0x681, 0x00 },
+    { "USART0_RXDATAL", 0x800, 0x00 },
+    { "USART0_RXDATAH", 0x801, 0x00 },
+    { "USART0_TXDATAL", 0x802, 0x00 },
+    { "USART0_TXDATAH", 0x803, 0x00 },
+    { "USART0_STATUS", 0x804, 0x00 },
+    { "USART0_CTRLA", 0x805, 0x00 },
+    { "USART0_CTRLB", 0x806, 0x00 },
+    { "USART0_CTRLC", 0x807, 0x00 },
+    { "USART0_BAUDL", 0x808, 0x00 },
+    { "USART0_BAUDH", 0x809, 0x00 },
+    { "USART0_DBGCTRL", 0x80B, 0x00 },
+    { "USART0_EVCTRL", 0x80C, 0x00 },
+    { "USART0_TXPLCTRL", 0x80D, 0x00 },
+    { "USART0_RXPLCTRL", 0x80E, 0x00 },
+    { "TWI0_CTRLA", 0x810, 0x00 },
+    { "TWI0_DBGCTRL", 0x812, 0x00 },
+    { "TWI0_MCTRLA", 0x813, 0x00 },
+    { "TWI0_MCTRLB", 0x814, 0x00 },
+    { "TWI0_MSTATUS", 0x815, 0x00 },
+    { "TWI0_MBAUD", 0x816, 0x00 },
+    { "TWI0_MADDR", 0x817, 0x00 },
+    { "TWI0_MDATA", 0x818, 0x00 },
+    { "TWI0_SCTRLA", 0x819, 0x00 },
+    { "TWI0_SCTRLB", 0x81A, 0x00 },
+    { "TWI0_SSTATUS", 0x81B, 0x00 },
+    { "TWI0_SADDR", 0x81C, 0x00 },
+    { "TWI0_SDATA", 0x81D, 0x00 },
+    { "TWI0_SADDRMASK", 0x81E, 0x00 },
+    { "SPI0_CTRLA", 0x820, 0x00 },
+    { "SPI0_CTRLB", 0x821, 0x00 },
+    { "SPI0_INTCTRL", 0x822, 0x00 },
+    { "SPI0_INTFLAGS", 0x823, 0x00 },
+    { "SPI0_DATA" , 0x824, 0x00 },
+    { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 },
+    { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 },
+    { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 },
+    { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 },
+    { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 },
+    { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 },
+    { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 },
+    { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 },
+    { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 },
+    { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 },
+    { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 },
+    { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 },
+    { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 },
+    { "TCA0_SPLIT_LCNT", 0xA20, 0x00 },
+    { "TCA0_SPLIT_HCNT", 0xA21, 0x00 },
+    { "TCA0_SPLIT_LPER", 0xA26, 0x00 },
+    { "TCA0_SPLIT_HPER", 0xA27, 0x00 },
+    { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 },
+    { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 },
+    { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 },
+    { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 },
+    { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 },
+    { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 },
+    { "TCB0_CTRLA", 0xA40, 0x00 },
+    { "TCB0_CTRLB", 0xA41, 0x00 },
+    { "TCB0_EVCTRL", 0xA44, 0x00 },
+    { "TCB0_INTCTRL", 0xA45, 0x00 },
+    { "TCB0_INTFLAGS", 0xA46, 0x00 },
+    { "TCB0_STATUS", 0xA47, 0x00 },
+    { "TCB0_DBGCTRL", 0xA48, 0x00 },
+    { "TCB0_TEMP" , 0xA49, 0x00 },
+    { "TCB0_CNTL" , 0xA4A, 0x00 },
+    { "TCB0_CNTH" , 0xA4B, 0x00 },
+    { "TCB0_CCMPL", 0xA4C, 0x00 },
+    { "TCB0_CCMPH", 0xA4D, 0x00 },
+    { "TCD0_CTRLA", 0xA80, 0x00 },
+    { "TCD0_CTRLB", 0xA81, 0x00 },
+    { "TCD0_CTRLC", 0xA82, 0x00 },
+    { "TCD0_CTRLD", 0xA83, 0x00 },
+    { "TCD0_CTRLE", 0xA84, 0x00 },
+    { "TCD0_EVCTRLA", 0xA88, 0x00 },
+    { "TCD0_EVCTRLB", 0xA89, 0x00 },
+    { "TCD0_INTCTRL", 0xA8C, 0x00 },
+    { "TCD0_INTFLAGS", 0xA8D, 0x00 },
+    { "TCD0_STATUS", 0xA8E, 0x00 },
+    { "TCD0_INPUTCTRLA", 0xA90, 0x00 },
+    { "TCD0_INPUTCTRLB", 0xA91, 0x00 },
+    { "TCD0_FAULTCTRL", 0xA92, 0x00 },
+    { "TCD0_DLYCTRL", 0xA94, 0x00 },
+    { "TCD0_DLYVAL", 0xA95, 0x00 },
+    { "TCD0_DITCTRL", 0xA98, 0x00 },
+    { "TCD0_DITVAL", 0xA99, 0x00 },
+    { "TCD0_DBGCTRL", 0xA9E, 0x00 },
+    { "TCD0_CAPTUREAL", 0xAA2, 0x00 },
+    { "TCD0_CAPTUREAH", 0xAA3, 0x00 },
+    { "TCD0_CAPTUREBL", 0xAA4, 0x00 },
+    { "TCD0_CAPTUREBH", 0xAA5, 0x00 },
+    { "TCD0_CMPASETL", 0xAA8, 0x00 },
+    { "TCD0_CMPASETH", 0xAA9, 0x00 },
+    { "TCD0_CMPACLRL", 0xAAA, 0x00 },
+    { "TCD0_CMPACLRH", 0xAAB, 0x00 },
+    { "TCD0_CMPBSETL", 0xAAC, 0x00 },
+    { "TCD0_CMPBSETH", 0xAAD, 0x00 },
+    { "TCD0_CMPBCLRL", 0xAAE, 0x00 },
+    { "TCD0_CMPBCLRH", 0xAAF, 0x00 },
+    { "SYSCFG_REVID", 0xF01, 0x00 },
+    { "SYSCFG_EXTBRK", 0xF02, 0x00 },
+    { "NVMCTRL_CTRLA", 0x1000, 0x00 },
+    { "NVMCTRL_CTRLB", 0x1001, 0x00 },
+    { "NVMCTRL_STATUS", 0x1002, 0x00 },
+    { "NVMCTRL_INTCTRL", 0x1003, 0x00 },
+    { "NVMCTRL_INTFLAGS", 0x1004, 0x00 },
+    { "NVMCTRL_DATAL", 0x1006, 0x00 },
+    { "NVMCTRL_DATAH", 0x1007, 0x00 },
+    { "NVMCTRL_ADDRL", 0x1008, 0x00 },
+    { "NVMCTRL_ADDRH", 0x1009, 0x00 },
+    { "SIGROW_DEVICEID0", 0x1100, 0x00 },
+    { "SIGROW_DEVICEID1", 0x1101, 0x00 },
+    { "SIGROW_DEVICEID2", 0x1102, 0x00 },
+    { "SIGROW_SERNUM0", 0x1103, 0x00 },
+    { "SIGROW_SERNUM1", 0x1104, 0x00 },
+    { "SIGROW_SERNUM2", 0x1105, 0x00 },
+    { "SIGROW_SERNUM3", 0x1106, 0x00 },
+    { "SIGROW_SERNUM4", 0x1107, 0x00 },
+    { "SIGROW_SERNUM5", 0x1108, 0x00 },
+    { "SIGROW_SERNUM6", 0x1109, 0x00 },
+    { "SIGROW_SERNUM7", 0x110A, 0x00 },
+    { "SIGROW_SERNUM8", 0x110B, 0x00 },
+    { "SIGROW_SERNUM9", 0x110C, 0x00 },
+    { "SIGROW_TEMPSENSE0", 0x1120, 0x00 },
+    { "SIGROW_TEMPSENSE1", 0x1121, 0x00 },
+    { "SIGROW_OSC16ERR3V", 0x1122, 0x00 },
+    { "SIGROW_OSC16ERR5V", 0x1123, 0x00 },
+    { "SIGROW_OSC20ERR3V", 0x1124, 0x00 },
+    { "SIGROW_OSC20ERR5V", 0x1125, 0x00 },
+    { "FUSE_WDTCFG", 0x1280, 0x00 },
+    { "FUSE_BODCFG", 0x1281, 0x00 },
+    { "FUSE_OSCCFG", 0x1282, 0x00 },
+    { "FUSE_TCD0CFG", 0x1284, 0x00 },
+    { "FUSE_SYSCFG0", 0x1285, 0x00 },
+    { "FUSE_SYSCFG1", 0x1286, 0x00 },
+    { "FUSE_APPEND", 0x1287, 0x00 },
+    { "FUSE_BOOTEND", 0x1288, 0x00 },
+    { "LOCKBIT_LOCKBIT", 0x128A, 0x00 },
+    { "USERROW_USERROW0", 0x1300, 0x00 },
+    { "USERROW_USERROW1", 0x1301, 0x00 },
+    { "USERROW_USERROW2", 0x1302, 0x00 },
+    { "USERROW_USERROW3", 0x1303, 0x00 },
+    { "USERROW_USERROW4", 0x1304, 0x00 },
+    { "USERROW_USERROW5", 0x1305, 0x00 },
+    { "USERROW_USERROW6", 0x1306, 0x00 },
+    { "USERROW_USERROW7", 0x1307, 0x00 },
+    { "USERROW_USERROW8", 0x1308, 0x00 },
+    { "USERROW_USERROW9", 0x1309, 0x00 },
+    { "USERROW_USERROW10", 0x130A, 0x00 },
+    { "USERROW_USERROW11", 0x130B, 0x00 },
+    { "USERROW_USERROW12", 0x130C, 0x00 },
+    { "USERROW_USERROW13", 0x130D, 0x00 },
+    { "USERROW_USERROW14", 0x130E, 0x00 },
+    { "USERROW_USERROW15", 0x130F, 0x00 },
+    { "USERROW_USERROW16", 0x1310, 0x00 },
+    { "USERROW_USERROW17", 0x1311, 0x00 },
+    { "USERROW_USERROW18", 0x1312, 0x00 },
+    { "USERROW_USERROW19", 0x1313, 0x00 },
+    { "USERROW_USERROW20", 0x1314, 0x00 },
+    { "USERROW_USERROW21", 0x1315, 0x00 },
+    { "USERROW_USERROW22", 0x1316, 0x00 },
+    { "USERROW_USERROW23", 0x1317, 0x00 },
+    { "USERROW_USERROW24", 0x1318, 0x00 },
+    { "USERROW_USERROW25", 0x1319, 0x00 },
+    { "USERROW_USERROW26", 0x131A, 0x00 },
+    { "USERROW_USERROW27", 0x131B, 0x00 },
+    { "USERROW_USERROW28", 0x131C, 0x00 },
+    { "USERROW_USERROW29", 0x131D, 0x00 },
+    { "USERROW_USERROW30", 0x131E, 0x00 },
+    { "USERROW_USERROW31", 0x131F, 0x00 },
+    { 0, 0, 0}
+};
+
+
 gdb_io_reg_def_type attiny861_io_registers[] =
 {
     { "TCCR1E", 0x20, 0x00 },
@@ -7464,6 +8578,1586 @@ gdb_io_reg_def_type atmega48p_io_registers[] =
 };
 
 
+gdb_io_reg_def_type atmega3208_io_registers[] =
+{
+    { "VPORTA_DIR", 0x0, 0x00 },
+    { "VPORTA_OUT", 0x1, 0x00 },
+    { "VPORTA_IN" , 0x2, 0x00 },
+    { "VPORTA_INTFLAGS", 0x3, 0x00 },
+    { "VPORTB_DIR", 0x4, 0x00 },
+    { "VPORTB_OUT", 0x5, 0x00 },
+    { "VPORTB_IN" , 0x6, 0x00 },
+    { "VPORTB_INTFLAGS", 0x7, 0x00 },
+    { "VPORTC_DIR", 0x8, 0x00 },
+    { "VPORTC_OUT", 0x9, 0x00 },
+    { "VPORTC_IN" , 0xA, 0x00 },
+    { "VPORTC_INTFLAGS", 0xB, 0x00 },
+    { "VPORTD_DIR", 0xC, 0x00 },
+    { "VPORTD_OUT", 0xD, 0x00 },
+    { "VPORTD_IN" , 0xE, 0x00 },
+    { "VPORTD_INTFLAGS", 0xF, 0x00 },
+    { "VPORTE_DIR", 0x10, 0x00 },
+    { "VPORTE_OUT", 0x11, 0x00 },
+    { "VPORTE_IN" , 0x12, 0x00 },
+    { "VPORTE_INTFLAGS", 0x13, 0x00 },
+    { "VPORTF_DIR", 0x14, 0x00 },
+    { "VPORTF_OUT", 0x15, 0x00 },
+    { "VPORTF_IN" , 0x16, 0x00 },
+    { "VPORTF_INTFLAGS", 0x17, 0x00 },
+    { "GPIO_GPIO0", 0x1C, 0x00 },
+    { "GPIO_GPIO1", 0x1D, 0x00 },
+    { "GPIO_GPIO2", 0x1E, 0x00 },
+    { "GPIO_GPIO3", 0x1F, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "RSTCTRL_RSTFR", 0x40, 0x00 },
+    { "RSTCTRL_SWRR", 0x41, 0x00 },
+    { "SLPCTRL_CTRLA", 0x50, 0x00 },
+    { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 },
+    { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 },
+    { "CLKCTRL_MCLKLOCK", 0x62, 0x00 },
+    { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 },
+    { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 },
+    { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 },
+    { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 },
+    { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 },
+    { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 },
+    { "BOD_CTRLA" , 0x80, 0x00 },
+    { "BOD_CTRLB" , 0x81, 0x00 },
+    { "BOD_VLMCTRLA", 0x88, 0x00 },
+    { "BOD_INTCTRL", 0x89, 0x00 },
+    { "BOD_INTFLAGS", 0x8A, 0x00 },
+    { "BOD_STATUS", 0x8B, 0x00 },
+    { "VREF_CTRLA", 0xA0, 0x00 },
+    { "VREF_CTRLB", 0xA1, 0x00 },
+    { "WDT_CTRLA" , 0x100, 0x00 },
+    { "WDT_STATUS", 0x101, 0x00 },
+    { "CPUINT_CTRLA", 0x110, 0x00 },
+    { "CPUINT_STATUS", 0x111, 0x00 },
+    { "CPUINT_LVL0PRI", 0x112, 0x00 },
+    { "CPUINT_LVL1VEC", 0x113, 0x00 },
+    { "CRCSCAN_CTRLA", 0x120, 0x00 },
+    { "CRCSCAN_CTRLB", 0x121, 0x00 },
+    { "CRCSCAN_STATUS", 0x122, 0x00 },
+    { "RTC_CTRLA" , 0x140, 0x00 },
+    { "RTC_STATUS", 0x141, 0x00 },
+    { "RTC_INTCTRL", 0x142, 0x00 },
+    { "RTC_INTFLAGS", 0x143, 0x00 },
+    { "RTC_TEMP"  , 0x144, 0x00 },
+    { "RTC_DBGCTRL", 0x145, 0x00 },
+    { "RTC_CALIB" , 0x146, 0x00 },
+    { "RTC_CLKSEL", 0x147, 0x00 },
+    { "RTC_CNTL"  , 0x148, 0x00 },
+    { "RTC_CNTH"  , 0x149, 0x00 },
+    { "RTC_PERL"  , 0x14A, 0x00 },
+    { "RTC_PERH"  , 0x14B, 0x00 },
+    { "RTC_CMPL"  , 0x14C, 0x00 },
+    { "RTC_CMPH"  , 0x14D, 0x00 },
+    { "RTC_PITCTRLA", 0x150, 0x00 },
+    { "RTC_PITSTATUS", 0x151, 0x00 },
+    { "RTC_PITINTCTRL", 0x152, 0x00 },
+    { "RTC_PITINTFLAGS", 0x153, 0x00 },
+    { "RTC_PITDBGCTRL", 0x155, 0x00 },
+    { "EVSYS_STROBE", 0x180, 0x00 },
+    { "EVSYS_CHANNEL0", 0x190, 0x00 },
+    { "EVSYS_CHANNEL1", 0x191, 0x00 },
+    { "EVSYS_CHANNEL2", 0x192, 0x00 },
+    { "EVSYS_CHANNEL3", 0x193, 0x00 },
+    { "EVSYS_CHANNEL4", 0x194, 0x00 },
+    { "EVSYS_CHANNEL5", 0x195, 0x00 },
+    { "EVSYS_USERCCLLUT0A", 0x1A0, 0x00 },
+    { "EVSYS_USERCCLLUT0B", 0x1A1, 0x00 },
+    { "EVSYS_USERCCLLUT1A", 0x1A2, 0x00 },
+    { "EVSYS_USERCCLLUT1B", 0x1A3, 0x00 },
+    { "EVSYS_USERCCLLUT2A", 0x1A4, 0x00 },
+    { "EVSYS_USERCCLLUT2B", 0x1A5, 0x00 },
+    { "EVSYS_USERCCLLUT3A", 0x1A6, 0x00 },
+    { "EVSYS_USERCCLLUT3B", 0x1A7, 0x00 },
+    { "EVSYS_USERADC0", 0x1A8, 0x00 },
+    { "EVSYS_USEREVOUTA", 0x1A9, 0x00 },
+    { "EVSYS_USEREVOUTB", 0x1AA, 0x00 },
+    { "EVSYS_USEREVOUTC", 0x1AB, 0x00 },
+    { "EVSYS_USEREVOUTD", 0x1AC, 0x00 },
+    { "EVSYS_USEREVOUTE", 0x1AD, 0x00 },
+    { "EVSYS_USEREVOUTF", 0x1AE, 0x00 },
+    { "EVSYS_USERUSART0", 0x1AF, 0x00 },
+    { "EVSYS_USERUSART1", 0x1B0, 0x00 },
+    { "EVSYS_USERUSART2", 0x1B1, 0x00 },
+    { "EVSYS_USERUSART3", 0x1B2, 0x00 },
+    { "EVSYS_USERTCA0", 0x1B3, 0x00 },
+    { "EVSYS_USERTCB0", 0x1B4, 0x00 },
+    { "EVSYS_USERTCB1", 0x1B5, 0x00 },
+    { "EVSYS_USERTCB2", 0x1B6, 0x00 },
+    { "EVSYS_USERTCB3", 0x1B7, 0x00 },
+    { "CCL_CTRLA" , 0x1C0, 0x00 },
+    { "CCL_SEQCTRL0", 0x1C1, 0x00 },
+    { "CCL_SEQCTRL1", 0x1C2, 0x00 },
+    { "CCL_INTCTRL0", 0x1C5, 0x00 },
+    { "CCL_INTFLAGS", 0x1C7, 0x00 },
+    { "CCL_LUT0CTRLA", 0x1C8, 0x00 },
+    { "CCL_LUT0CTRLB", 0x1C9, 0x00 },
+    { "CCL_LUT0CTRLC", 0x1CA, 0x00 },
+    { "CCL_TRUTH0", 0x1CB, 0x00 },
+    { "CCL_LUT1CTRLA", 0x1CC, 0x00 },
+    { "CCL_LUT1CTRLB", 0x1CD, 0x00 },
+    { "CCL_LUT1CTRLC", 0x1CE, 0x00 },
+    { "CCL_TRUTH1", 0x1CF, 0x00 },
+    { "CCL_LUT2CTRLA", 0x1D0, 0x00 },
+    { "CCL_LUT2CTRLB", 0x1D1, 0x00 },
+    { "CCL_LUT2CTRLC", 0x1D2, 0x00 },
+    { "CCL_TRUTH2", 0x1D3, 0x00 },
+    { "CCL_LUT3CTRLA", 0x1D4, 0x00 },
+    { "CCL_LUT3CTRLB", 0x1D5, 0x00 },
+    { "CCL_LUT3CTRLC", 0x1D6, 0x00 },
+    { "CCL_TRUTH3", 0x1D7, 0x00 },
+    { "PORTA_DIR" , 0x400, 0x00 },
+    { "PORTA_DIRSET", 0x401, 0x00 },
+    { "PORTA_DIRCLR", 0x402, 0x00 },
+    { "PORTA_DIRTGL", 0x403, 0x00 },
+    { "PORTA_OUT" , 0x404, 0x00 },
+    { "PORTA_OUTSET", 0x405, 0x00 },
+    { "PORTA_OUTCLR", 0x406, 0x00 },
+    { "PORTA_OUTTGL", 0x407, 0x00 },
+    { "PORTA_IN"  , 0x408, 0x00 },
+    { "PORTA_INTFLAGS", 0x409, 0x00 },
+    { "PORTA_PORTCTRL", 0x40A, 0x00 },
+    { "PORTA_PIN0CTRL", 0x410, 0x00 },
+    { "PORTA_PIN1CTRL", 0x411, 0x00 },
+    { "PORTA_PIN2CTRL", 0x412, 0x00 },
+    { "PORTA_PIN3CTRL", 0x413, 0x00 },
+    { "PORTA_PIN4CTRL", 0x414, 0x00 },
+    { "PORTA_PIN5CTRL", 0x415, 0x00 },
+    { "PORTA_PIN6CTRL", 0x416, 0x00 },
+    { "PORTA_PIN7CTRL", 0x417, 0x00 },
+    { "PORTB_DIR" , 0x420, 0x00 },
+    { "PORTB_DIRSET", 0x421, 0x00 },
+    { "PORTB_DIRCLR", 0x422, 0x00 },
+    { "PORTB_DIRTGL", 0x423, 0x00 },
+    { "PORTB_OUT" , 0x424, 0x00 },
+    { "PORTB_OUTSET", 0x425, 0x00 },
+    { "PORTB_OUTCLR", 0x426, 0x00 },
+    { "PORTB_OUTTGL", 0x427, 0x00 },
+    { "PORTB_IN"  , 0x428, 0x00 },
+    { "PORTB_INTFLAGS", 0x429, 0x00 },
+    { "PORTB_PORTCTRL", 0x42A, 0x00 },
+    { "PORTB_PIN0CTRL", 0x430, 0x00 },
+    { "PORTB_PIN1CTRL", 0x431, 0x00 },
+    { "PORTB_PIN2CTRL", 0x432, 0x00 },
+    { "PORTB_PIN3CTRL", 0x433, 0x00 },
+    { "PORTB_PIN4CTRL", 0x434, 0x00 },
+    { "PORTB_PIN5CTRL", 0x435, 0x00 },
+    { "PORTB_PIN6CTRL", 0x436, 0x00 },
+    { "PORTB_PIN7CTRL", 0x437, 0x00 },
+    { "PORTC_DIR" , 0x440, 0x00 },
+    { "PORTC_DIRSET", 0x441, 0x00 },
+    { "PORTC_DIRCLR", 0x442, 0x00 },
+    { "PORTC_DIRTGL", 0x443, 0x00 },
+    { "PORTC_OUT" , 0x444, 0x00 },
+    { "PORTC_OUTSET", 0x445, 0x00 },
+    { "PORTC_OUTCLR", 0x446, 0x00 },
+    { "PORTC_OUTTGL", 0x447, 0x00 },
+    { "PORTC_IN"  , 0x448, 0x00 },
+    { "PORTC_INTFLAGS", 0x449, 0x00 },
+    { "PORTC_PORTCTRL", 0x44A, 0x00 },
+    { "PORTC_PIN0CTRL", 0x450, 0x00 },
+    { "PORTC_PIN1CTRL", 0x451, 0x00 },
+    { "PORTC_PIN2CTRL", 0x452, 0x00 },
+    { "PORTC_PIN3CTRL", 0x453, 0x00 },
+    { "PORTC_PIN4CTRL", 0x454, 0x00 },
+    { "PORTC_PIN5CTRL", 0x455, 0x00 },
+    { "PORTC_PIN6CTRL", 0x456, 0x00 },
+    { "PORTC_PIN7CTRL", 0x457, 0x00 },
+    { "PORTD_DIR" , 0x460, 0x00 },
+    { "PORTD_DIRSET", 0x461, 0x00 },
+    { "PORTD_DIRCLR", 0x462, 0x00 },
+    { "PORTD_DIRTGL", 0x463, 0x00 },
+    { "PORTD_OUT" , 0x464, 0x00 },
+    { "PORTD_OUTSET", 0x465, 0x00 },
+    { "PORTD_OUTCLR", 0x466, 0x00 },
+    { "PORTD_OUTTGL", 0x467, 0x00 },
+    { "PORTD_IN"  , 0x468, 0x00 },
+    { "PORTD_INTFLAGS", 0x469, 0x00 },
+    { "PORTD_PORTCTRL", 0x46A, 0x00 },
+    { "PORTD_PIN0CTRL", 0x470, 0x00 },
+    { "PORTD_PIN1CTRL", 0x471, 0x00 },
+    { "PORTD_PIN2CTRL", 0x472, 0x00 },
+    { "PORTD_PIN3CTRL", 0x473, 0x00 },
+    { "PORTD_PIN4CTRL", 0x474, 0x00 },
+    { "PORTD_PIN5CTRL", 0x475, 0x00 },
+    { "PORTD_PIN6CTRL", 0x476, 0x00 },
+    { "PORTD_PIN7CTRL", 0x477, 0x00 },
+    { "PORTE_DIR" , 0x480, 0x00 },
+    { "PORTE_DIRSET", 0x481, 0x00 },
+    { "PORTE_DIRCLR", 0x482, 0x00 },
+    { "PORTE_DIRTGL", 0x483, 0x00 },
+    { "PORTE_OUT" , 0x484, 0x00 },
+    { "PORTE_OUTSET", 0x485, 0x00 },
+    { "PORTE_OUTCLR", 0x486, 0x00 },
+    { "PORTE_OUTTGL", 0x487, 0x00 },
+    { "PORTE_IN"  , 0x488, 0x00 },
+    { "PORTE_INTFLAGS", 0x489, 0x00 },
+    { "PORTE_PORTCTRL", 0x48A, 0x00 },
+    { "PORTE_PIN0CTRL", 0x490, 0x00 },
+    { "PORTE_PIN1CTRL", 0x491, 0x00 },
+    { "PORTE_PIN2CTRL", 0x492, 0x00 },
+    { "PORTE_PIN3CTRL", 0x493, 0x00 },
+    { "PORTE_PIN4CTRL", 0x494, 0x00 },
+    { "PORTE_PIN5CTRL", 0x495, 0x00 },
+    { "PORTE_PIN6CTRL", 0x496, 0x00 },
+    { "PORTE_PIN7CTRL", 0x497, 0x00 },
+    { "PORTF_DIR" , 0x4A0, 0x00 },
+    { "PORTF_DIRSET", 0x4A1, 0x00 },
+    { "PORTF_DIRCLR", 0x4A2, 0x00 },
+    { "PORTF_DIRTGL", 0x4A3, 0x00 },
+    { "PORTF_OUT" , 0x4A4, 0x00 },
+    { "PORTF_OUTSET", 0x4A5, 0x00 },
+    { "PORTF_OUTCLR", 0x4A6, 0x00 },
+    { "PORTF_OUTTGL", 0x4A7, 0x00 },
+    { "PORTF_IN"  , 0x4A8, 0x00 },
+    { "PORTF_INTFLAGS", 0x4A9, 0x00 },
+    { "PORTF_PORTCTRL", 0x4AA, 0x00 },
+    { "PORTF_PIN0CTRL", 0x4B0, 0x00 },
+    { "PORTF_PIN1CTRL", 0x4B1, 0x00 },
+    { "PORTF_PIN2CTRL", 0x4B2, 0x00 },
+    { "PORTF_PIN3CTRL", 0x4B3, 0x00 },
+    { "PORTF_PIN4CTRL", 0x4B4, 0x00 },
+    { "PORTF_PIN5CTRL", 0x4B5, 0x00 },
+    { "PORTF_PIN6CTRL", 0x4B6, 0x00 },
+    { "PORTF_PIN7CTRL", 0x4B7, 0x00 },
+    { "PORTMUX_EVSYSROUTEA", 0x5E0, 0x00 },
+    { "PORTMUX_CCLROUTEA", 0x5E1, 0x00 },
+    { "PORTMUX_USARTROUTEA", 0x5E2, 0x00 },
+    { "PORTMUX_TWISPIROUTEA", 0x5E3, 0x00 },
+    { "PORTMUX_TCAROUTEA", 0x5E4, 0x00 },
+    { "PORTMUX_TCBROUTEA", 0x5E5, 0x00 },
+    { "ADC0_CTRLA", 0x600, 0x00 },
+    { "ADC0_CTRLB", 0x601, 0x00 },
+    { "ADC0_CTRLC", 0x602, 0x00 },
+    { "ADC0_CTRLD", 0x603, 0x00 },
+    { "ADC0_CTRLE", 0x604, 0x00 },
+    { "ADC0_SAMPCTRL", 0x605, 0x00 },
+    { "ADC0_MUXPOS", 0x606, 0x00 },
+    { "ADC0_COMMAND", 0x608, 0x00 },
+    { "ADC0_EVCTRL", 0x609, 0x00 },
+    { "ADC0_INTCTRL", 0x60A, 0x00 },
+    { "ADC0_INTFLAGS", 0x60B, 0x00 },
+    { "ADC0_DBGCTRL", 0x60C, 0x00 },
+    { "ADC0_TEMP" , 0x60D, 0x00 },
+    { "ADC0_RESL" , 0x610, 0x00 },
+    { "ADC0_RESH" , 0x611, 0x00 },
+    { "ADC0_WINLTL", 0x612, 0x00 },
+    { "ADC0_WINLTH", 0x613, 0x00 },
+    { "ADC0_WINHTL", 0x614, 0x00 },
+    { "ADC0_WINHTH", 0x615, 0x00 },
+    { "ADC0_CALIB", 0x616, 0x00 },
+    { "AC0_CTRLA" , 0x680, 0x00 },
+    { "AC0_MUXCTRLA", 0x682, 0x00 },
+    { "AC0_DACREF", 0x684, 0x00 },
+    { "AC0_INTCTRL", 0x686, 0x00 },
+    { "AC0_STATUS", 0x687, 0x00 },
+    { "USART0_RXDATAL", 0x800, 0x00 },
+    { "USART0_RXDATAH", 0x801, 0x00 },
+    { "USART0_TXDATAL", 0x802, 0x00 },
+    { "USART0_TXDATAH", 0x803, 0x00 },
+    { "USART0_STATUS", 0x804, 0x00 },
+    { "USART0_CTRLA", 0x805, 0x00 },
+    { "USART0_CTRLB", 0x806, 0x00 },
+    { "USART0_CTRLC", 0x807, 0x00 },
+    { "USART0_BAUDL", 0x808, 0x00 },
+    { "USART0_BAUDH", 0x809, 0x00 },
+    { "USART0_CTRLD", 0x80A, 0x00 },
+    { "USART0_DBGCTRL", 0x80B, 0x00 },
+    { "USART0_EVCTRL", 0x80C, 0x00 },
+    { "USART0_TXPLCTRL", 0x80D, 0x00 },
+    { "USART0_RXPLCTRL", 0x80E, 0x00 },
+    { "USART1_RXDATAL", 0x820, 0x00 },
+    { "USART1_RXDATAH", 0x821, 0x00 },
+    { "USART1_TXDATAL", 0x822, 0x00 },
+    { "USART1_TXDATAH", 0x823, 0x00 },
+    { "USART1_STATUS", 0x824, 0x00 },
+    { "USART1_CTRLA", 0x825, 0x00 },
+    { "USART1_CTRLB", 0x826, 0x00 },
+    { "USART1_CTRLC", 0x827, 0x00 },
+    { "USART1_BAUDL", 0x828, 0x00 },
+    { "USART1_BAUDH", 0x829, 0x00 },
+    { "USART1_CTRLD", 0x82A, 0x00 },
+    { "USART1_DBGCTRL", 0x82B, 0x00 },
+    { "USART1_EVCTRL", 0x82C, 0x00 },
+    { "USART1_TXPLCTRL", 0x82D, 0x00 },
+    { "USART1_RXPLCTRL", 0x82E, 0x00 },
+    { "USART2_RXDATAL", 0x840, 0x00 },
+    { "USART2_RXDATAH", 0x841, 0x00 },
+    { "USART2_TXDATAL", 0x842, 0x00 },
+    { "USART2_TXDATAH", 0x843, 0x00 },
+    { "USART2_STATUS", 0x844, 0x00 },
+    { "USART2_CTRLA", 0x845, 0x00 },
+    { "USART2_CTRLB", 0x846, 0x00 },
+    { "USART2_CTRLC", 0x847, 0x00 },
+    { "USART2_BAUDL", 0x848, 0x00 },
+    { "USART2_BAUDH", 0x849, 0x00 },
+    { "USART2_CTRLD", 0x84A, 0x00 },
+    { "USART2_DBGCTRL", 0x84B, 0x00 },
+    { "USART2_EVCTRL", 0x84C, 0x00 },
+    { "USART2_TXPLCTRL", 0x84D, 0x00 },
+    { "USART2_RXPLCTRL", 0x84E, 0x00 },
+    { "TWI0_CTRLA", 0x8A0, 0x00 },
+    { "TWI0_DUALCTRL", 0x8A1, 0x00 },
+    { "TWI0_DBGCTRL", 0x8A2, 0x00 },
+    { "TWI0_MCTRLA", 0x8A3, 0x00 },
+    { "TWI0_MCTRLB", 0x8A4, 0x00 },
+    { "TWI0_MSTATUS", 0x8A5, 0x00 },
+    { "TWI0_MBAUD", 0x8A6, 0x00 },
+    { "TWI0_MADDR", 0x8A7, 0x00 },
+    { "TWI0_MDATA", 0x8A8, 0x00 },
+    { "TWI0_SCTRLA", 0x8A9, 0x00 },
+    { "TWI0_SCTRLB", 0x8AA, 0x00 },
+    { "TWI0_SSTATUS", 0x8AB, 0x00 },
+    { "TWI0_SADDR", 0x8AC, 0x00 },
+    { "TWI0_SDATA", 0x8AD, 0x00 },
+    { "TWI0_SADDRMASK", 0x8AE, 0x00 },
+    { "SPI0_CTRLA", 0x8C0, 0x00 },
+    { "SPI0_CTRLB", 0x8C1, 0x00 },
+    { "SPI0_INTCTRL", 0x8C2, 0x00 },
+    { "SPI0_INTFLAGS", 0x8C3, 0x00 },
+    { "SPI0_DATA" , 0x8C4, 0x00 },
+    { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 },
+    { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 },
+    { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 },
+    { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 },
+    { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 },
+    { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 },
+    { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 },
+    { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 },
+    { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 },
+    { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 },
+    { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 },
+    { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 },
+    { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 },
+    { "TCA0_SPLIT_LCNT", 0xA20, 0x00 },
+    { "TCA0_SPLIT_HCNT", 0xA21, 0x00 },
+    { "TCA0_SPLIT_LPER", 0xA26, 0x00 },
+    { "TCA0_SPLIT_HPER", 0xA27, 0x00 },
+    { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 },
+    { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 },
+    { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 },
+    { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 },
+    { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 },
+    { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 },
+    { "TCB0_CTRLA", 0xA80, 0x00 },
+    { "TCB0_CTRLB", 0xA81, 0x00 },
+    { "TCB0_EVCTRL", 0xA84, 0x00 },
+    { "TCB0_INTCTRL", 0xA85, 0x00 },
+    { "TCB0_INTFLAGS", 0xA86, 0x00 },
+    { "TCB0_STATUS", 0xA87, 0x00 },
+    { "TCB0_DBGCTRL", 0xA88, 0x00 },
+    { "TCB0_TEMP" , 0xA89, 0x00 },
+    { "TCB0_CNTL" , 0xA8A, 0x00 },
+    { "TCB0_CNTH" , 0xA8B, 0x00 },
+    { "TCB0_CCMPL", 0xA8C, 0x00 },
+    { "TCB0_CCMPH", 0xA8D, 0x00 },
+    { "TCB1_CTRLA", 0xA90, 0x00 },
+    { "TCB1_CTRLB", 0xA91, 0x00 },
+    { "TCB1_EVCTRL", 0xA94, 0x00 },
+    { "TCB1_INTCTRL", 0xA95, 0x00 },
+    { "TCB1_INTFLAGS", 0xA96, 0x00 },
+    { "TCB1_STATUS", 0xA97, 0x00 },
+    { "TCB1_DBGCTRL", 0xA98, 0x00 },
+    { "TCB1_TEMP" , 0xA99, 0x00 },
+    { "TCB1_CNTL" , 0xA9A, 0x00 },
+    { "TCB1_CNTH" , 0xA9B, 0x00 },
+    { "TCB1_CCMPL", 0xA9C, 0x00 },
+    { "TCB1_CCMPH", 0xA9D, 0x00 },
+    { "TCB2_CTRLA", 0xAA0, 0x00 },
+    { "TCB2_CTRLB", 0xAA1, 0x00 },
+    { "TCB2_EVCTRL", 0xAA4, 0x00 },
+    { "TCB2_INTCTRL", 0xAA5, 0x00 },
+    { "TCB2_INTFLAGS", 0xAA6, 0x00 },
+    { "TCB2_STATUS", 0xAA7, 0x00 },
+    { "TCB2_DBGCTRL", 0xAA8, 0x00 },
+    { "TCB2_TEMP" , 0xAA9, 0x00 },
+    { "TCB2_CNTL" , 0xAAA, 0x00 },
+    { "TCB2_CNTH" , 0xAAB, 0x00 },
+    { "TCB2_CCMPL", 0xAAC, 0x00 },
+    { "TCB2_CCMPH", 0xAAD, 0x00 },
+    { "SYSCFG_REVID", 0xF01, 0x00 },
+    { "SYSCFG_EXTBRK", 0xF02, 0x00 },
+    { "SYSCFG_OCDM", 0xF18, 0x00 },
+    { "SYSCFG_OCDMS", 0xF19, 0x00 },
+    { "NVMCTRL_CTRLA", 0x1000, 0x00 },
+    { "NVMCTRL_CTRLB", 0x1001, 0x00 },
+    { "NVMCTRL_STATUS", 0x1002, 0x00 },
+    { "NVMCTRL_INTCTRL", 0x1003, 0x00 },
+    { "NVMCTRL_INTFLAGS", 0x1004, 0x00 },
+    { "NVMCTRL_DATAL", 0x1006, 0x00 },
+    { "NVMCTRL_DATAH", 0x1007, 0x00 },
+    { "NVMCTRL_ADDRL", 0x1008, 0x00 },
+    { "NVMCTRL_ADDRH", 0x1009, 0x00 },
+    { "SIGROW_DEVICEID0", 0x1100, 0x00 },
+    { "SIGROW_DEVICEID1", 0x1101, 0x00 },
+    { "SIGROW_DEVICEID2", 0x1102, 0x00 },
+    { "SIGROW_SERNUM0", 0x1103, 0x00 },
+    { "SIGROW_SERNUM1", 0x1104, 0x00 },
+    { "SIGROW_SERNUM2", 0x1105, 0x00 },
+    { "SIGROW_SERNUM3", 0x1106, 0x00 },
+    { "SIGROW_SERNUM4", 0x1107, 0x00 },
+    { "SIGROW_SERNUM5", 0x1108, 0x00 },
+    { "SIGROW_SERNUM6", 0x1109, 0x00 },
+    { "SIGROW_SERNUM7", 0x110A, 0x00 },
+    { "SIGROW_SERNUM8", 0x110B, 0x00 },
+    { "SIGROW_SERNUM9", 0x110C, 0x00 },
+    { "SIGROW_OSCCAL32K", 0x1114, 0x00 },
+    { "SIGROW_OSCCAL16M0", 0x1118, 0x00 },
+    { "SIGROW_OSCCAL16M1", 0x1119, 0x00 },
+    { "SIGROW_OSCCAL20M0", 0x111A, 0x00 },
+    { "SIGROW_OSCCAL20M1", 0x111B, 0x00 },
+    { "SIGROW_TEMPSENSE0", 0x1120, 0x00 },
+    { "SIGROW_TEMPSENSE1", 0x1121, 0x00 },
+    { "SIGROW_OSC16ERR3V", 0x1122, 0x00 },
+    { "SIGROW_OSC16ERR5V", 0x1123, 0x00 },
+    { "SIGROW_OSC20ERR3V", 0x1124, 0x00 },
+    { "SIGROW_OSC20ERR5V", 0x1125, 0x00 },
+    { "SIGROW_CHECKSUM1", 0x112F, 0x00 },
+    { "FUSE_WDTCFG", 0x1280, 0x00 },
+    { "FUSE_BODCFG", 0x1281, 0x00 },
+    { "FUSE_OSCCFG", 0x1282, 0x00 },
+    { "FUSE_SYSCFG0", 0x1285, 0x00 },
+    { "FUSE_SYSCFG1", 0x1286, 0x00 },
+    { "FUSE_APPEND", 0x1287, 0x00 },
+    { "FUSE_BOOTEND", 0x1288, 0x00 },
+    { "LOCKBIT_LOCKBIT", 0x128A, 0x00 },
+    { "USERROW_USERROW0", 0x1300, 0x00 },
+    { "USERROW_USERROW1", 0x1301, 0x00 },
+    { "USERROW_USERROW2", 0x1302, 0x00 },
+    { "USERROW_USERROW3", 0x1303, 0x00 },
+    { "USERROW_USERROW4", 0x1304, 0x00 },
+    { "USERROW_USERROW5", 0x1305, 0x00 },
+    { "USERROW_USERROW6", 0x1306, 0x00 },
+    { "USERROW_USERROW7", 0x1307, 0x00 },
+    { "USERROW_USERROW8", 0x1308, 0x00 },
+    { "USERROW_USERROW9", 0x1309, 0x00 },
+    { "USERROW_USERROW10", 0x130A, 0x00 },
+    { "USERROW_USERROW11", 0x130B, 0x00 },
+    { "USERROW_USERROW12", 0x130C, 0x00 },
+    { "USERROW_USERROW13", 0x130D, 0x00 },
+    { "USERROW_USERROW14", 0x130E, 0x00 },
+    { "USERROW_USERROW15", 0x130F, 0x00 },
+    { "USERROW_USERROW16", 0x1310, 0x00 },
+    { "USERROW_USERROW17", 0x1311, 0x00 },
+    { "USERROW_USERROW18", 0x1312, 0x00 },
+    { "USERROW_USERROW19", 0x1313, 0x00 },
+    { "USERROW_USERROW20", 0x1314, 0x00 },
+    { "USERROW_USERROW21", 0x1315, 0x00 },
+    { "USERROW_USERROW22", 0x1316, 0x00 },
+    { "USERROW_USERROW23", 0x1317, 0x00 },
+    { "USERROW_USERROW24", 0x1318, 0x00 },
+    { "USERROW_USERROW25", 0x1319, 0x00 },
+    { "USERROW_USERROW26", 0x131A, 0x00 },
+    { "USERROW_USERROW27", 0x131B, 0x00 },
+    { "USERROW_USERROW28", 0x131C, 0x00 },
+    { "USERROW_USERROW29", 0x131D, 0x00 },
+    { "USERROW_USERROW30", 0x131E, 0x00 },
+    { "USERROW_USERROW31", 0x131F, 0x00 },
+    { "USERROW_USERROW32", 0x1320, 0x00 },
+    { "USERROW_USERROW33", 0x1321, 0x00 },
+    { "USERROW_USERROW34", 0x1322, 0x00 },
+    { "USERROW_USERROW35", 0x1323, 0x00 },
+    { "USERROW_USERROW36", 0x1324, 0x00 },
+    { "USERROW_USERROW37", 0x1325, 0x00 },
+    { "USERROW_USERROW38", 0x1326, 0x00 },
+    { "USERROW_USERROW39", 0x1327, 0x00 },
+    { "USERROW_USERROW40", 0x1328, 0x00 },
+    { "USERROW_USERROW41", 0x1329, 0x00 },
+    { "USERROW_USERROW42", 0x132A, 0x00 },
+    { "USERROW_USERROW43", 0x132B, 0x00 },
+    { "USERROW_USERROW44", 0x132C, 0x00 },
+    { "USERROW_USERROW45", 0x132D, 0x00 },
+    { "USERROW_USERROW46", 0x132E, 0x00 },
+    { "USERROW_USERROW47", 0x132F, 0x00 },
+    { "USERROW_USERROW48", 0x1330, 0x00 },
+    { "USERROW_USERROW49", 0x1331, 0x00 },
+    { "USERROW_USERROW50", 0x1332, 0x00 },
+    { "USERROW_USERROW51", 0x1333, 0x00 },
+    { "USERROW_USERROW52", 0x1334, 0x00 },
+    { "USERROW_USERROW53", 0x1335, 0x00 },
+    { "USERROW_USERROW54", 0x1336, 0x00 },
+    { "USERROW_USERROW55", 0x1337, 0x00 },
+    { "USERROW_USERROW56", 0x1338, 0x00 },
+    { "USERROW_USERROW57", 0x1339, 0x00 },
+    { "USERROW_USERROW58", 0x133A, 0x00 },
+    { "USERROW_USERROW59", 0x133B, 0x00 },
+    { "USERROW_USERROW60", 0x133C, 0x00 },
+    { "USERROW_USERROW61", 0x133D, 0x00 },
+    { "USERROW_USERROW62", 0x133E, 0x00 },
+    { "USERROW_USERROW63", 0x133F, 0x00 },
+    { 0, 0, 0}
+};
+
+
+gdb_io_reg_def_type atmega4808_io_registers[] =
+{
+    { "VPORTA_DIR", 0x0, 0x00 },
+    { "VPORTA_OUT", 0x1, 0x00 },
+    { "VPORTA_IN" , 0x2, 0x00 },
+    { "VPORTA_INTFLAGS", 0x3, 0x00 },
+    { "VPORTB_DIR", 0x4, 0x00 },
+    { "VPORTB_OUT", 0x5, 0x00 },
+    { "VPORTB_IN" , 0x6, 0x00 },
+    { "VPORTB_INTFLAGS", 0x7, 0x00 },
+    { "VPORTC_DIR", 0x8, 0x00 },
+    { "VPORTC_OUT", 0x9, 0x00 },
+    { "VPORTC_IN" , 0xA, 0x00 },
+    { "VPORTC_INTFLAGS", 0xB, 0x00 },
+    { "VPORTD_DIR", 0xC, 0x00 },
+    { "VPORTD_OUT", 0xD, 0x00 },
+    { "VPORTD_IN" , 0xE, 0x00 },
+    { "VPORTD_INTFLAGS", 0xF, 0x00 },
+    { "VPORTE_DIR", 0x10, 0x00 },
+    { "VPORTE_OUT", 0x11, 0x00 },
+    { "VPORTE_IN" , 0x12, 0x00 },
+    { "VPORTE_INTFLAGS", 0x13, 0x00 },
+    { "VPORTF_DIR", 0x14, 0x00 },
+    { "VPORTF_OUT", 0x15, 0x00 },
+    { "VPORTF_IN" , 0x16, 0x00 },
+    { "VPORTF_INTFLAGS", 0x17, 0x00 },
+    { "GPIO_GPIO0", 0x1C, 0x00 },
+    { "GPIO_GPIO1", 0x1D, 0x00 },
+    { "GPIO_GPIO2", 0x1E, 0x00 },
+    { "GPIO_GPIO3", 0x1F, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "RSTCTRL_RSTFR", 0x40, 0x00 },
+    { "RSTCTRL_SWRR", 0x41, 0x00 },
+    { "SLPCTRL_CTRLA", 0x50, 0x00 },
+    { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 },
+    { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 },
+    { "CLKCTRL_MCLKLOCK", 0x62, 0x00 },
+    { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 },
+    { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 },
+    { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 },
+    { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 },
+    { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 },
+    { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 },
+    { "BOD_CTRLA" , 0x80, 0x00 },
+    { "BOD_CTRLB" , 0x81, 0x00 },
+    { "BOD_VLMCTRLA", 0x88, 0x00 },
+    { "BOD_INTCTRL", 0x89, 0x00 },
+    { "BOD_INTFLAGS", 0x8A, 0x00 },
+    { "BOD_STATUS", 0x8B, 0x00 },
+    { "VREF_CTRLA", 0xA0, 0x00 },
+    { "VREF_CTRLB", 0xA1, 0x00 },
+    { "WDT_CTRLA" , 0x100, 0x00 },
+    { "WDT_STATUS", 0x101, 0x00 },
+    { "CPUINT_CTRLA", 0x110, 0x00 },
+    { "CPUINT_STATUS", 0x111, 0x00 },
+    { "CPUINT_LVL0PRI", 0x112, 0x00 },
+    { "CPUINT_LVL1VEC", 0x113, 0x00 },
+    { "CRCSCAN_CTRLA", 0x120, 0x00 },
+    { "CRCSCAN_CTRLB", 0x121, 0x00 },
+    { "CRCSCAN_STATUS", 0x122, 0x00 },
+    { "RTC_CTRLA" , 0x140, 0x00 },
+    { "RTC_STATUS", 0x141, 0x00 },
+    { "RTC_INTCTRL", 0x142, 0x00 },
+    { "RTC_INTFLAGS", 0x143, 0x00 },
+    { "RTC_TEMP"  , 0x144, 0x00 },
+    { "RTC_DBGCTRL", 0x145, 0x00 },
+    { "RTC_CALIB" , 0x146, 0x00 },
+    { "RTC_CLKSEL", 0x147, 0x00 },
+    { "RTC_CNTL"  , 0x148, 0x00 },
+    { "RTC_CNTH"  , 0x149, 0x00 },
+    { "RTC_PERL"  , 0x14A, 0x00 },
+    { "RTC_PERH"  , 0x14B, 0x00 },
+    { "RTC_CMPL"  , 0x14C, 0x00 },
+    { "RTC_CMPH"  , 0x14D, 0x00 },
+    { "RTC_PITCTRLA", 0x150, 0x00 },
+    { "RTC_PITSTATUS", 0x151, 0x00 },
+    { "RTC_PITINTCTRL", 0x152, 0x00 },
+    { "RTC_PITINTFLAGS", 0x153, 0x00 },
+    { "RTC_PITDBGCTRL", 0x155, 0x00 },
+    { "EVSYS_STROBE", 0x180, 0x00 },
+    { "EVSYS_CHANNEL0", 0x190, 0x00 },
+    { "EVSYS_CHANNEL1", 0x191, 0x00 },
+    { "EVSYS_CHANNEL2", 0x192, 0x00 },
+    { "EVSYS_CHANNEL3", 0x193, 0x00 },
+    { "EVSYS_CHANNEL4", 0x194, 0x00 },
+    { "EVSYS_CHANNEL5", 0x195, 0x00 },
+    { "EVSYS_USERCCLLUT0A", 0x1A0, 0x00 },
+    { "EVSYS_USERCCLLUT0B", 0x1A1, 0x00 },
+    { "EVSYS_USERCCLLUT1A", 0x1A2, 0x00 },
+    { "EVSYS_USERCCLLUT1B", 0x1A3, 0x00 },
+    { "EVSYS_USERCCLLUT2A", 0x1A4, 0x00 },
+    { "EVSYS_USERCCLLUT2B", 0x1A5, 0x00 },
+    { "EVSYS_USERCCLLUT3A", 0x1A6, 0x00 },
+    { "EVSYS_USERCCLLUT3B", 0x1A7, 0x00 },
+    { "EVSYS_USERADC0", 0x1A8, 0x00 },
+    { "EVSYS_USEREVOUTA", 0x1A9, 0x00 },
+    { "EVSYS_USEREVOUTB", 0x1AA, 0x00 },
+    { "EVSYS_USEREVOUTC", 0x1AB, 0x00 },
+    { "EVSYS_USEREVOUTD", 0x1AC, 0x00 },
+    { "EVSYS_USEREVOUTE", 0x1AD, 0x00 },
+    { "EVSYS_USEREVOUTF", 0x1AE, 0x00 },
+    { "EVSYS_USERUSART0", 0x1AF, 0x00 },
+    { "EVSYS_USERUSART1", 0x1B0, 0x00 },
+    { "EVSYS_USERUSART2", 0x1B1, 0x00 },
+    { "EVSYS_USERUSART3", 0x1B2, 0x00 },
+    { "EVSYS_USERTCA0", 0x1B3, 0x00 },
+    { "EVSYS_USERTCB0", 0x1B4, 0x00 },
+    { "EVSYS_USERTCB1", 0x1B5, 0x00 },
+    { "EVSYS_USERTCB2", 0x1B6, 0x00 },
+    { "EVSYS_USERTCB3", 0x1B7, 0x00 },
+    { "CCL_CTRLA" , 0x1C0, 0x00 },
+    { "CCL_SEQCTRL0", 0x1C1, 0x00 },
+    { "CCL_SEQCTRL1", 0x1C2, 0x00 },
+    { "CCL_INTCTRL0", 0x1C5, 0x00 },
+    { "CCL_INTFLAGS", 0x1C7, 0x00 },
+    { "CCL_LUT0CTRLA", 0x1C8, 0x00 },
+    { "CCL_LUT0CTRLB", 0x1C9, 0x00 },
+    { "CCL_LUT0CTRLC", 0x1CA, 0x00 },
+    { "CCL_TRUTH0", 0x1CB, 0x00 },
+    { "CCL_LUT1CTRLA", 0x1CC, 0x00 },
+    { "CCL_LUT1CTRLB", 0x1CD, 0x00 },
+    { "CCL_LUT1CTRLC", 0x1CE, 0x00 },
+    { "CCL_TRUTH1", 0x1CF, 0x00 },
+    { "CCL_LUT2CTRLA", 0x1D0, 0x00 },
+    { "CCL_LUT2CTRLB", 0x1D1, 0x00 },
+    { "CCL_LUT2CTRLC", 0x1D2, 0x00 },
+    { "CCL_TRUTH2", 0x1D3, 0x00 },
+    { "CCL_LUT3CTRLA", 0x1D4, 0x00 },
+    { "CCL_LUT3CTRLB", 0x1D5, 0x00 },
+    { "CCL_LUT3CTRLC", 0x1D6, 0x00 },
+    { "CCL_TRUTH3", 0x1D7, 0x00 },
+    { "PORTA_DIR" , 0x400, 0x00 },
+    { "PORTA_DIRSET", 0x401, 0x00 },
+    { "PORTA_DIRCLR", 0x402, 0x00 },
+    { "PORTA_DIRTGL", 0x403, 0x00 },
+    { "PORTA_OUT" , 0x404, 0x00 },
+    { "PORTA_OUTSET", 0x405, 0x00 },
+    { "PORTA_OUTCLR", 0x406, 0x00 },
+    { "PORTA_OUTTGL", 0x407, 0x00 },
+    { "PORTA_IN"  , 0x408, 0x00 },
+    { "PORTA_INTFLAGS", 0x409, 0x00 },
+    { "PORTA_PORTCTRL", 0x40A, 0x00 },
+    { "PORTA_PIN0CTRL", 0x410, 0x00 },
+    { "PORTA_PIN1CTRL", 0x411, 0x00 },
+    { "PORTA_PIN2CTRL", 0x412, 0x00 },
+    { "PORTA_PIN3CTRL", 0x413, 0x00 },
+    { "PORTA_PIN4CTRL", 0x414, 0x00 },
+    { "PORTA_PIN5CTRL", 0x415, 0x00 },
+    { "PORTA_PIN6CTRL", 0x416, 0x00 },
+    { "PORTA_PIN7CTRL", 0x417, 0x00 },
+    { "PORTB_DIR" , 0x420, 0x00 },
+    { "PORTB_DIRSET", 0x421, 0x00 },
+    { "PORTB_DIRCLR", 0x422, 0x00 },
+    { "PORTB_DIRTGL", 0x423, 0x00 },
+    { "PORTB_OUT" , 0x424, 0x00 },
+    { "PORTB_OUTSET", 0x425, 0x00 },
+    { "PORTB_OUTCLR", 0x426, 0x00 },
+    { "PORTB_OUTTGL", 0x427, 0x00 },
+    { "PORTB_IN"  , 0x428, 0x00 },
+    { "PORTB_INTFLAGS", 0x429, 0x00 },
+    { "PORTB_PORTCTRL", 0x42A, 0x00 },
+    { "PORTB_PIN0CTRL", 0x430, 0x00 },
+    { "PORTB_PIN1CTRL", 0x431, 0x00 },
+    { "PORTB_PIN2CTRL", 0x432, 0x00 },
+    { "PORTB_PIN3CTRL", 0x433, 0x00 },
+    { "PORTB_PIN4CTRL", 0x434, 0x00 },
+    { "PORTB_PIN5CTRL", 0x435, 0x00 },
+    { "PORTB_PIN6CTRL", 0x436, 0x00 },
+    { "PORTB_PIN7CTRL", 0x437, 0x00 },
+    { "PORTC_DIR" , 0x440, 0x00 },
+    { "PORTC_DIRSET", 0x441, 0x00 },
+    { "PORTC_DIRCLR", 0x442, 0x00 },
+    { "PORTC_DIRTGL", 0x443, 0x00 },
+    { "PORTC_OUT" , 0x444, 0x00 },
+    { "PORTC_OUTSET", 0x445, 0x00 },
+    { "PORTC_OUTCLR", 0x446, 0x00 },
+    { "PORTC_OUTTGL", 0x447, 0x00 },
+    { "PORTC_IN"  , 0x448, 0x00 },
+    { "PORTC_INTFLAGS", 0x449, 0x00 },
+    { "PORTC_PORTCTRL", 0x44A, 0x00 },
+    { "PORTC_PIN0CTRL", 0x450, 0x00 },
+    { "PORTC_PIN1CTRL", 0x451, 0x00 },
+    { "PORTC_PIN2CTRL", 0x452, 0x00 },
+    { "PORTC_PIN3CTRL", 0x453, 0x00 },
+    { "PORTC_PIN4CTRL", 0x454, 0x00 },
+    { "PORTC_PIN5CTRL", 0x455, 0x00 },
+    { "PORTC_PIN6CTRL", 0x456, 0x00 },
+    { "PORTC_PIN7CTRL", 0x457, 0x00 },
+    { "PORTD_DIR" , 0x460, 0x00 },
+    { "PORTD_DIRSET", 0x461, 0x00 },
+    { "PORTD_DIRCLR", 0x462, 0x00 },
+    { "PORTD_DIRTGL", 0x463, 0x00 },
+    { "PORTD_OUT" , 0x464, 0x00 },
+    { "PORTD_OUTSET", 0x465, 0x00 },
+    { "PORTD_OUTCLR", 0x466, 0x00 },
+    { "PORTD_OUTTGL", 0x467, 0x00 },
+    { "PORTD_IN"  , 0x468, 0x00 },
+    { "PORTD_INTFLAGS", 0x469, 0x00 },
+    { "PORTD_PORTCTRL", 0x46A, 0x00 },
+    { "PORTD_PIN0CTRL", 0x470, 0x00 },
+    { "PORTD_PIN1CTRL", 0x471, 0x00 },
+    { "PORTD_PIN2CTRL", 0x472, 0x00 },
+    { "PORTD_PIN3CTRL", 0x473, 0x00 },
+    { "PORTD_PIN4CTRL", 0x474, 0x00 },
+    { "PORTD_PIN5CTRL", 0x475, 0x00 },
+    { "PORTD_PIN6CTRL", 0x476, 0x00 },
+    { "PORTD_PIN7CTRL", 0x477, 0x00 },
+    { "PORTE_DIR" , 0x480, 0x00 },
+    { "PORTE_DIRSET", 0x481, 0x00 },
+    { "PORTE_DIRCLR", 0x482, 0x00 },
+    { "PORTE_DIRTGL", 0x483, 0x00 },
+    { "PORTE_OUT" , 0x484, 0x00 },
+    { "PORTE_OUTSET", 0x485, 0x00 },
+    { "PORTE_OUTCLR", 0x486, 0x00 },
+    { "PORTE_OUTTGL", 0x487, 0x00 },
+    { "PORTE_IN"  , 0x488, 0x00 },
+    { "PORTE_INTFLAGS", 0x489, 0x00 },
+    { "PORTE_PORTCTRL", 0x48A, 0x00 },
+    { "PORTE_PIN0CTRL", 0x490, 0x00 },
+    { "PORTE_PIN1CTRL", 0x491, 0x00 },
+    { "PORTE_PIN2CTRL", 0x492, 0x00 },
+    { "PORTE_PIN3CTRL", 0x493, 0x00 },
+    { "PORTE_PIN4CTRL", 0x494, 0x00 },
+    { "PORTE_PIN5CTRL", 0x495, 0x00 },
+    { "PORTE_PIN6CTRL", 0x496, 0x00 },
+    { "PORTE_PIN7CTRL", 0x497, 0x00 },
+    { "PORTF_DIR" , 0x4A0, 0x00 },
+    { "PORTF_DIRSET", 0x4A1, 0x00 },
+    { "PORTF_DIRCLR", 0x4A2, 0x00 },
+    { "PORTF_DIRTGL", 0x4A3, 0x00 },
+    { "PORTF_OUT" , 0x4A4, 0x00 },
+    { "PORTF_OUTSET", 0x4A5, 0x00 },
+    { "PORTF_OUTCLR", 0x4A6, 0x00 },
+    { "PORTF_OUTTGL", 0x4A7, 0x00 },
+    { "PORTF_IN"  , 0x4A8, 0x00 },
+    { "PORTF_INTFLAGS", 0x4A9, 0x00 },
+    { "PORTF_PORTCTRL", 0x4AA, 0x00 },
+    { "PORTF_PIN0CTRL", 0x4B0, 0x00 },
+    { "PORTF_PIN1CTRL", 0x4B1, 0x00 },
+    { "PORTF_PIN2CTRL", 0x4B2, 0x00 },
+    { "PORTF_PIN3CTRL", 0x4B3, 0x00 },
+    { "PORTF_PIN4CTRL", 0x4B4, 0x00 },
+    { "PORTF_PIN5CTRL", 0x4B5, 0x00 },
+    { "PORTF_PIN6CTRL", 0x4B6, 0x00 },
+    { "PORTF_PIN7CTRL", 0x4B7, 0x00 },
+    { "PORTMUX_EVSYSROUTEA", 0x5E0, 0x00 },
+    { "PORTMUX_CCLROUTEA", 0x5E1, 0x00 },
+    { "PORTMUX_USARTROUTEA", 0x5E2, 0x00 },
+    { "PORTMUX_TWISPIROUTEA", 0x5E3, 0x00 },
+    { "PORTMUX_TCAROUTEA", 0x5E4, 0x00 },
+    { "PORTMUX_TCBROUTEA", 0x5E5, 0x00 },
+    { "ADC0_CTRLA", 0x600, 0x00 },
+    { "ADC0_CTRLB", 0x601, 0x00 },
+    { "ADC0_CTRLC", 0x602, 0x00 },
+    { "ADC0_CTRLD", 0x603, 0x00 },
+    { "ADC0_CTRLE", 0x604, 0x00 },
+    { "ADC0_SAMPCTRL", 0x605, 0x00 },
+    { "ADC0_MUXPOS", 0x606, 0x00 },
+    { "ADC0_COMMAND", 0x608, 0x00 },
+    { "ADC0_EVCTRL", 0x609, 0x00 },
+    { "ADC0_INTCTRL", 0x60A, 0x00 },
+    { "ADC0_INTFLAGS", 0x60B, 0x00 },
+    { "ADC0_DBGCTRL", 0x60C, 0x00 },
+    { "ADC0_TEMP" , 0x60D, 0x00 },
+    { "ADC0_RESL" , 0x610, 0x00 },
+    { "ADC0_RESH" , 0x611, 0x00 },
+    { "ADC0_WINLTL", 0x612, 0x00 },
+    { "ADC0_WINLTH", 0x613, 0x00 },
+    { "ADC0_WINHTL", 0x614, 0x00 },
+    { "ADC0_WINHTH", 0x615, 0x00 },
+    { "ADC0_CALIB", 0x616, 0x00 },
+    { "AC0_CTRLA" , 0x680, 0x00 },
+    { "AC0_MUXCTRLA", 0x682, 0x00 },
+    { "AC0_DACREF", 0x684, 0x00 },
+    { "AC0_INTCTRL", 0x686, 0x00 },
+    { "AC0_STATUS", 0x687, 0x00 },
+    { "USART0_RXDATAL", 0x800, 0x00 },
+    { "USART0_RXDATAH", 0x801, 0x00 },
+    { "USART0_TXDATAL", 0x802, 0x00 },
+    { "USART0_TXDATAH", 0x803, 0x00 },
+    { "USART0_STATUS", 0x804, 0x00 },
+    { "USART0_CTRLA", 0x805, 0x00 },
+    { "USART0_CTRLB", 0x806, 0x00 },
+    { "USART0_CTRLC", 0x807, 0x00 },
+    { "USART0_BAUDL", 0x808, 0x00 },
+    { "USART0_BAUDH", 0x809, 0x00 },
+    { "USART0_CTRLD", 0x80A, 0x00 },
+    { "USART0_DBGCTRL", 0x80B, 0x00 },
+    { "USART0_EVCTRL", 0x80C, 0x00 },
+    { "USART0_TXPLCTRL", 0x80D, 0x00 },
+    { "USART0_RXPLCTRL", 0x80E, 0x00 },
+    { "USART1_RXDATAL", 0x820, 0x00 },
+    { "USART1_RXDATAH", 0x821, 0x00 },
+    { "USART1_TXDATAL", 0x822, 0x00 },
+    { "USART1_TXDATAH", 0x823, 0x00 },
+    { "USART1_STATUS", 0x824, 0x00 },
+    { "USART1_CTRLA", 0x825, 0x00 },
+    { "USART1_CTRLB", 0x826, 0x00 },
+    { "USART1_CTRLC", 0x827, 0x00 },
+    { "USART1_BAUDL", 0x828, 0x00 },
+    { "USART1_BAUDH", 0x829, 0x00 },
+    { "USART1_CTRLD", 0x82A, 0x00 },
+    { "USART1_DBGCTRL", 0x82B, 0x00 },
+    { "USART1_EVCTRL", 0x82C, 0x00 },
+    { "USART1_TXPLCTRL", 0x82D, 0x00 },
+    { "USART1_RXPLCTRL", 0x82E, 0x00 },
+    { "USART2_RXDATAL", 0x840, 0x00 },
+    { "USART2_RXDATAH", 0x841, 0x00 },
+    { "USART2_TXDATAL", 0x842, 0x00 },
+    { "USART2_TXDATAH", 0x843, 0x00 },
+    { "USART2_STATUS", 0x844, 0x00 },
+    { "USART2_CTRLA", 0x845, 0x00 },
+    { "USART2_CTRLB", 0x846, 0x00 },
+    { "USART2_CTRLC", 0x847, 0x00 },
+    { "USART2_BAUDL", 0x848, 0x00 },
+    { "USART2_BAUDH", 0x849, 0x00 },
+    { "USART2_CTRLD", 0x84A, 0x00 },
+    { "USART2_DBGCTRL", 0x84B, 0x00 },
+    { "USART2_EVCTRL", 0x84C, 0x00 },
+    { "USART2_TXPLCTRL", 0x84D, 0x00 },
+    { "USART2_RXPLCTRL", 0x84E, 0x00 },
+    { "TWI0_CTRLA", 0x8A0, 0x00 },
+    { "TWI0_DUALCTRL", 0x8A1, 0x00 },
+    { "TWI0_DBGCTRL", 0x8A2, 0x00 },
+    { "TWI0_MCTRLA", 0x8A3, 0x00 },
+    { "TWI0_MCTRLB", 0x8A4, 0x00 },
+    { "TWI0_MSTATUS", 0x8A5, 0x00 },
+    { "TWI0_MBAUD", 0x8A6, 0x00 },
+    { "TWI0_MADDR", 0x8A7, 0x00 },
+    { "TWI0_MDATA", 0x8A8, 0x00 },
+    { "TWI0_SCTRLA", 0x8A9, 0x00 },
+    { "TWI0_SCTRLB", 0x8AA, 0x00 },
+    { "TWI0_SSTATUS", 0x8AB, 0x00 },
+    { "TWI0_SADDR", 0x8AC, 0x00 },
+    { "TWI0_SDATA", 0x8AD, 0x00 },
+    { "TWI0_SADDRMASK", 0x8AE, 0x00 },
+    { "SPI0_CTRLA", 0x8C0, 0x00 },
+    { "SPI0_CTRLB", 0x8C1, 0x00 },
+    { "SPI0_INTCTRL", 0x8C2, 0x00 },
+    { "SPI0_INTFLAGS", 0x8C3, 0x00 },
+    { "SPI0_DATA" , 0x8C4, 0x00 },
+    { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 },
+    { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 },
+    { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 },
+    { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 },
+    { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 },
+    { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 },
+    { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 },
+    { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 },
+    { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 },
+    { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 },
+    { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 },
+    { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 },
+    { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 },
+    { "TCA0_SPLIT_LCNT", 0xA20, 0x00 },
+    { "TCA0_SPLIT_HCNT", 0xA21, 0x00 },
+    { "TCA0_SPLIT_LPER", 0xA26, 0x00 },
+    { "TCA0_SPLIT_HPER", 0xA27, 0x00 },
+    { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 },
+    { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 },
+    { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 },
+    { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 },
+    { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 },
+    { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 },
+    { "TCB0_CTRLA", 0xA80, 0x00 },
+    { "TCB0_CTRLB", 0xA81, 0x00 },
+    { "TCB0_EVCTRL", 0xA84, 0x00 },
+    { "TCB0_INTCTRL", 0xA85, 0x00 },
+    { "TCB0_INTFLAGS", 0xA86, 0x00 },
+    { "TCB0_STATUS", 0xA87, 0x00 },
+    { "TCB0_DBGCTRL", 0xA88, 0x00 },
+    { "TCB0_TEMP" , 0xA89, 0x00 },
+    { "TCB0_CNTL" , 0xA8A, 0x00 },
+    { "TCB0_CNTH" , 0xA8B, 0x00 },
+    { "TCB0_CCMPL", 0xA8C, 0x00 },
+    { "TCB0_CCMPH", 0xA8D, 0x00 },
+    { "TCB1_CTRLA", 0xA90, 0x00 },
+    { "TCB1_CTRLB", 0xA91, 0x00 },
+    { "TCB1_EVCTRL", 0xA94, 0x00 },
+    { "TCB1_INTCTRL", 0xA95, 0x00 },
+    { "TCB1_INTFLAGS", 0xA96, 0x00 },
+    { "TCB1_STATUS", 0xA97, 0x00 },
+    { "TCB1_DBGCTRL", 0xA98, 0x00 },
+    { "TCB1_TEMP" , 0xA99, 0x00 },
+    { "TCB1_CNTL" , 0xA9A, 0x00 },
+    { "TCB1_CNTH" , 0xA9B, 0x00 },
+    { "TCB1_CCMPL", 0xA9C, 0x00 },
+    { "TCB1_CCMPH", 0xA9D, 0x00 },
+    { "TCB2_CTRLA", 0xAA0, 0x00 },
+    { "TCB2_CTRLB", 0xAA1, 0x00 },
+    { "TCB2_EVCTRL", 0xAA4, 0x00 },
+    { "TCB2_INTCTRL", 0xAA5, 0x00 },
+    { "TCB2_INTFLAGS", 0xAA6, 0x00 },
+    { "TCB2_STATUS", 0xAA7, 0x00 },
+    { "TCB2_DBGCTRL", 0xAA8, 0x00 },
+    { "TCB2_TEMP" , 0xAA9, 0x00 },
+    { "TCB2_CNTL" , 0xAAA, 0x00 },
+    { "TCB2_CNTH" , 0xAAB, 0x00 },
+    { "TCB2_CCMPL", 0xAAC, 0x00 },
+    { "TCB2_CCMPH", 0xAAD, 0x00 },
+    { "SYSCFG_REVID", 0xF01, 0x00 },
+    { "SYSCFG_EXTBRK", 0xF02, 0x00 },
+    { "SYSCFG_OCDM", 0xF18, 0x00 },
+    { "SYSCFG_OCDMS", 0xF19, 0x00 },
+    { "NVMCTRL_CTRLA", 0x1000, 0x00 },
+    { "NVMCTRL_CTRLB", 0x1001, 0x00 },
+    { "NVMCTRL_STATUS", 0x1002, 0x00 },
+    { "NVMCTRL_INTCTRL", 0x1003, 0x00 },
+    { "NVMCTRL_INTFLAGS", 0x1004, 0x00 },
+    { "NVMCTRL_DATAL", 0x1006, 0x00 },
+    { "NVMCTRL_DATAH", 0x1007, 0x00 },
+    { "NVMCTRL_ADDRL", 0x1008, 0x00 },
+    { "NVMCTRL_ADDRH", 0x1009, 0x00 },
+    { "SIGROW_DEVICEID0", 0x1100, 0x00 },
+    { "SIGROW_DEVICEID1", 0x1101, 0x00 },
+    { "SIGROW_DEVICEID2", 0x1102, 0x00 },
+    { "SIGROW_SERNUM0", 0x1103, 0x00 },
+    { "SIGROW_SERNUM1", 0x1104, 0x00 },
+    { "SIGROW_SERNUM2", 0x1105, 0x00 },
+    { "SIGROW_SERNUM3", 0x1106, 0x00 },
+    { "SIGROW_SERNUM4", 0x1107, 0x00 },
+    { "SIGROW_SERNUM5", 0x1108, 0x00 },
+    { "SIGROW_SERNUM6", 0x1109, 0x00 },
+    { "SIGROW_SERNUM7", 0x110A, 0x00 },
+    { "SIGROW_SERNUM8", 0x110B, 0x00 },
+    { "SIGROW_SERNUM9", 0x110C, 0x00 },
+    { "SIGROW_OSCCAL32K", 0x1114, 0x00 },
+    { "SIGROW_OSCCAL16M0", 0x1118, 0x00 },
+    { "SIGROW_OSCCAL16M1", 0x1119, 0x00 },
+    { "SIGROW_OSCCAL20M0", 0x111A, 0x00 },
+    { "SIGROW_OSCCAL20M1", 0x111B, 0x00 },
+    { "SIGROW_TEMPSENSE0", 0x1120, 0x00 },
+    { "SIGROW_TEMPSENSE1", 0x1121, 0x00 },
+    { "SIGROW_OSC16ERR3V", 0x1122, 0x00 },
+    { "SIGROW_OSC16ERR5V", 0x1123, 0x00 },
+    { "SIGROW_OSC20ERR3V", 0x1124, 0x00 },
+    { "SIGROW_OSC20ERR5V", 0x1125, 0x00 },
+    { "SIGROW_CHECKSUM1", 0x112F, 0x00 },
+    { "FUSE_WDTCFG", 0x1280, 0x00 },
+    { "FUSE_BODCFG", 0x1281, 0x00 },
+    { "FUSE_OSCCFG", 0x1282, 0x00 },
+    { "FUSE_SYSCFG0", 0x1285, 0x00 },
+    { "FUSE_SYSCFG1", 0x1286, 0x00 },
+    { "FUSE_APPEND", 0x1287, 0x00 },
+    { "FUSE_BOOTEND", 0x1288, 0x00 },
+    { "LOCKBIT_LOCKBIT", 0x128A, 0x00 },
+    { "USERROW_USERROW0", 0x1300, 0x00 },
+    { "USERROW_USERROW1", 0x1301, 0x00 },
+    { "USERROW_USERROW2", 0x1302, 0x00 },
+    { "USERROW_USERROW3", 0x1303, 0x00 },
+    { "USERROW_USERROW4", 0x1304, 0x00 },
+    { "USERROW_USERROW5", 0x1305, 0x00 },
+    { "USERROW_USERROW6", 0x1306, 0x00 },
+    { "USERROW_USERROW7", 0x1307, 0x00 },
+    { "USERROW_USERROW8", 0x1308, 0x00 },
+    { "USERROW_USERROW9", 0x1309, 0x00 },
+    { "USERROW_USERROW10", 0x130A, 0x00 },
+    { "USERROW_USERROW11", 0x130B, 0x00 },
+    { "USERROW_USERROW12", 0x130C, 0x00 },
+    { "USERROW_USERROW13", 0x130D, 0x00 },
+    { "USERROW_USERROW14", 0x130E, 0x00 },
+    { "USERROW_USERROW15", 0x130F, 0x00 },
+    { "USERROW_USERROW16", 0x1310, 0x00 },
+    { "USERROW_USERROW17", 0x1311, 0x00 },
+    { "USERROW_USERROW18", 0x1312, 0x00 },
+    { "USERROW_USERROW19", 0x1313, 0x00 },
+    { "USERROW_USERROW20", 0x1314, 0x00 },
+    { "USERROW_USERROW21", 0x1315, 0x00 },
+    { "USERROW_USERROW22", 0x1316, 0x00 },
+    { "USERROW_USERROW23", 0x1317, 0x00 },
+    { "USERROW_USERROW24", 0x1318, 0x00 },
+    { "USERROW_USERROW25", 0x1319, 0x00 },
+    { "USERROW_USERROW26", 0x131A, 0x00 },
+    { "USERROW_USERROW27", 0x131B, 0x00 },
+    { "USERROW_USERROW28", 0x131C, 0x00 },
+    { "USERROW_USERROW29", 0x131D, 0x00 },
+    { "USERROW_USERROW30", 0x131E, 0x00 },
+    { "USERROW_USERROW31", 0x131F, 0x00 },
+    { "USERROW_USERROW32", 0x1320, 0x00 },
+    { "USERROW_USERROW33", 0x1321, 0x00 },
+    { "USERROW_USERROW34", 0x1322, 0x00 },
+    { "USERROW_USERROW35", 0x1323, 0x00 },
+    { "USERROW_USERROW36", 0x1324, 0x00 },
+    { "USERROW_USERROW37", 0x1325, 0x00 },
+    { "USERROW_USERROW38", 0x1326, 0x00 },
+    { "USERROW_USERROW39", 0x1327, 0x00 },
+    { "USERROW_USERROW40", 0x1328, 0x00 },
+    { "USERROW_USERROW41", 0x1329, 0x00 },
+    { "USERROW_USERROW42", 0x132A, 0x00 },
+    { "USERROW_USERROW43", 0x132B, 0x00 },
+    { "USERROW_USERROW44", 0x132C, 0x00 },
+    { "USERROW_USERROW45", 0x132D, 0x00 },
+    { "USERROW_USERROW46", 0x132E, 0x00 },
+    { "USERROW_USERROW47", 0x132F, 0x00 },
+    { "USERROW_USERROW48", 0x1330, 0x00 },
+    { "USERROW_USERROW49", 0x1331, 0x00 },
+    { "USERROW_USERROW50", 0x1332, 0x00 },
+    { "USERROW_USERROW51", 0x1333, 0x00 },
+    { "USERROW_USERROW52", 0x1334, 0x00 },
+    { "USERROW_USERROW53", 0x1335, 0x00 },
+    { "USERROW_USERROW54", 0x1336, 0x00 },
+    { "USERROW_USERROW55", 0x1337, 0x00 },
+    { "USERROW_USERROW56", 0x1338, 0x00 },
+    { "USERROW_USERROW57", 0x1339, 0x00 },
+    { "USERROW_USERROW58", 0x133A, 0x00 },
+    { "USERROW_USERROW59", 0x133B, 0x00 },
+    { "USERROW_USERROW60", 0x133C, 0x00 },
+    { "USERROW_USERROW61", 0x133D, 0x00 },
+    { "USERROW_USERROW62", 0x133E, 0x00 },
+    { "USERROW_USERROW63", 0x133F, 0x00 },
+    { 0, 0, 0}
+};
+
+
+gdb_io_reg_def_type atmega4809_io_registers[] =
+{
+    { "VPORTA_DIR", 0x0, 0x00 },
+    { "VPORTA_OUT", 0x1, 0x00 },
+    { "VPORTA_IN" , 0x2, 0x00 },
+    { "VPORTA_INTFLAGS", 0x3, 0x00 },
+    { "VPORTB_DIR", 0x4, 0x00 },
+    { "VPORTB_OUT", 0x5, 0x00 },
+    { "VPORTB_IN" , 0x6, 0x00 },
+    { "VPORTB_INTFLAGS", 0x7, 0x00 },
+    { "VPORTC_DIR", 0x8, 0x00 },
+    { "VPORTC_OUT", 0x9, 0x00 },
+    { "VPORTC_IN" , 0xA, 0x00 },
+    { "VPORTC_INTFLAGS", 0xB, 0x00 },
+    { "VPORTD_DIR", 0xC, 0x00 },
+    { "VPORTD_OUT", 0xD, 0x00 },
+    { "VPORTD_IN" , 0xE, 0x00 },
+    { "VPORTD_INTFLAGS", 0xF, 0x00 },
+    { "VPORTE_DIR", 0x10, 0x00 },
+    { "VPORTE_OUT", 0x11, 0x00 },
+    { "VPORTE_IN" , 0x12, 0x00 },
+    { "VPORTE_INTFLAGS", 0x13, 0x00 },
+    { "VPORTF_DIR", 0x14, 0x00 },
+    { "VPORTF_OUT", 0x15, 0x00 },
+    { "VPORTF_IN" , 0x16, 0x00 },
+    { "VPORTF_INTFLAGS", 0x17, 0x00 },
+    { "GPIO_GPIO0", 0x1C, 0x00 },
+    { "GPIO_GPIO1", 0x1D, 0x00 },
+    { "GPIO_GPIO2", 0x1E, 0x00 },
+    { "GPIO_GPIO3", 0x1F, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "RSTCTRL_RSTFR", 0x40, 0x00 },
+    { "RSTCTRL_SWRR", 0x41, 0x00 },
+    { "SLPCTRL_CTRLA", 0x50, 0x00 },
+    { "CLKCTRL_MCLKCTRLA", 0x60, 0x00 },
+    { "CLKCTRL_MCLKCTRLB", 0x61, 0x00 },
+    { "CLKCTRL_MCLKLOCK", 0x62, 0x00 },
+    { "CLKCTRL_MCLKSTATUS", 0x63, 0x00 },
+    { "CLKCTRL_OSC20MCTRLA", 0x70, 0x00 },
+    { "CLKCTRL_OSC20MCALIBA", 0x71, 0x00 },
+    { "CLKCTRL_OSC20MCALIBB", 0x72, 0x00 },
+    { "CLKCTRL_OSC32KCTRLA", 0x78, 0x00 },
+    { "CLKCTRL_XOSC32KCTRLA", 0x7C, 0x00 },
+    { "BOD_CTRLA" , 0x80, 0x00 },
+    { "BOD_CTRLB" , 0x81, 0x00 },
+    { "BOD_VLMCTRLA", 0x88, 0x00 },
+    { "BOD_INTCTRL", 0x89, 0x00 },
+    { "BOD_INTFLAGS", 0x8A, 0x00 },
+    { "BOD_STATUS", 0x8B, 0x00 },
+    { "VREF_CTRLA", 0xA0, 0x00 },
+    { "VREF_CTRLB", 0xA1, 0x00 },
+    { "WDT_CTRLA" , 0x100, 0x00 },
+    { "WDT_STATUS", 0x101, 0x00 },
+    { "CPUINT_CTRLA", 0x110, 0x00 },
+    { "CPUINT_STATUS", 0x111, 0x00 },
+    { "CPUINT_LVL0PRI", 0x112, 0x00 },
+    { "CPUINT_LVL1VEC", 0x113, 0x00 },
+    { "CRCSCAN_CTRLA", 0x120, 0x00 },
+    { "CRCSCAN_CTRLB", 0x121, 0x00 },
+    { "CRCSCAN_STATUS", 0x122, 0x00 },
+    { "RTC_CTRLA" , 0x140, 0x00 },
+    { "RTC_STATUS", 0x141, 0x00 },
+    { "RTC_INTCTRL", 0x142, 0x00 },
+    { "RTC_INTFLAGS", 0x143, 0x00 },
+    { "RTC_TEMP"  , 0x144, 0x00 },
+    { "RTC_DBGCTRL", 0x145, 0x00 },
+    { "RTC_CALIB" , 0x146, 0x00 },
+    { "RTC_CLKSEL", 0x147, 0x00 },
+    { "RTC_CNTL"  , 0x148, 0x00 },
+    { "RTC_CNTH"  , 0x149, 0x00 },
+    { "RTC_PERL"  , 0x14A, 0x00 },
+    { "RTC_PERH"  , 0x14B, 0x00 },
+    { "RTC_CMPL"  , 0x14C, 0x00 },
+    { "RTC_CMPH"  , 0x14D, 0x00 },
+    { "RTC_PITCTRLA", 0x150, 0x00 },
+    { "RTC_PITSTATUS", 0x151, 0x00 },
+    { "RTC_PITINTCTRL", 0x152, 0x00 },
+    { "RTC_PITINTFLAGS", 0x153, 0x00 },
+    { "RTC_PITDBGCTRL", 0x155, 0x00 },
+    { "EVSYS_STROBE", 0x180, 0x00 },
+    { "EVSYS_CHANNEL0", 0x190, 0x00 },
+    { "EVSYS_CHANNEL1", 0x191, 0x00 },
+    { "EVSYS_CHANNEL2", 0x192, 0x00 },
+    { "EVSYS_CHANNEL3", 0x193, 0x00 },
+    { "EVSYS_CHANNEL4", 0x194, 0x00 },
+    { "EVSYS_CHANNEL5", 0x195, 0x00 },
+    { "EVSYS_CHANNEL6", 0x196, 0x00 },
+    { "EVSYS_CHANNEL7", 0x197, 0x00 },
+    { "EVSYS_USERCCLLUT0A", 0x1A0, 0x00 },
+    { "EVSYS_USERCCLLUT0B", 0x1A1, 0x00 },
+    { "EVSYS_USERCCLLUT1A", 0x1A2, 0x00 },
+    { "EVSYS_USERCCLLUT1B", 0x1A3, 0x00 },
+    { "EVSYS_USERCCLLUT2A", 0x1A4, 0x00 },
+    { "EVSYS_USERCCLLUT2B", 0x1A5, 0x00 },
+    { "EVSYS_USERCCLLUT3A", 0x1A6, 0x00 },
+    { "EVSYS_USERCCLLUT3B", 0x1A7, 0x00 },
+    { "EVSYS_USERADC0", 0x1A8, 0x00 },
+    { "EVSYS_USEREVOUTA", 0x1A9, 0x00 },
+    { "EVSYS_USEREVOUTB", 0x1AA, 0x00 },
+    { "EVSYS_USEREVOUTC", 0x1AB, 0x00 },
+    { "EVSYS_USEREVOUTD", 0x1AC, 0x00 },
+    { "EVSYS_USEREVOUTE", 0x1AD, 0x00 },
+    { "EVSYS_USEREVOUTF", 0x1AE, 0x00 },
+    { "EVSYS_USERUSART0", 0x1AF, 0x00 },
+    { "EVSYS_USERUSART1", 0x1B0, 0x00 },
+    { "EVSYS_USERUSART2", 0x1B1, 0x00 },
+    { "EVSYS_USERUSART3", 0x1B2, 0x00 },
+    { "EVSYS_USERTCA0", 0x1B3, 0x00 },
+    { "EVSYS_USERTCB0", 0x1B4, 0x00 },
+    { "EVSYS_USERTCB1", 0x1B5, 0x00 },
+    { "EVSYS_USERTCB2", 0x1B6, 0x00 },
+    { "EVSYS_USERTCB3", 0x1B7, 0x00 },
+    { "CCL_CTRLA" , 0x1C0, 0x00 },
+    { "CCL_SEQCTRL0", 0x1C1, 0x00 },
+    { "CCL_SEQCTRL1", 0x1C2, 0x00 },
+    { "CCL_INTCTRL0", 0x1C5, 0x00 },
+    { "CCL_INTFLAGS", 0x1C7, 0x00 },
+    { "CCL_LUT0CTRLA", 0x1C8, 0x00 },
+    { "CCL_LUT0CTRLB", 0x1C9, 0x00 },
+    { "CCL_LUT0CTRLC", 0x1CA, 0x00 },
+    { "CCL_TRUTH0", 0x1CB, 0x00 },
+    { "CCL_LUT1CTRLA", 0x1CC, 0x00 },
+    { "CCL_LUT1CTRLB", 0x1CD, 0x00 },
+    { "CCL_LUT1CTRLC", 0x1CE, 0x00 },
+    { "CCL_TRUTH1", 0x1CF, 0x00 },
+    { "CCL_LUT2CTRLA", 0x1D0, 0x00 },
+    { "CCL_LUT2CTRLB", 0x1D1, 0x00 },
+    { "CCL_LUT2CTRLC", 0x1D2, 0x00 },
+    { "CCL_TRUTH2", 0x1D3, 0x00 },
+    { "CCL_LUT3CTRLA", 0x1D4, 0x00 },
+    { "CCL_LUT3CTRLB", 0x1D5, 0x00 },
+    { "CCL_LUT3CTRLC", 0x1D6, 0x00 },
+    { "CCL_TRUTH3", 0x1D7, 0x00 },
+    { "PORTA_DIR" , 0x400, 0x00 },
+    { "PORTA_DIRSET", 0x401, 0x00 },
+    { "PORTA_DIRCLR", 0x402, 0x00 },
+    { "PORTA_DIRTGL", 0x403, 0x00 },
+    { "PORTA_OUT" , 0x404, 0x00 },
+    { "PORTA_OUTSET", 0x405, 0x00 },
+    { "PORTA_OUTCLR", 0x406, 0x00 },
+    { "PORTA_OUTTGL", 0x407, 0x00 },
+    { "PORTA_IN"  , 0x408, 0x00 },
+    { "PORTA_INTFLAGS", 0x409, 0x00 },
+    { "PORTA_PORTCTRL", 0x40A, 0x00 },
+    { "PORTA_PIN0CTRL", 0x410, 0x00 },
+    { "PORTA_PIN1CTRL", 0x411, 0x00 },
+    { "PORTA_PIN2CTRL", 0x412, 0x00 },
+    { "PORTA_PIN3CTRL", 0x413, 0x00 },
+    { "PORTA_PIN4CTRL", 0x414, 0x00 },
+    { "PORTA_PIN5CTRL", 0x415, 0x00 },
+    { "PORTA_PIN6CTRL", 0x416, 0x00 },
+    { "PORTA_PIN7CTRL", 0x417, 0x00 },
+    { "PORTB_DIR" , 0x420, 0x00 },
+    { "PORTB_DIRSET", 0x421, 0x00 },
+    { "PORTB_DIRCLR", 0x422, 0x00 },
+    { "PORTB_DIRTGL", 0x423, 0x00 },
+    { "PORTB_OUT" , 0x424, 0x00 },
+    { "PORTB_OUTSET", 0x425, 0x00 },
+    { "PORTB_OUTCLR", 0x426, 0x00 },
+    { "PORTB_OUTTGL", 0x427, 0x00 },
+    { "PORTB_IN"  , 0x428, 0x00 },
+    { "PORTB_INTFLAGS", 0x429, 0x00 },
+    { "PORTB_PORTCTRL", 0x42A, 0x00 },
+    { "PORTB_PIN0CTRL", 0x430, 0x00 },
+    { "PORTB_PIN1CTRL", 0x431, 0x00 },
+    { "PORTB_PIN2CTRL", 0x432, 0x00 },
+    { "PORTB_PIN3CTRL", 0x433, 0x00 },
+    { "PORTB_PIN4CTRL", 0x434, 0x00 },
+    { "PORTB_PIN5CTRL", 0x435, 0x00 },
+    { "PORTB_PIN6CTRL", 0x436, 0x00 },
+    { "PORTB_PIN7CTRL", 0x437, 0x00 },
+    { "PORTC_DIR" , 0x440, 0x00 },
+    { "PORTC_DIRSET", 0x441, 0x00 },
+    { "PORTC_DIRCLR", 0x442, 0x00 },
+    { "PORTC_DIRTGL", 0x443, 0x00 },
+    { "PORTC_OUT" , 0x444, 0x00 },
+    { "PORTC_OUTSET", 0x445, 0x00 },
+    { "PORTC_OUTCLR", 0x446, 0x00 },
+    { "PORTC_OUTTGL", 0x447, 0x00 },
+    { "PORTC_IN"  , 0x448, 0x00 },
+    { "PORTC_INTFLAGS", 0x449, 0x00 },
+    { "PORTC_PORTCTRL", 0x44A, 0x00 },
+    { "PORTC_PIN0CTRL", 0x450, 0x00 },
+    { "PORTC_PIN1CTRL", 0x451, 0x00 },
+    { "PORTC_PIN2CTRL", 0x452, 0x00 },
+    { "PORTC_PIN3CTRL", 0x453, 0x00 },
+    { "PORTC_PIN4CTRL", 0x454, 0x00 },
+    { "PORTC_PIN5CTRL", 0x455, 0x00 },
+    { "PORTC_PIN6CTRL", 0x456, 0x00 },
+    { "PORTC_PIN7CTRL", 0x457, 0x00 },
+    { "PORTD_DIR" , 0x460, 0x00 },
+    { "PORTD_DIRSET", 0x461, 0x00 },
+    { "PORTD_DIRCLR", 0x462, 0x00 },
+    { "PORTD_DIRTGL", 0x463, 0x00 },
+    { "PORTD_OUT" , 0x464, 0x00 },
+    { "PORTD_OUTSET", 0x465, 0x00 },
+    { "PORTD_OUTCLR", 0x466, 0x00 },
+    { "PORTD_OUTTGL", 0x467, 0x00 },
+    { "PORTD_IN"  , 0x468, 0x00 },
+    { "PORTD_INTFLAGS", 0x469, 0x00 },
+    { "PORTD_PORTCTRL", 0x46A, 0x00 },
+    { "PORTD_PIN0CTRL", 0x470, 0x00 },
+    { "PORTD_PIN1CTRL", 0x471, 0x00 },
+    { "PORTD_PIN2CTRL", 0x472, 0x00 },
+    { "PORTD_PIN3CTRL", 0x473, 0x00 },
+    { "PORTD_PIN4CTRL", 0x474, 0x00 },
+    { "PORTD_PIN5CTRL", 0x475, 0x00 },
+    { "PORTD_PIN6CTRL", 0x476, 0x00 },
+    { "PORTD_PIN7CTRL", 0x477, 0x00 },
+    { "PORTE_DIR" , 0x480, 0x00 },
+    { "PORTE_DIRSET", 0x481, 0x00 },
+    { "PORTE_DIRCLR", 0x482, 0x00 },
+    { "PORTE_DIRTGL", 0x483, 0x00 },
+    { "PORTE_OUT" , 0x484, 0x00 },
+    { "PORTE_OUTSET", 0x485, 0x00 },
+    { "PORTE_OUTCLR", 0x486, 0x00 },
+    { "PORTE_OUTTGL", 0x487, 0x00 },
+    { "PORTE_IN"  , 0x488, 0x00 },
+    { "PORTE_INTFLAGS", 0x489, 0x00 },
+    { "PORTE_PORTCTRL", 0x48A, 0x00 },
+    { "PORTE_PIN0CTRL", 0x490, 0x00 },
+    { "PORTE_PIN1CTRL", 0x491, 0x00 },
+    { "PORTE_PIN2CTRL", 0x492, 0x00 },
+    { "PORTE_PIN3CTRL", 0x493, 0x00 },
+    { "PORTE_PIN4CTRL", 0x494, 0x00 },
+    { "PORTE_PIN5CTRL", 0x495, 0x00 },
+    { "PORTE_PIN6CTRL", 0x496, 0x00 },
+    { "PORTE_PIN7CTRL", 0x497, 0x00 },
+    { "PORTF_DIR" , 0x4A0, 0x00 },
+    { "PORTF_DIRSET", 0x4A1, 0x00 },
+    { "PORTF_DIRCLR", 0x4A2, 0x00 },
+    { "PORTF_DIRTGL", 0x4A3, 0x00 },
+    { "PORTF_OUT" , 0x4A4, 0x00 },
+    { "PORTF_OUTSET", 0x4A5, 0x00 },
+    { "PORTF_OUTCLR", 0x4A6, 0x00 },
+    { "PORTF_OUTTGL", 0x4A7, 0x00 },
+    { "PORTF_IN"  , 0x4A8, 0x00 },
+    { "PORTF_INTFLAGS", 0x4A9, 0x00 },
+    { "PORTF_PORTCTRL", 0x4AA, 0x00 },
+    { "PORTF_PIN0CTRL", 0x4B0, 0x00 },
+    { "PORTF_PIN1CTRL", 0x4B1, 0x00 },
+    { "PORTF_PIN2CTRL", 0x4B2, 0x00 },
+    { "PORTF_PIN3CTRL", 0x4B3, 0x00 },
+    { "PORTF_PIN4CTRL", 0x4B4, 0x00 },
+    { "PORTF_PIN5CTRL", 0x4B5, 0x00 },
+    { "PORTF_PIN6CTRL", 0x4B6, 0x00 },
+    { "PORTF_PIN7CTRL", 0x4B7, 0x00 },
+    { "PORTMUX_EVSYSROUTEA", 0x5E0, 0x00 },
+    { "PORTMUX_CCLROUTEA", 0x5E1, 0x00 },
+    { "PORTMUX_USARTROUTEA", 0x5E2, 0x00 },
+    { "PORTMUX_TWISPIROUTEA", 0x5E3, 0x00 },
+    { "PORTMUX_TCAROUTEA", 0x5E4, 0x00 },
+    { "PORTMUX_TCBROUTEA", 0x5E5, 0x00 },
+    { "ADC0_CTRLA", 0x600, 0x00 },
+    { "ADC0_CTRLB", 0x601, 0x00 },
+    { "ADC0_CTRLC", 0x602, 0x00 },
+    { "ADC0_CTRLD", 0x603, 0x00 },
+    { "ADC0_CTRLE", 0x604, 0x00 },
+    { "ADC0_SAMPCTRL", 0x605, 0x00 },
+    { "ADC0_MUXPOS", 0x606, 0x00 },
+    { "ADC0_COMMAND", 0x608, 0x00 },
+    { "ADC0_EVCTRL", 0x609, 0x00 },
+    { "ADC0_INTCTRL", 0x60A, 0x00 },
+    { "ADC0_INTFLAGS", 0x60B, 0x00 },
+    { "ADC0_DBGCTRL", 0x60C, 0x00 },
+    { "ADC0_TEMP" , 0x60D, 0x00 },
+    { "ADC0_RESL" , 0x610, 0x00 },
+    { "ADC0_RESH" , 0x611, 0x00 },
+    { "ADC0_WINLTL", 0x612, 0x00 },
+    { "ADC0_WINLTH", 0x613, 0x00 },
+    { "ADC0_WINHTL", 0x614, 0x00 },
+    { "ADC0_WINHTH", 0x615, 0x00 },
+    { "ADC0_CALIB", 0x616, 0x00 },
+    { "AC0_CTRLA" , 0x680, 0x00 },
+    { "AC0_MUXCTRLA", 0x682, 0x00 },
+    { "AC0_DACREF", 0x684, 0x00 },
+    { "AC0_INTCTRL", 0x686, 0x00 },
+    { "AC0_STATUS", 0x687, 0x00 },
+    { "USART0_RXDATAL", 0x800, 0x00 },
+    { "USART0_RXDATAH", 0x801, 0x00 },
+    { "USART0_TXDATAL", 0x802, 0x00 },
+    { "USART0_TXDATAH", 0x803, 0x00 },
+    { "USART0_STATUS", 0x804, 0x00 },
+    { "USART0_CTRLA", 0x805, 0x00 },
+    { "USART0_CTRLB", 0x806, 0x00 },
+    { "USART0_CTRLC", 0x807, 0x00 },
+    { "USART0_BAUDL", 0x808, 0x00 },
+    { "USART0_BAUDH", 0x809, 0x00 },
+    { "USART0_CTRLD", 0x80A, 0x00 },
+    { "USART0_DBGCTRL", 0x80B, 0x00 },
+    { "USART0_EVCTRL", 0x80C, 0x00 },
+    { "USART0_TXPLCTRL", 0x80D, 0x00 },
+    { "USART0_RXPLCTRL", 0x80E, 0x00 },
+    { "USART1_RXDATAL", 0x820, 0x00 },
+    { "USART1_RXDATAH", 0x821, 0x00 },
+    { "USART1_TXDATAL", 0x822, 0x00 },
+    { "USART1_TXDATAH", 0x823, 0x00 },
+    { "USART1_STATUS", 0x824, 0x00 },
+    { "USART1_CTRLA", 0x825, 0x00 },
+    { "USART1_CTRLB", 0x826, 0x00 },
+    { "USART1_CTRLC", 0x827, 0x00 },
+    { "USART1_BAUDL", 0x828, 0x00 },
+    { "USART1_BAUDH", 0x829, 0x00 },
+    { "USART1_CTRLD", 0x82A, 0x00 },
+    { "USART1_DBGCTRL", 0x82B, 0x00 },
+    { "USART1_EVCTRL", 0x82C, 0x00 },
+    { "USART1_TXPLCTRL", 0x82D, 0x00 },
+    { "USART1_RXPLCTRL", 0x82E, 0x00 },
+    { "USART2_RXDATAL", 0x840, 0x00 },
+    { "USART2_RXDATAH", 0x841, 0x00 },
+    { "USART2_TXDATAL", 0x842, 0x00 },
+    { "USART2_TXDATAH", 0x843, 0x00 },
+    { "USART2_STATUS", 0x844, 0x00 },
+    { "USART2_CTRLA", 0x845, 0x00 },
+    { "USART2_CTRLB", 0x846, 0x00 },
+    { "USART2_CTRLC", 0x847, 0x00 },
+    { "USART2_BAUDL", 0x848, 0x00 },
+    { "USART2_BAUDH", 0x849, 0x00 },
+    { "USART2_CTRLD", 0x84A, 0x00 },
+    { "USART2_DBGCTRL", 0x84B, 0x00 },
+    { "USART2_EVCTRL", 0x84C, 0x00 },
+    { "USART2_TXPLCTRL", 0x84D, 0x00 },
+    { "USART2_RXPLCTRL", 0x84E, 0x00 },
+    { "USART3_RXDATAL", 0x860, 0x00 },
+    { "USART3_RXDATAH", 0x861, 0x00 },
+    { "USART3_TXDATAL", 0x862, 0x00 },
+    { "USART3_TXDATAH", 0x863, 0x00 },
+    { "USART3_STATUS", 0x864, 0x00 },
+    { "USART3_CTRLA", 0x865, 0x00 },
+    { "USART3_CTRLB", 0x866, 0x00 },
+    { "USART3_CTRLC", 0x867, 0x00 },
+    { "USART3_BAUDL", 0x868, 0x00 },
+    { "USART3_BAUDH", 0x869, 0x00 },
+    { "USART3_CTRLD", 0x86A, 0x00 },
+    { "USART3_DBGCTRL", 0x86B, 0x00 },
+    { "USART3_EVCTRL", 0x86C, 0x00 },
+    { "USART3_TXPLCTRL", 0x86D, 0x00 },
+    { "USART3_RXPLCTRL", 0x86E, 0x00 },
+    { "TWI0_CTRLA", 0x8A0, 0x00 },
+    { "TWI0_DUALCTRL", 0x8A1, 0x00 },
+    { "TWI0_DBGCTRL", 0x8A2, 0x00 },
+    { "TWI0_MCTRLA", 0x8A3, 0x00 },
+    { "TWI0_MCTRLB", 0x8A4, 0x00 },
+    { "TWI0_MSTATUS", 0x8A5, 0x00 },
+    { "TWI0_MBAUD", 0x8A6, 0x00 },
+    { "TWI0_MADDR", 0x8A7, 0x00 },
+    { "TWI0_MDATA", 0x8A8, 0x00 },
+    { "TWI0_SCTRLA", 0x8A9, 0x00 },
+    { "TWI0_SCTRLB", 0x8AA, 0x00 },
+    { "TWI0_SSTATUS", 0x8AB, 0x00 },
+    { "TWI0_SADDR", 0x8AC, 0x00 },
+    { "TWI0_SDATA", 0x8AD, 0x00 },
+    { "TWI0_SADDRMASK", 0x8AE, 0x00 },
+    { "SPI0_CTRLA", 0x8C0, 0x00 },
+    { "SPI0_CTRLB", 0x8C1, 0x00 },
+    { "SPI0_INTCTRL", 0x8C2, 0x00 },
+    { "SPI0_INTFLAGS", 0x8C3, 0x00 },
+    { "SPI0_DATA" , 0x8C4, 0x00 },
+    { "TCA0_SPLIT_CTRLA", 0xA00, 0x00 },
+    { "TCA0_SPLIT_CTRLB", 0xA01, 0x00 },
+    { "TCA0_SPLIT_CTRLC", 0xA02, 0x00 },
+    { "TCA0_SPLIT_CTRLD", 0xA03, 0x00 },
+    { "TCA0_SPLIT_CTRLECLR", 0xA04, 0x00 },
+    { "TCA0_SPLIT_CTRLESET", 0xA05, 0x00 },
+    { "TCA0_SINGLE_CTRLFCLR", 0xA06, 0x00 },
+    { "TCA0_SINGLE_CTRLFSET", 0xA07, 0x00 },
+    { "TCA0_SINGLE_EVCTRL", 0xA09, 0x00 },
+    { "TCA0_SPLIT_INTCTRL", 0xA0A, 0x00 },
+    { "TCA0_SPLIT_INTFLAGS", 0xA0B, 0x00 },
+    { "TCA0_SPLIT_DBGCTRL", 0xA0E, 0x00 },
+    { "TCA0_SINGLE_TEMP", 0xA0F, 0x00 },
+    { "TCA0_SPLIT_LCNT", 0xA20, 0x00 },
+    { "TCA0_SPLIT_HCNT", 0xA21, 0x00 },
+    { "TCA0_SPLIT_LPER", 0xA26, 0x00 },
+    { "TCA0_SPLIT_HPER", 0xA27, 0x00 },
+    { "TCA0_SPLIT_LCMP0", 0xA28, 0x00 },
+    { "TCA0_SPLIT_HCMP0", 0xA29, 0x00 },
+    { "TCA0_SPLIT_LCMP1", 0xA2A, 0x00 },
+    { "TCA0_SPLIT_HCMP1", 0xA2B, 0x00 },
+    { "TCA0_SPLIT_LCMP2", 0xA2C, 0x00 },
+    { "TCA0_SPLIT_HCMP2", 0xA2D, 0x00 },
+    { "TCB0_CTRLA", 0xA80, 0x00 },
+    { "TCB0_CTRLB", 0xA81, 0x00 },
+    { "TCB0_EVCTRL", 0xA84, 0x00 },
+    { "TCB0_INTCTRL", 0xA85, 0x00 },
+    { "TCB0_INTFLAGS", 0xA86, 0x00 },
+    { "TCB0_STATUS", 0xA87, 0x00 },
+    { "TCB0_DBGCTRL", 0xA88, 0x00 },
+    { "TCB0_TEMP" , 0xA89, 0x00 },
+    { "TCB0_CNTL" , 0xA8A, 0x00 },
+    { "TCB0_CNTH" , 0xA8B, 0x00 },
+    { "TCB0_CCMPL", 0xA8C, 0x00 },
+    { "TCB0_CCMPH", 0xA8D, 0x00 },
+    { "TCB1_CTRLA", 0xA90, 0x00 },
+    { "TCB1_CTRLB", 0xA91, 0x00 },
+    { "TCB1_EVCTRL", 0xA94, 0x00 },
+    { "TCB1_INTCTRL", 0xA95, 0x00 },
+    { "TCB1_INTFLAGS", 0xA96, 0x00 },
+    { "TCB1_STATUS", 0xA97, 0x00 },
+    { "TCB1_DBGCTRL", 0xA98, 0x00 },
+    { "TCB1_TEMP" , 0xA99, 0x00 },
+    { "TCB1_CNTL" , 0xA9A, 0x00 },
+    { "TCB1_CNTH" , 0xA9B, 0x00 },
+    { "TCB1_CCMPL", 0xA9C, 0x00 },
+    { "TCB1_CCMPH", 0xA9D, 0x00 },
+    { "TCB2_CTRLA", 0xAA0, 0x00 },
+    { "TCB2_CTRLB", 0xAA1, 0x00 },
+    { "TCB2_EVCTRL", 0xAA4, 0x00 },
+    { "TCB2_INTCTRL", 0xAA5, 0x00 },
+    { "TCB2_INTFLAGS", 0xAA6, 0x00 },
+    { "TCB2_STATUS", 0xAA7, 0x00 },
+    { "TCB2_DBGCTRL", 0xAA8, 0x00 },
+    { "TCB2_TEMP" , 0xAA9, 0x00 },
+    { "TCB2_CNTL" , 0xAAA, 0x00 },
+    { "TCB2_CNTH" , 0xAAB, 0x00 },
+    { "TCB2_CCMPL", 0xAAC, 0x00 },
+    { "TCB2_CCMPH", 0xAAD, 0x00 },
+    { "TCB3_CTRLA", 0xAB0, 0x00 },
+    { "TCB3_CTRLB", 0xAB1, 0x00 },
+    { "TCB3_EVCTRL", 0xAB4, 0x00 },
+    { "TCB3_INTCTRL", 0xAB5, 0x00 },
+    { "TCB3_INTFLAGS", 0xAB6, 0x00 },
+    { "TCB3_STATUS", 0xAB7, 0x00 },
+    { "TCB3_DBGCTRL", 0xAB8, 0x00 },
+    { "TCB3_TEMP" , 0xAB9, 0x00 },
+    { "TCB3_CNTL" , 0xABA, 0x00 },
+    { "TCB3_CNTH" , 0xABB, 0x00 },
+    { "TCB3_CCMPL", 0xABC, 0x00 },
+    { "TCB3_CCMPH", 0xABD, 0x00 },
+    { "SYSCFG_REVID", 0xF01, 0x00 },
+    { "SYSCFG_EXTBRK", 0xF02, 0x00 },
+    { "SYSCFG_OCDM", 0xF18, 0x00 },
+    { "SYSCFG_OCDMS", 0xF19, 0x00 },
+    { "NVMCTRL_CTRLA", 0x1000, 0x00 },
+    { "NVMCTRL_CTRLB", 0x1001, 0x00 },
+    { "NVMCTRL_STATUS", 0x1002, 0x00 },
+    { "NVMCTRL_INTCTRL", 0x1003, 0x00 },
+    { "NVMCTRL_INTFLAGS", 0x1004, 0x00 },
+    { "NVMCTRL_DATAL", 0x1006, 0x00 },
+    { "NVMCTRL_DATAH", 0x1007, 0x00 },
+    { "NVMCTRL_ADDRL", 0x1008, 0x00 },
+    { "NVMCTRL_ADDRH", 0x1009, 0x00 },
+    { "SIGROW_DEVICEID0", 0x1100, 0x00 },
+    { "SIGROW_DEVICEID1", 0x1101, 0x00 },
+    { "SIGROW_DEVICEID2", 0x1102, 0x00 },
+    { "SIGROW_SERNUM0", 0x1103, 0x00 },
+    { "SIGROW_SERNUM1", 0x1104, 0x00 },
+    { "SIGROW_SERNUM2", 0x1105, 0x00 },
+    { "SIGROW_SERNUM3", 0x1106, 0x00 },
+    { "SIGROW_SERNUM4", 0x1107, 0x00 },
+    { "SIGROW_SERNUM5", 0x1108, 0x00 },
+    { "SIGROW_SERNUM6", 0x1109, 0x00 },
+    { "SIGROW_SERNUM7", 0x110A, 0x00 },
+    { "SIGROW_SERNUM8", 0x110B, 0x00 },
+    { "SIGROW_SERNUM9", 0x110C, 0x00 },
+    { "SIGROW_OSCCAL32K", 0x1114, 0x00 },
+    { "SIGROW_OSCCAL16M0", 0x1118, 0x00 },
+    { "SIGROW_OSCCAL16M1", 0x1119, 0x00 },
+    { "SIGROW_OSCCAL20M0", 0x111A, 0x00 },
+    { "SIGROW_OSCCAL20M1", 0x111B, 0x00 },
+    { "SIGROW_TEMPSENSE0", 0x1120, 0x00 },
+    { "SIGROW_TEMPSENSE1", 0x1121, 0x00 },
+    { "SIGROW_OSC16ERR3V", 0x1122, 0x00 },
+    { "SIGROW_OSC16ERR5V", 0x1123, 0x00 },
+    { "SIGROW_OSC20ERR3V", 0x1124, 0x00 },
+    { "SIGROW_OSC20ERR5V", 0x1125, 0x00 },
+    { "SIGROW_CHECKSUM1", 0x112F, 0x00 },
+    { "FUSE_WDTCFG", 0x1280, 0x00 },
+    { "FUSE_BODCFG", 0x1281, 0x00 },
+    { "FUSE_OSCCFG", 0x1282, 0x00 },
+    { "FUSE_SYSCFG0", 0x1285, 0x00 },
+    { "FUSE_SYSCFG1", 0x1286, 0x00 },
+    { "FUSE_APPEND", 0x1287, 0x00 },
+    { "FUSE_BOOTEND", 0x1288, 0x00 },
+    { "LOCKBIT_LOCKBIT", 0x128A, 0x00 },
+    { "USERROW_USERROW0", 0x1300, 0x00 },
+    { "USERROW_USERROW1", 0x1301, 0x00 },
+    { "USERROW_USERROW2", 0x1302, 0x00 },
+    { "USERROW_USERROW3", 0x1303, 0x00 },
+    { "USERROW_USERROW4", 0x1304, 0x00 },
+    { "USERROW_USERROW5", 0x1305, 0x00 },
+    { "USERROW_USERROW6", 0x1306, 0x00 },
+    { "USERROW_USERROW7", 0x1307, 0x00 },
+    { "USERROW_USERROW8", 0x1308, 0x00 },
+    { "USERROW_USERROW9", 0x1309, 0x00 },
+    { "USERROW_USERROW10", 0x130A, 0x00 },
+    { "USERROW_USERROW11", 0x130B, 0x00 },
+    { "USERROW_USERROW12", 0x130C, 0x00 },
+    { "USERROW_USERROW13", 0x130D, 0x00 },
+    { "USERROW_USERROW14", 0x130E, 0x00 },
+    { "USERROW_USERROW15", 0x130F, 0x00 },
+    { "USERROW_USERROW16", 0x1310, 0x00 },
+    { "USERROW_USERROW17", 0x1311, 0x00 },
+    { "USERROW_USERROW18", 0x1312, 0x00 },
+    { "USERROW_USERROW19", 0x1313, 0x00 },
+    { "USERROW_USERROW20", 0x1314, 0x00 },
+    { "USERROW_USERROW21", 0x1315, 0x00 },
+    { "USERROW_USERROW22", 0x1316, 0x00 },
+    { "USERROW_USERROW23", 0x1317, 0x00 },
+    { "USERROW_USERROW24", 0x1318, 0x00 },
+    { "USERROW_USERROW25", 0x1319, 0x00 },
+    { "USERROW_USERROW26", 0x131A, 0x00 },
+    { "USERROW_USERROW27", 0x131B, 0x00 },
+    { "USERROW_USERROW28", 0x131C, 0x00 },
+    { "USERROW_USERROW29", 0x131D, 0x00 },
+    { "USERROW_USERROW30", 0x131E, 0x00 },
+    { "USERROW_USERROW31", 0x131F, 0x00 },
+    { "USERROW_USERROW32", 0x1320, 0x00 },
+    { "USERROW_USERROW33", 0x1321, 0x00 },
+    { "USERROW_USERROW34", 0x1322, 0x00 },
+    { "USERROW_USERROW35", 0x1323, 0x00 },
+    { "USERROW_USERROW36", 0x1324, 0x00 },
+    { "USERROW_USERROW37", 0x1325, 0x00 },
+    { "USERROW_USERROW38", 0x1326, 0x00 },
+    { "USERROW_USERROW39", 0x1327, 0x00 },
+    { "USERROW_USERROW40", 0x1328, 0x00 },
+    { "USERROW_USERROW41", 0x1329, 0x00 },
+    { "USERROW_USERROW42", 0x132A, 0x00 },
+    { "USERROW_USERROW43", 0x132B, 0x00 },
+    { "USERROW_USERROW44", 0x132C, 0x00 },
+    { "USERROW_USERROW45", 0x132D, 0x00 },
+    { "USERROW_USERROW46", 0x132E, 0x00 },
+    { "USERROW_USERROW47", 0x132F, 0x00 },
+    { "USERROW_USERROW48", 0x1330, 0x00 },
+    { "USERROW_USERROW49", 0x1331, 0x00 },
+    { "USERROW_USERROW50", 0x1332, 0x00 },
+    { "USERROW_USERROW51", 0x1333, 0x00 },
+    { "USERROW_USERROW52", 0x1334, 0x00 },
+    { "USERROW_USERROW53", 0x1335, 0x00 },
+    { "USERROW_USERROW54", 0x1336, 0x00 },
+    { "USERROW_USERROW55", 0x1337, 0x00 },
+    { "USERROW_USERROW56", 0x1338, 0x00 },
+    { "USERROW_USERROW57", 0x1339, 0x00 },
+    { "USERROW_USERROW58", 0x133A, 0x00 },
+    { "USERROW_USERROW59", 0x133B, 0x00 },
+    { "USERROW_USERROW60", 0x133C, 0x00 },
+    { "USERROW_USERROW61", 0x133D, 0x00 },
+    { "USERROW_USERROW62", 0x133E, 0x00 },
+    { "USERROW_USERROW63", 0x133F, 0x00 },
+    { 0, 0, 0}
+};
+
+
 gdb_io_reg_def_type atmega644p_io_registers[] =
 {
     { "PINA", 0x20, 0x00 },
@@ -8523,3 +11217,579 @@ gdb_io_reg_def_type atmega256rfr2_io_registers[] =
     { "TRXFBEND", 0x1ff, 0x00 },
     { 0, 0, 0 }
 };
+
+gdb_io_reg_def_type atxmega16a4u_io_registers[] =
+{
+    { "PRODSIGNATURES_RCOSC2M", 0x0, 0x00 },
+    { "PRODSIGNATURES_RCOSC2MA", 0x1, 0x00 },
+    { "PRODSIGNATURES_RCOSC32K", 0x2, 0x00 },
+    { "PRODSIGNATURES_RCOSC32M", 0x3, 0x00 },
+    { "PRODSIGNATURES_RCOSC32MA", 0x4, 0x00 },
+    { "FUSE_FUSEBYTE5", 0x5, 0x00 },
+    { "GPIO_GPIO6", 0x6, 0x00 },
+    { "GPIO_GPIO7", 0x7, 0x00 },
+    { "PRODSIGNATURES_LOTNUM0", 0x8, 0x00 },
+    { "PRODSIGNATURES_LOTNUM1", 0x9, 0x00 },
+    { "PRODSIGNATURES_LOTNUM2", 0xA, 0x00 },
+    { "PRODSIGNATURES_LOTNUM3", 0xB, 0x00 },
+    { "PRODSIGNATURES_LOTNUM4", 0xC, 0x00 },
+    { "PRODSIGNATURES_LOTNUM5", 0xD, 0x00 },
+    { "GPIO_GPIOE", 0xE, 0x00 },
+    { "GPIO_GPIOF", 0xF, 0x00 },
+    { "VPORT0_DIR", 0x10, 0x00 },
+    { "VPORT0_OUT", 0x11, 0x00 },
+    { "VPORT0_IN" , 0x12, 0x00 },
+    { "VPORT0_INTFLAGS", 0x13, 0x00 },
+    { "VPORT1_DIR", 0x14, 0x00 },
+    { "VPORT1_OUT", 0x15, 0x00 },
+    { "VPORT1_IN" , 0x16, 0x00 },
+    { "VPORT1_INTFLAGS", 0x17, 0x00 },
+    { "VPORT2_DIR", 0x18, 0x00 },
+    { "VPORT2_OUT", 0x19, 0x00 },
+    { "VPORT2_IN" , 0x1A, 0x00 },
+    { "VPORT2_INTFLAGS", 0x1B, 0x00 },
+    { "VPORT3_DIR", 0x1C, 0x00 },
+    { "VPORT3_OUT", 0x1D, 0x00 },
+    { "VPORT3_IN" , 0x1E, 0x00 },
+    { "VPORT3_INTFLAGS", 0x1F, 0x00 },
+    { "PRODSIGNATURES_ADCACAL0", 0x20, 0x00 },
+    { "PRODSIGNATURES_ADCACAL1", 0x21, 0x00 },
+    { "PRODSIGNATURES_ADCBCAL0", 0x24, 0x00 },
+    { "PRODSIGNATURES_ADCBCAL1", 0x25, 0x00 },
+    { "OCD_OCDR0" , 0x2E, 0x00 },
+    { "OCD_OCDR1" , 0x2F, 0x00 },
+    { "PRODSIGNATURES_DACA0OFFCAL", 0x30, 0x00 },
+    { "PRODSIGNATURES_DACA0GAINCAL", 0x31, 0x00 },
+    { "PRODSIGNATURES_DACB0OFFCAL", 0x32, 0x00 },
+    { "PRODSIGNATURES_DACB0GAINCAL", 0x33, 0x00 },
+    { "CPU_CCP"   , 0x34, 0x00 },
+    { "PRODSIGNATURES_DACA1GAINCAL", 0x35, 0x00 },
+    { "PRODSIGNATURES_DACB1OFFCAL", 0x36, 0x00 },
+    { "PRODSIGNATURES_DACB1GAINCAL", 0x37, 0x00 },
+    { "CPU_RAMPD" , 0x38, 0x00 },
+    { "CPU_RAMPX" , 0x39, 0x00 },
+    { "CPU_RAMPY" , 0x3A, 0x00 },
+    { "CPU_RAMPZ" , 0x3B, 0x00 },
+    { "CPU_EIND"  , 0x3C, 0x00 },
+    { "CPU_SPL"   , 0x3D, 0x00 },
+    { "CPU_SPH"   , 0x3E, 0x00 },
+    { "CPU_SREG"  , 0x3F, 0x00 },
+    { "CLK_CTRL"  , 0x40, 0x00 },
+    { "CLK_PSCTRL", 0x41, 0x00 },
+    { "CLK_LOCK"  , 0x42, 0x00 },
+    { "CLK_RTCCTRL", 0x43, 0x00 },
+    { "CLK_USBCTRL", 0x44, 0x00 },
+    { "SLEEP_CTRL", 0x48, 0x00 },
+    { "OSC_CTRL"  , 0x50, 0x00 },
+    { "OSC_STATUS", 0x51, 0x00 },
+    { "OSC_XOSCCTRL", 0x52, 0x00 },
+    { "OSC_XOSCFAIL", 0x53, 0x00 },
+    { "OSC_RC32KCAL", 0x54, 0x00 },
+    { "OSC_PLLCTRL", 0x55, 0x00 },
+    { "OSC_DFLLCTRL", 0x56, 0x00 },
+    { "DFLLRC32M_CTRL", 0x60, 0x00 },
+    { "DFLLRC32M_CALA", 0x62, 0x00 },
+    { "DFLLRC32M_CALB", 0x63, 0x00 },
+    { "DFLLRC32M_COMP0", 0x64, 0x00 },
+    { "DFLLRC32M_COMP1", 0x65, 0x00 },
+    { "DFLLRC32M_COMP2", 0x66, 0x00 },
+    { "DFLLRC2M_CTRL", 0x68, 0x00 },
+    { "DFLLRC2M_CALA", 0x6A, 0x00 },
+    { "DFLLRC2M_CALB", 0x6B, 0x00 },
+    { "DFLLRC2M_COMP0", 0x6C, 0x00 },
+    { "DFLLRC2M_COMP1", 0x6D, 0x00 },
+    { "DFLLRC2M_COMP2", 0x6E, 0x00 },
+    { "PR_PRGEN"  , 0x70, 0x00 },
+    { "PR_PRPA"   , 0x71, 0x00 },
+    { "PR_PRPB"   , 0x72, 0x00 },
+    { "PR_PRPC"   , 0x73, 0x00 },
+    { "PR_PRPD"   , 0x74, 0x00 },
+    { "PR_PRPE"   , 0x75, 0x00 },
+    { "PR_PRPF"   , 0x76, 0x00 },
+    { "RST_STATUS", 0x78, 0x00 },
+    { "RST_CTRL"  , 0x79, 0x00 },
+    { "WDT_CTRL"  , 0x80, 0x00 },
+    { "WDT_WINCTRL", 0x81, 0x00 },
+    { "WDT_STATUS", 0x82, 0x00 },
+    { "MCU_DEVID0", 0x90, 0x00 },
+    { "MCU_DEVID1", 0x91, 0x00 },
+    { "MCU_DEVID2", 0x92, 0x00 },
+    { "MCU_REVID" , 0x93, 0x00 },
+    { "MCU_JTAGUID", 0x94, 0x00 },
+    { "MCU_MCUCR" , 0x96, 0x00 },
+    { "MCU_ANAINIT", 0x97, 0x00 },
+    { "MCU_EVSYSLOCK", 0x98, 0x00 },
+    { "MCU_AWEXLOCK", 0x99, 0x00 },
+    { "PMIC_STATUS", 0xA0, 0x00 },
+    { "PMIC_INTPRI", 0xA1, 0x00 },
+    { "PMIC_CTRL" , 0xA2, 0x00 },
+    { "PORTCFG_MPCMASK", 0xB0, 0x00 },
+    { "PORTCFG_VPCTRLA", 0xB2, 0x00 },
+    { "PORTCFG_VPCTRLB", 0xB3, 0x00 },
+    { "PORTCFG_CLKEVOUT", 0xB4, 0x00 },
+    { "PORTCFG_EBIOUT", 0xB5, 0x00 },
+    { "PORTCFG_EVOUTSEL", 0xB6, 0x00 },
+    { "AES_CTRL"  , 0xC0, 0x00 },
+    { "AES_STATUS", 0xC1, 0x00 },
+    { "AES_STATE" , 0xC2, 0x00 },
+    { "AES_KEY"   , 0xC3, 0x00 },
+    { "AES_INTCTRL", 0xC4, 0x00 },
+    { "CRC_CTRL"  , 0xD0, 0x00 },
+    { "CRC_STATUS", 0xD1, 0x00 },
+    { "CRC_DATAIN", 0xD3, 0x00 },
+    { "CRC_CHECKSUM0", 0xD4, 0x00 },
+    { "CRC_CHECKSUM1", 0xD5, 0x00 },
+    { "CRC_CHECKSUM2", 0xD6, 0x00 },
+    { "CRC_CHECKSUM3", 0xD7, 0x00 },
+    { "DMA_CTRL"  , 0x100, 0x00 },
+    { "DMA_INTFLAGS", 0x103, 0x00 },
+    { "DMA_STATUS", 0x104, 0x00 },
+    { "DMA_CH0_CTRLA", 0x110, 0x00 },
+    { "DMA_CH0_CTRLB", 0x111, 0x00 },
+    { "DMA_CH0_ADDRCTRL", 0x112, 0x00 },
+    { "DMA_CH0_TRIGSRC", 0x113, 0x00 },
+    { "DMA_CH0_REPCNT", 0x116, 0x00 },
+    { "DMA_CH0_SRCADDR0", 0x118, 0x00 },
+    { "DMA_CH0_SRCADDR1", 0x119, 0x00 },
+    { "DMA_CH0_SRCADDR2", 0x11A, 0x00 },
+    { "DMA_CH0_DESTADDR0", 0x11C, 0x00 },
+    { "DMA_CH0_DESTADDR1", 0x11D, 0x00 },
+    { "DMA_CH0_DESTADDR2", 0x11E, 0x00 },
+    { "DMA_CH1_CTRLA", 0x120, 0x00 },
+    { "DMA_CH1_CTRLB", 0x121, 0x00 },
+    { "DMA_CH1_ADDRCTRL", 0x122, 0x00 },
+    { "DMA_CH1_TRIGSRC", 0x123, 0x00 },
+    { "DMA_CH1_REPCNT", 0x126, 0x00 },
+    { "DMA_CH1_SRCADDR0", 0x128, 0x00 },
+    { "DMA_CH1_SRCADDR1", 0x129, 0x00 },
+    { "DMA_CH1_SRCADDR2", 0x12A, 0x00 },
+    { "DMA_CH1_DESTADDR0", 0x12C, 0x00 },
+    { "DMA_CH1_DESTADDR1", 0x12D, 0x00 },
+    { "DMA_CH1_DESTADDR2", 0x12E, 0x00 },
+    { "DMA_CH2_CTRLA", 0x130, 0x00 },
+    { "DMA_CH2_CTRLB", 0x131, 0x00 },
+    { "DMA_CH2_ADDRCTRL", 0x132, 0x00 },
+    { "DMA_CH2_TRIGSRC", 0x133, 0x00 },
+    { "DMA_CH2_REPCNT", 0x136, 0x00 },
+    { "DMA_CH2_SRCADDR0", 0x138, 0x00 },
+    { "DMA_CH2_SRCADDR1", 0x139, 0x00 },
+    { "DMA_CH2_SRCADDR2", 0x13A, 0x00 },
+    { "DMA_CH2_DESTADDR0", 0x13C, 0x00 },
+    { "DMA_CH2_DESTADDR1", 0x13D, 0x00 },
+    { "DMA_CH2_DESTADDR2", 0x13E, 0x00 },
+    { "DMA_CH3_CTRLA", 0x140, 0x00 },
+    { "DMA_CH3_CTRLB", 0x141, 0x00 },
+    { "DMA_CH3_ADDRCTRL", 0x142, 0x00 },
+    { "DMA_CH3_TRIGSRC", 0x143, 0x00 },
+    { "DMA_CH3_REPCNT", 0x146, 0x00 },
+    { "DMA_CH3_SRCADDR0", 0x148, 0x00 },
+    { "DMA_CH3_SRCADDR1", 0x149, 0x00 },
+    { "DMA_CH3_SRCADDR2", 0x14A, 0x00 },
+    { "DMA_CH3_DESTADDR0", 0x14C, 0x00 },
+    { "DMA_CH3_DESTADDR1", 0x14D, 0x00 },
+    { "DMA_CH3_DESTADDR2", 0x14E, 0x00 },
+    { "EVSYS_CH0MUX", 0x180, 0x00 },
+    { "EVSYS_CH1MUX", 0x181, 0x00 },
+    { "EVSYS_CH2MUX", 0x182, 0x00 },
+    { "EVSYS_CH3MUX", 0x183, 0x00 },
+    { "EVSYS_CH4MUX", 0x184, 0x00 },
+    { "EVSYS_CH5MUX", 0x185, 0x00 },
+    { "EVSYS_CH6MUX", 0x186, 0x00 },
+    { "EVSYS_CH7MUX", 0x187, 0x00 },
+    { "EVSYS_CH0CTRL", 0x188, 0x00 },
+    { "EVSYS_CH1CTRL", 0x189, 0x00 },
+    { "EVSYS_CH2CTRL", 0x18A, 0x00 },
+    { "EVSYS_CH3CTRL", 0x18B, 0x00 },
+    { "EVSYS_CH4CTRL", 0x18C, 0x00 },
+    { "EVSYS_CH5CTRL", 0x18D, 0x00 },
+    { "EVSYS_CH6CTRL", 0x18E, 0x00 },
+    { "EVSYS_CH7CTRL", 0x18F, 0x00 },
+    { "EVSYS_STROBE", 0x190, 0x00 },
+    { "EVSYS_DATA", 0x191, 0x00 },
+    { "NVM_ADDR0" , 0x1C0, 0x00 },
+    { "NVM_ADDR1" , 0x1C1, 0x00 },
+    { "NVM_ADDR2" , 0x1C2, 0x00 },
+    { "NVM_DATA0" , 0x1C4, 0x00 },
+    { "NVM_DATA1" , 0x1C5, 0x00 },
+    { "NVM_DATA2" , 0x1C6, 0x00 },
+    { "NVM_CMD"   , 0x1CA, 0x00 },
+    { "NVM_CTRLA" , 0x1CB, 0x00 },
+    { "NVM_CTRLB" , 0x1CC, 0x00 },
+    { "NVM_INTCTRL", 0x1CD, 0x00 },
+    { "NVM_STATUS", 0x1CF, 0x00 },
+    { "NVM_LOCKBITS", 0x1D0, 0x00 },
+    { "ADCA_CTRLA", 0x200, 0x00 },
+    { "ADCA_CTRLB", 0x201, 0x00 },
+    { "ADCA_REFCTRL", 0x202, 0x00 },
+    { "ADCA_EVCTRL", 0x203, 0x00 },
+    { "ADCA_PRESCALER", 0x204, 0x00 },
+    { "ADCA_INTFLAGS", 0x206, 0x00 },
+    { "ADCA_TEMP" , 0x207, 0x00 },
+    { "ADCA_CH0_CTRL", 0x220, 0x00 },
+    { "ADCA_CH0_MUXCTRL", 0x221, 0x00 },
+    { "ADCA_CH0_INTCTRL", 0x222, 0x00 },
+    { "ADCA_CH0_INTFLAGS", 0x223, 0x00 },
+    { "ADCA_CH0_SCAN", 0x226, 0x00 },
+    { "ADCA_CH1_CTRL", 0x228, 0x00 },
+    { "ADCA_CH1_MUXCTRL", 0x229, 0x00 },
+    { "ADCA_CH1_INTCTRL", 0x22A, 0x00 },
+    { "ADCA_CH1_INTFLAGS", 0x22B, 0x00 },
+    { "ADCA_CH1_SCAN", 0x22E, 0x00 },
+    { "ADCA_CH2_CTRL", 0x230, 0x00 },
+    { "ADCA_CH2_MUXCTRL", 0x231, 0x00 },
+    { "ADCA_CH2_INTCTRL", 0x232, 0x00 },
+    { "ADCA_CH2_INTFLAGS", 0x233, 0x00 },
+    { "ADCA_CH2_SCAN", 0x236, 0x00 },
+    { "ADCA_CH3_CTRL", 0x238, 0x00 },
+    { "ADCA_CH3_MUXCTRL", 0x239, 0x00 },
+    { "ADCA_CH3_INTCTRL", 0x23A, 0x00 },
+    { "ADCA_CH3_INTFLAGS", 0x23B, 0x00 },
+    { "ADCA_CH3_SCAN", 0x23E, 0x00 },
+    { "DACB_CTRLA", 0x320, 0x00 },
+    { "DACB_CTRLB", 0x321, 0x00 },
+    { "DACB_CTRLC", 0x322, 0x00 },
+    { "DACB_EVCTRL", 0x323, 0x00 },
+    { "DACB_STATUS", 0x325, 0x00 },
+    { "DACB_CH0GAINCAL", 0x328, 0x00 },
+    { "DACB_CH0OFFSETCAL", 0x329, 0x00 },
+    { "DACB_CH1GAINCAL", 0x32A, 0x00 },
+    { "DACB_CH1OFFSETCAL", 0x32B, 0x00 },
+    { "ACA_AC0CTRL", 0x380, 0x00 },
+    { "ACA_AC1CTRL", 0x381, 0x00 },
+    { "ACA_AC0MUXCTRL", 0x382, 0x00 },
+    { "ACA_AC1MUXCTRL", 0x383, 0x00 },
+    { "ACA_CTRLA" , 0x384, 0x00 },
+    { "ACA_CTRLB" , 0x385, 0x00 },
+    { "ACA_WINCTRL", 0x386, 0x00 },
+    { "ACA_STATUS", 0x387, 0x00 },
+    { "RTC_CTRL"  , 0x400, 0x00 },
+    { "RTC_STATUS", 0x401, 0x00 },
+    { "RTC_INTCTRL", 0x402, 0x00 },
+    { "RTC_INTFLAGS", 0x403, 0x00 },
+    { "RTC_TEMP"  , 0x404, 0x00 },
+    { "TWIC_CTRL" , 0x480, 0x00 },
+    { "TWIC_MASTER_CTRLA", 0x481, 0x00 },
+    { "TWIC_MASTER_CTRLB", 0x482, 0x00 },
+    { "TWIC_MASTER_CTRLC", 0x483, 0x00 },
+    { "TWIC_MASTER_STATUS", 0x484, 0x00 },
+    { "TWIC_MASTER_BAUD", 0x485, 0x00 },
+    { "TWIC_MASTER_ADDR", 0x486, 0x00 },
+    { "TWIC_MASTER_DATA", 0x487, 0x00 },
+    { "TWIC_SLAVE_CTRLA", 0x488, 0x00 },
+    { "TWIC_SLAVE_CTRLB", 0x489, 0x00 },
+    { "TWIC_SLAVE_STATUS", 0x48A, 0x00 },
+    { "TWIC_SLAVE_ADDR", 0x48B, 0x00 },
+    { "TWIC_SLAVE_DATA", 0x48C, 0x00 },
+    { "TWIC_SLAVE_ADDRMASK", 0x48D, 0x00 },
+    { "TWIE_CTRL" , 0x4A0, 0x00 },
+    { "TWIE_MASTER_CTRLA", 0x4A1, 0x00 },
+    { "TWIE_MASTER_CTRLB", 0x4A2, 0x00 },
+    { "TWIE_MASTER_CTRLC", 0x4A3, 0x00 },
+    { "TWIE_MASTER_STATUS", 0x4A4, 0x00 },
+    { "TWIE_MASTER_BAUD", 0x4A5, 0x00 },
+    { "TWIE_MASTER_ADDR", 0x4A6, 0x00 },
+    { "TWIE_MASTER_DATA", 0x4A7, 0x00 },
+    { "TWIE_SLAVE_CTRLA", 0x4A8, 0x00 },
+    { "TWIE_SLAVE_CTRLB", 0x4A9, 0x00 },
+    { "TWIE_SLAVE_STATUS", 0x4AA, 0x00 },
+    { "TWIE_SLAVE_ADDR", 0x4AB, 0x00 },
+    { "TWIE_SLAVE_DATA", 0x4AC, 0x00 },
+    { "TWIE_SLAVE_ADDRMASK", 0x4AD, 0x00 },
+    { "USB_CTRLA" , 0x4C0, 0x00 },
+    { "USB_CTRLB" , 0x4C1, 0x00 },
+    { "USB_STATUS", 0x4C2, 0x00 },
+    { "USB_ADDR"  , 0x4C3, 0x00 },
+    { "USB_FIFOWP", 0x4C4, 0x00 },
+    { "USB_FIFORP", 0x4C5, 0x00 },
+    { "USB_INTCTRLA", 0x4C8, 0x00 },
+    { "USB_INTCTRLB", 0x4C9, 0x00 },
+    { "USB_INTFLAGSACLR", 0x4CA, 0x00 },
+    { "USB_INTFLAGSASET", 0x4CB, 0x00 },
+    { "USB_INTFLAGSBCLR", 0x4CC, 0x00 },
+    { "USB_INTFLAGSBSET", 0x4CD, 0x00 },
+    { "USB_CAL0"  , 0x4FA, 0x00 },
+    { "USB_CAL1"  , 0x4FB, 0x00 },
+    { "PORTA_DIR" , 0x600, 0x00 },
+    { "PORTA_DIRSET", 0x601, 0x00 },
+    { "PORTA_DIRCLR", 0x602, 0x00 },
+    { "PORTA_DIRTGL", 0x603, 0x00 },
+    { "PORTA_OUT" , 0x604, 0x00 },
+    { "PORTA_OUTSET", 0x605, 0x00 },
+    { "PORTA_OUTCLR", 0x606, 0x00 },
+    { "PORTA_OUTTGL", 0x607, 0x00 },
+    { "PORTA_IN"  , 0x608, 0x00 },
+    { "PORTA_INTCTRL", 0x609, 0x00 },
+    { "PORTA_INT0MASK", 0x60A, 0x00 },
+    { "PORTA_INT1MASK", 0x60B, 0x00 },
+    { "PORTA_INTFLAGS", 0x60C, 0x00 },
+    { "PORTA_REMAP", 0x60E, 0x00 },
+    { "PORTA_PIN0CTRL", 0x610, 0x00 },
+    { "PORTA_PIN1CTRL", 0x611, 0x00 },
+    { "PORTA_PIN2CTRL", 0x612, 0x00 },
+    { "PORTA_PIN3CTRL", 0x613, 0x00 },
+    { "PORTA_PIN4CTRL", 0x614, 0x00 },
+    { "PORTA_PIN5CTRL", 0x615, 0x00 },
+    { "PORTA_PIN6CTRL", 0x616, 0x00 },
+    { "PORTA_PIN7CTRL", 0x617, 0x00 },
+    { "PORTB_DIR" , 0x620, 0x00 },
+    { "PORTB_DIRSET", 0x621, 0x00 },
+    { "PORTB_DIRCLR", 0x622, 0x00 },
+    { "PORTB_DIRTGL", 0x623, 0x00 },
+    { "PORTB_OUT" , 0x624, 0x00 },
+    { "PORTB_OUTSET", 0x625, 0x00 },
+    { "PORTB_OUTCLR", 0x626, 0x00 },
+    { "PORTB_OUTTGL", 0x627, 0x00 },
+    { "PORTB_IN"  , 0x628, 0x00 },
+    { "PORTB_INTCTRL", 0x629, 0x00 },
+    { "PORTB_INT0MASK", 0x62A, 0x00 },
+    { "PORTB_INT1MASK", 0x62B, 0x00 },
+    { "PORTB_INTFLAGS", 0x62C, 0x00 },
+    { "PORTB_REMAP", 0x62E, 0x00 },
+    { "PORTB_PIN0CTRL", 0x630, 0x00 },
+    { "PORTB_PIN1CTRL", 0x631, 0x00 },
+    { "PORTB_PIN2CTRL", 0x632, 0x00 },
+    { "PORTB_PIN3CTRL", 0x633, 0x00 },
+    { "PORTB_PIN4CTRL", 0x634, 0x00 },
+    { "PORTB_PIN5CTRL", 0x635, 0x00 },
+    { "PORTB_PIN6CTRL", 0x636, 0x00 },
+    { "PORTB_PIN7CTRL", 0x637, 0x00 },
+    { "PORTC_DIR" , 0x640, 0x00 },
+    { "PORTC_DIRSET", 0x641, 0x00 },
+    { "PORTC_DIRCLR", 0x642, 0x00 },
+    { "PORTC_DIRTGL", 0x643, 0x00 },
+    { "PORTC_OUT" , 0x644, 0x00 },
+    { "PORTC_OUTSET", 0x645, 0x00 },
+    { "PORTC_OUTCLR", 0x646, 0x00 },
+    { "PORTC_OUTTGL", 0x647, 0x00 },
+    { "PORTC_IN"  , 0x648, 0x00 },
+    { "PORTC_INTCTRL", 0x649, 0x00 },
+    { "PORTC_INT0MASK", 0x64A, 0x00 },
+    { "PORTC_INT1MASK", 0x64B, 0x00 },
+    { "PORTC_INTFLAGS", 0x64C, 0x00 },
+    { "PORTC_REMAP", 0x64E, 0x00 },
+    { "PORTC_PIN0CTRL", 0x650, 0x00 },
+    { "PORTC_PIN1CTRL", 0x651, 0x00 },
+    { "PORTC_PIN2CTRL", 0x652, 0x00 },
+    { "PORTC_PIN3CTRL", 0x653, 0x00 },
+    { "PORTC_PIN4CTRL", 0x654, 0x00 },
+    { "PORTC_PIN5CTRL", 0x655, 0x00 },
+    { "PORTC_PIN6CTRL", 0x656, 0x00 },
+    { "PORTC_PIN7CTRL", 0x657, 0x00 },
+    { "PORTD_DIR" , 0x660, 0x00 },
+    { "PORTD_DIRSET", 0x661, 0x00 },
+    { "PORTD_DIRCLR", 0x662, 0x00 },
+    { "PORTD_DIRTGL", 0x663, 0x00 },
+    { "PORTD_OUT" , 0x664, 0x00 },
+    { "PORTD_OUTSET", 0x665, 0x00 },
+    { "PORTD_OUTCLR", 0x666, 0x00 },
+    { "PORTD_OUTTGL", 0x667, 0x00 },
+    { "PORTD_IN"  , 0x668, 0x00 },
+    { "PORTD_INTCTRL", 0x669, 0x00 },
+    { "PORTD_INT0MASK", 0x66A, 0x00 },
+    { "PORTD_INT1MASK", 0x66B, 0x00 },
+    { "PORTD_INTFLAGS", 0x66C, 0x00 },
+    { "PORTD_REMAP", 0x66E, 0x00 },
+    { "PORTD_PIN0CTRL", 0x670, 0x00 },
+    { "PORTD_PIN1CTRL", 0x671, 0x00 },
+    { "PORTD_PIN2CTRL", 0x672, 0x00 },
+    { "PORTD_PIN3CTRL", 0x673, 0x00 },
+    { "PORTD_PIN4CTRL", 0x674, 0x00 },
+    { "PORTD_PIN5CTRL", 0x675, 0x00 },
+    { "PORTD_PIN6CTRL", 0x676, 0x00 },
+    { "PORTD_PIN7CTRL", 0x677, 0x00 },
+    { "PORTE_DIR" , 0x680, 0x00 },
+    { "PORTE_DIRSET", 0x681, 0x00 },
+    { "PORTE_DIRCLR", 0x682, 0x00 },
+    { "PORTE_DIRTGL", 0x683, 0x00 },
+    { "PORTE_OUT" , 0x684, 0x00 },
+    { "PORTE_OUTSET", 0x685, 0x00 },
+    { "PORTE_OUTCLR", 0x686, 0x00 },
+    { "PORTE_OUTTGL", 0x687, 0x00 },
+    { "PORTE_IN"  , 0x688, 0x00 },
+    { "PORTE_INTCTRL", 0x689, 0x00 },
+    { "PORTE_INT0MASK", 0x68A, 0x00 },
+    { "PORTE_INT1MASK", 0x68B, 0x00 },
+    { "PORTE_INTFLAGS", 0x68C, 0x00 },
+    { "PORTE_REMAP", 0x68E, 0x00 },
+    { "PORTE_PIN0CTRL", 0x690, 0x00 },
+    { "PORTE_PIN1CTRL", 0x691, 0x00 },
+    { "PORTE_PIN2CTRL", 0x692, 0x00 },
+    { "PORTE_PIN3CTRL", 0x693, 0x00 },
+    { "PORTE_PIN4CTRL", 0x694, 0x00 },
+    { "PORTE_PIN5CTRL", 0x695, 0x00 },
+    { "PORTE_PIN6CTRL", 0x696, 0x00 },
+    { "PORTE_PIN7CTRL", 0x697, 0x00 },
+    { "PORTR_DIR" , 0x7E0, 0x00 },
+    { "PORTR_DIRSET", 0x7E1, 0x00 },
+    { "PORTR_DIRCLR", 0x7E2, 0x00 },
+    { "PORTR_DIRTGL", 0x7E3, 0x00 },
+    { "PORTR_OUT" , 0x7E4, 0x00 },
+    { "PORTR_OUTSET", 0x7E5, 0x00 },
+    { "PORTR_OUTCLR", 0x7E6, 0x00 },
+    { "PORTR_OUTTGL", 0x7E7, 0x00 },
+    { "PORTR_IN"  , 0x7E8, 0x00 },
+    { "PORTR_INTCTRL", 0x7E9, 0x00 },
+    { "PORTR_INT0MASK", 0x7EA, 0x00 },
+    { "PORTR_INT1MASK", 0x7EB, 0x00 },
+    { "PORTR_INTFLAGS", 0x7EC, 0x00 },
+    { "PORTR_REMAP", 0x7EE, 0x00 },
+    { "PORTR_PIN0CTRL", 0x7F0, 0x00 },
+    { "PORTR_PIN1CTRL", 0x7F1, 0x00 },
+    { "PORTR_PIN2CTRL", 0x7F2, 0x00 },
+    { "PORTR_PIN3CTRL", 0x7F3, 0x00 },
+    { "PORTR_PIN4CTRL", 0x7F4, 0x00 },
+    { "PORTR_PIN5CTRL", 0x7F5, 0x00 },
+    { "PORTR_PIN6CTRL", 0x7F6, 0x00 },
+    { "PORTR_PIN7CTRL", 0x7F7, 0x00 },
+    { "TCC2_CTRLA", 0x800, 0x00 },
+    { "TCC2_CTRLB", 0x801, 0x00 },
+    { "TCC2_CTRLC", 0x802, 0x00 },
+    { "TCC0_CTRLD", 0x803, 0x00 },
+    { "TCC2_CTRLE", 0x804, 0x00 },
+    { "TCC2_INTCTRLA", 0x806, 0x00 },
+    { "TCC2_INTCTRLB", 0x807, 0x00 },
+    { "TCC0_CTRLFCLR", 0x808, 0x00 },
+    { "TCC2_CTRLF", 0x809, 0x00 },
+    { "TCC0_CTRLGCLR", 0x80A, 0x00 },
+    { "TCC0_CTRLGSET", 0x80B, 0x00 },
+    { "TCC2_INTFLAGS", 0x80C, 0x00 },
+    { "TCC0_TEMP" , 0x80F, 0x00 },
+    { "TCC2_LCNT" , 0x820, 0x00 },
+    { "TCC2_HCNT" , 0x821, 0x00 },
+    { "TCC2_LPER" , 0x826, 0x00 },
+    { "TCC2_HPER" , 0x827, 0x00 },
+    { "TCC2_LCMPA", 0x828, 0x00 },
+    { "TCC2_HCMPA", 0x829, 0x00 },
+    { "TCC2_LCMPB", 0x82A, 0x00 },
+    { "TCC2_HCMPB", 0x82B, 0x00 },
+    { "TCC2_LCMPC", 0x82C, 0x00 },
+    { "TCC2_HCMPC", 0x82D, 0x00 },
+    { "TCC2_LCMPD", 0x82E, 0x00 },
+    { "TCC2_HCMPD", 0x82F, 0x00 },
+    { "TCC1_CTRLA", 0x840, 0x00 },
+    { "TCC1_CTRLB", 0x841, 0x00 },
+    { "TCC1_CTRLC", 0x842, 0x00 },
+    { "TCC1_CTRLD", 0x843, 0x00 },
+    { "TCC1_CTRLE", 0x844, 0x00 },
+    { "TCC1_INTCTRLA", 0x846, 0x00 },
+    { "TCC1_INTCTRLB", 0x847, 0x00 },
+    { "TCC1_CTRLFCLR", 0x848, 0x00 },
+    { "TCC1_CTRLFSET", 0x849, 0x00 },
+    { "TCC1_CTRLGCLR", 0x84A, 0x00 },
+    { "TCC1_CTRLGSET", 0x84B, 0x00 },
+    { "TCC1_INTFLAGS", 0x84C, 0x00 },
+    { "TCC1_TEMP" , 0x84F, 0x00 },
+    { "AWEXC_CTRL", 0x880, 0x00 },
+    { "AWEXC_FDEMASK", 0x882, 0x00 },
+    { "AWEXC_FDCTRL", 0x883, 0x00 },
+    { "AWEXC_STATUS", 0x884, 0x00 },
+    { "AWEXC_STATUSSET", 0x885, 0x00 },
+    { "AWEXC_DTBOTH", 0x886, 0x00 },
+    { "AWEXC_DTBOTHBUF", 0x887, 0x00 },
+    { "AWEXC_DTLS", 0x888, 0x00 },
+    { "AWEXC_DTHS", 0x889, 0x00 },
+    { "AWEXC_DTLSBUF", 0x88A, 0x00 },
+    { "AWEXC_DTHSBUF", 0x88B, 0x00 },
+    { "AWEXC_OUTOVEN", 0x88C, 0x00 },
+    { "HIRESC_CTRLA", 0x890, 0x00 },
+    { "USARTC0_DATA", 0x8A0, 0x00 },
+    { "USARTC0_STATUS", 0x8A1, 0x00 },
+    { "USARTC0_CTRLA", 0x8A3, 0x00 },
+    { "USARTC0_CTRLB", 0x8A4, 0x00 },
+    { "USARTC0_CTRLC", 0x8A5, 0x00 },
+    { "USARTC0_BAUDCTRLA", 0x8A6, 0x00 },
+    { "USARTC0_BAUDCTRLB", 0x8A7, 0x00 },
+    { "USARTC1_DATA", 0x8B0, 0x00 },
+    { "USARTC1_STATUS", 0x8B1, 0x00 },
+    { "USARTC1_CTRLA", 0x8B3, 0x00 },
+    { "USARTC1_CTRLB", 0x8B4, 0x00 },
+    { "USARTC1_CTRLC", 0x8B5, 0x00 },
+    { "USARTC1_BAUDCTRLA", 0x8B6, 0x00 },
+    { "USARTC1_BAUDCTRLB", 0x8B7, 0x00 },
+    { "SPIC_CTRL" , 0x8C0, 0x00 },
+    { "SPIC_INTCTRL", 0x8C1, 0x00 },
+    { "SPIC_STATUS", 0x8C2, 0x00 },
+    { "SPIC_DATA" , 0x8C3, 0x00 },
+    { "IRCOM_CTRL", 0x8F8, 0x00 },
+    { "IRCOM_TXPLCTRL", 0x8F9, 0x00 },
+    { "IRCOM_RXPLCTRL", 0x8FA, 0x00 },
+    { "TCD2_CTRLA", 0x900, 0x00 },
+    { "TCD2_CTRLB", 0x901, 0x00 },
+    { "TCD2_CTRLC", 0x902, 0x00 },
+    { "TCD0_CTRLD", 0x903, 0x00 },
+    { "TCD2_CTRLE", 0x904, 0x00 },
+    { "TCD2_INTCTRLA", 0x906, 0x00 },
+    { "TCD2_INTCTRLB", 0x907, 0x00 },
+    { "TCD0_CTRLFCLR", 0x908, 0x00 },
+    { "TCD2_CTRLF", 0x909, 0x00 },
+    { "TCD0_CTRLGCLR", 0x90A, 0x00 },
+    { "TCD0_CTRLGSET", 0x90B, 0x00 },
+    { "TCD2_INTFLAGS", 0x90C, 0x00 },
+    { "TCD0_TEMP" , 0x90F, 0x00 },
+    { "TCD2_LCNT" , 0x920, 0x00 },
+    { "TCD2_HCNT" , 0x921, 0x00 },
+    { "TCD2_LPER" , 0x926, 0x00 },
+    { "TCD2_HPER" , 0x927, 0x00 },
+    { "TCD2_LCMPA", 0x928, 0x00 },
+    { "TCD2_HCMPA", 0x929, 0x00 },
+    { "TCD2_LCMPB", 0x92A, 0x00 },
+    { "TCD2_HCMPB", 0x92B, 0x00 },
+    { "TCD2_LCMPC", 0x92C, 0x00 },
+    { "TCD2_HCMPC", 0x92D, 0x00 },
+    { "TCD2_LCMPD", 0x92E, 0x00 },
+    { "TCD2_HCMPD", 0x92F, 0x00 },
+    { "TCD1_CTRLA", 0x940, 0x00 },
+    { "TCD1_CTRLB", 0x941, 0x00 },
+    { "TCD1_CTRLC", 0x942, 0x00 },
+    { "TCD1_CTRLD", 0x943, 0x00 },
+    { "TCD1_CTRLE", 0x944, 0x00 },
+    { "TCD1_INTCTRLA", 0x946, 0x00 },
+    { "TCD1_INTCTRLB", 0x947, 0x00 },
+    { "TCD1_CTRLFCLR", 0x948, 0x00 },
+    { "TCD1_CTRLFSET", 0x949, 0x00 },
+    { "TCD1_CTRLGCLR", 0x94A, 0x00 },
+    { "TCD1_CTRLGSET", 0x94B, 0x00 },
+    { "TCD1_INTFLAGS", 0x94C, 0x00 },
+    { "TCD1_TEMP" , 0x94F, 0x00 },
+    { "HIRESD_CTRLA", 0x990, 0x00 },
+    { "USARTD0_DATA", 0x9A0, 0x00 },
+    { "USARTD0_STATUS", 0x9A1, 0x00 },
+    { "USARTD0_CTRLA", 0x9A3, 0x00 },
+    { "USARTD0_CTRLB", 0x9A4, 0x00 },
+    { "USARTD0_CTRLC", 0x9A5, 0x00 },
+    { "USARTD0_BAUDCTRLA", 0x9A6, 0x00 },
+    { "USARTD0_BAUDCTRLB", 0x9A7, 0x00 },
+    { "USARTD1_DATA", 0x9B0, 0x00 },
+    { "USARTD1_STATUS", 0x9B1, 0x00 },
+    { "USARTD1_CTRLA", 0x9B3, 0x00 },
+    { "USARTD1_CTRLB", 0x9B4, 0x00 },
+    { "USARTD1_CTRLC", 0x9B5, 0x00 },
+    { "USARTD1_BAUDCTRLA", 0x9B6, 0x00 },
+    { "USARTD1_BAUDCTRLB", 0x9B7, 0x00 },
+    { "SPID_CTRL" , 0x9C0, 0x00 },
+    { "SPID_INTCTRL", 0x9C1, 0x00 },
+    { "SPID_STATUS", 0x9C2, 0x00 },
+    { "SPID_DATA" , 0x9C3, 0x00 },
+    { "TCE0_CTRLA", 0xA00, 0x00 },
+    { "TCE0_CTRLB", 0xA01, 0x00 },
+    { "TCE0_CTRLC", 0xA02, 0x00 },
+    { "TCE0_CTRLD", 0xA03, 0x00 },
+    { "TCE0_CTRLE", 0xA04, 0x00 },
+    { "TCE0_INTCTRLA", 0xA06, 0x00 },
+    { "TCE0_INTCTRLB", 0xA07, 0x00 },
+    { "TCE0_CTRLFCLR", 0xA08, 0x00 },
+    { "TCE0_CTRLFSET", 0xA09, 0x00 },
+    { "TCE0_CTRLGCLR", 0xA0A, 0x00 },
+    { "TCE0_CTRLGSET", 0xA0B, 0x00 },
+    { "TCE0_INTFLAGS", 0xA0C, 0x00 },
+    { "TCE0_TEMP" , 0xA0F, 0x00 },
+    { "HIRESE_CTRLA", 0xA90, 0x00 },
+    { "USARTE0_DATA", 0xAA0, 0x00 },
+    { "USARTE0_STATUS", 0xAA1, 0x00 },
+    { "USARTE0_CTRLA", 0xAA3, 0x00 },
+    { "USARTE0_CTRLB", 0xAA4, 0x00 },
+    { "USARTE0_CTRLC", 0xAA5, 0x00 },
+    { "USARTE0_BAUDCTRLA", 0xAA6, 0x00 },
+    { "USARTE0_BAUDCTRLB", 0xAA7, 0x00 },
+    { 0, 0, 0}
+};
diff --git a/src/ioreg.h b/src/ioreg.h
index 8f5066d..2f949bb 100644
--- a/src/ioreg.h
+++ b/src/ioreg.h
@@ -42,6 +42,7 @@ extern gdb_io_reg_def_type atmega64_io_registers[];
 extern gdb_io_reg_def_type at90can128_io_registers[];
 extern gdb_io_reg_def_type atmega164p_io_registers[];
 extern gdb_io_reg_def_type atmega324p_io_registers[];
+extern gdb_io_reg_def_type atmega324pb_io_registers[];
 extern gdb_io_reg_def_type atmega644_io_registers[];
 extern gdb_io_reg_def_type atmega325_io_registers[];
 extern gdb_io_reg_def_type atmega3250_io_registers[];
@@ -72,7 +73,10 @@ extern gdb_io_reg_def_type attiny25_io_registers[];
 extern gdb_io_reg_def_type attiny45_io_registers[];
 extern gdb_io_reg_def_type attiny85_io_registers[];
 extern gdb_io_reg_def_type attiny261_io_registers[];
+extern gdb_io_reg_def_type attiny402_io_registers[];
+extern gdb_io_reg_def_type attiny412_io_registers[];
 extern gdb_io_reg_def_type attiny461_io_registers[];
+extern gdb_io_reg_def_type attiny814_io_registers[];
 extern gdb_io_reg_def_type attiny861_io_registers[];
 extern gdb_io_reg_def_type atmega32c1_io_registers[];
 extern gdb_io_reg_def_type atmega32m1_io_registers[];
@@ -98,6 +102,9 @@ extern gdb_io_reg_def_type atmega32hvb_io_registers[];
 extern gdb_io_reg_def_type atmega32u4_io_registers[];
 extern gdb_io_reg_def_type atmega406_io_registers[];
 extern gdb_io_reg_def_type atmega48p_io_registers[];
+extern gdb_io_reg_def_type atmega3208_io_registers[];
+extern gdb_io_reg_def_type atmega4808_io_registers[];
+extern gdb_io_reg_def_type atmega4809_io_registers[];
 extern gdb_io_reg_def_type atmega644p_io_registers[];
 extern gdb_io_reg_def_type atmega88p_io_registers[];
 extern gdb_io_reg_def_type attiny167_io_registers[];
@@ -106,5 +113,6 @@ extern gdb_io_reg_def_type attiny48_io_registers[];
 extern gdb_io_reg_def_type attiny88_io_registers[];
 extern gdb_io_reg_def_type atmega128rfa1_io_registers[];
 extern gdb_io_reg_def_type atmega256rfr2_io_registers[];
+extern gdb_io_reg_def_type atxmega16a4u_io_registers[];
 
 #endif /* INCLUDE_IOREG_H */
diff --git a/src/jtag.h b/src/jtag.h
index 3f4f358..c27be33 100644
--- a/src/jtag.h
+++ b/src/jtag.h
@@ -190,6 +190,15 @@ typedef struct {
     unsigned char osccal_address;
 } jtag3_device_desc_type;
 
+/* UPDI device descriptor */
+struct updi_device_desc {
+    unsigned char prog_base[2];
+    unsigned char flash_page_size;
+    unsigned char eeprom_page_size;
+    unsigned char nvm_base_addr[2];
+    unsigned char ocd_base_addr[2];
+};
+
 #define fill_b4(u) \
 { ((u) & 0xffUL), (((u) & 0xff00UL) >> 8), \
   (((u) & 0xff0000UL) >> 16), (((u) & 0xff000000UL) >> 24) }
@@ -233,6 +242,8 @@ typedef struct {
     xmega_device_desc_type dev_desc3;  // Device descriptor to download for
                                        // Xmega devices in new (7+) firmware
                                        // JTAGICE mkII and AVR Dragon
+	updi_device_desc dev_desc4;		   // Device descriptor to download to
+									   // UPDI device
 } jtag_device_def_type;
 
 extern jtag_device_def_type deviceDefinitions[];
@@ -752,7 +763,7 @@ typedef struct {
 #define JTAG_EOM 0x20, 0x20
 
 enum debugproto {
-    PROTO_JTAG, PROTO_DW, PROTO_PDI,
+    PROTO_JTAG, PROTO_DW, PROTO_PDI, PROTO_UPDI
 };
 
 class jtag
diff --git a/src/jtag2io.cc b/src/jtag2io.cc
index 86ae19e..507c759 100644
--- a/src/jtag2io.cc
+++ b/src/jtag2io.cc
@@ -605,6 +605,8 @@ void jtag2::startJtagLink(void)
 		    val = EMULATOR_MODE_PDI;
 		    protoName = "PDI";
 		    break;
+		default:
+			break;
 	    }
 	    try
 	    {
diff --git a/src/jtag3.h b/src/jtag3.h
index 51914f0..267cd4c 100644
--- a/src/jtag3.h
+++ b/src/jtag3.h
@@ -139,6 +139,7 @@ enum jtag3consts
     PARM3_ARCH_TINY = 1,     /* also small megaAVR with ISP/DW only */
     PARM3_ARCH_MEGA = 2,
     PARM3_ARCH_XMEGA = 3,
+    PARM3_ARCH_UPDI = 5,
 
     PARM3_SESS_PURPOSE = 0x01, /* section 0, AVR scope, 1 byte */
     PARM3_SESS_PROGRAMMING = 1,
@@ -149,6 +150,7 @@ enum jtag3consts
     PARM3_CONN_JTAG = 4,
     PARM3_CONN_DW = 5,
     PARM3_CONN_PDI = 6,
+	  PARM3_CONN_UPDI = 8,
 
     PARM3_JTAGCHAIN = 0x01,     /* JTAG chain info, AVR scope (units
                                  * before/after, bits before/after),
diff --git a/src/jtag3io.cc b/src/jtag3io.cc
index f7544dc..024deb1 100644
--- a/src/jtag3io.cc
+++ b/src/jtag3io.cc
@@ -363,7 +363,12 @@ void jtag3::setDeviceDescriptor(jtag_device_def_type *dev)
   uchar *param, paramsize;
   jtag3_device_desc_type d3;
 
-  if (is_xmega)
+  if (proto == PROTO_UPDI)
+  {
+    param = (uchar *)&dev->dev_desc4;
+	paramsize = sizeof dev->dev_desc4;
+  }
+  else if (is_xmega)
   {
     param = (uchar *)&dev->dev_desc3 + 4;
     paramsize = sizeof dev->dev_desc3 - 4;
@@ -456,6 +461,8 @@ void jtag3::startJtagLink(void)
     paramdata[0] = PARM3_ARCH_XMEGA;
   else if (proto == PROTO_DW)
     paramdata[0] = PARM3_ARCH_TINY;
+  else if (proto == PROTO_UPDI)
+	paramdata[0] = PARM3_ARCH_UPDI;
   else
     paramdata[0] = PARM3_ARCH_MEGA;
   setJtagParameter(SCOPE_AVR, 0, PARM3_ARCH, paramdata, 1);
@@ -477,12 +484,37 @@ void jtag3::startJtagLink(void)
     case PROTO_PDI:
       paramdata[0] = PARM3_CONN_PDI;
       break;
+
+    case PROTO_UPDI:
+      paramdata[0] = PARM3_CONN_UPDI;
+      break;
   }
   setJtagParameter(SCOPE_AVR, 1, PARM3_CONNECTION, paramdata, 1);
 
   if (proto == PROTO_JTAG)
     configDaisyChain();
 
+  if (proto == PROTO_UPDI)
+  {
+	/*
+	* Unfortunately, for Xmega devices on UPDI, it's necessary
+	* to send the device descriptor before sign-on.  However,
+	* in order to do this, the JTAGICE3 needs a valid device
+	* descriptor already.
+	*
+	* Hopefully, the values below will remain constant for all
+	* Xmega devices ...
+	*/
+	jtag_device_def_type desc = { "dummy", 0 };
+
+	u16_to_b2(desc.dev_desc4.prog_base, 0x4000);
+	desc.dev_desc4.flash_page_size = 128;
+	desc.dev_desc4.eeprom_page_size = 64;
+	u16_to_b2(desc.dev_desc4.nvm_base_addr, 0x1000);
+	u16_to_b2(desc.dev_desc4.ocd_base_addr, 0x0F80);
+	setDeviceDescriptor(&desc);
+  }
+
   cmd[0] = SCOPE_AVR;
   cmd[1] = CMD3_SIGN_ON;
   cmd[2] = 0;
@@ -505,6 +537,15 @@ void jtag3::startJtagLink(void)
 
       device_id = (did & 0x0FFFF000) >> 12;
     }
+	else if (proto == PROTO_UPDI)
+	{
+      debugOut("AVR sign-on responded with %c%c%c%c\n",
+	    (did & 0x000000FF) >> 0,
+	    (did & 0x0000FF00) >> 8,
+	    (did & 0x00FF0000) >> 16,
+	    (did & 0xFF000000) >> 24);
+	  device_id = 0;
+	}
     else // debugWIRE
     {
       debugOut("AVR sign-on responded with device ID = 0x%0X\n", did);
diff --git a/src/jtag3rw.cc b/src/jtag3rw.cc
index ada7430..a3741ee 100644
--- a/src/jtag3rw.cc
+++ b/src/jtag3rw.cc
@@ -76,7 +76,7 @@ uchar jtag3::memorySpace(unsigned long &addr)
     case DATA_SPACE_ADDR_OFFSET:
 	return MTYPE_SRAM;
     default:
-	if (is_xmega)
+	if (is_xmega || proto == PROTO_UPDI)
 	    return MTYPE_XMEGA_APP_FLASH;
 	else if (proto == PROTO_DW || programmingEnabled)
 	    return MTYPE_FLASH_PAGE;
@@ -103,6 +103,7 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes)
         whichSpace < MTYPE_XMEGA_REG;
     unsigned int pageSize = 0;
     unsigned int offset = 0;
+	unsigned int alignSize = 0;
     bool wasProgmode = programmingEnabled;
     if (needProgmode && !programmingEnabled)
        enableProgramming();
@@ -112,6 +113,12 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes)
 
     switch (whichSpace)
     {
+	case MTYPE_SIGN_JTAG:
+	// The signature needs to be read from its exact address,
+	// not just the signature space with address 0.
+		if (proto == PROTO_UPDI)
+			addr = 0x1100;
+	break;
 	// Pad to even byte count for flash memory.
 	// Even MTYPE_SPM appears to cause a RSP_FAILED
 	// otherwise.
@@ -132,6 +139,12 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes)
 	cachePtr = eepromCache;
 	cacheBaseAddr = &eepromCachePageAddr;
 	break;
+
+	case MTYPE_XMEGA_APP_FLASH:
+		// Flash for UPDI devices can only be accessed in word (16bit) chunks
+		if (proto == PROTO_UPDI)
+			alignSize = 2;
+	break;
     }
 
     uchar cmd[12];
@@ -197,8 +210,37 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes)
 	    pageAddr += pageSize;
 	}
     } else {
-	u32_to_b4(cmd + 8, numBytes);
-	u32_to_b4(cmd + 4, addr);
+		unsigned int addrAdj = addr;
+		unsigned int numBytesAdj = numBytes;
+		// Access to some memories may only be allowed in chunks aligned
+		// to a certain size. If that is the case, properly align what is
+		// read from the device (thus reading more than asked), then only
+		// return to GDB the requested data.
+		if (alignSize != 0)
+		{
+			// Get address adjustment by rounding down to alignment size
+			// e.g. For alignmentSize of 10
+			// 39 becomes 30 => adjustment of 9
+			addrAdj = (addr / alignSize) * alignSize;
+			// Get length adjustment by rounding up to number of bytes
+			// e.g. For alignmentSize of 10
+			// 39 becomes 40 => adjustment of 1
+			numBytesAdj = ((numBytes + alignSize - 1) / alignSize) * alignSize;
+
+			if (addr + numBytes > addrAdj + numBytesAdj)
+			{
+				// If both address and length are not aligned in request, our
+				// alignment may make us read less than requested range.
+				// Add alignmentSize to correct for this.
+				// e.g. For alignmentSize of 10
+				// 39 bytes from address 39 => bytes #39-77 requested
+				// but 40 bytes from address 30 => bytes #30-69 read.
+				// Adding 10 => bytes #30-79 read which covers expected range
+				numBytesAdj += alignSize;
+			}
+		}
+	u32_to_b4(cmd + 8, numBytesAdj);
+	u32_to_b4(cmd + 4, addrAdj);
 
         int cnt = 0;
       again:
@@ -225,6 +267,8 @@ uchar *jtag3::jtagRead(unsigned long addr, unsigned int numBytes)
                     e.what());
             throw;
         }
+	responsesize -= (addr - addrAdj) + (numBytesAdj - numBytes);
+	offset = (addr - addrAdj);
 	if (offset > 0)
 	    memmove(response, response + 3 + offset, responsesize - 1 - offset);
 	else
diff --git a/src/jtaggeneric.cc b/src/jtaggeneric.cc
index 5da08e2..dd3764d 100644
--- a/src/jtaggeneric.cc
+++ b/src/jtaggeneric.cc
@@ -468,7 +468,7 @@ static unsigned int countFuses(unsigned int fusemap)
 {
     unsigned int nfuses = 0;
 
-    for (unsigned int i = 7, mask = 0x80;
+    for (unsigned int i = 15, mask = 0x8000;
          mask != 0;
          i--, mask >>= 1)
     {
@@ -560,8 +560,8 @@ void jtag::jtagDisplayFuses(uchar *fuseBits)
     }
     else
     {
-        // Xmega: fuse0 ... fuse7 (or just some of them)
-        for (unsigned int i = 7, mask = 0x80;
+        // Xmega: fuse0 ... fuse15 (or just some of them)
+        for (unsigned int i = 15, mask = 0x8000;
              mask != 0;
              i--, mask >>= 1)
         {
diff --git a/src/main.cc b/src/main.cc
index 652c19c..71110ff 100644
--- a/src/main.cc
+++ b/src/main.cc
@@ -226,6 +226,8 @@ static void usage(const char *progname)
             "  -r, --read-fuses            Read fuses bytes.\n");
     fprintf(stderr,
             "  -R, --reset-srst            External reset through nSRST signal.\n");
+    fprintf(stderr,
+            "  -u, --updi                  AVR part is an ATxmega device, using UPDI.\n");
     fprintf(stderr,
 	    "  -V, --version               Print version information.\n");
 #if ENABLE_TARGET_PROGRAMMING
@@ -332,6 +334,7 @@ static struct option long_opts[] = {
     { "program",             0,       0,     'p' },
     { "reset-srst",          0,       0,     'R' },
     { "read-fuses",          0,       0,     'r' },
+    { "updi",                0,       0,     'u' },
     { "version",             0,       0,     'V' },
     { "verify",              0,       0,     'v' },
     { "debugwire",           0,       0,     'w' },
@@ -389,7 +392,7 @@ int main(int argc, char **argv)
 
     while (1)
     {
-        int c = getopt_long (argc, argv, "1234B:Cc:DdeE:f:ghIj:kL:lP:pRrVvwW:xX",
+        int c = getopt_long (argc, argv, "1234B:Cc:DdeE:f:ghIj:kL:lP:pRruVvwW:xX",
                              long_opts, &option_index);
         if (c == -1)
             break;              /* no more options */
@@ -475,6 +478,9 @@ int main(int argc, char **argv)
             case 'r':
                 readFuses = true;
                 break;
+            case 'u':
+		proto = PROTO_UPDI;
+		break;
             case 'V':
                 exit(0);
             case 'v':
diff --git a/src/remote.cc b/src/remote.cc
index caa6b87..704f00c 100644
--- a/src/remote.cc
+++ b/src/remote.cc
@@ -1024,7 +1024,7 @@ void talkToGdb(void)
         }
 	else if (strncmp(ptr, "Supported:", 10) == 0)
 	{
-	    strcpy(remcomOutBuffer, "qXfer:memory-map:read+");
+	    strcpy(remcomOutBuffer, "PacketSize=40;qXfer:memory-map:read+");
 	}
 	else if (strncmp(ptr, "Xfer:memory-map:read::", 22) == 0)
 	{