diff --git a/src/devdescr.cc b/src/devdescr.cc index 41b49cd..63f5195 100644 --- a/src/devdescr.cc +++ b/src/devdescr.cc @@ -5320,6 +5320,89 @@ jtag_device_def_type deviceDefinitions[] = { fill_b2(0x90), // IO space address of MCU control }, }, + // DEV_ATXMEGA16A4U + { + "atxmega16a4u", + 0x9441, + 256, 80, // 20480 bytes flash + 32, 32, // 1024 bytes EEPROM + 94 * 4, // 94 interrupt vectors? + DEVFL_MKII_ONLY, + atxmega16a4u_io_registers, // registers + true, + 0x37, 0x0000, // fuses + 0, // osccal + 0, // OCD revision + { + 0 // no mkI support + }, + { + CMND_SET_DEVICE_DESCRIPTOR, + { 0xFF,0xFF,0xFF,0xF9,0xFF,0x3D,0xB9,0xF8 }, // ucReadIO + { 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 }, // ucReadIOShadow + { 0xFF,0xFF,0x1F,0xE0,0xFF,0x1D,0xA9,0xF8 }, // ucWriteIO + { 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00 }, // ucWriteIOShadow + { 0x73,0xFF,0x3F,0xFF,0xF7,0x3F,0xF7,0x3F, + 0xF7,0x3F,0x5F,0x3F,0x37,0x37,0x36,0x00, + 0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00, + 0xF7,0x3F,0x36,0x00 }, // ucReadExtIO + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }, // ucReadIOExtShadow + { 0x73,0xFF,0x3F,0xF8,0xF7,0x3F,0xF7,0x3F, + 0xF7,0x3F,0x5F,0x2F,0x36,0x36,0x36,0x00, + 0x00,0x00,0x00,0x00,0xFF,0x0F,0x00,0x00, + 0xF7,0x3F,0x36,0x00 }, // ucWriteExtIO + { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00 }, // ucWriteIOExtShadow + 0x31, // ucIDRAddress + 0x57, // ucSPMCRAddress + 0, // ucRAMPZAddress + fill_b2(256), // uiFlashPageSize + 32, // ucEepromPageSize + fill_b4(0x4000), // ulBootAddress -- byte address + fill_b2(0x136), // uiUpperExtIOLoc + fill_b4(256 * 80), // ulFlashSize (page size * pages) + { 0x00 }, // ucEepromInst + { 0x00 }, // ucFlashInst + 0x3E, // ucSPHaddr + 0x3D, // ucSPLaddr + fill_b2(80), // uiFlashpages (64 application + 16 boot) + 0x00, // ucDWDRAddress + 0x00, // ucDWBasePC + 0x00, // ucAllowFullPageBitstream + fill_b2(0x00), // uiStartSmallestBootLoaderSection + 1, // EnablePageProgramming + 0x02, // ucCacheType + fill_b2(8192), // uiSramStartAddr + 0, // ucResetType + 0, // ucPCMaskExtended + 0, // ucPCMaskHigh + 0, // ucEindAddress + fill_b2(0), // EECRAddress + }, + { + CMND_SET_XMEGA_PARAMS, // cmd + fill_b2(2), // whatever + 47, // length of following data + fill_b4(0x800000), // NVM offset for application flash + fill_b4(0x804000), // NVM offset for boot flash + fill_b4(0x8c0000), // NVM offset for EEPROM + fill_b4(0x8f0020), // NVM offset for fuses + fill_b4(0x8f0027), // NVM offset for lock bits + fill_b4(0x8e0400), // NVM offset for user signature row + fill_b4(0x8e0200), // NVM offset for production sig. row + fill_b4(0x1000000), // NVM offset for data memory + fill_b4(20480), // size of application flash + fill_b2(4096), // size of boot flash + fill_b2(256), // flash page size + fill_b2(1024), // size of EEPROM + 32, // EEPROM page size + fill_b2(0x1c0), // IO space base address of NVM controller + fill_b2(0x90), // IO space address of MCU control + }, + }, // DEV_ATXMEGA128A3 { "atxmega128a3", diff --git a/src/ioreg.cc b/src/ioreg.cc index c21bb93..cf9cb58 100644 --- a/src/ioreg.cc +++ b/src/ioreg.cc @@ -7976,6 +7976,584 @@ gdb_io_reg_def_type attiny88_io_registers[] = }; +gdb_io_reg_def_type atxmega16a4u_io_registers[] = +{ + { "PRODSIGNATURES_RCOSC2M", 0x0, 0x00 }, + { "PRODSIGNATURES_RCOSC2MA", 0x1, 0x00 }, + { "PRODSIGNATURES_RCOSC32K", 0x2, 0x00 }, + { "PRODSIGNATURES_RCOSC32M", 0x3, 0x00 }, + { "PRODSIGNATURES_RCOSC32MA", 0x4, 0x00 }, + { "FUSE_FUSEBYTE5", 0x5, 0x00 }, + { "GPIO_GPIO6", 0x6, 0x00 }, + { "GPIO_GPIO7", 0x7, 0x00 }, + { "PRODSIGNATURES_LOTNUM0", 0x8, 0x00 }, + { "PRODSIGNATURES_LOTNUM1", 0x9, 0x00 }, + { "PRODSIGNATURES_LOTNUM2", 0xA, 0x00 }, + { "PRODSIGNATURES_LOTNUM3", 0xB, 0x00 }, + { "PRODSIGNATURES_LOTNUM4", 0xC, 0x00 }, + { "PRODSIGNATURES_LOTNUM5", 0xD, 0x00 }, + { "GPIO_GPIOE", 0xE, 0x00 }, + { "GPIO_GPIOF", 0xF, 0x00 }, + { "VPORT0_DIR", 0x10, 0x00 }, + { "VPORT0_OUT", 0x11, 0x00 }, + { "VPORT0_IN" , 0x12, 0x00 }, + { "VPORT0_INTFLAGS", 0x13, 0x00 }, + { "VPORT1_DIR", 0x14, 0x00 }, + { "VPORT1_OUT", 0x15, 0x00 }, + { "VPORT1_IN" , 0x16, 0x00 }, + { "VPORT1_INTFLAGS", 0x17, 0x00 }, + { "VPORT2_DIR", 0x18, 0x00 }, + { "VPORT2_OUT", 0x19, 0x00 }, + { "VPORT2_IN" , 0x1A, 0x00 }, + { "VPORT2_INTFLAGS", 0x1B, 0x00 }, + { "VPORT3_DIR", 0x1C, 0x00 }, + { "VPORT3_OUT", 0x1D, 0x00 }, + { "VPORT3_IN" , 0x1E, 0x00 }, + { "VPORT3_INTFLAGS", 0x1F, 0x00 }, + { "PRODSIGNATURES_ADCACAL0", 0x20, 0x00 }, + { "PRODSIGNATURES_ADCACAL1", 0x21, 0x00 }, + { "PRODSIGNATURES_ADCBCAL0", 0x24, 0x00 }, + { "PRODSIGNATURES_ADCBCAL1", 0x25, 0x00 }, + { "OCD_OCDR0" , 0x2E, 0x00 }, + { "OCD_OCDR1" , 0x2F, 0x00 }, + { "PRODSIGNATURES_DACA0OFFCAL", 0x30, 0x00 }, + { "PRODSIGNATURES_DACA0GAINCAL", 0x31, 0x00 }, + { "PRODSIGNATURES_DACB0OFFCAL", 0x32, 0x00 }, + { "PRODSIGNATURES_DACB0GAINCAL", 0x33, 0x00 }, + { "CPU_CCP" , 0x34, 0x00 }, + { "PRODSIGNATURES_DACA1GAINCAL", 0x35, 0x00 }, + { "PRODSIGNATURES_DACB1OFFCAL", 0x36, 0x00 }, + { "PRODSIGNATURES_DACB1GAINCAL", 0x37, 0x00 }, + { "CPU_RAMPD" , 0x38, 0x00 }, + { "CPU_RAMPX" , 0x39, 0x00 }, + { "CPU_RAMPY" , 0x3A, 0x00 }, + { "CPU_RAMPZ" , 0x3B, 0x00 }, + { "CPU_EIND" , 0x3C, 0x00 }, + { "CPU_SPL" , 0x3D, 0x00 }, + { "CPU_SPH" , 0x3E, 0x00 }, + { "CPU_SREG" , 0x3F, 0x00 }, + { "CLK_CTRL" , 0x40, 0x00 }, + { "CLK_PSCTRL", 0x41, 0x00 }, + { "CLK_LOCK" , 0x42, 0x00 }, + { "CLK_RTCCTRL", 0x43, 0x00 }, + { "CLK_USBCTRL", 0x44, 0x00 }, + { "SLEEP_CTRL", 0x48, 0x00 }, + { "OSC_CTRL" , 0x50, 0x00 }, + { "OSC_STATUS", 0x51, 0x00 }, + { "OSC_XOSCCTRL", 0x52, 0x00 }, + { "OSC_XOSCFAIL", 0x53, 0x00 }, + { "OSC_RC32KCAL", 0x54, 0x00 }, + { "OSC_PLLCTRL", 0x55, 0x00 }, + { "OSC_DFLLCTRL", 0x56, 0x00 }, + { "DFLLRC32M_CTRL", 0x60, 0x00 }, + { "DFLLRC32M_CALA", 0x62, 0x00 }, + { "DFLLRC32M_CALB", 0x63, 0x00 }, + { "DFLLRC32M_COMP0", 0x64, 0x00 }, + { "DFLLRC32M_COMP1", 0x65, 0x00 }, + { "DFLLRC32M_COMP2", 0x66, 0x00 }, + { "DFLLRC2M_CTRL", 0x68, 0x00 }, + { "DFLLRC2M_CALA", 0x6A, 0x00 }, + { "DFLLRC2M_CALB", 0x6B, 0x00 }, + { "DFLLRC2M_COMP0", 0x6C, 0x00 }, + { "DFLLRC2M_COMP1", 0x6D, 0x00 }, + { "DFLLRC2M_COMP2", 0x6E, 0x00 }, + { "PR_PRGEN" , 0x70, 0x00 }, + { "PR_PRPA" , 0x71, 0x00 }, + { "PR_PRPB" , 0x72, 0x00 }, + { "PR_PRPC" , 0x73, 0x00 }, + { "PR_PRPD" , 0x74, 0x00 }, + { "PR_PRPE" , 0x75, 0x00 }, + { "PR_PRPF" , 0x76, 0x00 }, + { "RST_STATUS", 0x78, 0x00 }, + { "RST_CTRL" , 0x79, 0x00 }, + { "WDT_CTRL" , 0x80, 0x00 }, + { "WDT_WINCTRL", 0x81, 0x00 }, + { "WDT_STATUS", 0x82, 0x00 }, + { "MCU_DEVID0", 0x90, 0x00 }, + { "MCU_DEVID1", 0x91, 0x00 }, + { "MCU_DEVID2", 0x92, 0x00 }, + { "MCU_REVID" , 0x93, 0x00 }, + { "MCU_JTAGUID", 0x94, 0x00 }, + { "MCU_MCUCR" , 0x96, 0x00 }, + { "MCU_ANAINIT", 0x97, 0x00 }, + { "MCU_EVSYSLOCK", 0x98, 0x00 }, + { "MCU_AWEXLOCK", 0x99, 0x00 }, + { "PMIC_STATUS", 0xA0, 0x00 }, + { "PMIC_INTPRI", 0xA1, 0x00 }, + { "PMIC_CTRL" , 0xA2, 0x00 }, + { "PORTCFG_MPCMASK", 0xB0, 0x00 }, + { "PORTCFG_VPCTRLA", 0xB2, 0x00 }, + { "PORTCFG_VPCTRLB", 0xB3, 0x00 }, + { "PORTCFG_CLKEVOUT", 0xB4, 0x00 }, + { "PORTCFG_EBIOUT", 0xB5, 0x00 }, + { "PORTCFG_EVOUTSEL", 0xB6, 0x00 }, + { "AES_CTRL" , 0xC0, 0x00 }, + { "AES_STATUS", 0xC1, 0x00 }, + { "AES_STATE" , 0xC2, 0x00 }, + { "AES_KEY" , 0xC3, 0x00 }, + { "AES_INTCTRL", 0xC4, 0x00 }, + { "CRC_CTRL" , 0xD0, 0x00 }, + { "CRC_STATUS", 0xD1, 0x00 }, + { "CRC_DATAIN", 0xD3, 0x00 }, + { "CRC_CHECKSUM0", 0xD4, 0x00 }, + { "CRC_CHECKSUM1", 0xD5, 0x00 }, + { "CRC_CHECKSUM2", 0xD6, 0x00 }, + { "CRC_CHECKSUM3", 0xD7, 0x00 }, + { "DMA_CTRL" , 0x100, 0x00 }, + { "DMA_INTFLAGS", 0x103, 0x00 }, + { "DMA_STATUS", 0x104, 0x00 }, + { "DMA_CH0_CTRLA", 0x110, 0x00 }, + { "DMA_CH0_CTRLB", 0x111, 0x00 }, + { "DMA_CH0_ADDRCTRL", 0x112, 0x00 }, + { "DMA_CH0_TRIGSRC", 0x113, 0x00 }, + { "DMA_CH0_REPCNT", 0x116, 0x00 }, + { "DMA_CH0_SRCADDR0", 0x118, 0x00 }, + { "DMA_CH0_SRCADDR1", 0x119, 0x00 }, + { "DMA_CH0_SRCADDR2", 0x11A, 0x00 }, + { "DMA_CH0_DESTADDR0", 0x11C, 0x00 }, + { "DMA_CH0_DESTADDR1", 0x11D, 0x00 }, + { "DMA_CH0_DESTADDR2", 0x11E, 0x00 }, + { "DMA_CH1_CTRLA", 0x120, 0x00 }, + { "DMA_CH1_CTRLB", 0x121, 0x00 }, + { "DMA_CH1_ADDRCTRL", 0x122, 0x00 }, + { "DMA_CH1_TRIGSRC", 0x123, 0x00 }, + { "DMA_CH1_REPCNT", 0x126, 0x00 }, + { "DMA_CH1_SRCADDR0", 0x128, 0x00 }, + { "DMA_CH1_SRCADDR1", 0x129, 0x00 }, + { "DMA_CH1_SRCADDR2", 0x12A, 0x00 }, + { "DMA_CH1_DESTADDR0", 0x12C, 0x00 }, + { "DMA_CH1_DESTADDR1", 0x12D, 0x00 }, + { "DMA_CH1_DESTADDR2", 0x12E, 0x00 }, + { "DMA_CH2_CTRLA", 0x130, 0x00 }, + { "DMA_CH2_CTRLB", 0x131, 0x00 }, + { "DMA_CH2_ADDRCTRL", 0x132, 0x00 }, + { "DMA_CH2_TRIGSRC", 0x133, 0x00 }, + { "DMA_CH2_REPCNT", 0x136, 0x00 }, + { "DMA_CH2_SRCADDR0", 0x138, 0x00 }, + { "DMA_CH2_SRCADDR1", 0x139, 0x00 }, + { "DMA_CH2_SRCADDR2", 0x13A, 0x00 }, + { "DMA_CH2_DESTADDR0", 0x13C, 0x00 }, + { "DMA_CH2_DESTADDR1", 0x13D, 0x00 }, + { "DMA_CH2_DESTADDR2", 0x13E, 0x00 }, + { "DMA_CH3_CTRLA", 0x140, 0x00 }, + { "DMA_CH3_CTRLB", 0x141, 0x00 }, + { "DMA_CH3_ADDRCTRL", 0x142, 0x00 }, + { "DMA_CH3_TRIGSRC", 0x143, 0x00 }, + { "DMA_CH3_REPCNT", 0x146, 0x00 }, + { "DMA_CH3_SRCADDR0", 0x148, 0x00 }, + { "DMA_CH3_SRCADDR1", 0x149, 0x00 }, + { "DMA_CH3_SRCADDR2", 0x14A, 0x00 }, + { "DMA_CH3_DESTADDR0", 0x14C, 0x00 }, + { "DMA_CH3_DESTADDR1", 0x14D, 0x00 }, + { "DMA_CH3_DESTADDR2", 0x14E, 0x00 }, + { "EVSYS_CH0MUX", 0x180, 0x00 }, + { "EVSYS_CH1MUX", 0x181, 0x00 }, + { "EVSYS_CH2MUX", 0x182, 0x00 }, + { "EVSYS_CH3MUX", 0x183, 0x00 }, + { "EVSYS_CH4MUX", 0x184, 0x00 }, + { "EVSYS_CH5MUX", 0x185, 0x00 }, + { "EVSYS_CH6MUX", 0x186, 0x00 }, + { "EVSYS_CH7MUX", 0x187, 0x00 }, + { "EVSYS_CH0CTRL", 0x188, 0x00 }, + { "EVSYS_CH1CTRL", 0x189, 0x00 }, + { "EVSYS_CH2CTRL", 0x18A, 0x00 }, + { "EVSYS_CH3CTRL", 0x18B, 0x00 }, + { "EVSYS_CH4CTRL", 0x18C, 0x00 }, + { "EVSYS_CH5CTRL", 0x18D, 0x00 }, + { "EVSYS_CH6CTRL", 0x18E, 0x00 }, + { "EVSYS_CH7CTRL", 0x18F, 0x00 }, + { "EVSYS_STROBE", 0x190, 0x00 }, + { "EVSYS_DATA", 0x191, 0x00 }, + { "NVM_ADDR0" , 0x1C0, 0x00 }, + { "NVM_ADDR1" , 0x1C1, 0x00 }, + { "NVM_ADDR2" , 0x1C2, 0x00 }, + { "NVM_DATA0" , 0x1C4, 0x00 }, + { "NVM_DATA1" , 0x1C5, 0x00 }, + { "NVM_DATA2" , 0x1C6, 0x00 }, + { "NVM_CMD" , 0x1CA, 0x00 }, + { "NVM_CTRLA" , 0x1CB, 0x00 }, + { "NVM_CTRLB" , 0x1CC, 0x00 }, + { "NVM_INTCTRL", 0x1CD, 0x00 }, + { "NVM_STATUS", 0x1CF, 0x00 }, + { "NVM_LOCKBITS", 0x1D0, 0x00 }, + { "ADCA_CTRLA", 0x200, 0x00 }, + { "ADCA_CTRLB", 0x201, 0x00 }, + { "ADCA_REFCTRL", 0x202, 0x00 }, + { "ADCA_EVCTRL", 0x203, 0x00 }, + { "ADCA_PRESCALER", 0x204, 0x00 }, + { "ADCA_INTFLAGS", 0x206, 0x00 }, + { "ADCA_TEMP" , 0x207, 0x00 }, + { "ADCA_CH0_CTRL", 0x220, 0x00 }, + { "ADCA_CH0_MUXCTRL", 0x221, 0x00 }, + { "ADCA_CH0_INTCTRL", 0x222, 0x00 }, + { "ADCA_CH0_INTFLAGS", 0x223, 0x00 }, + { "ADCA_CH0_SCAN", 0x226, 0x00 }, + { "ADCA_CH1_CTRL", 0x228, 0x00 }, + { "ADCA_CH1_MUXCTRL", 0x229, 0x00 }, + { "ADCA_CH1_INTCTRL", 0x22A, 0x00 }, + { "ADCA_CH1_INTFLAGS", 0x22B, 0x00 }, + { "ADCA_CH1_SCAN", 0x22E, 0x00 }, + { "ADCA_CH2_CTRL", 0x230, 0x00 }, + { "ADCA_CH2_MUXCTRL", 0x231, 0x00 }, + { "ADCA_CH2_INTCTRL", 0x232, 0x00 }, + { "ADCA_CH2_INTFLAGS", 0x233, 0x00 }, + { "ADCA_CH2_SCAN", 0x236, 0x00 }, + { "ADCA_CH3_CTRL", 0x238, 0x00 }, + { "ADCA_CH3_MUXCTRL", 0x239, 0x00 }, + { "ADCA_CH3_INTCTRL", 0x23A, 0x00 }, + { "ADCA_CH3_INTFLAGS", 0x23B, 0x00 }, + { "ADCA_CH3_SCAN", 0x23E, 0x00 }, + { "DACB_CTRLA", 0x320, 0x00 }, + { "DACB_CTRLB", 0x321, 0x00 }, + { "DACB_CTRLC", 0x322, 0x00 }, + { "DACB_EVCTRL", 0x323, 0x00 }, + { "DACB_STATUS", 0x325, 0x00 }, + { "DACB_CH0GAINCAL", 0x328, 0x00 }, + { "DACB_CH0OFFSETCAL", 0x329, 0x00 }, + { "DACB_CH1GAINCAL", 0x32A, 0x00 }, + { "DACB_CH1OFFSETCAL", 0x32B, 0x00 }, + { "ACA_AC0CTRL", 0x380, 0x00 }, + { "ACA_AC1CTRL", 0x381, 0x00 }, + { "ACA_AC0MUXCTRL", 0x382, 0x00 }, + { "ACA_AC1MUXCTRL", 0x383, 0x00 }, + { "ACA_CTRLA" , 0x384, 0x00 }, + { "ACA_CTRLB" , 0x385, 0x00 }, + { "ACA_WINCTRL", 0x386, 0x00 }, + { "ACA_STATUS", 0x387, 0x00 }, + { "RTC_CTRL" , 0x400, 0x00 }, + { "RTC_STATUS", 0x401, 0x00 }, + { "RTC_INTCTRL", 0x402, 0x00 }, + { "RTC_INTFLAGS", 0x403, 0x00 }, + { "RTC_TEMP" , 0x404, 0x00 }, + { "TWIC_CTRL" , 0x480, 0x00 }, + { "TWIC_MASTER_CTRLA", 0x481, 0x00 }, + { "TWIC_MASTER_CTRLB", 0x482, 0x00 }, + { "TWIC_MASTER_CTRLC", 0x483, 0x00 }, + { "TWIC_MASTER_STATUS", 0x484, 0x00 }, + { "TWIC_MASTER_BAUD", 0x485, 0x00 }, + { "TWIC_MASTER_ADDR", 0x486, 0x00 }, + { "TWIC_MASTER_DATA", 0x487, 0x00 }, + { "TWIC_SLAVE_CTRLA", 0x488, 0x00 }, + { "TWIC_SLAVE_CTRLB", 0x489, 0x00 }, + { "TWIC_SLAVE_STATUS", 0x48A, 0x00 }, + { "TWIC_SLAVE_ADDR", 0x48B, 0x00 }, + { "TWIC_SLAVE_DATA", 0x48C, 0x00 }, + { "TWIC_SLAVE_ADDRMASK", 0x48D, 0x00 }, + { "TWIE_CTRL" , 0x4A0, 0x00 }, + { "TWIE_MASTER_CTRLA", 0x4A1, 0x00 }, + { "TWIE_MASTER_CTRLB", 0x4A2, 0x00 }, + { "TWIE_MASTER_CTRLC", 0x4A3, 0x00 }, + { "TWIE_MASTER_STATUS", 0x4A4, 0x00 }, + { "TWIE_MASTER_BAUD", 0x4A5, 0x00 }, + { "TWIE_MASTER_ADDR", 0x4A6, 0x00 }, + { "TWIE_MASTER_DATA", 0x4A7, 0x00 }, + { "TWIE_SLAVE_CTRLA", 0x4A8, 0x00 }, + { "TWIE_SLAVE_CTRLB", 0x4A9, 0x00 }, + { "TWIE_SLAVE_STATUS", 0x4AA, 0x00 }, + { "TWIE_SLAVE_ADDR", 0x4AB, 0x00 }, + { "TWIE_SLAVE_DATA", 0x4AC, 0x00 }, + { "TWIE_SLAVE_ADDRMASK", 0x4AD, 0x00 }, + { "USB_CTRLA" , 0x4C0, 0x00 }, + { "USB_CTRLB" , 0x4C1, 0x00 }, + { "USB_STATUS", 0x4C2, 0x00 }, + { "USB_ADDR" , 0x4C3, 0x00 }, + { "USB_FIFOWP", 0x4C4, 0x00 }, + { "USB_FIFORP", 0x4C5, 0x00 }, + { "USB_INTCTRLA", 0x4C8, 0x00 }, + { "USB_INTCTRLB", 0x4C9, 0x00 }, + { "USB_INTFLAGSACLR", 0x4CA, 0x00 }, + { "USB_INTFLAGSASET", 0x4CB, 0x00 }, + { "USB_INTFLAGSBCLR", 0x4CC, 0x00 }, + { "USB_INTFLAGSBSET", 0x4CD, 0x00 }, + { "USB_CAL0" , 0x4FA, 0x00 }, + { "USB_CAL1" , 0x4FB, 0x00 }, + { "PORTA_DIR" , 0x600, 0x00 }, + { "PORTA_DIRSET", 0x601, 0x00 }, + { "PORTA_DIRCLR", 0x602, 0x00 }, + { "PORTA_DIRTGL", 0x603, 0x00 }, + { "PORTA_OUT" , 0x604, 0x00 }, + { "PORTA_OUTSET", 0x605, 0x00 }, + { "PORTA_OUTCLR", 0x606, 0x00 }, + { "PORTA_OUTTGL", 0x607, 0x00 }, + { "PORTA_IN" , 0x608, 0x00 }, + { "PORTA_INTCTRL", 0x609, 0x00 }, + { "PORTA_INT0MASK", 0x60A, 0x00 }, + { "PORTA_INT1MASK", 0x60B, 0x00 }, + { "PORTA_INTFLAGS", 0x60C, 0x00 }, + { "PORTA_REMAP", 0x60E, 0x00 }, + { "PORTA_PIN0CTRL", 0x610, 0x00 }, + { "PORTA_PIN1CTRL", 0x611, 0x00 }, + { "PORTA_PIN2CTRL", 0x612, 0x00 }, + { "PORTA_PIN3CTRL", 0x613, 0x00 }, + { "PORTA_PIN4CTRL", 0x614, 0x00 }, + { "PORTA_PIN5CTRL", 0x615, 0x00 }, + { "PORTA_PIN6CTRL", 0x616, 0x00 }, + { "PORTA_PIN7CTRL", 0x617, 0x00 }, + { "PORTB_DIR" , 0x620, 0x00 }, + { "PORTB_DIRSET", 0x621, 0x00 }, + { "PORTB_DIRCLR", 0x622, 0x00 }, + { "PORTB_DIRTGL", 0x623, 0x00 }, + { "PORTB_OUT" , 0x624, 0x00 }, + { "PORTB_OUTSET", 0x625, 0x00 }, + { "PORTB_OUTCLR", 0x626, 0x00 }, + { "PORTB_OUTTGL", 0x627, 0x00 }, + { "PORTB_IN" , 0x628, 0x00 }, + { "PORTB_INTCTRL", 0x629, 0x00 }, + { "PORTB_INT0MASK", 0x62A, 0x00 }, + { "PORTB_INT1MASK", 0x62B, 0x00 }, + { "PORTB_INTFLAGS", 0x62C, 0x00 }, + { "PORTB_REMAP", 0x62E, 0x00 }, + { "PORTB_PIN0CTRL", 0x630, 0x00 }, + { "PORTB_PIN1CTRL", 0x631, 0x00 }, + { "PORTB_PIN2CTRL", 0x632, 0x00 }, + { "PORTB_PIN3CTRL", 0x633, 0x00 }, + { "PORTB_PIN4CTRL", 0x634, 0x00 }, + { "PORTB_PIN5CTRL", 0x635, 0x00 }, + { "PORTB_PIN6CTRL", 0x636, 0x00 }, + { "PORTB_PIN7CTRL", 0x637, 0x00 }, + { "PORTC_DIR" , 0x640, 0x00 }, + { "PORTC_DIRSET", 0x641, 0x00 }, + { "PORTC_DIRCLR", 0x642, 0x00 }, + { "PORTC_DIRTGL", 0x643, 0x00 }, + { "PORTC_OUT" , 0x644, 0x00 }, + { "PORTC_OUTSET", 0x645, 0x00 }, + { "PORTC_OUTCLR", 0x646, 0x00 }, + { "PORTC_OUTTGL", 0x647, 0x00 }, + { "PORTC_IN" , 0x648, 0x00 }, + { "PORTC_INTCTRL", 0x649, 0x00 }, + { "PORTC_INT0MASK", 0x64A, 0x00 }, + { "PORTC_INT1MASK", 0x64B, 0x00 }, + { "PORTC_INTFLAGS", 0x64C, 0x00 }, + { "PORTC_REMAP", 0x64E, 0x00 }, + { "PORTC_PIN0CTRL", 0x650, 0x00 }, + { "PORTC_PIN1CTRL", 0x651, 0x00 }, + { "PORTC_PIN2CTRL", 0x652, 0x00 }, + { "PORTC_PIN3CTRL", 0x653, 0x00 }, + { "PORTC_PIN4CTRL", 0x654, 0x00 }, + { "PORTC_PIN5CTRL", 0x655, 0x00 }, + { "PORTC_PIN6CTRL", 0x656, 0x00 }, + { "PORTC_PIN7CTRL", 0x657, 0x00 }, + { "PORTD_DIR" , 0x660, 0x00 }, + { "PORTD_DIRSET", 0x661, 0x00 }, + { "PORTD_DIRCLR", 0x662, 0x00 }, + { "PORTD_DIRTGL", 0x663, 0x00 }, + { "PORTD_OUT" , 0x664, 0x00 }, + { "PORTD_OUTSET", 0x665, 0x00 }, + { "PORTD_OUTCLR", 0x666, 0x00 }, + { "PORTD_OUTTGL", 0x667, 0x00 }, + { "PORTD_IN" , 0x668, 0x00 }, + { "PORTD_INTCTRL", 0x669, 0x00 }, + { "PORTD_INT0MASK", 0x66A, 0x00 }, + { "PORTD_INT1MASK", 0x66B, 0x00 }, + { "PORTD_INTFLAGS", 0x66C, 0x00 }, + { "PORTD_REMAP", 0x66E, 0x00 }, + { "PORTD_PIN0CTRL", 0x670, 0x00 }, + { "PORTD_PIN1CTRL", 0x671, 0x00 }, + { "PORTD_PIN2CTRL", 0x672, 0x00 }, + { "PORTD_PIN3CTRL", 0x673, 0x00 }, + { "PORTD_PIN4CTRL", 0x674, 0x00 }, + { "PORTD_PIN5CTRL", 0x675, 0x00 }, + { "PORTD_PIN6CTRL", 0x676, 0x00 }, + { "PORTD_PIN7CTRL", 0x677, 0x00 }, + { "PORTE_DIR" , 0x680, 0x00 }, + { "PORTE_DIRSET", 0x681, 0x00 }, + { "PORTE_DIRCLR", 0x682, 0x00 }, + { "PORTE_DIRTGL", 0x683, 0x00 }, + { "PORTE_OUT" , 0x684, 0x00 }, + { "PORTE_OUTSET", 0x685, 0x00 }, + { "PORTE_OUTCLR", 0x686, 0x00 }, + { "PORTE_OUTTGL", 0x687, 0x00 }, + { "PORTE_IN" , 0x688, 0x00 }, + { "PORTE_INTCTRL", 0x689, 0x00 }, + { "PORTE_INT0MASK", 0x68A, 0x00 }, + { "PORTE_INT1MASK", 0x68B, 0x00 }, + { "PORTE_INTFLAGS", 0x68C, 0x00 }, + { "PORTE_REMAP", 0x68E, 0x00 }, + { "PORTE_PIN0CTRL", 0x690, 0x00 }, + { "PORTE_PIN1CTRL", 0x691, 0x00 }, + { "PORTE_PIN2CTRL", 0x692, 0x00 }, + { "PORTE_PIN3CTRL", 0x693, 0x00 }, + { "PORTE_PIN4CTRL", 0x694, 0x00 }, + { "PORTE_PIN5CTRL", 0x695, 0x00 }, + { "PORTE_PIN6CTRL", 0x696, 0x00 }, + { "PORTE_PIN7CTRL", 0x697, 0x00 }, + { "PORTR_DIR" , 0x7E0, 0x00 }, + { "PORTR_DIRSET", 0x7E1, 0x00 }, + { "PORTR_DIRCLR", 0x7E2, 0x00 }, + { "PORTR_DIRTGL", 0x7E3, 0x00 }, + { "PORTR_OUT" , 0x7E4, 0x00 }, + { "PORTR_OUTSET", 0x7E5, 0x00 }, + { "PORTR_OUTCLR", 0x7E6, 0x00 }, + { "PORTR_OUTTGL", 0x7E7, 0x00 }, + { "PORTR_IN" , 0x7E8, 0x00 }, + { "PORTR_INTCTRL", 0x7E9, 0x00 }, + { "PORTR_INT0MASK", 0x7EA, 0x00 }, + { "PORTR_INT1MASK", 0x7EB, 0x00 }, + { "PORTR_INTFLAGS", 0x7EC, 0x00 }, + { "PORTR_REMAP", 0x7EE, 0x00 }, + { "PORTR_PIN0CTRL", 0x7F0, 0x00 }, + { "PORTR_PIN1CTRL", 0x7F1, 0x00 }, + { "PORTR_PIN2CTRL", 0x7F2, 0x00 }, + { "PORTR_PIN3CTRL", 0x7F3, 0x00 }, + { "PORTR_PIN4CTRL", 0x7F4, 0x00 }, + { "PORTR_PIN5CTRL", 0x7F5, 0x00 }, + { "PORTR_PIN6CTRL", 0x7F6, 0x00 }, + { "PORTR_PIN7CTRL", 0x7F7, 0x00 }, + { "TCC2_CTRLA", 0x800, 0x00 }, + { "TCC2_CTRLB", 0x801, 0x00 }, + { "TCC2_CTRLC", 0x802, 0x00 }, + { "TCC0_CTRLD", 0x803, 0x00 }, + { "TCC2_CTRLE", 0x804, 0x00 }, + { "TCC2_INTCTRLA", 0x806, 0x00 }, + { "TCC2_INTCTRLB", 0x807, 0x00 }, + { "TCC0_CTRLFCLR", 0x808, 0x00 }, + { "TCC2_CTRLF", 0x809, 0x00 }, + { "TCC0_CTRLGCLR", 0x80A, 0x00 }, + { "TCC0_CTRLGSET", 0x80B, 0x00 }, + { "TCC2_INTFLAGS", 0x80C, 0x00 }, + { "TCC0_TEMP" , 0x80F, 0x00 }, + { "TCC2_LCNT" , 0x820, 0x00 }, + { "TCC2_HCNT" , 0x821, 0x00 }, + { "TCC2_LPER" , 0x826, 0x00 }, + { "TCC2_HPER" , 0x827, 0x00 }, + { "TCC2_LCMPA", 0x828, 0x00 }, + { "TCC2_HCMPA", 0x829, 0x00 }, + { "TCC2_LCMPB", 0x82A, 0x00 }, + { "TCC2_HCMPB", 0x82B, 0x00 }, + { "TCC2_LCMPC", 0x82C, 0x00 }, + { "TCC2_HCMPC", 0x82D, 0x00 }, + { "TCC2_LCMPD", 0x82E, 0x00 }, + { "TCC2_HCMPD", 0x82F, 0x00 }, + { "TCC1_CTRLA", 0x840, 0x00 }, + { "TCC1_CTRLB", 0x841, 0x00 }, + { "TCC1_CTRLC", 0x842, 0x00 }, + { "TCC1_CTRLD", 0x843, 0x00 }, + { "TCC1_CTRLE", 0x844, 0x00 }, + { "TCC1_INTCTRLA", 0x846, 0x00 }, + { "TCC1_INTCTRLB", 0x847, 0x00 }, + { "TCC1_CTRLFCLR", 0x848, 0x00 }, + { "TCC1_CTRLFSET", 0x849, 0x00 }, + { "TCC1_CTRLGCLR", 0x84A, 0x00 }, + { "TCC1_CTRLGSET", 0x84B, 0x00 }, + { "TCC1_INTFLAGS", 0x84C, 0x00 }, + { "TCC1_TEMP" , 0x84F, 0x00 }, + { "AWEXC_CTRL", 0x880, 0x00 }, + { "AWEXC_FDEMASK", 0x882, 0x00 }, + { "AWEXC_FDCTRL", 0x883, 0x00 }, + { "AWEXC_STATUS", 0x884, 0x00 }, + { "AWEXC_STATUSSET", 0x885, 0x00 }, + { "AWEXC_DTBOTH", 0x886, 0x00 }, + { "AWEXC_DTBOTHBUF", 0x887, 0x00 }, + { "AWEXC_DTLS", 0x888, 0x00 }, + { "AWEXC_DTHS", 0x889, 0x00 }, + { "AWEXC_DTLSBUF", 0x88A, 0x00 }, + { "AWEXC_DTHSBUF", 0x88B, 0x00 }, + { "AWEXC_OUTOVEN", 0x88C, 0x00 }, + { "HIRESC_CTRLA", 0x890, 0x00 }, + { "USARTC0_DATA", 0x8A0, 0x00 }, + { "USARTC0_STATUS", 0x8A1, 0x00 }, + { "USARTC0_CTRLA", 0x8A3, 0x00 }, + { "USARTC0_CTRLB", 0x8A4, 0x00 }, + { "USARTC0_CTRLC", 0x8A5, 0x00 }, + { "USARTC0_BAUDCTRLA", 0x8A6, 0x00 }, + { "USARTC0_BAUDCTRLB", 0x8A7, 0x00 }, + { "USARTC1_DATA", 0x8B0, 0x00 }, + { "USARTC1_STATUS", 0x8B1, 0x00 }, + { "USARTC1_CTRLA", 0x8B3, 0x00 }, + { "USARTC1_CTRLB", 0x8B4, 0x00 }, + { "USARTC1_CTRLC", 0x8B5, 0x00 }, + { "USARTC1_BAUDCTRLA", 0x8B6, 0x00 }, + { "USARTC1_BAUDCTRLB", 0x8B7, 0x00 }, + { "SPIC_CTRL" , 0x8C0, 0x00 }, + { "SPIC_INTCTRL", 0x8C1, 0x00 }, + { "SPIC_STATUS", 0x8C2, 0x00 }, + { "SPIC_DATA" , 0x8C3, 0x00 }, + { "IRCOM_CTRL", 0x8F8, 0x00 }, + { "IRCOM_TXPLCTRL", 0x8F9, 0x00 }, + { "IRCOM_RXPLCTRL", 0x8FA, 0x00 }, + { "TCD2_CTRLA", 0x900, 0x00 }, + { "TCD2_CTRLB", 0x901, 0x00 }, + { "TCD2_CTRLC", 0x902, 0x00 }, + { "TCD0_CTRLD", 0x903, 0x00 }, + { "TCD2_CTRLE", 0x904, 0x00 }, + { "TCD2_INTCTRLA", 0x906, 0x00 }, + { "TCD2_INTCTRLB", 0x907, 0x00 }, + { "TCD0_CTRLFCLR", 0x908, 0x00 }, + { "TCD2_CTRLF", 0x909, 0x00 }, + { "TCD0_CTRLGCLR", 0x90A, 0x00 }, + { "TCD0_CTRLGSET", 0x90B, 0x00 }, + { "TCD2_INTFLAGS", 0x90C, 0x00 }, + { "TCD0_TEMP" , 0x90F, 0x00 }, + { "TCD2_LCNT" , 0x920, 0x00 }, + { "TCD2_HCNT" , 0x921, 0x00 }, + { "TCD2_LPER" , 0x926, 0x00 }, + { "TCD2_HPER" , 0x927, 0x00 }, + { "TCD2_LCMPA", 0x928, 0x00 }, + { "TCD2_HCMPA", 0x929, 0x00 }, + { "TCD2_LCMPB", 0x92A, 0x00 }, + { "TCD2_HCMPB", 0x92B, 0x00 }, + { "TCD2_LCMPC", 0x92C, 0x00 }, + { "TCD2_HCMPC", 0x92D, 0x00 }, + { "TCD2_LCMPD", 0x92E, 0x00 }, + { "TCD2_HCMPD", 0x92F, 0x00 }, + { "TCD1_CTRLA", 0x940, 0x00 }, + { "TCD1_CTRLB", 0x941, 0x00 }, + { "TCD1_CTRLC", 0x942, 0x00 }, + { "TCD1_CTRLD", 0x943, 0x00 }, + { "TCD1_CTRLE", 0x944, 0x00 }, + { "TCD1_INTCTRLA", 0x946, 0x00 }, + { "TCD1_INTCTRLB", 0x947, 0x00 }, + { "TCD1_CTRLFCLR", 0x948, 0x00 }, + { "TCD1_CTRLFSET", 0x949, 0x00 }, + { "TCD1_CTRLGCLR", 0x94A, 0x00 }, + { "TCD1_CTRLGSET", 0x94B, 0x00 }, + { "TCD1_INTFLAGS", 0x94C, 0x00 }, + { "TCD1_TEMP" , 0x94F, 0x00 }, + { "HIRESD_CTRLA", 0x990, 0x00 }, + { "USARTD0_DATA", 0x9A0, 0x00 }, + { "USARTD0_STATUS", 0x9A1, 0x00 }, + { "USARTD0_CTRLA", 0x9A3, 0x00 }, + { "USARTD0_CTRLB", 0x9A4, 0x00 }, + { "USARTD0_CTRLC", 0x9A5, 0x00 }, + { "USARTD0_BAUDCTRLA", 0x9A6, 0x00 }, + { "USARTD0_BAUDCTRLB", 0x9A7, 0x00 }, + { "USARTD1_DATA", 0x9B0, 0x00 }, + { "USARTD1_STATUS", 0x9B1, 0x00 }, + { "USARTD1_CTRLA", 0x9B3, 0x00 }, + { "USARTD1_CTRLB", 0x9B4, 0x00 }, + { "USARTD1_CTRLC", 0x9B5, 0x00 }, + { "USARTD1_BAUDCTRLA", 0x9B6, 0x00 }, + { "USARTD1_BAUDCTRLB", 0x9B7, 0x00 }, + { "SPID_CTRL" , 0x9C0, 0x00 }, + { "SPID_INTCTRL", 0x9C1, 0x00 }, + { "SPID_STATUS", 0x9C2, 0x00 }, + { "SPID_DATA" , 0x9C3, 0x00 }, + { "TCE0_CTRLA", 0xA00, 0x00 }, + { "TCE0_CTRLB", 0xA01, 0x00 }, + { "TCE0_CTRLC", 0xA02, 0x00 }, + { "TCE0_CTRLD", 0xA03, 0x00 }, + { "TCE0_CTRLE", 0xA04, 0x00 }, + { "TCE0_INTCTRLA", 0xA06, 0x00 }, + { "TCE0_INTCTRLB", 0xA07, 0x00 }, + { "TCE0_CTRLFCLR", 0xA08, 0x00 }, + { "TCE0_CTRLFSET", 0xA09, 0x00 }, + { "TCE0_CTRLGCLR", 0xA0A, 0x00 }, + { "TCE0_CTRLGSET", 0xA0B, 0x00 }, + { "TCE0_INTFLAGS", 0xA0C, 0x00 }, + { "TCE0_TEMP" , 0xA0F, 0x00 }, + { "HIRESE_CTRLA", 0xA90, 0x00 }, + { "USARTE0_DATA", 0xAA0, 0x00 }, + { "USARTE0_STATUS", 0xAA1, 0x00 }, + { "USARTE0_CTRLA", 0xAA3, 0x00 }, + { "USARTE0_CTRLB", 0xAA4, 0x00 }, + { "USARTE0_CTRLC", 0xAA5, 0x00 }, + { "USARTE0_BAUDCTRLA", 0xAA6, 0x00 }, + { "USARTE0_BAUDCTRLB", 0xAA7, 0x00 }, + /* May need to add SREG, SPL, SPH, and eeprom registers. */ + { 0, 0, 0} +}; + + gdb_io_reg_def_type atmega128rfa1_io_registers[] = { { "PINA", 0x20, 0x00 }, diff --git a/src/ioreg.h b/src/ioreg.h index 8f5066d..fdfd240 100644 --- a/src/ioreg.h +++ b/src/ioreg.h @@ -104,6 +104,7 @@ extern gdb_io_reg_def_type attiny167_io_registers[]; extern gdb_io_reg_def_type attiny43u_io_registers[]; extern gdb_io_reg_def_type attiny48_io_registers[]; extern gdb_io_reg_def_type attiny88_io_registers[]; +extern gdb_io_reg_def_type atxmega16a4u_io_registers[]; extern gdb_io_reg_def_type atmega128rfa1_io_registers[]; extern gdb_io_reg_def_type atmega256rfr2_io_registers[];