add note about DDRx memory DQ/DQS signals

Author: felixheld

schematic-checklist.md

@@ -51,6 +51,7 @@ off as invalid.
 * [ ] AC coupling caps on gigabit transceivers
 * [ ] TX/RX paired correctly for UART, SPI, MGT, etc
 * [ ] Differential pair polarity / pairing correct
+* [ ] DDR memory DQS pairs are connected that they correspond to the DQ byte lanes if the SoC/FPGA doesn't support arbitrary DQS pair swapping
 * [ ] Active high/low enable signal polarity correct
 * [ ] I/O banking rules met on FPGAs etc