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Trying to fix boot on FU740
1 parent 289cfeb commit 95a1159

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2 files changed

+34
-4
lines changed

2 files changed

+34
-4
lines changed

kernel/port/generic/port.mk

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,3 +13,9 @@ image: build $(OUTPUT)/image.hdd
1313

1414
burn: image
1515
sudo dd if=$(OUTPUT)/image.hdd of=$(DRIVE) bs=1M oflag=sync conv=nocreat
16+
17+
.PHONY: monitor
18+
monitor:
19+
echo -e "\033[1mType ^A^X to exit.\033[0m"
20+
picocom -q -b 115200 '$(PORT)' \
21+
| ../tools/address-filter.py -A $(CROSS_COMPILE)addr2line '$(OUTPUT)/badger-os.elf'; echo -e '\033[0m'

kernel/port/generic/src/driver/pcie.c

Lines changed: 28 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@ bool pcie_memprotect(pcie_controller_t *ctl) {
2929
// Initialise the PCIe controller.
3030
// Init successful or not, takes ownership of the memory in `ctl`.
3131
static bool pcie_controller_init() {
32+
logkf(LOG_DEBUG, "PCIe config paddr: 0x%{size;x}", ctl.config_paddr);
33+
3234
// Allocate ranges of virtual memory to map the controller into.
3335
size_t bus_count = ctl.bus_end - ctl.bus_start + 1;
3436
size_t config_size = bus_count * PCIE_ECAM_SIZE_PER_BUS;
@@ -79,7 +81,7 @@ static void pcie_ecam_func_detect(uint8_t bus, uint8_t dev, uint8_t func) {
7981
hdr->classcode.subclass,
8082
hdr->classcode.progif
8183
);
82-
find_pci_driver(hdr->classcode, (pci_addr_t){bus, dev, func});
84+
// find_pci_driver(hdr->classcode, (pci_addr_t){bus, dev, func});
8385
}
8486

8587
// Enumerate device via ECAM.
@@ -380,12 +382,34 @@ static void
380382
return;
381383
}
382384
ctl.type = PCIE_CTYPE_SIFIVE_FU740;
385+
386+
// Read FU740 PCIe configuration space physical address.
387+
ctl.config_paddr = dtb_read_cells(handle, node, "reg", 4, addr_cells);
388+
389+
// Read bus range.
390+
dtb_prop_t *bus_range = dtb_get_prop(handle, node, "bus-range");
391+
if (bus_range->content_len != 8) {
392+
logk(LOG_ERROR, "Incorrect bus-range for PCI");
393+
goto malformed_dtb;
394+
}
395+
ctl.bus_start = dtb_prop_read_cell(handle, bus_range, 0);
396+
ctl.bus_end = dtb_prop_read_cell(handle, bus_range, 1);
397+
398+
// Read PCIe interrupt mappings.
399+
if (!pci_dtb_irqmap(handle, node)) {
400+
goto malformed_dtb;
401+
}
402+
403+
// Read PCIe range mappings.
383404
if (!pci_dtb_ranges(handle, node)) {
384-
logk(LOG_WARN, "Malformed DTB; ignoring this PCIe controller!");
385-
return;
405+
goto malformed_dtb;
386406
}
387-
// TODO: Find FU740 PCIe configuration space.
407+
388408
pcie_controller_init();
409+
return;
410+
411+
malformed_dtb:
412+
logk(LOG_WARN, "Initialization failed; ignoring this PCIe controller!");
389413
}
390414
#endif
391415
#endif

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