Minecraft Verilog synthesizer
cargo build
cargo run --bin yosys -- -s res/verilog/adder.v
cargo run --bin veristone -- -s res/verilog/adder.v- Verilog -> Yosys -> netlist (graph data structure)
- Netlist -> our code -> mcfunction
- https://doc.rust-lang.org/stable/rust-by-example/index.html
- Backup: Python
- https://github.com/itsfrank/MinecraftHDL
- https://github.com/MinecraftMachina/FabricHDL
- https://github.com/Kenny2github/V2MC
- https://github.com/InputBlackBoxOutput/Redstone-HDL
- https://github.com/PietPtr/verilog2minecraft
- https://github.com/google/minetest_pnr
- http://sigtbd.csail.mit.edu/ (doesn't load???)
- https://github.com/qmn/pershing
- https://github.com/qmn/dewey
sudo apt-get install iverilog yosys graphviz
curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | shBasic usage of Icarus Verilog:
(g2012 enables systemverilog)
iverilog -g2012 adder.v -o adderLinks for generating BLIF netlists with Yosys: