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‎accel_driver.vhd

+523
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‎clock_div.vhd

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--clock div
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity clock_div is
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generic(clk_in_freq : natural := 4;
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clk_out_freq : natural := 2);
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port (
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clk_in : in std_logic;
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clk_out : out std_logic;
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rst : in std_logic;
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enable : in std_logic;
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bytes : in std_logic_vector(3 downto 0);
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polarity : in std_logic;
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clk_active : out std_logic;
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byte_flag : out std_logic
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);
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end clock_div;
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architecture bhv of clock_div is
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constant max : natural := clk_in_freq / clk_out_freq / 2;
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signal count, lastByteCount : integer range 0 to max*2;
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signal clock_signal : std_logic;
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signal byte_count : std_logic_vector (3 downto 0);
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signal bit_count : integer range 0 to 8;
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begin
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process(clk_in, rst)
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begin
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if(rst = '1' or enable = '0') then
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count <= 0;
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lastByteCount <= 0;
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clk_active <= '0';
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clock_signal <= polarity;
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bit_count <= 0;
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byte_count <= (others => '0');
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byte_flag <= '0';
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elsif(clk_in'event and clk_in = '1') then
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if(enable = '1' and byte_count < bytes) then
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clk_active <= '1';
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if (count = max-1) then
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count <= 0;
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clock_signal <= not clock_signal;
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if((not clock_signal) = polarity) then
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--increment bit count
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--increment byte count after 8 bits and clean bit count
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--clear byte count after numOfBytes and clear active_clk
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byte_flag <= '0'; -- clear the byte flag
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if(bit_count = 7) then
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byte_count <= std_logic_vector(unsigned(byte_count) + 1);
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bit_count <= 0;
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byte_flag <= '1'; --set byte flag for one sclk cycle
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if( byte_count = std_logic_vector(unsigned(bytes) - 1)) then
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--clk_active <= '0';
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--clock_signal <= clock_signal; --do not toggle clock
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end if;
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else
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bit_count <= bit_count + 1;
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end if;
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-- if( byte_count = bytes) then
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-- clk_active <= '0';
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-- end if;
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end if;
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else
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count <= count + 1;
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end if;
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elsif(enable = '1') then
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clk_active <= '1';
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if (lastByteCount = max-1) then
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lastByteCount <= 0;
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clk_active <= '0';
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else
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lastByteCount <= lastByteCount + 1;
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end if;
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end if;
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end if;
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-- if(rst = '1' or enable = '0') then
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-- count <= 0;
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-- lastByteCount <= 0;
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-- clk_active <= '0';
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-- clock_signal <= polarity;
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-- bit_count <= 0;
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-- byte_count <= (others => '0');
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-- byte_flag <= '0';
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--
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-- elsif(rising_edge(clk_in) and enable = '1' and byte_count < bytes) then
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--
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-- clk_active <= '1';
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-- if (count = max-1) then
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-- count <= 0;
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-- clock_signal <= not clock_signal;
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--
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-- if((not clock_signal) = polarity) then
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-- --increment bit count
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-- --increment byte count after 8 bits and clean bit count
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-- --clear byte count after numOfBytes and clear active_clk
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--
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-- byte_flag <= '0'; -- clear the byte flag
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--
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-- if(bit_count = 7) then
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-- byte_count <= std_logic_vector(unsigned(byte_count) + 1);
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-- bit_count <= 0;
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-- byte_flag <= '1'; --set byte flag for one cycle
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--
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-- if( byte_count = std_logic_vector(unsigned(bytes) - 1)) then
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-- --clk_active <= '0';
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-- --clock_signal <= clock_signal; --do not toggle clock
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--
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-- end if;
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--
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--
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-- else
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-- bit_count <= bit_count + 1;
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-- end if;
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--
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---- if( byte_count = bytes) then
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---- clk_active <= '0';
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---- end if;
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--
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-- end if;
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-- else
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-- count <= count + 1;
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-- end if;
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--
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--
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-- elsif(rising_edge(clk_in) and enable = '1') then
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--
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-- clk_active <= '1';
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-- if (lastByteCount = max-1) then
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-- lastByteCount <= 0;
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-- clk_active <= '0';
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-- else
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-- lastByteCount <= lastByteCount + 1;
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-- end if;
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--
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--
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--
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-- end if;
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--clk_out <= clock_signal;
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end process;
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clk_out <= clock_signal;
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end bhv;

‎clock_div_tb.vhd

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--clock_div_tb
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity clock_div_tb is
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end clock_div_tb;
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architecture TB of clock_div_tb is
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-----------------------------------
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--signals
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-----------------------------------
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signal clk50MHz : std_logic := '0';
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signal sclk : std_logic;
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signal rst : std_logic;
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signal enable : std_logic;
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signal bytes : std_logic_vector (3 downto 0);
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signal polarity : std_logic;
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signal clk_active : std_logic;
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signal byte_flag : std_logic;
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begin
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-----------------------------------
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--units under test
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-----------------------------------
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U_CLOCK_DIV : entity work.clock_div
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generic map(
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clk_in_freq => 50000000,
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clk_out_freq => 1000)
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port map(
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clk_in => clk50MHz,
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clk_out => sclk,
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rst => rst,
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enable => enable,
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bytes => bytes,
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polarity => polarity,
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clk_active => clk_active,
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byte_flag => byte_flag);
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clk50MHz <= not clk50MHz after 10 ns; --50MHz
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process
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begin
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--reset
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rst <= '1';
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enable <='0';
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bytes <= "0100";
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polarity <= '1';
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wait for 1 ms;
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--go
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rst <= '0';
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wait for 1 ms;
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enable <= '1';
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wait for 4 ms;
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wait until clk_active = '0';
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enable <= '0';
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wait for 4 ms;
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enable <= '1';
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polarity <= '0';
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wait for 4 ms;
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wait until clk_active = '0';
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enable <= '0';
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wait for 1 ms;
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for i in 0 to 900000000 loop
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wait until clk50MHz'event and clk50MHz = '1';
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end loop;
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end process;
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end TB;

‎decoder7seg.vhd

+39
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--decoder7seg
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library ieee;
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use ieee.std_logic_1164.all;
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entity decoder7seg is
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port (
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input : in std_logic_vector(3 downto 0);
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output : out std_logic_vector(6 downto 0));
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end decoder7seg;
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architecture BHV of decoder7seg is
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begin -- BHV
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process(input)
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begin
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case input is
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when "0000" => output <= "1000000";--"0000001";
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when "0001" => output <= "1111001";--"1001111";
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when "0010" => output <= "0100100";--"0010010";
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when "0011" => output <= "0110000";--"0000110";
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when "0100" => output <= "0011001";--"1001100";
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when "0101" => output <= "0010010";--"0100100";
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when "0110" => output <= "0000010";--"0100000";
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when "0111" => output <= "1111000";--"0001111";
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when "1000" => output <= "0000000";--"0000000";
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when "1001" => output <= "0011000";--"0001100";
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when "1010" => output <= "0001000";--"0001000";
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when "1011" => output <= "0000011";--"1100000";
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when "1100" => output <= "1000110";--"0110001";
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when "1101" => output <= "0100001";--"1000010";
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when "1110" => output <= "0000110";--"0110000";
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when "1111" => output <= "0001110";--"0111000";
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when others => output <= "XXXXXXX";
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end case;
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end process;
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end BHV;

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