Bare metal support?

[sequencer]

We are working on an open source multiple lane RVV for HPC market https://github.com/chipsalliance/t1 with intensive chaining support. To provide as much as possible memory bandwidth. We don’t support mmu and coherency for now. Thus there is no Linux support.
We wanna provide a bare metal support for this repo, will it be acceptable?

[camel-cdr]

Yeah, that sounds great.

The current code works in freestanding mode with linux, porting it to other platforms only requires porting exit() and memwrite() in nolibc.h. Memory allocation is done via a static array in freestanding, and malloc() in hosted mode.

Does bare metal mean it runs in privilege mode? In that case, we may need to additional parameterize rdcycle to use csrr x, cycle and csrr x, mcycle instead.