AArch64 memory load immediate disponent truncated

[OBarronCS]

Work environment

Questions	Answers
Capstone module affected	aarch64
Source of Capstone	source
Version/git commit	latest next branch, commit hash 905d2d2

The metadata value indicating the memory disponent of aarch64 memory access instructions appears to be truncated to 32 bits.

On latest version of Capstone:

> cstool -d aarch64 a8792958 0x100c894d4
100c894d4  a8 79 29 58  ldr	x8, 0x100cdc408
	ID: 634 (ldr)
	op_count: 2
		operands[0].type: REG = x8
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.disp: 0xcdc408
		operands[1].access: READ
	Registers modified: x8

Expected: that .disp would be 0x100cdc408.

Previous version (5.0.7)

> cstool -d arm64 a8792958 0x100c894d4
100c894d4  a8 79 29 58  ldr	x8, #0x100cdc408
	ID: 558 (ldr)
	op_count: 2
		operands[0].type: REG = x8
		operands[0].access: WRITE
		operands[1].type: IMM = 0x100cdc408
		operands[1].access: READ
	Registers modified: x8

[OBarronCS]

Looks like the underlying datatype is int32_t

capstone/include/capstone/aarch64.h

Lines 2786 to 2790 in 905d2d2

	typedef struct aarch64_op_mem {
	aarch64_reg base; ///< base register
	aarch64_reg index; ///< index register
	int32_t disp; ///< displacement/offset value
	} aarch64_op_mem;

[OBarronCS]

Or perhaps the .mem.disp should not summed with the instruction address automatically? It seems to be happening in the special case where the .disp is the only thing in the memory operand. The bug here is probably that Capstone is automatically adding the address to the .disp, but since the address can be above 32bits, it truncates the result.

In the following case where there is also a .base, the instruction address is not embedded into the .disp:

> cstool -d aarch64 "20 0c 40 f9" 0x1010120 
1010120  20 0c 40 f9  ldr	x0, [x1, #0x18]
	ID: 634 (ldr)
	op_count: 2
		operands[0].type: REG = x0
		operands[0].access: WRITE
		operands[1].type: MEM
			operands[1].mem.base: REG = x1
			operands[1].mem.disp: 0x18
		operands[1].access: READ
	Registers read: x1
	Registers modified: x0