diff --git a/README.md b/README.md
index bd21fb5e..d6fa129b 100644
--- a/README.md
+++ b/README.md
@@ -31,25 +31,33 @@ See the [`capstone-sys`](capstone-sys) page for the requirements and supported p
 ```rust
 extern crate capstone;
 
+use capstone::arch::x86::X86ArchTag;
 use capstone::prelude::*;
 
 const X86_CODE: &'static [u8] = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\x14\x9e\x08\x00\x45\x31\xe4";
 
 /// Print register names
-fn reg_names(cs: &Capstone, regs: &[RegId]) -> String {
-    let names: Vec<String> = regs.iter().map(|&x| cs.reg_name(x).unwrap()).collect();
+fn reg_names<A, I>(cs: &Capstone<A>, regs: I) -> String
+where
+    A: ArchTag,
+    I: Iterator<Item = A::RegId>,
+{
+    let names: Vec<String> = regs.map(|x| cs.reg_name(x).unwrap()).collect();
     names.join(", ")
 }
 
 /// Print instruction group names
-fn group_names(cs: &Capstone, regs: &[InsnGroupId]) -> String {
-    let names: Vec<String> = regs.iter().map(|&x| cs.group_name(x).unwrap()).collect();
+fn group_names<A, I>(cs: &Capstone<A>, regs: I) -> String
+where
+    A: ArchTag,
+    I: Iterator<Item = A::InsnGroupId>,
+{
+    let names: Vec<String> = regs.map(|x| cs.group_name(x).unwrap()).collect();
     names.join(", ")
 }
 
 fn main() {
-    let cs = Capstone::new()
-        .x86()
+    let cs = Capstone::<X86ArchTag>::new()
         .mode(arch::x86::ArchMode::Mode64)
         .syntax(arch::x86::ArchSyntax::Att)
         .detail(true)
@@ -63,8 +71,8 @@ fn main() {
         println!();
         println!("{}", i);
 
-        let detail: InsnDetail = cs.insn_detail(&i).expect("Failed to get insn detail");
-        let arch_detail: ArchDetail = detail.arch_detail();
+        let detail = cs.insn_detail(&i).expect("Failed to get insn detail");
+        let arch_detail = detail.arch_detail();
         let ops = arch_detail.operands();
 
         let output: &[(&str, String)] = &[
diff --git a/capstone-rs/benches/my_benchmark.rs b/capstone-rs/benches/my_benchmark.rs
index 09b3ebdc..4c57e995 100644
--- a/capstone-rs/benches/my_benchmark.rs
+++ b/capstone-rs/benches/my_benchmark.rs
@@ -2,6 +2,7 @@ extern crate capstone;
 #[macro_use]
 extern crate criterion;
 
+use capstone::arch::DynamicArchTag;
 use capstone::prelude::*;
 use capstone::{Arch, Endian, ExtraMode, Mode, NO_EXTRA_MODE};
 use criterion::{black_box, Criterion};
@@ -17,8 +18,8 @@ fn arch_bench<T: Iterator<Item = ExtraMode>>(
     endian: Option<Endian>,
     detail: bool,
 ) {
-    let mut cs =
-        Capstone::new_raw(arch, mode, extra_mode, endian).expect("failed to make capstone");
+    let mut cs = Capstone::<DynamicArchTag>::new_raw(arch, mode, extra_mode, endian)
+        .expect("failed to make capstone");
     cs.set_detail(detail).expect("failed to set detail");
 
     let insns = cs.disasm_all(code, 0x1000).expect("failed to disassemble");
diff --git a/capstone-rs/examples/demo.rs b/capstone-rs/examples/demo.rs
index 387e7068..e1045329 100644
--- a/capstone-rs/examples/demo.rs
+++ b/capstone-rs/examples/demo.rs
@@ -1,7 +1,9 @@
 extern crate capstone;
 
+use capstone::arch::mips::MipsArchTag;
+use capstone::arch::x86::X86ArchTag;
+use capstone::arch::{ArchTag, DetailsArchInsn};
 use capstone::prelude::*;
-use capstone::InsnDetail;
 
 const MIPS_CODE: &[u8] = b"\x56\x34\x21\x34\xc2\x17\x01\x00";
 
@@ -9,29 +11,40 @@ const X86_CODE: &[u8] = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\x14\x9e\x08\x00\x
 
 #[cfg(feature = "full")]
 /// Print register names
-fn reg_names(cs: &Capstone, regs: &[RegId]) -> String {
-    let names: Vec<String> = regs.iter().map(|&x| cs.reg_name(x).unwrap()).collect();
+fn reg_names<A, I>(cs: &Capstone<A>, regs: I) -> String
+where
+    A: ArchTag,
+    I: Iterator<Item = A::RegId>,
+{
+    let names: Vec<String> = regs.map(|x| cs.reg_name(x).unwrap()).collect();
     names.join(", ")
 }
 
 #[cfg(feature = "full")]
 /// Print instruction group names
-fn group_names(cs: &Capstone, regs: &[InsnGroupId]) -> String {
-    let names: Vec<String> = regs.iter().map(|&x| cs.group_name(x).unwrap()).collect();
+fn group_names<A, I>(cs: &Capstone<A>, regs: I) -> String
+where
+    A: ArchTag,
+    I: Iterator<Item = A::InsnGroupId>,
+{
+    let names: Vec<String> = regs.map(|x| cs.group_name(x).unwrap()).collect();
     names.join(", ")
 }
 
 /// Disassemble code and print information
-fn arch_example(cs: &mut Capstone, code: &[u8]) -> CsResult<()> {
+fn arch_example<A: ArchTag>(arch: &'static str, cs: &mut Capstone<A>, code: &[u8]) -> CsResult<()> {
+    println!("\n*************************************");
+    println!("Architecture {}:", arch);
+
     let insns = cs.disasm_all(code, 0x1000)?;
     println!("Found {} instructions", insns.len());
     for i in insns.iter() {
         println!();
         println!("{}", i);
 
-        let detail: InsnDetail = cs.insn_detail(i)?;
-        let arch_detail: ArchDetail = detail.arch_detail();
-        let ops = arch_detail.operands();
+        let detail = cs.insn_detail(i)?;
+        let arch_detail = detail.arch_detail();
+        let ops: Vec<_> = arch_detail.operands().collect();
 
         #[cfg(feature = "full")]
         let output: &[(&str, String)] = &[
@@ -61,26 +74,19 @@ fn arch_example(cs: &mut Capstone, code: &[u8]) -> CsResult<()> {
 }
 
 fn example() -> CsResult<()> {
-    let cs_mips: Capstone = Capstone::new()
-        .mips()
+    let mut cs_mips = Capstone::<MipsArchTag>::new()
         .mode(arch::mips::ArchMode::Mips32R6)
         .detail(true)
         .build()?;
 
-    let cs_x86 = Capstone::new()
-        .x86()
+    let mut cs_x86 = Capstone::<X86ArchTag>::new()
         .mode(arch::x86::ArchMode::Mode64)
         .syntax(arch::x86::ArchSyntax::Att)
         .detail(true)
         .build()?;
 
-    let mut examples = [("MIPS", cs_mips, MIPS_CODE), ("X86", cs_x86, X86_CODE)];
-
-    for &mut (arch, ref mut cs, code) in examples.iter_mut() {
-        println!("\n*************************************");
-        println!("Architecture {}:", arch);
-        arch_example(cs, code)?;
-    }
+    arch_example("MIPS", &mut cs_mips, MIPS_CODE)?;
+    arch_example("X86", &mut cs_x86, X86_CODE)?;
 
     Ok(())
 }
diff --git a/capstone-rs/examples/objdump.rs b/capstone-rs/examples/objdump.rs
index cc09f041..2fbbd078 100644
--- a/capstone-rs/examples/objdump.rs
+++ b/capstone-rs/examples/objdump.rs
@@ -1,6 +1,7 @@
 extern crate capstone;
 extern crate macho;
 
+use capstone::arch::x86::X86ArchTag;
 use capstone::prelude::*;
 use std::env;
 use std::fs;
@@ -8,8 +9,7 @@ use std::io::Read;
 use std::process;
 
 fn main() {
-    let cs = Capstone::new()
-        .x86()
+    let cs = Capstone::<X86ArchTag>::new()
         .mode(arch::x86::ArchMode::Mode64)
         .build()
         .expect("Failed to create capstone handle");
diff --git a/capstone-rs/examples/parallel.rs b/capstone-rs/examples/parallel.rs
index 6d21bdd5..da495970 100644
--- a/capstone-rs/examples/parallel.rs
+++ b/capstone-rs/examples/parallel.rs
@@ -3,14 +3,14 @@
 //!
 //! We shard the input by using parallel iterators from the rayon crate.
 
+use capstone::arch::x86::X86ArchTag;
 use capstone::prelude::*;
 use rayon::prelude::*;
 
 fn main() -> CsResult<()> {
     // Closure to create `Capstone` instance
-    let create_cs = || -> CsResult<Capstone> {
-        let cs = Capstone::new()
-            .x86()
+    let create_cs = || -> CsResult<Capstone<X86ArchTag>> {
+        let cs = Capstone::<X86ArchTag>::new()
             .mode(arch::x86::ArchMode::Mode64)
             .detail(true)
             .build()?;
diff --git a/capstone-rs/fuzz/fuzz_targets/fuzz_target_disasm_x86_64.rs b/capstone-rs/fuzz/fuzz_targets/fuzz_target_disasm_x86_64.rs
index 437cf411..5eae85c2 100644
--- a/capstone-rs/fuzz/fuzz_targets/fuzz_target_disasm_x86_64.rs
+++ b/capstone-rs/fuzz/fuzz_targets/fuzz_target_disasm_x86_64.rs
@@ -3,18 +3,18 @@
 extern crate libfuzzer_sys;
 extern crate capstone;
 
+use capstone::arch::x86::X86ArchTag;
 use capstone::prelude::*;
 
 fuzz_target!(|data: &[u8]| {
-    let mut cs = Capstone::new()
-        .x86()
+    let mut cs = Capstone::<X86ArchTag>::new()
         .mode(arch::x86::ArchMode::Mode64)
         .detail(true)
         .build()
         .unwrap();
     for i in cs.disasm_all(data, 0x1000).unwrap().iter() {
-        let detail: InsnDetail = cs.insn_detail(&i).unwrap();
-        let arch_detail: ArchDetail = detail.arch_detail();
+        let detail = cs.insn_detail(&i).unwrap();
+        let arch_detail = detail.arch_detail();
         arch_detail.operands().iter().for_each(drop);
         detail.regs_read().iter().for_each(drop);
         detail.regs_write().iter().for_each(drop);
diff --git a/capstone-rs/src/arch/arm.rs b/capstone-rs/src/arch/arm.rs
index aa598c76..293f636c 100644
--- a/capstone-rs/src/arch/arm.rs
+++ b/capstone-rs/src/arch/arm.rs
@@ -1,7 +1,6 @@
 //! Contains arm-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 use capstone_sys::{
     arm_op_mem, arm_op_type, cs_arm, cs_arm_op, arm_shifter,
@@ -9,8 +8,10 @@ use capstone_sys::{
 use libc::c_uint;
 
 pub use crate::arch::arch_builder::arm::*;
-use crate::arch::DetailsArchInsn;
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
 use crate::instruction::{RegId, RegIdInt};
+use crate::{Arch, InsnDetail};
 
 pub use capstone_sys::arm_insn_group as ArmInsnGroup;
 pub use capstone_sys::arm_insn as ArmInsn;
@@ -22,9 +23,38 @@ pub use capstone_sys::arm_cc as ArmCC;
 pub use capstone_sys::arm_mem_barrier as ArmMemBarrier;
 pub use capstone_sys::arm_setend_type as ArmSetendType;
 
+/// Architecture tag that represents ARM.
+pub struct ArmArchTag;
+
+impl ArchTagSealed for ArmArchTag {}
+
+impl ArchTag for ArmArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = ArmReg;
+    type InsnId = ArmInsn;
+    type InsnGroupId = ArmInsnGroup;
+
+    type InsnDetail<'a> = ArmInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::ARM
+    }
+}
+
 /// Contains ARM-specific details for an instruction
 pub struct ArmInsnDetail<'a>(pub(crate) &'a cs_arm);
 
+impl<'a, 'i> From<&'i InsnDetail<'a, ArmArchTag>> for ArmInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, ArmArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.arm })
+    }
+}
+
 /// ARM shift amount
 #[derive(Clone, Copy, Debug, Eq, PartialEq, Hash)]
 pub enum ArmShift {
@@ -221,12 +251,12 @@ impl_PartialEq_repr_fields!(ArmInsnDetail<'a> [ 'a ];
 impl ArmOpMem {
     /// Base register
     pub fn base(&self) -> RegId {
-        RegId(self.0.base as RegIdInt)
+        RegId(self.0.base.0 as RegIdInt)
     }
 
     /// Index value
     pub fn index(&self) -> RegId {
-        RegId(self.0.index as RegIdInt)
+        RegId(self.0.index.0 as RegIdInt)
     }
 
     /// Scale for index register (can be 1, or -1)
@@ -244,7 +274,7 @@ impl_PartialEq_repr_fields!(ArmOpMem;
     base, index, scale, disp
 );
 
-impl cmp::Eq for ArmOpMem {}
+impl Eq for ArmOpMem {}
 
 impl Default for ArmOperand {
     fn default() -> Self {
@@ -280,7 +310,7 @@ def_arch_details_struct!(
     Operand = ArmOperand;
     OperandIterator = ArmOperandIterator;
     OperandIteratorLife = ArmOperandIterator<'a>;
-    [ pub struct ArmOperandIterator<'a>(slice::Iter<'a, cs_arm_op>); ]
+    [ pub struct ArmOperandIterator<'a>(core::slice::Iter<'a, cs_arm_op>); ]
     cs_arch_op = cs_arm_op;
     cs_arch = cs_arm;
 );
diff --git a/capstone-rs/src/arch/arm64.rs b/capstone-rs/src/arch/arm64.rs
index 1ef9ac19..22f64de6 100644
--- a/capstone-rs/src/arch/arm64.rs
+++ b/capstone-rs/src/arch/arm64.rs
@@ -1,13 +1,16 @@
 //! Contains arm64-specific types
 
+use core::convert::From;
+use core::{cmp, mem, slice};
+
+use capstone_sys::{arm64_op_mem, arm64_op_type, cs_arm64, cs_arm64_op};
 use libc::c_uint;
 
 pub use crate::arch::arch_builder::arm64::*;
-use crate::arch::DetailsArchInsn;
-use capstone_sys::{arm64_op_mem, arm64_op_type, cs_arm64, cs_arm64_op};
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
 use crate::instruction::{RegId, RegIdInt};
-use core::convert::From;
-use core::{cmp, fmt, mem, slice};
+use crate::{Arch, InsnDetail};
 
 // Re-exports
 pub use capstone_sys::arm64_insn_group as Arm64InsnGroup;
@@ -26,10 +29,38 @@ pub use capstone_sys::arm64_barrier_op as Arm64BarrierOp;
 use capstone_sys::cs_arm64_op__bindgen_ty_2;
 use capstone_sys::arm64_shifter;
 
+/// Architecture tag that represents ARM64.
+pub struct Arm64ArchTag;
+
+impl ArchTagSealed for Arm64ArchTag {}
+
+impl ArchTag for Arm64ArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = Arm64Reg;
+    type InsnId = Arm64Insn;
+    type InsnGroupId = Arm64InsnGroup;
+
+    type InsnDetail<'a> = Arm64InsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::ARM64
+    }
+}
 
 /// Contains ARM64-specific details for an instruction
 pub struct Arm64InsnDetail<'a>(pub(crate) &'a cs_arm64);
 
+impl<'a, 'i> From<&'i InsnDetail<'a, Arm64ArchTag>> for Arm64InsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, Arm64ArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.arm64 })
+    }
+}
+
 /// ARM64 shift amount
 #[derive(Clone, Copy, Debug, Eq, PartialEq, Hash)]
 pub enum Arm64Shift {
@@ -58,7 +89,7 @@ impl Arm64OperandType {
 
         match op_type {
             ARM64_OP_INVALID => Invalid,
-            ARM64_OP_REG => Reg(RegId(unsafe { value.reg } as RegIdInt)),
+            ARM64_OP_REG => Reg(RegId(unsafe { value.reg.0 } as RegIdInt)),
             ARM64_OP_IMM => Imm(unsafe { value.imm }),
             ARM64_OP_MEM => Mem(Arm64OpMem(unsafe { value.mem })),
             ARM64_OP_FP => Fp(unsafe { value.fp }),
@@ -160,12 +191,12 @@ impl_PartialEq_repr_fields!(Arm64InsnDetail<'a> [ 'a ];
 impl Arm64OpMem {
     /// Base register
     pub fn base(&self) -> RegId {
-        RegId(self.0.base as RegIdInt)
+        RegId(self.0.base.0 as RegIdInt)
     }
 
     /// Index register
     pub fn index(&self) -> RegId {
-        RegId(self.0.index as RegIdInt)
+        RegId(self.0.index.0 as RegIdInt)
     }
 
     /// Disp value
@@ -288,11 +319,11 @@ mod test {
         }
 
         t(
-            (ARM64_OP_INVALID, cs_arm64_op__bindgen_ty_2 { reg: 0 }),
+            (ARM64_OP_INVALID, cs_arm64_op__bindgen_ty_2 { reg: Arm64Reg::ARM64_REG_INVALID }),
             Invalid,
         );
         t(
-            (ARM64_OP_REG, cs_arm64_op__bindgen_ty_2 { reg: 0 }),
+            (ARM64_OP_REG, cs_arm64_op__bindgen_ty_2 { reg: Arm64Reg::ARM64_REG_INVALID }),
             Reg(RegId(0)),
         );
         t(
@@ -300,7 +331,7 @@ mod test {
             Imm(42),
         );
         t(
-            (ARM64_OP_REG_MRS, cs_arm64_op__bindgen_ty_2 { reg: ARM64_SYSREG_MDRAR_EL1 as u32 }),
+            (ARM64_OP_REG_MRS, cs_arm64_op__bindgen_ty_2 { reg: Arm64Reg(ARM64_SYSREG_MDRAR_EL1 as u32) }),
             RegMrs(ARM64_SYSREG_MDRAR_EL1),
         );
         t(
@@ -317,8 +348,8 @@ mod test {
         );
         t(
             (ARM64_OP_REG_MSR, cs_arm64_op__bindgen_ty_2 {
-                reg: arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1 as u32 }),
-            RegMsr(arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1),
+                reg: Arm64Reg(ARM64_SYSREG_ICC_EOIR1_EL1 as u32) }),
+            RegMsr(ARM64_SYSREG_ICC_EOIR1_EL1),
         );
         t(
             (ARM64_OP_SYS, cs_arm64_op__bindgen_ty_2 { sys: arm64_sys_op::ARM64_AT_S1E0R }),
diff --git a/capstone-rs/src/arch/evm.rs b/capstone-rs/src/arch/evm.rs
index f9136b51..977b08a3 100644
--- a/capstone-rs/src/arch/evm.rs
+++ b/capstone-rs/src/arch/evm.rs
@@ -1,6 +1,7 @@
 //! Contains EVM-specific types
 
-use core::fmt;
+use core::fmt::{Debug, Formatter};
+use core::marker::PhantomData;
 
 use capstone_sys::cs_evm;
 
@@ -9,7 +10,32 @@ pub use capstone_sys::evm_insn_group as EvmInsnGroup;
 pub use capstone_sys::evm_insn as EvmInsn;
 
 pub use crate::arch::arch_builder::evm::*;
-use crate::arch::DetailsArchInsn;
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
+use crate::{Arch, InsnDetail, RegIdInt};
+
+/// Architecture tag that represents EVM.
+pub struct EvmArchTag;
+
+impl ArchTagSealed for EvmArchTag {}
+
+impl ArchTag for EvmArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = RegIdInt;
+    type InsnId = EvmInsn;
+    type InsnGroupId = EvmInsnGroup;
+
+    type InsnDetail<'a> = EvmInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::EVM
+    }
+}
 
 /// Contains EVM-specific details for an instruction
 pub struct EvmInsnDetail<'a>(pub(crate) &'a cs_evm);
@@ -35,6 +61,12 @@ impl_PartialEq_repr_fields!(EvmInsnDetail<'a> [ 'a ];
     popped_items, pushed_items, fee
 );
 
+impl<'a, 'i> From<&'i InsnDetail<'a, EvmArchTag>> for EvmInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, EvmArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.evm })
+    }
+}
+
 /// EVM has no operands, so this is a zero-size type.
 #[derive(Clone, Debug, Eq, PartialEq, Default)]
 pub struct EvmOperand(());
@@ -43,15 +75,15 @@ pub struct EvmOperand(());
 
 /// Iterates over instruction operands
 #[derive(Clone)]
-pub struct EvmOperandIterator(());
+pub struct EvmOperandIterator<'a>(PhantomData<&'a ()>);
 
-impl EvmOperandIterator {
-    fn new() -> EvmOperandIterator {
-        EvmOperandIterator(())
+impl<'a> EvmOperandIterator<'a> {
+    fn new() -> EvmOperandIterator<'a> {
+        EvmOperandIterator(PhantomData::default())
     }
 }
 
-impl Iterator for EvmOperandIterator {
+impl<'a> Iterator for EvmOperandIterator<'a> {
     type Item = EvmOperand;
 
     fn next(&mut self) -> Option<Self::Item> {
@@ -59,26 +91,26 @@ impl Iterator for EvmOperandIterator {
     }
 }
 
-impl ExactSizeIterator for EvmOperandIterator {
+impl<'a> ExactSizeIterator for EvmOperandIterator<'a> {
     fn len(&self) -> usize {
         0
     }
 }
 
-impl PartialEq for EvmOperandIterator {
+impl<'a> PartialEq for EvmOperandIterator<'a> {
     fn eq(&self, _other: &EvmOperandIterator) -> bool {
         false
     }
 }
 
-impl fmt::Debug for EvmOperandIterator {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> ::core::fmt::Result {
+impl<'a> Debug for EvmOperandIterator<'a> {
+    fn fmt(&self, fmt: &mut Formatter) -> ::core::fmt::Result {
         fmt.debug_struct("EvmOperandIterator").finish()
     }
 }
 
-impl<'a> fmt::Debug for EvmInsnDetail<'a> {
-    fn fmt(&self, fmt: &mut fmt::Formatter) -> ::core::fmt::Result {
+impl<'a> Debug for EvmInsnDetail<'a> {
+    fn fmt(&self, fmt: &mut Formatter) -> ::core::fmt::Result {
         fmt.debug_struct("EvmInsnDetail")
             .field("cs_evm", &(self.0 as *const cs_evm))
             .finish()
@@ -86,10 +118,10 @@ impl<'a> fmt::Debug for EvmInsnDetail<'a> {
 }
 
 impl<'a> DetailsArchInsn for EvmInsnDetail<'a> {
-    type OperandIterator = EvmOperandIterator;
+    type OperandIterator = EvmOperandIterator<'a>;
     type Operand = EvmOperand;
 
-    fn operands(&self) -> EvmOperandIterator {
+    fn operands(&self) -> EvmOperandIterator<'a> {
         EvmOperandIterator::new()
     }
 }
diff --git a/capstone-rs/src/arch/m680x.rs b/capstone-rs/src/arch/m680x.rs
index cbc7dedd..076a80f5 100644
--- a/capstone-rs/src/arch/m680x.rs
+++ b/capstone-rs/src/arch/m680x.rs
@@ -1,7 +1,6 @@
 //! Contains m680x-specific types
 
 use core::convert::From;
-use core::{fmt, slice};
 
 use capstone_sys::{
     cs_m680x, cs_m680x_op, m680x_op_ext, m680x_op_idx, m680x_op_rel, m680x_op_type,
@@ -10,11 +9,36 @@ use capstone_sys::{
 // XXX todo(tmfink): create rusty versions
 pub use capstone_sys::m680x_insn as M680xInsn;
 pub use capstone_sys::m680x_reg as M680xReg;
+pub use capstone_sys::m680x_group_type as M680xInsnGroup;
 
 pub use crate::arch::arch_builder::m680x::*;
-use crate::arch::DetailsArchInsn;
-use crate::instruction::{RegId, RegIdInt};
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
+use crate::instruction::RegId;
+use crate::{Arch, InsnDetail};
 
+/// Architecture tag that represents M680X.
+pub struct M680xArchTag;
+
+impl ArchTagSealed for M680xArchTag {}
+
+impl ArchTag for M680xArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = M680xReg;
+    type InsnId = M680xInsn;
+    type InsnGroupId = M680xInsnGroup;
+
+    type InsnDetail<'a> = M680xInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::M680X
+    }
+}
 
 /// Contains M680X-specific details for an instruction
 pub struct M680xInsnDetail<'a>(pub(crate) &'a cs_m680x);
@@ -23,6 +47,12 @@ impl_PartialEq_repr_fields!(M680xInsnDetail<'a> [ 'a ];
     operands, flags
 );
 
+impl<'a, 'i> From<&'i InsnDetail<'a, M680xArchTag>> for M680xInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, M680xArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.m680x })
+    }
+}
+
 // M680X instruction flags
 const M680X_FIRST_OP_IN_MNEM: u8 = 1;
 const M680X_SECOND_OP_IN_MNEM: u8 = 2;
@@ -59,7 +89,7 @@ macro_rules! define_m680x_register_option_getter {
             if (self.0).$field == M680xReg::M680X_REG_INVALID {
                 None
             } else {
-                Some(RegId((self.0).$field as RegIdInt))
+                Some(self.0.$field.into())
             }
         }
     }
@@ -185,7 +215,7 @@ impl<'a> From<&'a cs_m680x_op> for M680xOperand {
     fn from(op: &cs_m680x_op) -> M680xOperand {
         let op_type = match op.type_ {
             m680x_op_type::M680X_OP_REGISTER => {
-                M680xOperandType::Reg(RegId(unsafe { op.__bindgen_anon_1.reg } as RegIdInt))
+                M680xOperandType::Reg(unsafe { op.__bindgen_anon_1.reg.into() })
             }
             m680x_op_type::M680X_OP_IMMEDIATE => {
                 M680xOperandType::Imm(unsafe { op.__bindgen_anon_1.imm })
@@ -238,7 +268,7 @@ def_arch_details_struct!(
     Operand = M680xOperand;
     OperandIterator = M680xOperandIterator;
     OperandIteratorLife = M680xOperandIterator<'a>;
-    [ pub struct M680xOperandIterator<'a>(slice::Iter<'a, cs_m680x_op>); ]
+    [ pub struct M680xOperandIterator<'a>(core::slice::Iter<'a, cs_m680x_op>); ]
     cs_arch_op = cs_m680x_op;
     cs_arch = cs_m680x;
 );
@@ -252,7 +282,7 @@ mod test {
     fn m680x_op_type() {
         let op_base = cs_m680x_op {
             type_: m680x_op_type::M680X_OP_INVALID,
-            __bindgen_anon_1: cs_m680x_op__bindgen_ty_1 { reg: 0 },
+            __bindgen_anon_1: cs_m680x_op__bindgen_ty_1 { reg: M680xReg(0) },
             size: 1,
             access: 0,
         };
@@ -270,7 +300,7 @@ mod test {
                 ..op_base
             })
             .op_type,
-            M680xOperandType::Reg(RegId(M680xReg::M680X_REG_E as RegIdInt))
+            M680xOperandType::Reg(M680xReg::M680X_REG_E.into())
         );
         assert_eq!(
             M680xOperand::from(&cs_m680x_op {
@@ -362,8 +392,8 @@ mod test {
             flags: 7,
         });
 
-        assert_eq!(idx.base_reg(), Some(RegId(base_reg as RegIdInt)));
-        assert_eq!(idx.offset_reg(), Some(RegId(offset_reg as RegIdInt)));
+        assert_eq!(idx.base_reg(), Some(base_reg.into()));
+        assert_eq!(idx.offset_reg(), Some(offset_reg.into()));
         assert_eq!(idx.offset(), offset);
         assert_eq!(idx.offset_addr(), offset_addr);
         assert_eq!(idx.offset_bits(), offset_bits);
diff --git a/capstone-rs/src/arch/m68k.rs b/capstone-rs/src/arch/m68k.rs
index 274f99b3..061e9a1b 100644
--- a/capstone-rs/src/arch/m68k.rs
+++ b/capstone-rs/src/arch/m68k.rs
@@ -1,7 +1,6 @@
 //! Contains m68k-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 use capstone_sys::{
     cs_m68k, cs_m68k_op, cs_m68k_op__bindgen_ty_1, m68k_address_mode, m68k_cpu_size, m68k_fpu_size,
@@ -10,15 +9,39 @@ use capstone_sys::{
 
 // XXX todo(tmfink): create rusty versions
 pub use capstone_sys::m68k_address_mode as M68kAddressMode;
+pub use capstone_sys::m68k_group_type as M68kInsnGroup;
 pub use capstone_sys::m68k_insn as M68kInsn;
 pub use capstone_sys::m68k_reg as M68kReg;
 
 pub use crate::arch::arch_builder::m68k::*;
-use crate::arch::DetailsArchInsn;
-use crate::Error;
+use crate::arch::internal::ArchTagSealed;
+use crate::arch::{ArchTag, DetailsArchInsn};
 use crate::instruction::{RegId, RegIdInt};
 use crate::prelude::*;
+use crate::{Arch, Error, InsnDetail};
 
+/// Architecture tag that represents M68K.
+pub struct M68kArchTag;
+
+impl ArchTagSealed for M68kArchTag {}
+
+impl ArchTag for M68kArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = M68kReg;
+    type InsnId = M68kInsn;
+    type InsnGroupId = M68kInsnGroup;
+
+    type InsnDetail<'a> = M68kInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::M68K
+    }
+}
 
 /// Contains M68K-specific details for an instruction
 pub struct M68kInsnDetail<'a>(pub(crate) &'a cs_m68k);
@@ -30,6 +53,12 @@ impl<'a> M68kInsnDetail<'a> {
     }
 }
 
+impl<'a, 'i> From<&'i InsnDetail<'a, M68kArchTag>> for M68kInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, M68kArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.m68k })
+    }
+}
+
 define_cs_enum_wrapper_reverse!(
     [
         /// Operation size of the CPU instructions
@@ -124,7 +153,7 @@ pub struct M68kRegisterBits {
 
 /// Allowed bits are 1; disallowed bits are 0
 const M68K_REGISTER_BITS_ALLOWED_MASK: u32 =
-    (1_u32 << ((m68k_reg::M68K_REG_FP7 as u8 - m68k_reg::M68K_REG_D0 as u8) + 1_u8)) - 1;
+    (1_u32 << ((m68k_reg::M68K_REG_FP7.0 - m68k_reg::M68K_REG_D0.0) + 1)) - 1;
 
 impl M68kRegisterBits {
     /// Create from a bitfield where 0th bit is d0, 1th bit is d1, ...
@@ -149,7 +178,7 @@ impl M68kRegisterBits {
 
     /// Create from iterator over registers: d0-d7, a0-a7, fp0-fp7
     /// Invalid registers will cause an error
-    pub fn from_register_iter<T: Iterator<Item = R>, R: Into<M68kReg::Type>>(
+    pub fn from_register_iter<T: Iterator<Item = R>, R: Into<M68kReg>>(
         reg_iter: T,
     ) -> CsResult<Self> {
         let mut bits: u32 = 0;
@@ -163,11 +192,9 @@ impl M68kRegisterBits {
     ///
     /// Returns an error if the register is invalid
     #[inline]
-    pub fn m68k_reg_to_bit_idx(reg: M68kReg::Type) -> CsResult<u8> {
-        use capstone_sys::m68k_reg::*;
-
-        if (M68K_REG_D0..=M68K_REG_FP7).contains(&reg) {
-            Ok((reg - M68K_REG_D0) as u8)
+    pub fn m68k_reg_to_bit_idx(reg: M68kReg) -> CsResult<u8> {
+        if (M68kReg::M68K_REG_D0.0..=M68kReg::M68K_REG_FP7.0).contains(&reg.0) {
+            Ok((reg.0 - M68kReg::M68K_REG_D0.0) as u8)
         } else {
             Err(Error::InvalidM68kBitfieldRegister)
         }
@@ -219,7 +246,7 @@ impl M68kOperand {
         let value: cs_m68k_op__bindgen_ty_1 = cs_op.__bindgen_anon_1;
 
         match cs_op.type_ {
-            M68K_OP_REG => Reg(RegId(unsafe { value.reg } as RegIdInt)),
+            M68K_OP_REG => Reg(RegId(unsafe { value.reg.0 } as RegIdInt)),
             M68K_OP_IMM => Imm(unsafe { value.imm } as u32),
             M68K_OP_MEM => Mem(M68kOpMem::new(cs_op)),
             M68K_OP_FP_SINGLE => FpSingle(unsafe { value.simm }),
@@ -230,8 +257,8 @@ impl M68kOperand {
             M68K_OP_REG_PAIR => {
                 let reg_pair = unsafe { value.reg_pair };
                 RegPair(
-                    RegId(reg_pair.reg_0 as RegIdInt),
-                    RegId(reg_pair.reg_1 as RegIdInt),
+                    RegId(reg_pair.reg_0.0 as RegIdInt),
+                    RegId(reg_pair.reg_1.0 as RegIdInt),
                 )
             }
             M68K_OP_BR_DISP => Displacement(cs_op.br_disp.into()),
@@ -294,7 +321,7 @@ macro_rules! define_m68k_register_option_getter {
             if self.op_mem.$field == M68kReg::M68K_REG_INVALID {
                 None
             } else {
-                Some(RegId(self.op_mem.$field as RegIdInt))
+                Some(self.op_mem.$field.into())
             }
         }
     }
@@ -334,9 +361,7 @@ impl M68kOpMem {
             | M68K_AM_REG_DIRECT_ADDR
             | M68K_AM_REGI_ADDR
             | M68K_AM_REGI_ADDR_POST_INC
-            | M68K_AM_REGI_ADDR_PRE_DEC => {
-                M68kOpMemExtraInfo::Reg(RegId(unsafe { value.reg } as RegIdInt))
-            }
+            | M68K_AM_REGI_ADDR_PRE_DEC => M68kOpMemExtraInfo::Reg(unsafe { value.reg.into() }),
 
             // The M68K_AM_IMMEDIATE case cannot be floating point because type will not be op_mem
             M68K_AM_ABSOLUTE_DATA_LONG | M68K_AM_ABSOLUTE_DATA_SHORT | M68K_AM_IMMEDIATE => {
@@ -442,7 +467,7 @@ impl_PartialEq_repr_fields!(M68kOpMem;
     address_mode, extra_info
 );
 
-impl cmp::Eq for M68kOpMem {}
+impl Eq for M68kOpMem {}
 
 impl<'a> From<&'a cs_m68k_op> for M68kOperand {
     fn from(insn: &cs_m68k_op) -> M68kOperand {
@@ -455,7 +480,7 @@ def_arch_details_struct!(
     Operand = M68kOperand;
     OperandIterator = M68kOperandIterator;
     OperandIteratorLife = M68kOperandIterator<'a>;
-    [ pub struct M68kOperandIterator<'a>(slice::Iter<'a, cs_m68k_op>); ]
+    [ pub struct M68kOperandIterator<'a>(core::slice::Iter<'a, cs_m68k_op>); ]
     cs_arch_op = cs_m68k_op;
     cs_arch = cs_m68k;
 );
@@ -465,12 +490,11 @@ mod test {
     use super::*;
     use capstone_sys::m68k_address_mode::*;
     use capstone_sys::m68k_op_type::*;
-    use capstone_sys::m68k_reg::*;
 
     const MEM_ZERO: m68k_op_mem = m68k_op_mem {
-        base_reg: M68K_REG_INVALID,
-        index_reg: M68K_REG_INVALID,
-        in_base_reg: M68K_REG_INVALID,
+        base_reg: M68kReg::M68K_REG_INVALID,
+        index_reg: M68kReg::M68K_REG_INVALID,
+        in_base_reg: M68kReg::M68K_REG_INVALID,
         in_disp: 0,
         out_disp: 0,
         disp: 0,
@@ -497,13 +521,15 @@ mod test {
 
         // Reg
         let op_reg = cs_m68k_op {
-            __bindgen_anon_1: cs_m68k_op__bindgen_ty_1 { reg: M68K_REG_D7 },
+            __bindgen_anon_1: cs_m68k_op__bindgen_ty_1 {
+                reg: M68kReg::M68K_REG_D7,
+            },
             type_: M68K_OP_REG,
             ..op_zero
         };
         assert_eq!(
             M68kOperand::new(&op_reg),
-            M68kOperand::Reg(RegId(M68K_REG_D7 as RegIdInt))
+            M68kOperand::Reg(RegId(M68kReg::M68K_REG_D7.0 as RegIdInt))
         );
 
         // Imm
@@ -516,8 +542,8 @@ mod test {
 
         // Mem
         let op_mem1 = m68k_op_mem {
-            base_reg: M68K_REG_A0,
-            index_reg: M68K_REG_D0,
+            base_reg: M68kReg::M68K_REG_A0,
+            index_reg: M68kReg::M68K_REG_D0,
             index_size: 0, // w
             ..MEM_ZERO
         };
@@ -536,10 +562,13 @@ mod test {
             M68kOperand::new(&op_mem),
             M68kOperand::Mem(rust_op_mem.clone())
         );
-        assert_eq!(rust_op_mem.base_reg(), Some(RegId(M68K_REG_A0 as RegIdInt)));
+        assert_eq!(
+            rust_op_mem.base_reg(),
+            Some(RegId(M68kReg::M68K_REG_A0.0 as RegIdInt))
+        );
         assert_eq!(
             rust_op_mem.index_reg(),
-            Some(RegId(M68K_REG_D0 as RegIdInt))
+            Some(RegId(M68kReg::M68K_REG_D0.0 as RegIdInt))
         );
         assert_eq!(rust_op_mem.in_base_reg(), None);
         assert_eq!(rust_op_mem.disp(), 0);
@@ -567,18 +596,24 @@ mod test {
 
     #[test]
     fn register_bits_from_iter() {
-        let empty: &[m68k_reg::Type] = &[];
+        let empty: &[M68kReg] = &[];
         assert_eq!(
             M68kRegisterBits::from_register_iter(empty.iter().copied()),
             Ok(M68kRegisterBits { bits: 0 })
         );
         assert_eq!(
-            M68kRegisterBits::from_register_iter([M68K_REG_D1].iter().copied()),
+            M68kRegisterBits::from_register_iter([M68kReg::M68K_REG_D1].iter().copied()),
             Ok(M68kRegisterBits { bits: 0b10 })
         );
         assert_eq!(
             M68kRegisterBits::from_register_iter(
-                [M68K_REG_D1, M68K_REG_A2, M68K_REG_FP7].iter().copied()
+                [
+                    M68kReg::M68K_REG_D1,
+                    M68kReg::M68K_REG_A2,
+                    M68kReg::M68K_REG_FP7
+                ]
+                .iter()
+                .copied()
             ),
             Ok(M68kRegisterBits {
                 bits: 0b1000_0000_0000_0100_0000_0010
@@ -598,21 +633,32 @@ mod test {
     #[test]
     fn op_eq() {
         use crate::arch::m68k::M68kOperand::*;
-        use crate::arch::m68k::M68kReg::*;
         use crate::arch::m68k::*;
         use capstone_sys::m68k_address_mode::*;
 
         assert_ne!(
             M68kOperand::RegBits(
                 M68kRegisterBits::from_register_iter(
-                    [M68K_REG_D0, M68K_REG_D2, M68K_REG_A2, M68K_REG_A3]
-                        .iter().copied()
+                    [
+                        M68kReg::M68K_REG_D0,
+                        M68kReg::M68K_REG_D2,
+                        M68kReg::M68K_REG_A2,
+                        M68kReg::M68K_REG_A3
+                    ]
+                    .iter()
+                    .copied()
                 )
                 .unwrap()
             ),
             M68kOperand::RegBits(
                 M68kRegisterBits::from_register_iter(
-                    [M68K_REG_D0, M68K_REG_A2, M68K_REG_A3].iter().copied()
+                    [
+                        M68kReg::M68K_REG_D0,
+                        M68kReg::M68K_REG_A2,
+                        M68kReg::M68K_REG_A3
+                    ]
+                    .iter()
+                    .copied()
                 )
                 .unwrap()
             )
@@ -621,12 +667,12 @@ mod test {
             Mem(M68kOpMem {
                 op_mem: MEM_ZERO,
                 address_mode: M68K_AM_REGI_ADDR_PRE_DEC,
-                extra_info: M68kOpMemExtraInfo::Reg(RegId(M68K_REG_A7 as RegIdInt)),
+                extra_info: M68kOpMemExtraInfo::Reg(M68kReg::M68K_REG_A7.into()),
             }),
             Mem(M68kOpMem {
                 op_mem: MEM_ZERO,
                 address_mode: M68K_AM_REGI_ADDR_PRE_DEC,
-                extra_info: M68kOpMemExtraInfo::Reg(RegId(M68K_REG_A6 as RegIdInt)),
+                extra_info: M68kOpMemExtraInfo::Reg(M68kReg::M68K_REG_A6.into()),
             })
         );
     }
@@ -634,12 +680,11 @@ mod test {
     #[cfg(feature = "full")]
     #[test]
     fn extra_info() {
-        use alloc::vec::Vec;
-        use crate::instruction::*;
         use crate::arch::DetailsArchInsn;
+        use crate::instruction::*;
+        use alloc::vec::Vec;
 
-        let cs = Capstone::new()
-            .m68k()
+        let cs = Capstone::<M68kArchTag>::new()
             .mode(arch::m68k::ArchMode::M68k040)
             .detail(true)
             .build()
@@ -649,18 +694,14 @@ mod test {
             // jsr     $12.l
             b"\x4e\xb9\x00\x00\x00\x12",
         ];
-        let code: Vec<u8> = code_parts
-            .iter()
-            .flat_map(|x| x.iter()).copied()
-            .collect();
+        let code: Vec<u8> = code_parts.iter().flat_map(|x| x.iter()).copied().collect();
         let insns = cs.disasm_all(&code, 0x1000).expect("Failed to disasm");
         let mut insns_iter = insns.iter();
 
         // jsr
-        let insn_jsr: &Insn = insns_iter.next().unwrap();
+        let insn_jsr: &Insn<M68kArchTag> = insns_iter.next().unwrap();
         let detail = cs.insn_detail(insn_jsr).unwrap();
-        let _arch_detail = detail.arch_detail();
-        let arch_detail = _arch_detail.m68k().unwrap();
+        let arch_detail = detail.arch_detail();
         let mut ops = arch_detail.operands();
         if let M68kOperand::Mem(mem) = ops.next().unwrap() {
             assert_eq!(mem.imm(), Some(0x12));
diff --git a/capstone-rs/src/arch/mips.rs b/capstone-rs/src/arch/mips.rs
index 331dc879..9b990199 100644
--- a/capstone-rs/src/arch/mips.rs
+++ b/capstone-rs/src/arch/mips.rs
@@ -1,7 +1,6 @@
 //! Contains mips-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 use capstone_sys::{cs_mips, cs_mips_op, mips_op_mem, mips_op_type};
 
@@ -11,8 +10,33 @@ pub use capstone_sys::mips_insn as MipsInsn;
 pub use capstone_sys::mips_reg as MipsReg;
 
 pub use crate::arch::arch_builder::mips::*;
-use crate::arch::DetailsArchInsn;
-use crate::instruction::{RegId, RegIdInt};
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
+use crate::instruction::RegId;
+use crate::{Arch, InsnDetail};
+
+/// Architecture tag that represents MIPS.
+pub struct MipsArchTag;
+
+impl ArchTagSealed for MipsArchTag {}
+
+impl ArchTag for MipsArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = MipsReg;
+    type InsnId = MipsInsn;
+    type InsnGroupId = MipsInsnGroup;
+
+    type InsnDetail<'a> = MipsInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::MIPS
+    }
+}
 
 /// Contains MIPS-specific details for an instruction
 pub struct MipsInsnDetail<'a>(pub(crate) &'a cs_mips);
@@ -21,6 +45,12 @@ impl_PartialEq_repr_fields!(MipsInsnDetail<'a> [ 'a ];
     operands
 );
 
+impl<'a, 'i> From<&'i InsnDetail<'a, MipsArchTag>> for MipsInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, MipsArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.mips })
+    }
+}
+
 /// MIPS operand
 #[derive(Clone, Debug, Eq, PartialEq)]
 pub enum MipsOperand {
@@ -50,7 +80,7 @@ pub struct MipsOpMem(pub(crate) mips_op_mem);
 impl MipsOpMem {
     /// Base register
     pub fn base(&self) -> RegId {
-        RegId(self.0.base as RegIdInt)
+        self.0.base.into()
     }
 
     /// Disp value
@@ -63,13 +93,13 @@ impl_PartialEq_repr_fields!(MipsOpMem;
     base, disp
 );
 
-impl cmp::Eq for MipsOpMem {}
+impl Eq for MipsOpMem {}
 
 impl<'a> From<&'a cs_mips_op> for MipsOperand {
     fn from(insn: &cs_mips_op) -> MipsOperand {
         match insn.type_ {
             mips_op_type::MIPS_OP_REG => {
-                MipsOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+                MipsOperand::Reg(unsafe { insn.__bindgen_anon_1.reg.into() })
             }
             mips_op_type::MIPS_OP_IMM => MipsOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
             mips_op_type::MIPS_OP_MEM => {
@@ -85,7 +115,7 @@ def_arch_details_struct!(
     Operand = MipsOperand;
     OperandIterator = MipsOperandIterator;
     OperandIteratorLife = MipsOperandIterator<'a>;
-    [ pub struct MipsOperandIterator<'a>(slice::Iter<'a, cs_mips_op>); ]
+    [ pub struct MipsOperandIterator<'a>(core::slice::Iter<'a, cs_mips_op>); ]
     cs_arch_op = cs_mips_op;
     cs_arch = cs_mips;
 );
@@ -99,7 +129,7 @@ mod test {
     fn test_mips_op_from() {
         let op = cs_mips_op {
             type_: mips_op_type::MIPS_OP_INVALID,
-            __bindgen_anon_1: cs_mips_op__bindgen_ty_1 { reg: 0 },
+            __bindgen_anon_1: cs_mips_op__bindgen_ty_1 { reg: MipsReg(0) },
         };
         assert_eq!(MipsOperand::from(&op), MipsOperand::Invalid);
     }
diff --git a/capstone-rs/src/arch/mod.rs b/capstone-rs/src/arch/mod.rs
index a2e58340..a300941c 100644
--- a/capstone-rs/src/arch/mod.rs
+++ b/capstone-rs/src/arch/mod.rs
@@ -6,11 +6,11 @@
 
 use alloc::vec::Vec;
 use core::fmt::Debug;
-use core::marker::PhantomData;
 
 use crate::capstone::Capstone;
 use crate::constants::Endian;
 use crate::error::CsResult;
+use crate::{Arch, Error, ExtraMode, InsnDetail, InsnGroupId, InsnId, Mode, RegId, Syntax};
 
 macro_rules! define_subset_enum {
     ( [
@@ -40,9 +40,9 @@ macro_rules! define_subset_enum {
 /// Define arch builders
 macro_rules! define_arch_builder {
     // ExtraMode rules
-    ( @extra_modes () ) => {};
-    ( @extra_modes ( $( $extra_mode:ident, )+ ) ) => {
-        impl super::BuildsCapstoneExtraMode<ArchMode, ArchExtraMode> for ArchCapstoneBuilder {
+    ( @extra_modes ( $arch:ident, $arch_tag:ident, ) ) => {};
+    ( @extra_modes ( $arch:ident, $arch_tag:ident, $( $extra_mode:ident, )+ ) ) => {
+        impl super::BuildsCapstoneExtraMode<crate::arch::$arch::$arch_tag> for ArchCapstoneBuilder {
             fn extra_mode<T: Iterator<Item=ArchExtraMode>>(mut self, extra_mode: T) -> Self {
                 self.extra_mode.clear();
                 self.extra_mode.extend(extra_mode);
@@ -52,9 +52,9 @@ macro_rules! define_arch_builder {
     };
 
     // Syntax rules
-    ( @syntax () ) => {};
-    ( @syntax ( $( $syntax:ident, )+ ) ) => {
-        impl super::BuildsCapstoneSyntax<ArchMode, ArchSyntax> for ArchCapstoneBuilder {
+    ( @syntax ( $arch:ident, $arch_tag:ident, ) ) => {};
+    ( @syntax ( $arch:ident, $arch_tag:ident, $( $syntax:ident, )+ ) ) => {
+        impl super::BuildsCapstoneSyntax<crate::arch::$arch::$arch_tag> for ArchCapstoneBuilder {
             fn syntax(mut self, syntax: ArchSyntax) -> Self {
                 self.syntax = Some(syntax);
                 self
@@ -63,9 +63,9 @@ macro_rules! define_arch_builder {
     };
 
     // Endian rules
-    ( @endian ( false) ) => {};
-    ( @endian ( true ) ) => {
-        impl super::BuildsCapstoneEndian<ArchMode> for ArchCapstoneBuilder {
+    ( @endian ( $arch:ident, $arch_tag:ident, false) ) => {};
+    ( @endian ( $arch:ident, $arch_tag:ident, true ) ) => {
+        impl super::BuildsCapstoneEndian<crate::arch::$arch::$arch_tag> for ArchCapstoneBuilder {
             fn endian(mut self, endian: Endian) -> Self {
                 self.endian = Some(endian);
                 self
@@ -76,7 +76,7 @@ macro_rules! define_arch_builder {
     // Entrance rule
     (
         $( [
-            ( $arch:ident, $arch_variant:ident )
+            ( $arch:ident, $arch_variant:ident, $arch_tag:ident )
             ( mode: $( $mode:ident, )+ )
             ( extra_modes: $( $extra_mode:ident, )* )
             ( syntax: $( $syntax:ident, )* )
@@ -95,9 +95,9 @@ macro_rules! define_arch_builder {
                 use crate::constants::{Arch, Endian, ExtraMode, Mode, Syntax};
                 use crate::error::{CsResult, Error};
 
-                define_arch_builder!( @syntax ( $( $syntax, )* ) );
-                define_arch_builder!( @endian ( $( $endian )* ) );
-                define_arch_builder!( @extra_modes ( $( $extra_mode, )* ) );
+                define_arch_builder!( @syntax ( $arch, $arch_tag, $( $syntax, )* ) );
+                define_arch_builder!( @endian ( $arch, $arch_tag, $( $endian )* ) );
+                define_arch_builder!( @extra_modes ( $arch, $arch_tag, $( $extra_mode, )* ) );
 
                 define_subset_enum!(
                     [ ArchMode = Mode ]
@@ -123,7 +123,7 @@ macro_rules! define_arch_builder {
                     pub(crate) endian: Option<Endian>,
                 }
 
-                impl super::BuildsCapstone<ArchMode> for ArchCapstoneBuilder {
+                impl super::BuildsCapstone<crate::arch::$arch::$arch_tag> for ArchCapstoneBuilder {
                     fn mode(mut self, mode: ArchMode) -> Self {
                         self.mode = Some(mode);
                         self
@@ -134,7 +134,7 @@ macro_rules! define_arch_builder {
                         self
                     }
 
-                    fn build(self) -> CsResult<Capstone> {
+                    fn build(self) -> CsResult<Capstone<crate::arch::$arch::$arch_tag>> {
                         let mode = match self.mode {
                             Some(mode) => mode,
                             None => {
@@ -146,14 +146,13 @@ macro_rules! define_arch_builder {
                                 return Err(Error::CustomError(msg));
                             }
                         };
-                        let extra_mode = self.extra_mode.iter().map(|x| ExtraMode::from(*x));
                         let mut capstone = Capstone::new_raw(Arch::$arch_variant,
                                                              mode.into(),
-                                                             extra_mode,
+                                                             self.extra_mode.iter().copied().map(|x| x.into()),
                                                              self.endian)?;
 
                         if let Some(syntax) = self.syntax {
-                            capstone.set_syntax(Syntax::from(syntax))?;
+                            capstone.set_syntax(syntax)?;
                         }
                         if self.is_detail {
                             capstone.set_detail(self.is_detail)?;
@@ -176,14 +175,6 @@ macro_rules! define_arch_builder {
                 }
             }
         )+
-
-        impl CapstoneBuilder {
-            $(
-                pub fn $arch(self) -> $arch::ArchCapstoneBuilder {
-                    Default::default()
-                }
-            )*
-        }
     }
 }
 
@@ -197,7 +188,7 @@ macro_rules! arch_info_base {
     ($x_macro:ident) => {
         $x_macro!(
             [
-                ( arm, ARM )
+                ( arm, ARM, ArmArchTag )
                 ( mode:
                     Arm,
                     Thumb,
@@ -212,7 +203,7 @@ macro_rules! arch_info_base {
                 ( both_endian: true )
             ]
             [
-                ( arm64, ARM64 )
+                ( arm64, ARM64, Arm64ArchTag )
                 ( mode:
                     Arm,
                     )
@@ -221,7 +212,7 @@ macro_rules! arch_info_base {
                 ( both_endian: true )
             ]
             [
-                ( evm, EVM )
+                ( evm, EVM, EvmArchTag )
                 ( mode:
                     Default,
                     )
@@ -230,7 +221,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( m680x, M680X )
+                ( m680x, M680X, M680xArchTag )
                 ( mode:
                     M680x6301,
                     M680x6309,
@@ -248,7 +239,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( m68k, M68K )
+                ( m68k, M68K, M68kArchTag )
                 ( mode:
                     M68k000,
                     M68k010,
@@ -261,7 +252,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( mips, MIPS )
+                ( mips, MIPS, MipsArchTag )
                 ( mode:
                     Mips32,
                     Mips64,
@@ -276,7 +267,7 @@ macro_rules! arch_info_base {
                 ( both_endian: true )
             ]
             [
-                ( ppc, PPC )
+                ( ppc, PPC, PpcArchTag )
                 ( mode:
                     Mode32,
                     Mode64,
@@ -289,7 +280,7 @@ macro_rules! arch_info_base {
                 ( both_endian: true )
             ]
             [
-                ( riscv, RISCV )
+                ( riscv, RISCV, RiscVArchTag )
                 ( mode:
                     RiscV32,
                     RiscV64,
@@ -301,7 +292,7 @@ macro_rules! arch_info_base {
                 ( both_endian: true )
             ]
             [
-                ( sparc, SPARC )
+                ( sparc, SPARC, SparcArchTag )
                 ( mode:
                     Default,
                     V9,
@@ -311,7 +302,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( sysz, SYSZ )
+                ( sysz, SYSZ, SyszArchTag )
                 ( mode:
                     Default,
                     )
@@ -320,7 +311,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( tms320c64x, TMS320C64X )
+                ( tms320c64x, TMS320C64X, Tms320c64xArchTag )
                 ( mode:
                     Default,
                     )
@@ -329,7 +320,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( x86, X86 )
+                ( x86, X86, X86ArchTag )
                 ( mode:
                     Mode16,
                     Mode32,
@@ -344,7 +335,7 @@ macro_rules! arch_info_base {
                 ( both_endian: false )
             ]
             [
-                ( xcore, XCORE )
+                ( xcore, XCORE, XcoreArchTag )
                 ( mode:
                     Default,
                     )
@@ -356,32 +347,92 @@ macro_rules! arch_info_base {
     };
 }
 
+mod internal {
+    /// Make sure that only this crate can implement `ArchTag`.
+    pub trait ArchTagSealed {}
+}
+
+/// Provides types relative to a specific arch.
+pub trait ArchTag: internal::ArchTagSealed + 'static + Sized {
+    /// Type of capstone builder that builds [`Capstone`] instances for this architecture.
+    ///
+    /// Objects of this type are returned from the `Capstone::new` function.
+    type Builder: Default;
+
+    /// Type that represents the disassembler's mode.
+    type Mode: Copy + Into<Mode>;
+
+    /// Type that represents the disassembler's extra modes.
+    type ExtraMode: Copy + Into<ExtraMode>;
+
+    /// Type that represents the disassembler's syntax specifier.
+    type Syntax: Copy + Into<Syntax>;
+
+    /// Type that represents the registers provided by the architecture.
+    type RegId: Copy + From<RegId> + Into<RegId>;
+
+    /// Type that represents the instruction IDs provided by the architecture.
+    type InsnId: Copy + Into<InsnId>;
+
+    /// Type that represents the instruction group IDs provided by the architecture.
+    type InsnGroupId: Copy + From<InsnGroupId> + Into<InsnGroupId>;
+
+    /// Type that provides detailed information about an instruction under the architecture.
+    type InsnDetail<'a>: DetailsArchInsn + for<'i> From<&'i InsnDetail<'a, Self>>;
+
+    /// Determine whether the given [`Arch`] value is supported by this arch tag.
+    fn support_arch(arch: Arch) -> bool;
+}
+
+/// An architecture tag that indicates the architecture is unknown at compile-time.
+pub struct DynamicArchTag;
+
+impl internal::ArchTagSealed for DynamicArchTag {}
+
+impl ArchTag for DynamicArchTag {
+    type Builder = CapstoneBuilder;
+
+    type Mode = Mode;
+    type ExtraMode = ExtraMode;
+    type Syntax = Syntax;
+
+    type RegId = RegId;
+    type InsnId = InsnId;
+    type InsnGroupId = InsnGroupId;
+
+    type InsnDetail<'a> = ArchInsnDetail<'a>;
+
+    fn support_arch(_: Arch) -> bool {
+        true
+    }
+}
+
 /// Builds a `Capstone` struct
-pub trait BuildsCapstone<ArchMode> {
+pub trait BuildsCapstone<A: ArchTag> {
     /// Set the disassembly mode
-    fn mode(self, mode: ArchMode) -> Self;
+    fn mode(self, mode: A::Mode) -> Self;
 
     /// Enable detailed output
     fn detail(self, enable_detail: bool) -> Self;
 
     /// Get final `Capstone`
-    fn build(self) -> CsResult<Capstone>;
+    fn build(self) -> CsResult<Capstone<A>>;
 }
 
 /// Implies that a `CapstoneBuilder` architecture has extra modes
-pub trait BuildsCapstoneExtraMode<ArchMode, ArchExtraMode>: BuildsCapstone<ArchMode> {
+pub trait BuildsCapstoneExtraMode<A: ArchTag>: BuildsCapstone<A> {
     /// Set architecture endianness
-    fn extra_mode<T: Iterator<Item = ArchExtraMode>>(self, extra_mode: T) -> Self;
+    fn extra_mode<T: Iterator<Item = A::ExtraMode>>(self, extra_mode: T) -> Self;
 }
 
 /// Implies that a `CapstoneBuilder` has different syntax options
-pub trait BuildsCapstoneSyntax<ArchMode, ArchSyntax>: BuildsCapstone<ArchMode> {
+pub trait BuildsCapstoneSyntax<A: ArchTag>: BuildsCapstone<A> {
     /// Set the disassembly syntax
-    fn syntax(self, syntax: ArchSyntax) -> Self;
+    fn syntax(self, syntax: A::Syntax) -> Self;
 }
 
 /// Implies that a `CapstoneBuilder` architecture has a configurable endianness
-pub trait BuildsCapstoneEndian<ArchMode>: BuildsCapstone<ArchMode> {
+pub trait BuildsCapstoneEndian<A: ArchTag>: BuildsCapstone<A> {
     /// Set architecture endianness
     fn endian(self, endian: Endian) -> Self;
 }
@@ -394,16 +445,82 @@ pub(crate) mod arch_builder {
 }
 
 /// Builds `Capstone` object
-#[derive(Debug)]
-pub struct CapstoneBuilder(
-    /// Hidden field to prevent users from instantiating `CapstoneBuilder`
-    PhantomData<()>,
-);
+#[derive(Debug, Default)]
+pub struct CapstoneBuilder {
+    arch: Option<Arch>,
+    mode: Option<Mode>,
+    is_detail: bool,
+    extra_mode: Vec<ExtraMode>,
+    syntax: Option<Syntax>,
+    endian: Option<Endian>,
+}
 
 impl CapstoneBuilder {
-    /// Create a `CapstoneBuilder`
-    pub(crate) fn new() -> Self {
-        CapstoneBuilder(PhantomData)
+    /// Set the capstone architecture.
+    ///
+    /// This function must be called before the `build` function is called.
+    pub fn arch(mut self, arch: Arch) -> Self {
+        self.arch = Some(arch);
+        self
+    }
+}
+
+impl BuildsCapstone<DynamicArchTag> for CapstoneBuilder {
+    fn mode(mut self, mode: Mode) -> Self {
+        self.mode = Some(mode);
+        self
+    }
+
+    fn detail(mut self, enable_detail: bool) -> Self {
+        self.is_detail = enable_detail;
+        self
+    }
+
+    fn build(self) -> CsResult<Capstone<DynamicArchTag>> {
+        let arch = self
+            .arch
+            .ok_or_else(|| Error::CustomError("Must specify arch with `arch()` method"))?;
+        let mode = self
+            .mode
+            .ok_or_else(|| Error::CustomError("Must specify mode with `mode()` method"))?;
+
+        let mut capstone = Capstone::new_raw(
+            arch,
+            mode.into(),
+            self.extra_mode.iter().copied().map(|x| x.into()),
+            self.endian,
+        )?;
+
+        if let Some(syntax) = self.syntax {
+            capstone.set_syntax(syntax)?;
+        }
+        if self.is_detail {
+            capstone.set_detail(self.is_detail)?;
+        }
+
+        Ok(capstone)
+    }
+}
+
+impl BuildsCapstoneEndian<DynamicArchTag> for CapstoneBuilder {
+    fn endian(mut self, endian: Endian) -> Self {
+        self.endian = Some(endian);
+        self
+    }
+}
+
+impl BuildsCapstoneExtraMode<DynamicArchTag> for CapstoneBuilder {
+    fn extra_mode<T: Iterator<Item = ExtraMode>>(mut self, extra_mode: T) -> Self {
+        self.extra_mode.clear();
+        self.extra_mode.extend(extra_mode);
+        self
+    }
+}
+
+impl BuildsCapstoneSyntax<DynamicArchTag> for CapstoneBuilder {
+    fn syntax(mut self, syntax: Syntax) -> Self {
+        self.syntax = Some(syntax);
+        self
     }
 }
 
@@ -454,6 +571,7 @@ macro_rules! detail_arch_base {
                 detail = ArmDetail,
                 insn_detail = ArmInsnDetail<'a>,
                 op = ArmOperand,
+                op_iter = ArmOperandIterator,
                 /// Returns the ARM details, if any
                 => arch_name = arm,
             ]
@@ -461,6 +579,7 @@ macro_rules! detail_arch_base {
                 detail = Arm64Detail,
                 insn_detail = Arm64InsnDetail<'a>,
                 op = Arm64Operand,
+                op_iter = Arm64OperandIterator,
                 /// Returns the ARM64 details, if any
                 => arch_name = arm64,
             ]
@@ -468,6 +587,7 @@ macro_rules! detail_arch_base {
                 detail = EvmDetail,
                 insn_detail = EvmInsnDetail<'a>,
                 op = EvmOperand,
+                op_iter = EvmOperandIterator,
                 /// Returns the EVM details, if any
                 => arch_name = evm,
             ]
@@ -475,6 +595,7 @@ macro_rules! detail_arch_base {
                 detail = M680xDetail,
                 insn_detail = M680xInsnDetail<'a>,
                 op = M680xOperand,
+                op_iter = M680xOperandIterator,
                 /// Returns the M680X details, if any
                 => arch_name = m680x,
             ]
@@ -482,6 +603,7 @@ macro_rules! detail_arch_base {
                 detail = M68kDetail,
                 insn_detail = M68kInsnDetail<'a>,
                 op = M68kOperand,
+                op_iter = M68kOperandIterator,
                 /// Returns the M68K details, if any
                 => arch_name = m68k,
             ]
@@ -489,6 +611,7 @@ macro_rules! detail_arch_base {
                 detail = MipsDetail,
                 insn_detail = MipsInsnDetail<'a>,
                 op = MipsOperand,
+                op_iter = MipsOperandIterator,
                 /// Returns the MIPS details, if any
                 => arch_name = mips,
             ]
@@ -496,6 +619,7 @@ macro_rules! detail_arch_base {
                 detail = PpcDetail,
                 insn_detail = PpcInsnDetail<'a>,
                 op = PpcOperand,
+                op_iter = PpcOperandIterator,
                 /// Returns the PPC details, if any
                 => arch_name = ppc,
             ]
@@ -503,6 +627,7 @@ macro_rules! detail_arch_base {
                 detail = RiscVDetail,
                 insn_detail = RiscVInsnDetail<'a>,
                 op = RiscVOperand,
+                op_iter = RiscVOperandIterator,
                 /// Returns the RISCV details, if any
                 => arch_name = riscv,
             ]
@@ -510,13 +635,23 @@ macro_rules! detail_arch_base {
                 detail = SparcDetail,
                 insn_detail = SparcInsnDetail<'a>,
                 op = SparcOperand,
+                op_iter = SparcOperandIterator,
                 /// Returns the SPARC details, if any
                 => arch_name = sparc,
             ]
+            [
+                detail = SyszDetail,
+                insn_detail = SyszInsnDetail<'a>,
+                op = SyszOperand,
+                op_iter = SyszOperandIterator,
+                /// Returns the Sysz details, if any
+                => arch_name = sysz,
+            ]
             [
                 detail = Tms320c64xDetail,
                 insn_detail = Tms320c64xInsnDetail<'a>,
                 op = Tms320c64xOperand,
+                op_iter = Tms320c64xOperandIterator,
                 /// Returns the Tms320c64x details, if any
                 => arch_name = tms320c64x,
             ]
@@ -524,6 +659,7 @@ macro_rules! detail_arch_base {
                 detail = X86Detail,
                 insn_detail = X86InsnDetail<'a>,
                 op = X86Operand,
+                op_iter = X86OperandIterator,
                 /// Returns the X86 details, if any
                 => arch_name = x86,
             ]
@@ -531,6 +667,7 @@ macro_rules! detail_arch_base {
                 detail = XcoreDetail,
                 insn_detail = XcoreInsnDetail<'a>,
                 op = XcoreOperand,
+                op_iter = XcoreOperandIterator,
                 /// Returns the XCore details, if any
                 => arch_name = xcore,
             ]
@@ -538,13 +675,14 @@ macro_rules! detail_arch_base {
     };
 }
 
-/// Define ArchDetail enum, ArchOperand enum, and From<$Operand> for ArchOperand
+/// Define ArchInsnDetail enum, ArchOperand enum, ArchOperandIterator enum, and From<$Operand> for ArchOperand
 macro_rules! detail_defs {
     (
         $( [
             detail = $Detail:tt,
             insn_detail = $InsnDetail:ty,
             op = $Operand:tt,
+            op_iter = $OperandIter:tt,
             $( #[$func_attr:meta] )+
             => arch_name = $arch_name:ident,
         ] )+
@@ -558,36 +696,28 @@ macro_rules! detail_defs {
         /// For convenience, there are methods for each architecture that return an `Option` of that
         /// architecture's detail structure. This allows you to use an `if let Some(...) = { /* ... */ }`
         /// instead of a match statement.
-        #[derive(Debug)]
-        pub enum ArchDetail<'a> {
+        #[derive(Debug, PartialEq)]
+        pub enum ArchInsnDetail<'a> {
             $( $Detail($InsnDetail), )+
         }
 
         /// Architecture-independent enum of operands
         #[derive(Clone, Debug, PartialEq)]
         pub enum ArchOperand {
+            Invalid,
             $( $Operand($Operand), )+
         }
 
-        impl<'a> ArchDetail<'a> {
-            /// Returns architecture independent set of operands
-            pub fn operands(&'a self) -> Vec<ArchOperand> {
-                match *self {
-                    $(
-                        ArchDetail::$Detail(ref detail) => {
-                            let ops = detail.operands();
-                            let map = ops.map(ArchOperand::from);
-                            let vec: Vec<ArchOperand> = map.collect();
-                            vec
-                        }
-                    )+
-                }
-            }
+        /// Iterate arch-specific operands of an instruction.
+        pub enum ArchOperandIterator<'a> {
+            $( $OperandIter($OperandIter<'a>), )+
+        }
 
+        impl<'a> ArchInsnDetail<'a> {
             $(
                 $( #[$func_attr] )+
                 pub fn $arch_name(&'a self) -> Option<& $InsnDetail> {
-                    if let ArchDetail::$Detail(ref arch_detail) = *self {
+                    if let ArchInsnDetail::$Detail(ref arch_detail) = *self {
                         Some(arch_detail)
                     } else {
                         None
@@ -596,6 +726,20 @@ macro_rules! detail_defs {
             )+
         }
 
+        $(
+            impl<'a> From<$InsnDetail> for ArchInsnDetail<'a> {
+                fn from(insn_detail: $InsnDetail) -> Self {
+                    Self::$Detail(insn_detail)
+                }
+            }
+        )+
+
+        impl Default for ArchOperand {
+            fn default() -> Self {
+                Self::Invalid
+            }
+        }
+
         $(
             impl From<$Operand> for ArchOperand {
                 fn from(op: $Operand) -> ArchOperand {
@@ -603,6 +747,65 @@ macro_rules! detail_defs {
                 }
             }
         )+
+
+        impl<'a> Iterator for ArchOperandIterator<'a> {
+            type Item = ArchOperand;
+
+            fn next(&mut self) -> Option<Self::Item> {
+                match self {
+                    $(
+                        Self::$OperandIter( op_iter ) => op_iter.next().map(From::from),
+                    )+
+                }
+            }
+        }
+
+        impl<'a> DetailsArchInsn for ArchInsnDetail<'a> {
+            type Operand = ArchOperand;
+            type OperandIterator = ArchOperandIterator<'a>;
+
+            fn operands(&self) -> Self::OperandIterator {
+                todo!()
+            }
+        }
+    }
+}
+
+impl<'a, 'i> From<&'i InsnDetail<'a, DynamicArchTag>> for ArchInsnDetail<'a> {
+    fn from(insn_detail: &'i InsnDetail<'a, DynamicArchTag>) -> Self {
+        macro_rules! def_arch_detail_match {
+            (
+                $( [ $ARCH:ident, $detail:ident, $insn_detail:ident, $arch:ident ] )*
+            ) => {
+                use self::ArchInsnDetail::*;
+                use crate::Arch::*;
+                $( use crate::arch::$arch::$insn_detail; )*
+
+                return match insn_detail.1 {
+                    $(
+                        $ARCH => {
+                            $detail($insn_detail(unsafe { &insn_detail.0.__bindgen_anon_1.$arch }))
+                        }
+                    )*
+                    _ => panic!("Unsupported detail arch"),
+                }
+            }
+        }
+
+        def_arch_detail_match!(
+            [ARM, ArmDetail, ArmInsnDetail, arm]
+            [ARM64, Arm64Detail, Arm64InsnDetail, arm64]
+            [EVM, EvmDetail, EvmInsnDetail, evm]
+            [M680X, M680xDetail, M680xInsnDetail, m680x]
+            [M68K, M68kDetail, M68kInsnDetail, m68k]
+            [MIPS, MipsDetail, MipsInsnDetail, mips]
+            [PPC, PpcDetail, PpcInsnDetail, ppc]
+            [RISCV, RiscVDetail, RiscVInsnDetail, riscv]
+            [SPARC, SparcDetail, SparcInsnDetail, sparc]
+            [TMS320C64X, Tms320c64xDetail, Tms320c64xInsnDetail, tms320c64x]
+            [X86, X86Detail, X86InsnDetail, x86]
+            [XCORE, XcoreDetail, XcoreInsnDetail, xcore]
+        );
     }
 }
 
@@ -654,13 +857,13 @@ macro_rules! def_arch_details_struct {
         }
 
         impl<'a> ::core::fmt::Debug for $OperandIteratorLife {
-            fn fmt(&self, fmt: &mut fmt::Formatter) -> ::core::fmt::Result {
+            fn fmt(&self, fmt: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
                 fmt.debug_struct(stringify!($OperandIterator)).finish()
             }
         }
 
         impl<'a> ::core::fmt::Debug for $InsnDetail<'a> {
-            fn fmt(&self, fmt: &mut fmt::Formatter) -> ::core::fmt::Result {
+            fn fmt(&self, fmt: &mut ::core::fmt::Formatter) -> ::core::fmt::Result {
                 fmt.debug_struct(stringify!($InsnDetail))
                     .field(stringify!($cs_arch), &(self.0 as *const $cs_arch))
                     .finish()
@@ -684,7 +887,7 @@ detail_arch_base!(detail_defs);
 macro_rules! define_arch_mods {
     (
         $( [
-            ( $arch:ident, $arch_variant:ident )
+            ( $arch:ident, $arch_variant:ident, $arch_tag:ident )
             ( mode: $( $mode:ident, )+ )
             ( extra_modes: $( $extra_mode:ident, )* )
             ( syntax: $( $syntax:ident, )* )
diff --git a/capstone-rs/src/arch/ppc.rs b/capstone-rs/src/arch/ppc.rs
index ae4c9a08..7708c924 100644
--- a/capstone-rs/src/arch/ppc.rs
+++ b/capstone-rs/src/arch/ppc.rs
@@ -1,7 +1,6 @@
 //! Contains ppc-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 // XXX todo(tmfink): create rusty versions
 pub use capstone_sys::ppc_insn_group as PpcInsnGroup;
@@ -12,8 +11,33 @@ pub use capstone_sys::ppc_bh as PpcBh;
 use capstone_sys::{cs_ppc, cs_ppc_op, ppc_op_mem, ppc_op_crx, ppc_op_type};
 
 pub use crate::arch::arch_builder::ppc::*;
-use crate::arch::DetailsArchInsn;
-use crate::instruction::{RegId, RegIdInt};
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
+use crate::instruction::RegId;
+use crate::{Arch, InsnDetail};
+
+/// Architecture tag that represents PPC.
+pub struct PpcArchTag;
+
+impl ArchTagSealed for PpcArchTag {}
+
+impl ArchTag for PpcArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = PpcReg;
+    type InsnId = PpcInsn;
+    type InsnGroupId = PpcInsnGroup;
+
+    type InsnDetail<'a> = PpcInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::PPC
+    }
+}
 
 /// Contains PPC-specific details for an instruction
 pub struct PpcInsnDetail<'a>(pub(crate) &'a cs_ppc);
@@ -39,6 +63,12 @@ impl_PartialEq_repr_fields!(PpcInsnDetail<'a> [ 'a ];
     bc, bh, update_cr0, operands
 );
 
+impl<'a, 'i> From<&'i InsnDetail<'a, PpcArchTag>> for PpcInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, PpcArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.ppc })
+    }
+}
+
 /// PPC operand
 #[derive(Clone, Debug, Eq, PartialEq)]
 pub enum PpcOperand {
@@ -71,7 +101,7 @@ pub struct PpcOpMem(pub(crate) ppc_op_mem);
 impl PpcOpMem {
     /// Base register
     pub fn base(&self) -> RegId {
-        RegId(self.0.base as RegIdInt)
+        self.0.base.into()
     }
 
     /// Disp value
@@ -84,7 +114,7 @@ impl_PartialEq_repr_fields!(PpcOpMem;
     base, disp
 );
 
-impl cmp::Eq for PpcOpMem {}
+impl Eq for PpcOpMem {}
 
 /// PPC condition register field
 #[derive(Debug, Copy, Clone)]
@@ -98,7 +128,7 @@ impl PpcOpCrx {
 
     /// Register value
     pub fn reg(&self) -> RegId {
-        RegId(self.0.reg as RegIdInt)
+        self.0.reg.into()
     }
 
     /// Condition value
@@ -107,19 +137,19 @@ impl PpcOpCrx {
     }
 }
 
-impl cmp::PartialEq for PpcOpCrx {
+impl PartialEq for PpcOpCrx {
     fn eq(&self, other: &Self) -> bool {
         (self.scale(), self.reg(), self.cond()) == (other.scale(), other.reg(), other.cond())
     }
 }
 
-impl cmp::Eq for PpcOpCrx {}
+impl Eq for PpcOpCrx {}
 
 impl<'a> From<&'a cs_ppc_op> for PpcOperand {
     fn from(insn: &cs_ppc_op) -> PpcOperand {
         match insn.type_ {
             ppc_op_type::PPC_OP_REG => {
-                PpcOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+                PpcOperand::Reg(unsafe { insn.__bindgen_anon_1.reg.into() })
             }
             ppc_op_type::PPC_OP_IMM => PpcOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
             ppc_op_type::PPC_OP_MEM => {
@@ -138,7 +168,7 @@ def_arch_details_struct!(
     Operand = PpcOperand;
     OperandIterator = PpcOperandIterator;
     OperandIteratorLife = PpcOperandIterator<'a>;
-    [ pub struct PpcOperandIterator<'a>(slice::Iter<'a, cs_ppc_op>); ]
+    [ pub struct PpcOperandIterator<'a>(core::slice::Iter<'a, cs_ppc_op>); ]
     cs_arch_op = cs_ppc_op;
     cs_arch = cs_ppc;
 );
@@ -152,7 +182,6 @@ mod test {
         use capstone_sys::*;
         use super::ppc_op_type::*;
         use super::PpcBc::*;
-        use super::PpcReg::*;
         use self::PpcOperand::*;
 
         fn t(
@@ -167,11 +196,11 @@ mod test {
         }
 
         t(
-            (PPC_OP_INVALID, cs_ppc_op__bindgen_ty_1 { reg: 0 }),
+            (PPC_OP_INVALID, cs_ppc_op__bindgen_ty_1 { reg: PpcReg(0) }),
             Invalid,
         );
         t(
-            (PPC_OP_REG, cs_ppc_op__bindgen_ty_1 { reg: 0 }),
+            (PPC_OP_REG, cs_ppc_op__bindgen_ty_1 { reg: PpcReg(0) }),
             Reg(RegId(0)),
         );
         t(
@@ -179,7 +208,7 @@ mod test {
             Imm(42),
         );
 
-        let crx = ppc_op_crx { scale: 0, reg: PPC_REG_R0, cond: PPC_BC_LT };
+        let crx = ppc_op_crx { scale: 0, reg: PpcReg::PPC_REG_R0, cond: PPC_BC_LT };
         t(
             (PPC_OP_CRX, cs_ppc_op__bindgen_ty_1 { crx }),
             Crx(PpcOpCrx(crx)),
@@ -188,13 +217,13 @@ mod test {
         let op_mem = PpcOperand::from(&cs_ppc_op {
             type_: PPC_OP_MEM,
             __bindgen_anon_1: cs_ppc_op__bindgen_ty_1 { mem: ppc_op_mem {
-                base: PPC_REG_VS38,
+                base: PpcReg::PPC_REG_VS38,
                 disp: -10 }}
         });
         if let Mem(op_mem) = op_mem {
             assert_eq!(
                 (op_mem.base(), op_mem.disp()),
-                (RegId(PPC_REG_VS38 as RegIdInt), -10)
+                (PpcReg::PPC_REG_VS38.into(), -10)
             );
         } else {
             panic!("Did not get expected Mem");
diff --git a/capstone-rs/src/arch/riscv.rs b/capstone-rs/src/arch/riscv.rs
index 72d814a4..1dd346ec 100644
--- a/capstone-rs/src/arch/riscv.rs
+++ b/capstone-rs/src/arch/riscv.rs
@@ -1,7 +1,6 @@
 //! Contains riscv-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 // XXX todo(tmfink): create rusty versions
 pub use capstone_sys::riscv_insn_group as RiscVInsnGroup;
@@ -10,8 +9,33 @@ pub use capstone_sys::riscv_reg as RiscVReg;
 use capstone_sys::{cs_riscv, cs_riscv_op, riscv_op_mem, riscv_op_type};
 
 pub use crate::arch::arch_builder::riscv::*;
-use crate::arch::DetailsArchInsn;
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
 use crate::instruction::{RegId, RegIdInt};
+use crate::{Arch, InsnDetail};
+
+/// Architecture tag that represents RISC-V.
+pub struct RiscVArchTag;
+
+impl ArchTagSealed for RiscVArchTag {}
+
+impl ArchTag for RiscVArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = RiscVReg;
+    type InsnId = RiscVInsn;
+    type InsnGroupId = RiscVInsnGroup;
+
+    type InsnDetail<'a> = RiscVInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::RISCV
+    }
+}
 
 /// Contains RISCV-specific details for an instruction
 pub struct RiscVInsnDetail<'a>(pub(crate) &'a cs_riscv);
@@ -20,6 +44,12 @@ impl_PartialEq_repr_fields!(RiscVInsnDetail<'a> [ 'a ];
     operands
 );
 
+impl<'a, 'i> From<&'i InsnDetail<'a, RiscVArchTag>> for RiscVInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, RiscVArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.riscv })
+    }
+}
+
 /// RISCV operand
 #[derive(Clone, Debug, Eq, PartialEq)]
 pub enum RiscVOperand {
@@ -62,7 +92,7 @@ impl_PartialEq_repr_fields!(RiscVOpMem;
     base, disp
 );
 
-impl cmp::Eq for RiscVOpMem {}
+impl Eq for RiscVOpMem {}
 
 impl<'a> From<&'a cs_riscv_op> for RiscVOperand {
     fn from(insn: &cs_riscv_op) -> RiscVOperand {
@@ -84,7 +114,7 @@ def_arch_details_struct!(
     Operand = RiscVOperand;
     OperandIterator = RiscVOperandIterator;
     OperandIteratorLife = RiscVOperandIterator<'a>;
-    [ pub struct RiscVOperandIterator<'a>(slice::Iter<'a, cs_riscv_op>); ]
+    [ pub struct RiscVOperandIterator<'a>(core::slice::Iter<'a, cs_riscv_op>); ]
     cs_arch_op = cs_riscv_op;
     cs_arch = cs_riscv;
 );
diff --git a/capstone-rs/src/arch/sparc.rs b/capstone-rs/src/arch/sparc.rs
index 10b35d8f..dfee9914 100644
--- a/capstone-rs/src/arch/sparc.rs
+++ b/capstone-rs/src/arch/sparc.rs
@@ -1,7 +1,6 @@
 //! Contains sparc-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 // XXX todo(tmfink): create rusty versions
 pub use capstone_sys::sparc_insn_group as SparcInsnGroup;
@@ -12,13 +11,43 @@ pub use capstone_sys::sparc_hint as SparcHint;
 use capstone_sys::{cs_sparc, cs_sparc_op, sparc_op_mem, sparc_op_type};
 
 pub use crate::arch::arch_builder::sparc::*;
-use crate::arch::DetailsArchInsn;
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
 use crate::instruction::{RegId, RegIdInt};
+use crate::{Arch, InsnDetail};
 
+/// Architecture tag that represents Sparc.
+pub struct SparcArchTag;
+
+impl ArchTagSealed for SparcArchTag {}
+
+impl ArchTag for SparcArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = SparcReg;
+    type InsnId = SparcInsn;
+    type InsnGroupId = SparcInsnGroup;
+
+    type InsnDetail<'a> = SparcInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::SPARC
+    }
+}
 
 /// Contains SPARC-specific details for an instruction
 pub struct SparcInsnDetail<'a>(pub(crate) &'a cs_sparc);
 
+impl<'a, 'i> From<&'i InsnDetail<'a, SparcArchTag>> for SparcInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, SparcArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.sparc })
+    }
+}
+
 /// SPARC operand
 #[derive(Clone, Debug, Eq, PartialEq)]
 pub enum SparcOperand {
@@ -82,13 +111,13 @@ impl_PartialEq_repr_fields!(SparcOpMem;
     base, index, disp
 );
 
-impl cmp::Eq for SparcOpMem {}
+impl Eq for SparcOpMem {}
 
 impl<'a> From<&'a cs_sparc_op> for SparcOperand {
     fn from(insn: &cs_sparc_op) -> SparcOperand {
         match insn.type_ {
             sparc_op_type::SPARC_OP_REG => {
-                SparcOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+                SparcOperand::Reg(unsafe { insn.__bindgen_anon_1.reg.into() })
             }
             sparc_op_type::SPARC_OP_IMM => SparcOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
             sparc_op_type::SPARC_OP_MEM => {
@@ -104,7 +133,7 @@ def_arch_details_struct!(
     Operand = SparcOperand;
     OperandIterator = SparcOperandIterator;
     OperandIteratorLife = SparcOperandIterator<'a>;
-    [ pub struct SparcOperandIterator<'a>(slice::Iter<'a, cs_sparc_op>); ]
+    [ pub struct SparcOperandIterator<'a>(core::slice::Iter<'a, cs_sparc_op>); ]
     cs_arch_op = cs_sparc_op;
     cs_arch = cs_sparc;
 );
diff --git a/capstone-rs/src/arch/sysz.rs b/capstone-rs/src/arch/sysz.rs
index bdbb13cc..ffeeb896 100644
--- a/capstone-rs/src/arch/sysz.rs
+++ b/capstone-rs/src/arch/sysz.rs
@@ -1,3 +1,119 @@
 //! Contains sysz-specific types
 
+use capstone_sys::{cs_sysz, cs_sysz_op, sysz_op_mem, sysz_op_type};
+
+pub use capstone_sys::sysz_cc as SyszCC;
+pub use capstone_sys::sysz_insn as SyszInsn;
+pub use capstone_sys::sysz_insn_group as SyszInsnGroup;
+pub use capstone_sys::sysz_reg as SyszReg;
+
 pub use crate::arch::arch_builder::sysz::*;
+use crate::arch::internal::ArchTagSealed;
+use crate::arch::ArchTag;
+use crate::{Arch, InsnDetail};
+
+use super::DetailsArchInsn;
+
+/// Architecture tag that represents Sysz.
+pub struct SyszArchTag;
+
+impl ArchTagSealed for SyszArchTag {}
+
+impl ArchTag for SyszArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = SyszReg;
+    type InsnId = SyszInsn;
+    type InsnGroupId = SyszInsnGroup;
+
+    type InsnDetail<'a> = SyszInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::SYSZ
+    }
+}
+
+/// Contains sysz-specific details for an instruction
+pub struct SyszInsnDetail<'a>(pub(crate) &'a cs_sysz);
+
+impl<'a> SyszInsnDetail<'a> {
+    pub fn cc(&self) -> SyszCC {
+        self.0.cc
+    }
+
+    pub fn op_count(&self) -> u8 {
+        self.0.op_count
+    }
+}
+
+impl<'a, 'i> From<&'i InsnDetail<'a, SyszArchTag>> for SyszInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, SyszArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.sysz })
+    }
+}
+
+impl_PartialEq_repr_fields!(SyszInsnDetail<'a> [ 'a ];
+    cc, op_count, operands
+);
+
+#[derive(Clone, Debug, PartialEq)]
+pub enum SyszOperand {
+    Invalid,
+    Reg(SyszReg),
+    Imm(i64),
+    Mem(SyszMemOp),
+    AcReg,
+}
+
+impl Default for SyszOperand {
+    fn default() -> Self {
+        Self::Invalid
+    }
+}
+
+impl<'a> From<&'a cs_sysz_op> for SyszOperand {
+    fn from(value: &'a cs_sysz_op) -> Self {
+        use sysz_op_type::*;
+
+        match value.type_ {
+            SYSZ_OP_INVALID => Self::Invalid,
+            SYSZ_OP_REG => Self::Reg(unsafe { value.__bindgen_anon_1.reg.into() }),
+            SYSZ_OP_IMM => Self::Imm(unsafe { value.__bindgen_anon_1.imm }),
+            SYSZ_OP_MEM => Self::Mem(unsafe { value.__bindgen_anon_1.mem.into() }),
+            SYSZ_OP_ACREG => Self::AcReg,
+        }
+    }
+}
+
+#[derive(Clone, Debug, PartialEq)]
+pub struct SyszMemOp {
+    pub base: u8,
+    pub index: u8,
+    pub length: u64,
+    pub disp: i64,
+}
+
+impl From<sysz_op_mem> for SyszMemOp {
+    fn from(value: sysz_op_mem) -> Self {
+        Self {
+            base: value.base,
+            index: value.index,
+            length: value.length,
+            disp: value.disp,
+        }
+    }
+}
+
+def_arch_details_struct!(
+    InsnDetail = SyszInsnDetail;
+    Operand = SyszOperand;
+    OperandIterator = SyszOperandIterator;
+    OperandIteratorLife = SyszOperandIterator<'a>;
+    [ pub struct SyszOperandIterator<'a>(core::slice::Iter<'a, cs_sysz_op>); ]
+    cs_arch_op = cs_sysz_op;
+    cs_arch = cs_sysz;
+);
diff --git a/capstone-rs/src/arch/tms320c64x.rs b/capstone-rs/src/arch/tms320c64x.rs
index 08512468..0cc00ecc 100644
--- a/capstone-rs/src/arch/tms320c64x.rs
+++ b/capstone-rs/src/arch/tms320c64x.rs
@@ -1,7 +1,6 @@
 //! Contains tms320c64x-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 use libc::c_int;
 use capstone_sys::{
@@ -15,12 +14,43 @@ pub use capstone_sys::tms320c64x_insn_group as Tms320c64xInsnGroup;
 pub use capstone_sys::tms320c64x_reg as Tms320c64xReg;
 
 pub use crate::arch::arch_builder::tms320c64x::*;
+use crate::arch::ArchTag;
+use crate::arch::internal::ArchTagSealed;
 use crate::instruction::{RegId, RegIdInt};
+use crate::{Arch, InsnDetail};
 
+/// Architecture tag that represents TMS320C64X.
+pub struct Tms320c64xArchTag;
+
+impl ArchTagSealed for Tms320c64xArchTag {}
+
+impl ArchTag for Tms320c64xArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = Tms320c64xReg;
+    type InsnId = Tms320c64xInsn;
+    type InsnGroupId = Tms320c64xInsnGroup;
+
+    type InsnDetail<'a> = Tms320c64xInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::TMS320C64X
+    }
+}
 
 /// Contains TMS320C64X-specific details for an instruction
 pub struct Tms320c64xInsnDetail<'a>(pub(crate) &'a cs_tms320c64x);
 
+impl<'a, 'i> From<&'i InsnDetail<'a, Tms320c64xArchTag>> for Tms320c64xInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, Tms320c64xArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.tms320c64x })
+    }
+}
+
 define_cs_enum_wrapper_reverse!(
     [
         /// TMS320C64X Functional Unit
@@ -218,7 +248,7 @@ impl_PartialEq_repr_fields!(Tms320c64xOpMem;
     base, disp, unit, scaled, display_type, direction, modify
 );
 
-impl cmp::Eq for Tms320c64xOpMem {}
+impl Eq for Tms320c64xOpMem {}
 
 impl<'a> From<&'a cs_tms320c64x_op> for Tms320c64xOperand {
     fn from(insn: &cs_tms320c64x_op) -> Tms320c64xOperand {
@@ -247,7 +277,7 @@ def_arch_details_struct!(
     Operand = Tms320c64xOperand;
     OperandIterator = Tms320c64xOperandIterator;
     OperandIteratorLife = Tms320c64xOperandIterator<'a>;
-    [ pub struct Tms320c64xOperandIterator<'a>(slice::Iter<'a, cs_tms320c64x_op>); ]
+    [ pub struct Tms320c64xOperandIterator<'a>(core::slice::Iter<'a, cs_tms320c64x_op>); ]
     cs_arch_op = cs_tms320c64x_op;
     cs_arch = cs_tms320c64x;
 );
@@ -278,7 +308,7 @@ mod test {
             op_count: 0,
             operands: [op; 8],
             condition: cs_tms320c64x__bindgen_ty_1 {
-                reg: tms320c64x_reg::TMS320C64X_REG_GPLYA as c_uint,
+                reg: tms320c64x_reg::TMS320C64X_REG_GPLYA.0,
                 zero: 1,
             },
             funit: cs_tms320c64x__bindgen_ty_2 {
@@ -293,7 +323,7 @@ mod test {
         assert!(d.is_condition_zero());
         assert_eq!(
             d.condition_reg(),
-            RegId(Tms320c64xReg::TMS320C64X_REG_GPLYA as RegIdInt)
+            Tms320c64xReg::TMS320C64X_REG_GPLYA.into()
         );
         assert_eq!(d.functional_unit(), Tms320c64xFuntionalUnit::L);
         assert_eq!(d.functional_unit_side(), 18);
@@ -340,21 +370,21 @@ mod test {
         assert_eq!(
             Tms320c64xOpMem(tms320c64x_op_mem {
                 disptype: tms320c64x_mem_disp::TMS320C64X_MEM_DISP_REGISTER as c_uint,
-                disp: tms320c64x_reg::TMS320C64X_REG_A13 as c_uint,
+                disp: tms320c64x_reg::TMS320C64X_REG_A13.0,
                 ..OP_MEM_ZERO
             })
             .display(),
-            Tms320c64xMemDisplay::Register(RegId(Tms320c64xReg::TMS320C64X_REG_A13 as RegIdInt))
+            Tms320c64xMemDisplay::Register(Tms320c64xReg::TMS320C64X_REG_A13.into())
         );
 
         // Simple getters
         assert_eq!(
             Tms320c64xOpMem(tms320c64x_op_mem {
-                base: tms320c64x_reg::TMS320C64X_REG_A13 as c_uint,
+                base: tms320c64x_reg::TMS320C64X_REG_A13.0,
                 ..OP_MEM_ZERO
             })
             .base(),
-            RegId(Tms320c64xReg::TMS320C64X_REG_A13 as RegIdInt)
+            Tms320c64xReg::TMS320C64X_REG_A13.into()
         );
         assert_eq!(
             Tms320c64xOpMem(tms320c64x_op_mem {
diff --git a/capstone-rs/src/arch/x86.rs b/capstone-rs/src/arch/x86.rs
index e96ef03c..d8f1f455 100644
--- a/capstone-rs/src/arch/x86.rs
+++ b/capstone-rs/src/arch/x86.rs
@@ -2,7 +2,6 @@
 
 use core::convert::From;
 use core::convert::TryInto;
-use core::{cmp, fmt, slice};
 
 use capstone_sys::{
     cs_ac_type, cs_x86, cs_x86_op, cs_x86_op__bindgen_ty_1, x86_op_mem, x86_op_type,
@@ -18,12 +17,43 @@ pub use capstone_sys::x86_xop_cc as X86XopCC;
 pub use capstone_sys::x86_avx_rm as X86AvxRm;
 
 pub use crate::arch::arch_builder::x86::*;
-use crate::arch::DetailsArchInsn;
-use crate::instruction::{RegAccessType, RegId, RegIdInt};
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
+use crate::instruction::{RegAccessType, RegId};
+use crate::{Arch, InsnDetail};
+
+pub struct X86ArchTag;
+
+impl ArchTagSealed for X86ArchTag {}
+
+/// Architecture that represents both x86 and x86_64.
+impl ArchTag for X86ArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = X86Reg;
+    type InsnId = X86Insn;
+    type InsnGroupId = X86InsnGroup;
+
+    type InsnDetail<'a> = X86InsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::X86
+    }
+}
 
 /// Contains X86-specific details for an instruction
 pub struct X86InsnDetail<'a>(pub(crate) &'a cs_x86);
 
+impl<'a, 'i> From<&'i InsnDetail<'a, X86ArchTag>> for X86InsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, X86ArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.x86 })
+    }
+}
+
 // todo(tmfink): expose new types cs_x86__bindgen_ty_1, cs_x86_encoding, x86_xop_cc,
 // cs_x86_op::access
 
@@ -33,7 +63,7 @@ impl X86OperandType {
         use self::X86OperandType::*;
 
         match op_type {
-            X86_OP_REG => Reg(RegId(unsafe { value.reg } as RegIdInt)),
+            X86_OP_REG => Reg(unsafe { value.reg.into() }),
             X86_OP_IMM => Imm(unsafe { value.imm }),
             X86_OP_MEM => Mem(X86OpMem(unsafe { value.mem })),
             X86_OP_INVALID => Invalid,
@@ -132,7 +162,7 @@ impl<'a> X86InsnDetail<'a> {
 
     /// Scaled Index Byte (SIB) index, or X86_REG_INVALID when irrelevant
     pub fn sib_index(&self) -> RegId {
-        RegId(self.0.sib_index as RegIdInt)
+        self.0.sib_index.into()
     }
 
     /// Scaled Index Byte (SIB) scale, or X86_REG_INVALID when irrelevant
@@ -142,7 +172,7 @@ impl<'a> X86InsnDetail<'a> {
 
     /// Scaled Index Byte (SIB) base register, or X86_REG_INVALID when irrelevant
     pub fn sib_base(&self) -> RegId {
-        RegId(self.0.sib_base as RegIdInt)
+        self.0.sib_base.into()
     }
 
     /// eXtended Operations (XOP) Code Condition
@@ -179,17 +209,17 @@ impl_PartialEq_repr_fields!(X86InsnDetail<'a> [ 'a ];
 impl X86OpMem {
     /// Segment
     pub fn segment(&self) -> RegId {
-        RegId(self.0.segment as RegIdInt)
+        self.0.segment.into()
     }
 
     /// Base register
     pub fn base(&self) -> RegId {
-        RegId(self.0.base as RegIdInt)
+        self.0.base.into()
     }
 
     /// Index register
     pub fn index(&self) -> RegId {
-        RegId(self.0.index as RegIdInt)
+        self.0.index.into()
     }
 
     /// Scale
@@ -207,7 +237,7 @@ impl_PartialEq_repr_fields!(X86OpMem;
     segment, base, index, scale, disp
 );
 
-impl cmp::Eq for X86OpMem {}
+impl Eq for X86OpMem {}
 
 impl Default for X86Operand {
     fn default() -> Self {
@@ -239,7 +269,7 @@ def_arch_details_struct!(
     Operand = X86Operand;
     OperandIterator = X86OperandIterator;
     OperandIteratorLife = X86OperandIterator<'a>;
-    [ pub struct X86OperandIterator<'a>(slice::Iter<'a, cs_x86_op>); ]
+    [ pub struct X86OperandIterator<'a>(core::slice::Iter<'a, cs_x86_op>); ]
     cs_arch_op = cs_x86_op;
     cs_arch = cs_x86;
 );
@@ -264,11 +294,11 @@ mod test {
         }
 
         t(
-            (X86_OP_INVALID, cs_x86_op__bindgen_ty_1 { reg: 0 }),
+            (X86_OP_INVALID, cs_x86_op__bindgen_ty_1 { reg: X86Reg(0) }),
             Invalid,
         );
         t(
-            (X86_OP_REG, cs_x86_op__bindgen_ty_1 { reg: 0 }),
+            (X86_OP_REG, cs_x86_op__bindgen_ty_1 { reg: X86Reg(0) }),
             Reg(RegId(0)),
         );
     }
diff --git a/capstone-rs/src/arch/xcore.rs b/capstone-rs/src/arch/xcore.rs
index f78134b1..aa237938 100644
--- a/capstone-rs/src/arch/xcore.rs
+++ b/capstone-rs/src/arch/xcore.rs
@@ -1,7 +1,6 @@
 //! Contains xcore-specific types
 
 use core::convert::From;
-use core::{cmp, fmt, slice};
 
 // XXX todo(tmfink): create rusty versions
 pub use capstone_sys::xcore_insn_group as XcoreInsnGroup;
@@ -10,8 +9,33 @@ pub use capstone_sys::xcore_reg as XcoreReg;
 use capstone_sys::{cs_xcore, cs_xcore_op, xcore_op_mem, xcore_op_type};
 
 pub use crate::arch::arch_builder::xcore::*;
-use crate::arch::DetailsArchInsn;
+use crate::arch::{ArchTag, DetailsArchInsn};
+use crate::arch::internal::ArchTagSealed;
 use crate::instruction::{RegId, RegIdInt};
+use crate::{Arch, InsnDetail};
+
+/// Architecture tag that represents Xcore.
+pub struct XcoreArchTag;
+
+impl ArchTagSealed for XcoreArchTag {}
+
+impl ArchTag for XcoreArchTag {
+    type Builder = ArchCapstoneBuilder;
+
+    type Mode = ArchMode;
+    type ExtraMode = ArchExtraMode;
+    type Syntax = ArchSyntax;
+
+    type RegId = XcoreReg;
+    type InsnId = XcoreInsn;
+    type InsnGroupId = XcoreInsnGroup;
+
+    type InsnDetail<'a> = XcoreInsnDetail<'a>;
+
+    fn support_arch(arch: Arch) -> bool {
+        arch == Arch::XCORE
+    }
+}
 
 /// Contains XCORE-specific details for an instruction
 pub struct XcoreInsnDetail<'a>(pub(crate) &'a cs_xcore);
@@ -20,6 +44,12 @@ impl_PartialEq_repr_fields!(XcoreInsnDetail<'a> [ 'a ];
     operands
 );
 
+impl<'a, 'i> From<&'i InsnDetail<'a, XcoreArchTag>> for XcoreInsnDetail<'a> {
+    fn from(value: &'i InsnDetail<'a, XcoreArchTag>) -> Self {
+        Self(unsafe { &value.0.__bindgen_anon_1.xcore })
+    }
+}
+
 /// XCORE operand
 #[derive(Clone, Debug, Eq, PartialEq)]
 pub enum XcoreOperand {
@@ -72,13 +102,13 @@ impl_PartialEq_repr_fields!(XcoreOpMem;
     base, index, disp, direct
 );
 
-impl cmp::Eq for XcoreOpMem {}
+impl Eq for XcoreOpMem {}
 
 impl<'a> From<&'a cs_xcore_op> for XcoreOperand {
     fn from(insn: &cs_xcore_op) -> XcoreOperand {
         match insn.type_ {
             xcore_op_type::XCORE_OP_REG => {
-                XcoreOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+                XcoreOperand::Reg(unsafe { insn.__bindgen_anon_1.reg.into() })
             }
             xcore_op_type::XCORE_OP_IMM => XcoreOperand::Imm(unsafe { insn.__bindgen_anon_1.imm }),
             xcore_op_type::XCORE_OP_MEM => {
@@ -94,7 +124,7 @@ def_arch_details_struct!(
     Operand = XcoreOperand;
     OperandIterator = XcoreOperandIterator;
     OperandIteratorLife = XcoreOperandIterator<'a>;
-    [ pub struct XcoreOperandIterator<'a>(slice::Iter<'a, cs_xcore_op>); ]
+    [ pub struct XcoreOperandIterator<'a>(core::slice::Iter<'a, cs_xcore_op>); ]
     cs_arch_op = cs_xcore_op;
     cs_arch = cs_xcore;
 );
diff --git a/capstone-rs/src/capstone.rs b/capstone-rs/src/capstone.rs
index f9b5df4c..00ff66a7 100644
--- a/capstone-rs/src/capstone.rs
+++ b/capstone-rs/src/capstone.rs
@@ -1,24 +1,31 @@
-use alloc::string::String;
+use alloc::string::{String, ToString};
 use core::convert::From;
+use core::fmt::{Debug, Formatter};
 use core::marker::PhantomData;
 
 use libc::{c_int, c_void};
 
-use capstone_sys::cs_opt_value::*;
 use capstone_sys::*;
 
-use crate::arch::CapstoneBuilder;
-use crate::constants::{Arch, Endian, ExtraMode, Mode, OptValue, Syntax};
+use crate::arch::ArchTag;
+use crate::constants::{Arch, Endian, ExtraMode, Mode, OptValue};
 use crate::error::*;
-use crate::instruction::{Insn, InsnDetail, InsnGroupId, InsnId, Instructions, RegId};
+use crate::ffi::str_from_cstr_ptr;
+use crate::instruction::{Insn, InsnDetail, Instructions};
 
-use {crate::ffi::str_from_cstr_ptr, alloc::string::ToString, libc::c_uint};
-
-/// An instance of the capstone disassembler
+/// An instance of the capstone disassembler.
+///
+/// The generic type parameter `A` is called the "architecture tag" and it allows you to specify the target architecture
+/// of the disassembler. For example, a Capstone disassembler that disassembles x86 and x86_64 code has the type
+/// `Capstone<X86ArchTag>`. For the full list of architecture tags, please refer to the "implementors" section of the
+/// [`ArchTag`] trait.
+///
+/// If the target architecture is unknown at compile time, you can use the special architecture tag [`DynamicArchTag`].
+///
+/// [`DynamicArchTag`]: ./arch/struct.DynamicArchTag.html
 ///
 /// Create with an instance with [`.new()`](Self::new) and disassemble bytes with [`.disasm_all()`](Self::disasm_all).
-#[derive(Debug)]
-pub struct Capstone {
+pub struct Capstone<A: ArchTag> {
     /// Opaque handle to cs_engine
     /// Stored as a pointer to ensure `Capstone` is `!Send`/`!Sync`
     csh: *mut c_void,
@@ -30,7 +37,7 @@ pub struct Capstone {
     endian: cs_mode,
 
     /// Syntax
-    syntax: cs_opt_value::Type,
+    syntax: cs_opt_value,
 
     /// Internal extra mode bitfield
     extra_mode: cs_mode,
@@ -48,6 +55,24 @@ pub struct Capstone {
 
     /// Architecture
     arch: Arch,
+
+    _arch_tag: PhantomData<A>,
+}
+
+impl<A: ArchTag> Debug for Capstone<A> {
+    fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result {
+        f.debug_struct("Capstone")
+            .field("csh", &self.csh)
+            .field("mode", &self.mode)
+            .field("endian", &self.endian)
+            .field("syntax", &self.syntax)
+            .field("extra_mode", &self.extra_mode)
+            .field("detail_enabled", &self.detail_enabled)
+            .field("skipdata_enabled", &self.skipdata_enabled)
+            .field("raw_mode", &self.raw_mode)
+            .field("arch", &self.arch)
+            .finish()
+    }
 }
 
 /// Defines a setter on `Capstone` that speculatively changes the arch-specific mode (which
@@ -100,25 +125,30 @@ impl Iterator for EmptyExtraModeIter {
     }
 }
 
-impl Capstone {
+impl<A: ArchTag> Capstone<A> {
     /// Create a new instance of the decompiler using the builder pattern interface.
     /// This is the recommended interface to `Capstone`.
     ///
     /// ```
+    /// use capstone::arch::x86::X86ArchTag;
     /// use capstone::prelude::*;
-    /// let cs = Capstone::new().x86().mode(arch::x86::ArchMode::Mode32).build();
+    /// let cs = Capstone::<X86ArchTag>::new().mode(arch::x86::ArchMode::Mode32).build();
     /// ```
     #[allow(clippy::new_ret_no_self)]
-    pub fn new() -> CapstoneBuilder {
-        CapstoneBuilder::new()
+    pub fn new() -> A::Builder {
+        A::Builder::default()
     }
 
-    /// Create a new instance of the decompiler using the "raw" interface.
-    /// The user must ensure that only sensible `Arch`/`Mode` combinations are used.
+    /// Create a new instance of the decompiler using the "raw" interface. The user must ensure that only sensible
+    /// [`Arch`] / [`Mode`] combinations are used.
+    ///
+    /// This function will return an `Err` value if the given [`Arch`], [`Mode`], or extra modes are invalid for the
+    /// disassembler's target architecture specified by `A`.
     ///
     /// ```
     /// use capstone::{Arch, Capstone, NO_EXTRA_MODE, Mode};
-    /// let cs = Capstone::new_raw(Arch::X86, Mode::Mode64, NO_EXTRA_MODE, None);
+    /// use capstone::arch::DynamicArchTag;
+    /// let cs = Capstone::<DynamicArchTag>::new_raw(Arch::X86, Mode::Mode64, NO_EXTRA_MODE, None);
     /// assert!(cs.is_ok());
     /// ```
     pub fn new_raw<T: Iterator<Item = ExtraMode>>(
@@ -126,7 +156,11 @@ impl Capstone {
         mode: Mode,
         extra_mode: T,
         endian: Option<Endian>,
-    ) -> CsResult<Capstone> {
+    ) -> CsResult<Self> {
+        if !A::support_arch(arch) {
+            return Err(Error::UnsupportedArch);
+        }
+
         let mut handle: csh = 0;
         let csarch: cs_arch = arch.into();
         let csmode: cs_mode = mode.into();
@@ -137,13 +171,13 @@ impl Capstone {
             Some(endian) => cs_mode::from(endian),
             None => cs_mode(0),
         };
-        let extra_mode = Self::extra_mode_value(extra_mode);
+        let extra_mode = extra_mode_value(extra_mode);
 
         let combined_mode = csmode | endian | extra_mode;
         let err = unsafe { cs_open(csarch, combined_mode, &mut handle) };
 
         if cs_err::CS_ERR_OK == err {
-            let syntax = CS_OPT_SYNTAX_DEFAULT;
+            let syntax = cs_opt_value::CS_OPT_SYNTAX_DEFAULT;
             let raw_mode = cs_mode(0);
             let detail_enabled = false;
             let skipdata_enabled = detail_enabled;
@@ -158,6 +192,7 @@ impl Capstone {
                 skipdata_enabled,
                 raw_mode,
                 arch,
+                _arch_tag: PhantomData::default(),
             };
             cs.update_raw_mode();
             Ok(cs)
@@ -166,24 +201,25 @@ impl Capstone {
         }
     }
 
-    /// Disassemble all instructions in buffer
+    /// Disassemble all instructions in buffer.
     ///
     /// ```
     /// # use capstone::prelude::*;
-    /// # let cs = Capstone::new().x86().mode(arch::x86::ArchMode::Mode32).build().unwrap();
+    /// # use capstone::arch::x86::X86ArchTag;
+    /// # let cs = Capstone::<X86ArchTag>::new().mode(arch::x86::ArchMode::Mode32).build().unwrap();
     /// cs.disasm_all(b"\x90", 0x1000).unwrap();
     /// ```
-    pub fn disasm_all<'a>(&'a self, code: &[u8], addr: u64) -> CsResult<Instructions<'a>> {
+    pub fn disasm_all<'a>(&'a self, code: &[u8], addr: u64) -> CsResult<Instructions<'a, A>> {
         self.disasm(code, addr, 0)
     }
 
-    /// Disassemble `count` instructions in `code`
+    /// Disassemble `count` instructions in `code`.
     pub fn disasm_count<'a>(
         &'a self,
         code: &[u8],
         addr: u64,
         count: usize,
-    ) -> CsResult<Instructions<'a>> {
+    ) -> CsResult<Instructions<'a, A>> {
         if count == 0 {
             return Err(Error::CustomError("Invalid dissasemble count; must be > 0"));
         }
@@ -193,7 +229,7 @@ impl Capstone {
     /// Disassembles a `&[u8]` full of instructions.
     ///
     /// Pass `count = 0` to disassemble all instructions in the buffer.
-    fn disasm<'a>(&'a self, code: &[u8], addr: u64, count: usize) -> CsResult<Instructions<'a>> {
+    fn disasm<'a>(&'a self, code: &[u8], addr: u64, count: usize) -> CsResult<Instructions<'a, A>> {
         // SAFETY NOTE: `cs_disasm()` will write the error state into the
         // `struct cs_struct` (true form of the `self.csh`) `errnum` field.
         // CLAIM: since:
@@ -214,13 +250,13 @@ impl Capstone {
         }
     }
 
-    /// Returns csh handle
+    /// Returns csh handle.
     #[inline]
     fn csh(&self) -> csh {
         self.csh as csh
     }
 
-    /// Returns the raw mode value, which is useful for debugging
+    /// Returns the raw mode value, which is useful for debugging.
     #[allow(dead_code)]
     pub(crate) fn raw_mode(&self) -> cs_mode {
         self.raw_mode
@@ -234,17 +270,14 @@ impl Capstone {
         self.raw_mode
     }
 
-    /// Return the integer value used by capstone to represent the set of extra modes
-    fn extra_mode_value<T: Iterator<Item = ExtraMode>>(extra_mode: T) -> cs_mode {
-        // Bitwise OR extra modes
-        extra_mode.fold(cs_mode(0), |acc, x| acc | cs_mode::from(x))
-    }
-
-    /// Set extra modes in addition to normal `mode`
-    pub fn set_extra_mode<T: Iterator<Item = ExtraMode>>(&mut self, extra_mode: T) -> CsResult<()> {
+    /// Set extra modes in addition to normal `mode`.
+    pub fn set_extra_mode<T: Iterator<Item = A::ExtraMode>>(
+        &mut self,
+        extra_mode: T,
+    ) -> CsResult<()> {
         let old_val = self.extra_mode;
 
-        self.extra_mode = Self::extra_mode_value(extra_mode);
+        self.extra_mode = extra_mode_value(extra_mode.map(|x| x.into()));
 
         let old_mode = self.raw_mode;
         let new_mode = self.update_raw_mode();
@@ -259,11 +292,11 @@ impl Capstone {
         result
     }
 
-    /// Set the assembly syntax (has no effect on some platforms)
-    pub fn set_syntax(&mut self, syntax: Syntax) -> CsResult<()> {
+    /// Set the assembly syntax (has no effect on some platforms).
+    pub fn set_syntax(&mut self, syntax: A::Syntax) -> CsResult<()> {
         // Todo(tmfink) check for valid syntax
-        let syntax_int = cs_opt_value::Type::from(syntax);
-        let result = self._set_cs_option(cs_opt_type::CS_OPT_SYNTAX, syntax_int as usize);
+        let syntax_int = cs_opt_value::from(syntax.into());
+        let result = self._set_cs_option(cs_opt_type::CS_OPT_SYNTAX, syntax_int.0 as usize);
 
         if result.is_ok() {
             self.syntax = syntax_int;
@@ -305,11 +338,11 @@ impl Capstone {
         }
     }
 
-    /// Controls whether to capstone will generate extra details about disassembled instructions.
+    /// Controls whether capstone should generate extra details about disassembled instructions.
     ///
     /// Pass `true` to enable detail or `false` to disable detail.
     pub fn set_detail(&mut self, enable_detail: bool) -> CsResult<()> {
-        let option_value: usize = OptValue::from(enable_detail).0 as usize;
+        let option_value: usize = OptValue::from(enable_detail).0 .0 as usize;
         let result = self._set_cs_option(cs_opt_type::CS_OPT_DETAIL, option_value);
 
         // Only update internal state on success
@@ -320,11 +353,11 @@ impl Capstone {
         result
     }
 
-    /// Controls whether capstone will skip over invalid or data instructions.
+    /// Controls whether capstone should skip over invalid or data instructions.
     ///
     /// Pass `true` to enable skipdata or `false` to disable skipdata.
     pub fn set_skipdata(&mut self, enable_skipdata: bool) -> CsResult<()> {
-        let option_value: usize = OptValue::from(enable_skipdata).0 as usize;
+        let option_value: usize = OptValue::from(enable_skipdata).0 .0 as usize;
         let result = self._set_cs_option(cs_opt_type::CS_OPT_SKIPDATA, option_value);
 
         // Only update internal state on success
@@ -336,11 +369,11 @@ impl Capstone {
     }
 
     /// Converts a register id `reg_id` to a `String` containing the register name.
-    /// Unavailable in Diet mode
-    pub fn reg_name(&self, reg_id: RegId) -> Option<String> {
+    /// Unavailable in Diet mode.
+    pub fn reg_name(&self, reg_id: A::RegId) -> Option<String> {
         if cfg!(feature = "full") {
             let reg_name = unsafe {
-                let _reg_name = cs_reg_name(self.csh(), c_uint::from(reg_id.0));
+                let _reg_name = cs_reg_name(self.csh(), reg_id.into().0 as libc::c_uint);
                 str_from_cstr_ptr(_reg_name)?.to_string()
             };
             Some(reg_name)
@@ -352,10 +385,10 @@ impl Capstone {
     /// Converts an instruction id `insn_id` to a `String` containing the instruction name.
     /// Unavailable in Diet mode.
     /// Note: This function ignores the current syntax and uses the default syntax.
-    pub fn insn_name(&self, insn_id: InsnId) -> Option<String> {
+    pub fn insn_name(&self, insn_id: A::InsnId) -> Option<String> {
         if cfg!(feature = "full") {
             let insn_name = unsafe {
-                let _insn_name = cs_insn_name(self.csh(), insn_id.0 as c_uint);
+                let _insn_name = cs_insn_name(self.csh(), insn_id.into().0 as libc::c_uint);
                 str_from_cstr_ptr(_insn_name)?.to_string()
             };
 
@@ -366,11 +399,11 @@ impl Capstone {
     }
 
     /// Converts a group id `group_id` to a `String` containing the group name.
-    /// Unavailable in Diet mode
-    pub fn group_name(&self, group_id: InsnGroupId) -> Option<String> {
+    /// Unavailable in Diet mode.
+    pub fn group_name(&self, group_id: A::InsnGroupId) -> Option<String> {
         if cfg!(feature = "full") {
             let group_name = unsafe {
-                let _group_name = cs_group_name(self.csh(), c_uint::from(group_id.0));
+                let _group_name = cs_group_name(self.csh(), group_id.into().0 as libc::c_uint);
                 str_from_cstr_ptr(_group_name)?.to_string()
             };
 
@@ -380,13 +413,13 @@ impl Capstone {
         }
     }
 
-    /// Returns `Detail` structure for a given instruction
+    /// Returns `Detail` structure for a given instruction.
     ///
     /// Requires:
     ///
-    /// 1. Instruction was created with detail enabled
-    /// 2. Skipdata is disabled
-    pub fn insn_detail<'s, 'i: 's>(&'s self, insn: &'i Insn) -> CsResult<InsnDetail<'i>> {
+    /// 1. Instruction was created with details enabled.
+    /// 2. Skipdata is disabled.
+    pub fn insn_detail<'s, 'i: 's>(&'s self, insn: &'i Insn<A>) -> CsResult<InsnDetail<'i, A>> {
         if !self.detail_enabled {
             Err(Error::DetailOff)
         } else if insn.id().0 == 0 {
@@ -395,34 +428,40 @@ impl Capstone {
             Ok(unsafe { insn.detail(self.arch) })
         }
     }
+}
 
-    /// Returns a tuple (major, minor) indicating the version of the capstone C library.
-    pub fn lib_version() -> (u32, u32) {
-        let mut major: c_int = 0;
-        let mut minor: c_int = 0;
-        let major_ptr: *mut c_int = &mut major;
-        let minor_ptr: *mut c_int = &mut minor;
+impl<A: ArchTag> Drop for Capstone<A> {
+    fn drop(&mut self) {
+        unsafe { cs_close(&mut self.csh()) };
+    }
+}
 
-        // We can ignore the "hexical" version returned by capstone because we already have the
-        // major and minor versions
-        let _ = unsafe { cs_version(major_ptr, minor_ptr) };
+/// Returns a tuple (major, minor) indicating the version of the capstone C library.
+pub fn lib_version() -> (u32, u32) {
+    let mut major: c_int = 0;
+    let mut minor: c_int = 0;
+    let major_ptr: *mut c_int = &mut major;
+    let minor_ptr: *mut c_int = &mut minor;
 
-        (major as u32, minor as u32)
-    }
+    // We can ignore the "hexical" version returned by capstone because we already have the
+    // major and minor versions
+    let _ = unsafe { cs_version(major_ptr, minor_ptr) };
 
-    /// Returns whether the capstone library supports a given architecture.
-    pub fn supports_arch(arch: Arch) -> bool {
-        unsafe { cs_support(arch as c_int) }
-    }
+    (major as u32, minor as u32)
+}
 
-    /// Returns whether the capstone library was compiled in diet mode.
-    pub fn is_diet() -> bool {
-        unsafe { cs_support(CS_SUPPORT_DIET as c_int) }
-    }
+/// Returns whether the capstone library supports a given architecture.
+pub fn supports_arch(arch: Arch) -> bool {
+    unsafe { cs_support(arch as c_int) }
 }
 
-impl Drop for Capstone {
-    fn drop(&mut self) {
-        unsafe { cs_close(&mut self.csh()) };
-    }
+/// Returns whether the capstone library was compiled in diet mode.
+pub fn is_diet() -> bool {
+    unsafe { cs_support(CS_SUPPORT_DIET as c_int) }
+}
+
+/// Return the integer value used by capstone to represent the set of extra modes
+fn extra_mode_value<T: Iterator<Item = ExtraMode>>(extra_mode: T) -> cs_mode {
+    // Bitwise OR extra modes
+    extra_mode.fold(cs_mode(0), |acc, x| acc | cs_mode::from(x))
 }
diff --git a/capstone-rs/src/constants.rs b/capstone-rs/src/constants.rs
index 0011f298..d0d43b15 100644
--- a/capstone-rs/src/constants.rs
+++ b/capstone-rs/src/constants.rs
@@ -1,10 +1,9 @@
-use capstone_sys::cs_arch::*;
-use capstone_sys::cs_opt_value::*;
-use capstone_sys::*;
 use core::convert::From;
 use core::fmt::{self, Display};
 use core::str::FromStr;
 
+use capstone_sys::*;
+
 /// A C-like enum can list its variants
 pub trait EnumList
 where
@@ -57,7 +56,7 @@ macro_rules! define_cs_enum_wrapper {
             fn from(other: $rust_enum) -> Self {
                 match other {
                     $(
-                        $rust_enum::$rust_variant => $cs_variant,
+                        $rust_enum::$rust_variant => <$cs_enum>::$cs_variant,
                     )*
                 }
             }
@@ -319,7 +318,7 @@ define_cs_enum_wrapper!(
 define_cs_enum_wrapper!(
     [
         /// Disassembly syntax
-        => Syntax = cs_opt_value::Type
+        => Syntax = cs_opt_value
     ]
     /// Intel syntax
     => Intel = CS_OPT_SYNTAX_INTEL;
@@ -331,7 +330,7 @@ define_cs_enum_wrapper!(
     => NoRegName = CS_OPT_SYNTAX_NOREGNAME;
 );
 
-pub(crate) struct OptValue(pub cs_opt_value::Type);
+pub(crate) struct OptValue(pub cs_opt_value);
 
 impl From<bool> for OptValue {
     fn from(value: bool) -> Self {
diff --git a/capstone-rs/src/error.rs b/capstone-rs/src/error.rs
index 0a9f68f5..30f55dfd 100644
--- a/capstone-rs/src/error.rs
+++ b/capstone-rs/src/error.rs
@@ -1,7 +1,5 @@
 //! Capstone errors
 
-use capstone_sys::cs_err::*;
-
 use core::fmt;
 use core::result;
 
@@ -28,11 +26,11 @@ macro_rules! capstone_error_def {
             CustomError(&'static str),
         }
 
-        impl From<capstone_sys::cs_err::Type> for Error {
-            fn from(err: capstone_sys::cs_err::Type) -> Self {
+        impl From<capstone_sys::cs_err> for Error {
+            fn from(err: capstone_sys::cs_err) -> Self {
                 match err {
                     $(
-                        $cs_variant => Error::$rust_variant,
+                        capstone_sys::cs_err::$cs_variant => Error::$rust_variant,
                     )*
                     _ => Error::UnknownCapstoneError,
                 }
@@ -125,7 +123,7 @@ mod test {
             Error::UnknownCapstoneError,
             Error::CustomError("custom error"),
             Error::from(cs_err::CS_ERR_ARCH),
-            Error::from(500 as cs_err::Type),
+            Error::from(cs_err(500)),
         ];
 
         for error in errors.iter() {
diff --git a/capstone-rs/src/instruction.rs b/capstone-rs/src/instruction.rs
index aaa1242b..80bac322 100644
--- a/capstone-rs/src/instruction.rs
+++ b/capstone-rs/src/instruction.rs
@@ -3,12 +3,13 @@ use core::convert::{TryFrom, TryInto};
 use core::fmt::{self, Debug, Display, Error, Formatter};
 use core::marker::PhantomData;
 use core::ops::Deref;
+use core::ptr::NonNull;
 use core::slice;
 use core::str;
 
 use capstone_sys::*;
 
-use crate::arch::ArchDetail;
+use crate::arch::ArchTag;
 use crate::constants::Arch;
 
 use crate::ffi::str_from_cstr_ptr;
@@ -17,16 +18,27 @@ use crate::ffi::str_from_cstr_ptr;
 ///
 /// To access inner [`&[Insn]`](Insn), use [`.as_ref()`](AsRef::as_ref).
 /// ```
-/// # use capstone::Instructions;
+/// # use capstone::arch::x86::X86ArchTag;
 /// # use capstone::prelude::*;
-/// # let cs = Capstone::new().x86().mode(arch::x86::ArchMode::Mode32).build().unwrap();
-/// let insns: Instructions = cs.disasm_all(b"\x55\x48\x8b\x05", 0x1000).unwrap();
+/// # let cs = Capstone::<X86ArchTag>::new().mode(arch::x86::ArchMode::Mode32).build().unwrap();
+/// let insns = cs.disasm_all(b"\x55\x48\x8b\x05", 0x1000).unwrap();
 /// for insn in insns.as_ref() {
 ///     println!("{}", insn);
 /// }
 /// ```
-#[derive(Debug)]
-pub struct Instructions<'a>(&'a mut [cs_insn]);
+pub struct Instructions<'a, A: ArchTag>(&'a mut [cs_insn], PhantomData<A>);
+
+impl<'a, A: ArchTag> Instructions<'a, A> {
+    fn new(insns: &'a mut [cs_insn]) -> Self {
+        Self(insns, PhantomData::default())
+    }
+}
+
+impl<'a, A: ArchTag> Debug for Instructions<'a, A> {
+    fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result {
+        f.debug_tuple("Instructions").field(&self.0).finish()
+    }
+}
 
 /// Integer type used in `InsnId`
 pub type InsnIdInt = u32;
@@ -37,6 +49,34 @@ pub type InsnIdInt = u32;
 #[derive(Copy, Clone, Debug, Hash, PartialEq, Eq, PartialOrd, Ord)]
 pub struct InsnId(pub InsnIdInt);
 
+macro_rules! define_arch_insn_conversions {
+    ( $( [ $arch:ident, $arch_insn:ident ] ),+ $(,)? ) => {
+        $(
+            impl From<$crate::arch::$arch::$arch_insn> for InsnId {
+                fn from(arch_insn: $crate::arch::$arch::$arch_insn) -> Self {
+                    Self(arch_insn as InsnIdInt)
+                }
+            }
+        )+
+    };
+}
+
+define_arch_insn_conversions![
+    [arm, ArmInsn],
+    [arm64, Arm64Insn],
+    [evm, EvmInsn],
+    [m68k, M68kInsn],
+    [m680x, M680xInsn],
+    [mips, MipsInsn],
+    [ppc, PpcInsn],
+    [riscv, RiscVInsn],
+    [sparc, SparcInsn],
+    [sysz, SyszInsn],
+    [tms320c64x, Tms320c64xInsn],
+    [x86, X86Insn],
+    [xcore, XcoreInsn],
+];
+
 /// Integer type used in `InsnGroupId`
 pub type InsnGroupIdInt = u8;
 
@@ -47,6 +87,50 @@ pub type InsnGroupIdInt = u8;
 #[repr(transparent)]
 pub struct InsnGroupId(pub InsnGroupIdInt);
 
+impl InsnGroupId {
+    pub const INVALID_GROUP: Self = Self(0);
+}
+
+impl From<u32> for InsnGroupId {
+    fn from(value: u32) -> Self {
+        Self(value.try_into().ok().unwrap_or(Self::INVALID_GROUP.0))
+    }
+}
+
+macro_rules! define_arch_grp_id_conversions {
+    ( $( [ $arch:ident, $arch_insn_grp:ident ] ),+ $(,)? ) => {
+        $(
+            impl From<$crate::arch::$arch::$arch_insn_grp> for InsnGroupId {
+                fn from(arch_insn_grp: $crate::arch::$arch::$arch_insn_grp) -> Self {
+                    Self(arch_insn_grp.0 as InsnGroupIdInt)
+                }
+            }
+
+            impl From<InsnGroupId> for $crate::arch::$arch::$arch_insn_grp {
+                fn from(insn_grp: InsnGroupId) -> Self {
+                    Self(insn_grp.0 as _)
+                }
+            }
+        )+
+    };
+}
+
+define_arch_grp_id_conversions![
+    [arm, ArmInsnGroup],
+    [arm64, Arm64InsnGroup],
+    [evm, EvmInsnGroup],
+    [m68k, M68kInsnGroup],
+    [m680x, M680xInsnGroup],
+    [mips, MipsInsnGroup],
+    [ppc, PpcInsnGroup],
+    [riscv, RiscVInsnGroup],
+    [sparc, SparcInsnGroup],
+    [sysz, SyszInsnGroup],
+    [tms320c64x, Tms320c64xInsnGroup],
+    [x86, X86InsnGroup],
+    [xcore, XcoreInsnGroup],
+];
+
 pub use capstone_sys::cs_group_type as InsnGroupType;
 
 /// Integer type used in `RegId`
@@ -64,12 +148,51 @@ impl RegId {
     pub const INVALID_REG: Self = Self(0);
 }
 
-impl core::convert::From<u32> for RegId {
-    fn from(v: u32) -> RegId {
-        RegId(v.try_into().ok().unwrap_or(Self::INVALID_REG.0))
+impl From<RegIdInt> for RegId {
+    fn from(value: RegIdInt) -> Self {
+        Self(value)
+    }
+}
+
+impl From<RegId> for RegIdInt {
+    fn from(value: RegId) -> Self {
+        value.0
     }
 }
 
+macro_rules! define_arch_reg_conversions {
+    ( $( [ $arch:ident, $arch_reg:ident ] ),+ $(,)? ) => {
+        $(
+            impl From<$crate::arch::$arch::$arch_reg> for RegId {
+                fn from(arch_reg: $crate::arch::$arch::$arch_reg) -> Self {
+                    Self(arch_reg.0 as _)
+                }
+            }
+
+            impl From<RegId> for $crate::arch::$arch::$arch_reg {
+                fn from(reg_id: RegId) -> Self {
+                    Self(reg_id.0 as _)
+                }
+            }
+        )+
+    };
+}
+
+define_arch_reg_conversions![
+    [arm, ArmReg],
+    [arm64, Arm64Reg],
+    [m68k, M68kReg],
+    [m680x, M680xReg],
+    [mips, MipsReg],
+    [ppc, PpcReg],
+    [riscv, RiscVReg],
+    [sparc, SparcReg],
+    [sysz, SyszReg],
+    [tms320c64x, Tms320c64xReg],
+    [x86, X86Reg],
+    [xcore, XcoreReg],
+];
+
 /// Represents how the register is accessed.
 #[derive(Copy, Clone, Debug, Hash, PartialEq, Eq)]
 pub enum RegAccessType {
@@ -106,13 +229,13 @@ impl TryFrom<cs_ac_type> for RegAccessType {
 
     fn try_from(access: cs_ac_type) -> Result<Self, Self::Error> {
         // Check for flags other than CS_AC_READ or CS_AC_WRITE.
-        let unknown_flag_mask = !(CS_AC_READ | CS_AC_WRITE).0;
+        let unknown_flag_mask = !(cs_ac_type::CS_AC_READ | cs_ac_type::CS_AC_WRITE).0;
         if (access.0 & unknown_flag_mask) != 0 {
             return Err(());
         }
 
-        let is_readable = (access & CS_AC_READ).0 != 0;
-        let is_writable = (access & CS_AC_WRITE).0 != 0;
+        let is_readable = (access & cs_ac_type::CS_AC_READ).0 != 0;
+        let is_writable = (access & cs_ac_type::CS_AC_WRITE).0 != 0;
         match (is_readable, is_writable) {
             (true, false) => Ok(RegAccessType::ReadOnly),
             (false, true) => Ok(RegAccessType::WriteOnly),
@@ -122,34 +245,34 @@ impl TryFrom<cs_ac_type> for RegAccessType {
     }
 }
 
-impl<'a> Instructions<'a> {
-    pub(crate) unsafe fn from_raw_parts(ptr: *mut cs_insn, len: usize) -> Instructions<'a> {
-        Instructions(slice::from_raw_parts_mut(ptr, len))
+impl<'a, A: ArchTag> Instructions<'a, A> {
+    pub(crate) unsafe fn from_raw_parts(ptr: *mut cs_insn, len: usize) -> Instructions<'a, A> {
+        Instructions::new(slice::from_raw_parts_mut(ptr, len))
     }
 
-    pub(crate) fn new_empty() -> Instructions<'a> {
-        Instructions(&mut [])
+    pub(crate) fn new_empty() -> Instructions<'a, A> {
+        Instructions::new(&mut [])
     }
 }
 
-impl<'a> core::ops::Deref for Instructions<'a> {
-    type Target = [Insn<'a>];
+impl<'a, A: ArchTag> Deref for Instructions<'a, A> {
+    type Target = [Insn<'a, A>];
 
     #[inline]
-    fn deref(&self) -> &[Insn<'a>] {
+    fn deref(&self) -> &[Insn<'a, A>] {
         // SAFETY: `cs_insn` has the same memory layout as `Insn`
-        unsafe { &*(self.0 as *const [cs_insn] as *const [Insn]) }
+        unsafe { &*(self.0 as *const [cs_insn] as *const [Insn<'a, A>]) }
     }
 }
 
-impl<'a> AsRef<[Insn<'a>]> for Instructions<'a> {
+impl<'a, A: ArchTag> AsRef<[Insn<'a, A>]> for Instructions<'a, A> {
     #[inline]
-    fn as_ref(&self) -> &[Insn<'a>] {
+    fn as_ref(&self) -> &[Insn<'a, A>] {
         self.deref()
     }
 }
 
-impl<'a> Drop for Instructions<'a> {
+impl<'a, A: ArchTag> Drop for Instructions<'a, A> {
     fn drop(&mut self) {
         if !self.is_empty() {
             unsafe {
@@ -165,12 +288,12 @@ impl<'a> Drop for Instructions<'a> {
 ///
 /// To learn how to get more instruction details, see [`InsnDetail`].
 #[repr(transparent)]
-pub struct Insn<'a> {
+pub struct Insn<'a, A: ArchTag> {
     /// Inner `cs_insn`
     pub(crate) insn: cs_insn,
 
     /// Adds lifetime
-    pub(crate) _marker: PhantomData<&'a InsnDetail<'a>>,
+    pub(crate) _marker: PhantomData<&'a InsnDetail<'a, A>>,
 }
 
 /// Contains architecture-independent details about an [`Insn`].
@@ -181,10 +304,9 @@ pub struct Insn<'a> {
 /// [`Capstone::insn_detail()`](crate::Capstone::insn_detail).
 ///
 /// ```
-/// # use capstone::Instructions;
+/// # use capstone::arch::x86::X86ArchTag;
 /// # use capstone::prelude::*;
-/// let cs = Capstone::new()
-///     .x86()
+/// let cs = Capstone::<X86ArchTag>::new()
 ///     .mode(arch::x86::ArchMode::Mode32)
 ///     .detail(true) // needed to enable detail
 ///     .build()
@@ -192,8 +314,8 @@ pub struct Insn<'a> {
 /// let insns = cs.disasm_all(b"\x90", 0x1000).unwrap();
 /// for insn in insns.as_ref() {
 ///     println!("{}", insn);
-///     let insn_detail: InsnDetail = cs.insn_detail(insn).unwrap();
-///     println!("    {:?}", insn_detail.groups());
+///     let insn_detail = cs.insn_detail(insn).unwrap();
+///     println!("    {:?}", insn_detail.groups().collect::<Vec<_>>());
 /// }
 /// ```
 ///
@@ -202,10 +324,16 @@ pub struct Insn<'a> {
 /// To get additional architecture-specific information, use the
 /// [`.arch_detail()`](Self::arch_detail) method to get an `ArchDetail` enum.
 ///
-pub struct InsnDetail<'a>(pub(crate) &'a cs_detail, pub(crate) Arch);
+pub struct InsnDetail<'a, A: ArchTag>(pub(crate) &'a cs_detail, pub(crate) Arch, PhantomData<A>);
+
+impl<'a, A: ArchTag> InsnDetail<'a, A> {
+    fn new(detail: &'a cs_detail, arch: Arch) -> Self {
+        Self(detail, arch, PhantomData::default())
+    }
+}
 
 #[allow(clippy::len_without_is_empty)]
-impl<'a> Insn<'a> {
+impl<'a, A: ArchTag> Insn<'a, A> {
     /// Create an `Insn` from a raw pointer to a [`capstone_sys::cs_insn`].
     ///
     /// This function serves to allow integration with libraries which generate `capstone_sys::cs_insn`'s internally.
@@ -215,13 +343,15 @@ impl<'a> Insn<'a> {
     /// Note that this function is unsafe, and assumes that you know what you are doing. In
     /// particular, it generates a lifetime for the `Insn` from nothing, and that lifetime is in
     /// no-way actually tied to the cs_insn itself. It is the responsibility of the caller to
-    /// ensure that the resulting `Insn` lives only as long as the `cs_insn`. This function
-    /// assumes that the pointer passed is non-null and a valid `cs_insn` pointer.
+    /// ensure that:
+    /// - The resulting `Insn` does not outlive the given `cs_insn` object.
+    /// - The pointer passed in as `insn` is non-null and is a valid pointer to a `cs_insn` object.
+    /// - The architecture of the instruction matches the architecture specified by the architecture tag `A`.
     ///
     /// The caller is fully responsible for the backing allocations lifetime, including freeing.
-    pub unsafe fn from_raw(insn: *const cs_insn) -> Self {
+    pub unsafe fn from_raw(insn: NonNull<cs_insn>) -> Self {
         Self {
-            insn: core::ptr::read(insn),
+            insn: core::ptr::read(insn.as_ptr()),
             _marker: PhantomData,
         }
     }
@@ -248,25 +378,25 @@ impl<'a> Insn<'a> {
         }
     }
 
-    /// Access instruction id
+    /// Access instruction id.
     #[inline]
     pub fn id(&self) -> InsnId {
         InsnId(self.insn.id)
     }
 
-    /// Size of instruction (in bytes)
+    /// Size of instruction (in bytes).
     #[inline]
     pub fn len(&self) -> usize {
         self.insn.size as usize
     }
 
-    /// Instruction address
+    /// Instruction address.
     #[inline]
     pub fn address(&self) -> u64 {
         self.insn.address
     }
 
-    /// Byte-level representation of the instruction
+    /// Byte-level representation of the instruction.
     #[inline]
     pub fn bytes(&self) -> &[u8] {
         &self.insn.bytes[..self.len()]
@@ -276,21 +406,21 @@ impl<'a> Insn<'a> {
     /// the pre-conditions are satisfied.
     ///
     /// Be careful this is still in early stages and largely untested with various `cs_option` and
-    /// architecture matrices
+    /// architecture matrices.
     ///
     /// # Safety
     /// The [`cs_insn::detail`] pointer must be valid and non-null.
     #[inline]
-    pub(crate) unsafe fn detail(&self, arch: Arch) -> InsnDetail {
-        InsnDetail(&*self.insn.detail, arch)
+    pub(crate) unsafe fn detail(&self, arch: Arch) -> InsnDetail<'_, A> {
+        InsnDetail::new(&*self.insn.detail, arch)
     }
 }
 
-impl<'a> From<&Insn<'_>> for OwnedInsn<'a> {
+impl<'a, A: ArchTag> From<&Insn<'_, A>> for OwnedInsn<'a, A> {
     // SAFETY: assumes that `cs_detail` struct transitively only contains owned
     // types and no pointers, including the union over the architecture-specific
     // types.
-    fn from(insn: &Insn<'_>) -> Self {
+    fn from(insn: &Insn<'_, A>) -> Self {
         let mut new = unsafe { <*const cs_insn>::read(&insn.insn as _) };
         new.detail = if new.detail.is_null() {
             new.detail
@@ -310,10 +440,10 @@ impl<'a> From<&Insn<'_>> for OwnedInsn<'a> {
 /// SAFETY:
 /// 1. [`OwnedInsn`] and [`Insn`] must be `#repr(transparent)` of [`cs_insn`]
 /// 2. all [`Insn`] methods must be safe to perform for an [`OwnedInsn`]
-impl<'a> Deref for OwnedInsn<'a> {
-    type Target = Insn<'a>;
+impl<'a, A: ArchTag> Deref for OwnedInsn<'a, A> {
+    type Target = Insn<'a, A>;
     fn deref(&self) -> &Self::Target {
-        unsafe { &*(&self.insn as *const cs_insn as *const Insn) }
+        unsafe { &*(&self.insn as *const cs_insn as *const Insn<'a, A>) }
     }
 }
 
@@ -322,15 +452,15 @@ impl<'a> Deref for OwnedInsn<'a> {
 /// # Detail
 ///
 /// To learn how to get more instruction details, see [`InsnDetail`].
-pub struct OwnedInsn<'a> {
+pub struct OwnedInsn<'a, A: ArchTag> {
     /// Inner cs_insn
     pub(crate) insn: cs_insn,
 
     /// Adds lifetime
-    pub(crate) _marker: PhantomData<&'a InsnDetail<'a>>,
+    pub(crate) _marker: PhantomData<&'a InsnDetail<'a, A>>,
 }
 
-impl<'a> Debug for Insn<'a> {
+impl<'a, A: ArchTag> Debug for Insn<'a, A> {
     fn fmt(&self, fmt: &mut Formatter) -> Result<(), Error> {
         fmt.debug_struct("Insn")
             .field("address", &self.address())
@@ -342,7 +472,7 @@ impl<'a> Debug for Insn<'a> {
     }
 }
 
-impl<'a> Display for Insn<'a> {
+impl<'a, A: ArchTag> Display for Insn<'a, A> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         write!(fmt, "{:#x}: ", self.address())?;
         if let Some(mnemonic) = self.mnemonic() {
@@ -355,7 +485,7 @@ impl<'a> Display for Insn<'a> {
     }
 }
 
-impl<'a> Drop for OwnedInsn<'a> {
+impl<'a, A: ArchTag> Drop for OwnedInsn<'a, A> {
     fn drop(&mut self) {
         if let Some(ptr) = core::ptr::NonNull::new(self.insn.detail) {
             unsafe { drop(Box::from_raw(ptr.as_ptr())) }
@@ -363,13 +493,13 @@ impl<'a> Drop for OwnedInsn<'a> {
     }
 }
 
-impl<'a> Debug for OwnedInsn<'a> {
+impl<'a, A: ArchTag> Debug for OwnedInsn<'a, A> {
     fn fmt(&self, fmt: &mut Formatter) -> Result<(), Error> {
         Debug::fmt(&self.deref(), fmt)
     }
 }
 
-impl<'a> Display for OwnedInsn<'a> {
+impl<'a, A: ArchTag> Display for OwnedInsn<'a, A> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         Display::fmt(&self.deref(), fmt)
     }
@@ -379,78 +509,48 @@ impl<'a> Display for OwnedInsn<'a> {
 #[derive(Debug, Clone)]
 pub struct InsnGroupIter<'a>(slice::Iter<'a, InsnGroupIdInt>);
 
-impl<'a> InsnDetail<'a> {
+impl<'a, A: ArchTag> InsnDetail<'a, A> {
     #[cfg(feature = "full")]
     /// Returns the implicit read registers
-    pub fn regs_read(&self) -> &[RegId] {
-        unsafe {
-            &*(&self.0.regs_read[..self.0.regs_read_count as usize] as *const [RegIdInt]
-                as *const [RegId])
-        }
+    pub fn regs_read(&self) -> impl Iterator<Item = A::RegId> + '_ {
+        self.0.regs_read[..self.0.regs_read_count as usize]
+            .iter()
+            .map(|raw_reg| A::RegId::from(RegId(*raw_reg)))
     }
 
     #[cfg(feature = "full")]
     /// Returns the implicit write registers
-    pub fn regs_write(&self) -> &[RegId] {
-        unsafe {
-            &*(&self.0.regs_write[..self.0.regs_write_count as usize] as *const [RegIdInt]
-                as *const [RegId])
-        }
+    pub fn regs_write(&self) -> impl Iterator<Item = A::RegId> + '_ {
+        self.0.regs_write[..self.0.regs_write_count as usize]
+            .iter()
+            .map(|raw_reg| A::RegId::from(RegId(*raw_reg)))
     }
 
     #[cfg(feature = "full")]
     /// Returns the groups to which this instruction belongs
-    pub fn groups(&self) -> &[InsnGroupId] {
-        unsafe {
-            &*(&self.0.groups[..self.0.groups_count as usize] as *const [InsnGroupIdInt]
-                as *const [InsnGroupId])
-        }
+    pub fn groups(&self) -> impl Iterator<Item = A::InsnGroupId> + '_ {
+        self.0.groups[..self.0.groups_count as usize]
+            .iter()
+            .map(|raw_grp| A::InsnGroupId::from(InsnGroupId(*raw_grp)))
     }
 
     /// Architecture-specific detail
-    pub fn arch_detail(&self) -> ArchDetail {
-        macro_rules! def_arch_detail_match {
-            (
-                $( [ $ARCH:ident, $detail:ident, $insn_detail:ident, $arch:ident ] )*
-            ) => {
-                use self::ArchDetail::*;
-                use crate::Arch::*;
-                $( use crate::arch::$arch::$insn_detail; )*
-
-                return match self.1 {
-                    $(
-                        $ARCH => {
-                            $detail($insn_detail(unsafe { &self.0.__bindgen_anon_1.$arch }))
-                        }
-                    )*
-                    _ => panic!("Unsupported detail arch"),
-                }
-            }
-        }
-        def_arch_detail_match!(
-            [ARM, ArmDetail, ArmInsnDetail, arm]
-            [ARM64, Arm64Detail, Arm64InsnDetail, arm64]
-            [EVM, EvmDetail, EvmInsnDetail, evm]
-            [M680X, M680xDetail, M680xInsnDetail, m680x]
-            [M68K, M68kDetail, M68kInsnDetail, m68k]
-            [MIPS, MipsDetail, MipsInsnDetail, mips]
-            [PPC, PpcDetail, PpcInsnDetail, ppc]
-            [RISCV, RiscVDetail, RiscVInsnDetail, riscv]
-            [SPARC, SparcDetail, SparcInsnDetail, sparc]
-            [TMS320C64X, Tms320c64xDetail, Tms320c64xInsnDetail, tms320c64x]
-            [X86, X86Detail, X86InsnDetail, x86]
-            [XCORE, XcoreDetail, XcoreInsnDetail, xcore]
-        );
+    pub fn arch_detail(&self) -> A::InsnDetail<'_> {
+        A::InsnDetail::from(self)
     }
 }
 
 #[cfg(feature = "full")]
-impl<'a> Debug for InsnDetail<'a> {
+impl<'a, A: ArchTag> Debug for InsnDetail<'a, A>
+where
+    A::RegId: Debug,
+    A::InsnGroupId: Debug,
+{
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         fmt.debug_struct("Detail")
-            .field("regs_read", &self.regs_read())
-            .field("regs_write", &self.regs_write())
-            .field("groups", &self.groups())
+            .field("regs_read", &self.regs_read().collect::<Vec<_>>())
+            .field("regs_write", &self.regs_write().collect::<Vec<_>>())
+            .field("groups", &self.groups().collect::<Vec<_>>())
             .finish()
     }
 }
@@ -462,7 +562,7 @@ impl<'a> Debug for InsnDetail<'a> {
     }
 }
 
-impl<'a> Display for Instructions<'a> {
+impl<'a, A: ArchTag> Display for Instructions<'a, A> {
     fn fmt(&self, fmt: &mut Formatter) -> fmt::Result {
         for instruction in self.iter() {
             write!(fmt, "{:x}:\t", instruction.address())?;
diff --git a/capstone-rs/src/lib.rs b/capstone-rs/src/lib.rs
index 42ce0c3f..07a7cb41 100644
--- a/capstone-rs/src/lib.rs
+++ b/capstone-rs/src/lib.rs
@@ -26,8 +26,8 @@ mod error;
 mod ffi;
 mod instruction;
 
-#[cfg(test)]
-mod test;
+// #[cfg(test)]
+// mod test;
 
 pub use crate::capstone::*;
 pub use crate::constants::*;
@@ -43,8 +43,8 @@ pub use crate::instruction::*;
 /// ```
 pub mod prelude {
     pub use crate::arch::{
-        self, ArchDetail, BuildsCapstone, BuildsCapstoneEndian, BuildsCapstoneExtraMode,
-        BuildsCapstoneSyntax, DetailsArchInsn,
+        self, ArchInsnDetail, ArchTag, BuildsCapstone, BuildsCapstoneEndian,
+        BuildsCapstoneExtraMode, BuildsCapstoneSyntax, DetailsArchInsn,
     };
     pub use crate::{
         Capstone, CsResult, InsnDetail, InsnGroupId, InsnGroupIdInt, InsnId, InsnIdInt, RegId,
diff --git a/capstone-rs/src/test.rs b/capstone-rs/src/test.rs
index cb98c7d4..590619d8 100644
--- a/capstone-rs/src/test.rs
+++ b/capstone-rs/src/test.rs
@@ -12,6 +12,10 @@ use {alloc::string::String, std::collections::HashSet};
 use capstone_sys::cs_group_type;
 use libc::c_uint;
 
+use crate::arch::arm::ArmArchTag;
+use crate::arch::arm64::Arm64ArchTag;
+use crate::arch::x86::{X86ArchTag, X86Insn, X86Reg};
+
 use super::arch::*;
 use super::*;
 
@@ -30,7 +34,10 @@ const START_TEST_ADDR: u64 = 0x1000;
 
 #[test]
 fn test_x86_simple() {
-    match Capstone::new().x86().mode(x86::ArchMode::Mode64).build() {
+    match Capstone::<X86ArchTag>::new()
+        .mode(x86::ArchMode::Mode64)
+        .build()
+    {
         Ok(cs) => match cs.disasm_all(X86_CODE, START_TEST_ADDR) {
             Ok(insns) => {
                 assert_eq!(insns.len(), 2);
@@ -56,7 +63,10 @@ fn test_x86_simple() {
 
 #[test]
 fn test_arm_simple() {
-    match Capstone::new().arm().mode(arm::ArchMode::Arm).build() {
+    match Capstone::<ArmArchTag>::new()
+        .mode(arm::ArchMode::Arm)
+        .build()
+    {
         Ok(cs) => match cs.disasm_all(ARM_CODE, START_TEST_ADDR) {
             Ok(insns) => {
                 assert_eq!(insns.len(), 2);
@@ -79,8 +89,7 @@ fn test_arm_simple() {
 
 #[test]
 fn test_arm64_none() {
-    let cs = Capstone::new()
-        .arm64()
+    let cs = Capstone::<Arm64ArchTag>::new()
         .mode(arm64::ArchMode::Arm)
         .build()
         .unwrap();
@@ -90,23 +99,26 @@ fn test_arm64_none() {
 #[cfg(feature = "full")]
 #[test]
 fn test_x86_names() {
-    match Capstone::new().x86().mode(x86::ArchMode::Mode32).build() {
+    match Capstone::<X86ArchTag>::new()
+        .mode(x86::ArchMode::Mode32)
+        .build()
+    {
         Ok(cs) => {
-            let reg_id = RegId(1);
+            let reg_id = X86Reg::X86_REG_AH;
             match cs.reg_name(reg_id) {
                 Some(reg_name) => assert_eq!(reg_name, "ah"),
                 None => panic!("Couldn't get register name"),
             }
 
-            let insn_id = InsnId(1);
+            let insn_id = X86Insn::X86_INS_AAA;
             match cs.insn_name(insn_id) {
                 Some(insn_name) => assert_eq!(insn_name, "aaa"),
                 None => panic!("Couldn't get instruction name"),
             }
 
-            assert_eq!(cs.group_name(InsnGroupId(1)), Some(String::from("jump")));
+            assert_eq!(cs.group_name(1), Some(String::from("jump")));
 
-            let reg_id = RegId(250);
+            let reg_id = 250 as X86Reg::Type;
             match cs.reg_name(reg_id) {
                 Some(_) => panic!("invalid register worked"),
                 None => {}
@@ -118,7 +130,7 @@ fn test_x86_names() {
                 None => {}
             }
 
-            assert_eq!(cs.group_name(InsnGroupId(250)), None);
+            assert_eq!(cs.group_name(250), None);
         }
         Err(e) => {
             panic!("Couldn't create a cs engine: {}", e);
@@ -128,8 +140,7 @@ fn test_x86_names() {
 
 #[test]
 fn test_detail_false_fail() {
-    let mut cs = Capstone::new()
-        .x86()
+    let mut cs = Capstone::<X86ArchTag>::new()
         .mode(x86::ArchMode::Mode64)
         .build()
         .unwrap();
@@ -145,8 +156,7 @@ fn test_detail_false_fail() {
 fn test_skipdata() {
     use capstone_sys::x86_insn;
 
-    let mut cs = Capstone::new()
-        .x86()
+    let mut cs = Capstone::<X86ArchTag>::new()
         .mode(x86::ArchMode::Mode64)
         .build()
         .unwrap();
@@ -165,15 +175,13 @@ fn test_skipdata() {
 #[cfg(feature = "full")]
 #[test]
 fn test_detail_true() {
-    let mut cs1 = Capstone::new()
-        .x86()
+    let mut cs1 = Capstone::<X86ArchTag>::new()
         .mode(x86::ArchMode::Mode64)
         .build()
         .unwrap();
     cs1.set_detail(true).unwrap();
 
-    let cs2 = Capstone::new()
-        .x86()
+    let cs2 = Capstone::<X86ArchTag>::new()
         .mode(x86::ArchMode::Mode64)
         .detail(true)
         .build()
@@ -201,9 +209,9 @@ fn test_detail_true() {
 }
 
 #[allow(unused)]
-fn test_instruction_helper(
-    cs: &Capstone,
-    insn: &Insn,
+fn test_instruction_helper<A: ArchTag>(
+    cs: &Capstone<A>,
+    insn: &Insn<A>,
     mnemonic_name: &str,
     bytes: &[u8],
     has_default_syntax: bool,
@@ -228,9 +236,9 @@ fn test_instruction_helper(
     assert_eq!(bytes, insn.bytes());
 }
 
-fn test_instruction_detail_helper<T>(
-    cs: &Capstone,
-    insn: &Insn,
+fn test_instruction_detail_helper<T, A: ArchTag>(
+    cs: &Capstone<A>,
+    insn: &Insn<A>,
     info: &DetailedInsnInfo<T>,
     has_default_syntax: bool,
 ) where
@@ -277,9 +285,9 @@ fn test_instruction_detail_helper<T>(
 #[cfg(feature = "full")]
 /// Assert instruction belongs or does not belong to groups, testing both insn_belongs_to_group
 /// and insn_group_ids
-fn test_instruction_group_helper<R: Copy + Into<RegId>>(
-    cs: &Capstone,
-    insn: &Insn,
+fn test_instruction_group_helper<R: Copy + Into<RegId>, A: ArchTag>(
+    cs: &Capstone<A>,
+    insn: &Insn<A>,
     mnemonic_name: &str,
     bytes: &[u8],
     expected_groups: &[cs_group_type::Type],
@@ -346,8 +354,8 @@ type ExpectedInsns<'a, R> = (
 );
 
 #[allow(unused)]
-fn instructions_match_group<R: Copy + Into<RegId>>(
-    cs: &mut Capstone,
+fn instructions_match_group<R: Copy + Into<RegId>, A: ArchTag>(
+    cs: &mut Capstone<A>,
     expected_insns: &[ExpectedInsns<R>],
     has_default_syntax: bool,
 ) {
@@ -393,8 +401,8 @@ fn instructions_match_group<R: Copy + Into<RegId>>(
     }
 }
 
-fn instructions_match(
-    cs: &mut Capstone,
+fn instructions_match<A: ArchTag>(
+    cs: &mut Capstone<A>,
     expected_insns: &[(&str, &[u8])],
     has_default_syntax: bool,
 ) {
@@ -430,8 +438,8 @@ fn instructions_match(
     }
 }
 
-fn instructions_match_detail<T>(
-    cs: &mut Capstone,
+fn instructions_match_detail<T, A: ArchTag>(
+    cs: &mut Capstone<A>,
     info: &[DetailedInsnInfo<T>],
     has_default_syntax: bool,
 ) where
@@ -491,8 +499,7 @@ fn test_instruction_details() {
         ("mov", b"\xb9\x04\x02\x00\x00", &[], &[], &[]),
     ];
 
-    let mut cs = Capstone::new()
-        .x86()
+    let mut cs = Capstone::<X86ArchTag>::new()
         .mode(x86::ArchMode::Mode64)
         .build()
         .unwrap();
@@ -500,7 +507,7 @@ fn test_instruction_details() {
 }
 
 #[allow(unused)]
-fn test_insns_match(cs: &mut Capstone, insns: &[(&str, &[u8])]) {
+fn test_insns_match<A: ArchTag>(cs: &mut Capstone<A>, insns: &[(&str, &[u8])]) {
     for &(mnemonic, bytes) in insns.iter() {
         let insns = cs.disasm_all(bytes, START_TEST_ADDR).unwrap();
         assert_eq!(insns.len(), 1);
@@ -544,8 +551,8 @@ fn test_extra_mode() {
     );
 }
 
-fn test_arch_mode_endian_insns(
-    cs: &mut Capstone,
+fn test_arch_mode_endian_insns<A: ArchTag>(
+    cs: &mut Capstone<A>,
     arch: Arch,
     mode: Mode,
     endian: Option<Endian>,
@@ -599,8 +606,8 @@ where
     }
 }
 
-fn test_arch_mode_endian_insns_detail<T>(
-    cs: &mut Capstone,
+fn test_arch_mode_endian_insns_detail<T, A: ArchTag>(
+    cs: &mut Capstone<A>,
     arch: Arch,
     mode: Mode,
     endian: Option<Endian>,
@@ -610,7 +617,7 @@ fn test_arch_mode_endian_insns_detail<T>(
     T: Into<ArchOperand> + Clone,
 {
     let extra_mode = extra_mode.iter().copied();
-    let mut cs_raw = Capstone::new_raw(arch, mode, extra_mode, endian).unwrap();
+    let mut cs_raw = Capstone::<A>::new_raw(arch, mode, extra_mode, endian).unwrap();
 
     instructions_match_detail(&mut cs_raw, insns, true);
     instructions_match_detail(cs, insns, true);
diff --git a/capstone-sys/Cargo.toml b/capstone-sys/Cargo.toml
index 846b3e74..739c9c73 100644
--- a/capstone-sys/Cargo.toml
+++ b/capstone-sys/Cargo.toml
@@ -26,7 +26,7 @@ travis-ci = { repository = "capstone-rust/capstone-sys" }
 libc = { version = "0.2.59", default-features = false }
 
 [build-dependencies]
-bindgen = { optional = true, version = "0.59.1" }
+bindgen = { optional = true, version = "0.66.1" }
 regex = { optional = true, version = "1.3.1" }
 cc = "1.0"
 
diff --git a/capstone-sys/build.rs b/capstone-sys/build.rs
index ef1ae715..204dfbe0 100644
--- a/capstone-sys/build.rs
+++ b/capstone-sys/build.rs
@@ -240,7 +240,7 @@ fn write_bindgen_bindings(
     out_impl_path: PathBuf,
 ) {
     let mut builder = bindgen::Builder::default()
-        .rust_target(bindgen::RustTarget::Stable_1_19)
+        .rust_target(bindgen::RustTarget::Stable_1_59)
         .size_t_is_usize(true)
         .use_core()
         .ctypes_prefix("libc")
@@ -255,7 +255,7 @@ fn write_bindgen_bindings(
         .generate_comments(true)
         .layout_tests(false) // eliminate test failures on platforms with different pointer sizes
         .impl_debug(true)
-        .constified_enum_module("cs_err|cs_group_type|cs_opt_value")
+        .newtype_enum("cs_err|cs_group_type|cs_opt_value")
         .bitfield_enum("cs_mode|cs_ac_type")
         .rustified_enum(".*")
         .no_copy("cs_insn");
@@ -270,10 +270,10 @@ fn write_bindgen_bindings(
     for arch in ARCH_INCLUDES {
         // .*(^|_)ARCH(_|$).*
         let arch_type_pattern = format!(".*(^|_){}(_|$).*", arch.cs_name);
-        let const_mod_pattern = format!("^{}_(reg|insn_group)$", arch.cs_name);
+        let const_mod_pattern = format!("^{}_(reg|insn_group|group_type)$", arch.cs_name);
         builder = builder
             .allowlist_type(&arch_type_pattern)
-            .constified_enum_module(&const_mod_pattern);
+            .newtype_enum(&const_mod_pattern);
     }
 
     let bindings = builder.generate().expect("Unable to generate bindings");
diff --git a/capstone-sys/pre_generated/capstone.rs b/capstone-sys/pre_generated/capstone.rs
index f8df3088..1968c85c 100644
--- a/capstone-sys/pre_generated/capstone.rs
+++ b/capstone-sys/pre_generated/capstone.rs
@@ -1,14 +1,6 @@
-/* automatically generated by rust-bindgen 0.59.2 */
+/* automatically generated by rust-bindgen 0.66.1 */
 
 pub type va_list = __builtin_va_list;
-pub type __int8_t = libc::c_schar;
-pub type __uint8_t = libc::c_uchar;
-pub type __int16_t = libc::c_short;
-pub type __uint16_t = libc::c_ushort;
-pub type __int32_t = libc::c_int;
-pub type __uint32_t = libc::c_uint;
-pub type __int64_t = libc::c_long;
-pub type __uint64_t = libc::c_ulong;
 pub type csh = usize;
 #[repr(u32)]
 #[doc = " Architecture type"]
@@ -49,100 +41,193 @@ pub enum cs_arch {
     CS_ARCH_MAX = 16,
     CS_ARCH_ALL = 65535,
 }
-#[doc = "< little-endian mode (default mode)"]
-pub const CS_MODE_LITTLE_ENDIAN: cs_mode = cs_mode(0);
-#[doc = "< 32-bit ARM"]
-pub const CS_MODE_ARM: cs_mode = cs_mode(0);
-#[doc = "< 16-bit mode (X86)"]
-pub const CS_MODE_16: cs_mode = cs_mode(2);
-#[doc = "< 32-bit mode (X86)"]
-pub const CS_MODE_32: cs_mode = cs_mode(4);
-#[doc = "< 64-bit mode (X86, PPC)"]
-pub const CS_MODE_64: cs_mode = cs_mode(8);
-#[doc = "< ARM's Thumb mode, including Thumb-2"]
-pub const CS_MODE_THUMB: cs_mode = cs_mode(16);
-#[doc = "< ARM's Cortex-M series"]
-pub const CS_MODE_MCLASS: cs_mode = cs_mode(32);
-#[doc = "< ARMv8 A32 encodings for ARM"]
-pub const CS_MODE_V8: cs_mode = cs_mode(64);
-#[doc = "< MicroMips mode (MIPS)"]
-pub const CS_MODE_MICRO: cs_mode = cs_mode(16);
-#[doc = "< Mips III ISA"]
-pub const CS_MODE_MIPS3: cs_mode = cs_mode(32);
-#[doc = "< Mips32r6 ISA"]
-pub const CS_MODE_MIPS32R6: cs_mode = cs_mode(64);
-#[doc = "< Mips II ISA"]
-pub const CS_MODE_MIPS2: cs_mode = cs_mode(128);
-#[doc = "< SparcV9 mode (Sparc)"]
-pub const CS_MODE_V9: cs_mode = cs_mode(16);
-#[doc = "< Quad Processing eXtensions mode (PPC)"]
-pub const CS_MODE_QPX: cs_mode = cs_mode(16);
-#[doc = "< Signal Processing Engine mode (PPC)"]
-pub const CS_MODE_SPE: cs_mode = cs_mode(32);
-#[doc = "< Book-E mode (PPC)"]
-pub const CS_MODE_BOOKE: cs_mode = cs_mode(64);
-#[doc = "< M68K 68000 mode"]
-pub const CS_MODE_M68K_000: cs_mode = cs_mode(2);
-#[doc = "< M68K 68010 mode"]
-pub const CS_MODE_M68K_010: cs_mode = cs_mode(4);
-#[doc = "< M68K 68020 mode"]
-pub const CS_MODE_M68K_020: cs_mode = cs_mode(8);
-#[doc = "< M68K 68030 mode"]
-pub const CS_MODE_M68K_030: cs_mode = cs_mode(16);
-#[doc = "< M68K 68040 mode"]
-pub const CS_MODE_M68K_040: cs_mode = cs_mode(32);
-#[doc = "< M68K 68060 mode"]
-pub const CS_MODE_M68K_060: cs_mode = cs_mode(64);
-#[doc = "< big-endian mode"]
-pub const CS_MODE_BIG_ENDIAN: cs_mode = cs_mode(2147483648);
-#[doc = "< Mips32 ISA (Mips)"]
-pub const CS_MODE_MIPS32: cs_mode = cs_mode(4);
-#[doc = "< Mips64 ISA (Mips)"]
-pub const CS_MODE_MIPS64: cs_mode = cs_mode(8);
-#[doc = "< M680X Hitachi 6301,6303 mode"]
-pub const CS_MODE_M680X_6301: cs_mode = cs_mode(2);
-#[doc = "< M680X Hitachi 6309 mode"]
-pub const CS_MODE_M680X_6309: cs_mode = cs_mode(4);
-#[doc = "< M680X Motorola 6800,6802 mode"]
-pub const CS_MODE_M680X_6800: cs_mode = cs_mode(8);
-#[doc = "< M680X Motorola 6801,6803 mode"]
-pub const CS_MODE_M680X_6801: cs_mode = cs_mode(16);
-#[doc = "< M680X Motorola/Freescale 6805 mode"]
-pub const CS_MODE_M680X_6805: cs_mode = cs_mode(32);
-#[doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"]
-pub const CS_MODE_M680X_6808: cs_mode = cs_mode(64);
-#[doc = "< M680X Motorola 6809 mode"]
-pub const CS_MODE_M680X_6809: cs_mode = cs_mode(128);
-#[doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"]
-pub const CS_MODE_M680X_6811: cs_mode = cs_mode(256);
-#[doc = "< M680X Motorola/Freescale/NXP CPU12"]
-#[doc = "< used on M68HC12/HCS12"]
-pub const CS_MODE_M680X_CPU12: cs_mode = cs_mode(512);
-#[doc = "< M680X Freescale/NXP HCS08 mode"]
-pub const CS_MODE_M680X_HCS08: cs_mode = cs_mode(1024);
-#[doc = "< Classic BPF mode (default)"]
-pub const CS_MODE_BPF_CLASSIC: cs_mode = cs_mode(0);
-#[doc = "< Extended BPF mode"]
-pub const CS_MODE_BPF_EXTENDED: cs_mode = cs_mode(1);
-#[doc = "< RISCV RV32G"]
-pub const CS_MODE_RISCV32: cs_mode = cs_mode(1);
-#[doc = "< RISCV RV64G"]
-pub const CS_MODE_RISCV64: cs_mode = cs_mode(2);
-#[doc = "< RISCV compressed instructure mode"]
-pub const CS_MODE_RISCVC: cs_mode = cs_mode(4);
-#[doc = "< MOS65XXX MOS 6502"]
-pub const CS_MODE_MOS65XX_6502: cs_mode = cs_mode(2);
-#[doc = "< MOS65XXX WDC 65c02"]
-pub const CS_MODE_MOS65XX_65C02: cs_mode = cs_mode(4);
-#[doc = "< MOS65XXX WDC W65c02"]
-pub const CS_MODE_MOS65XX_W65C02: cs_mode = cs_mode(8);
-#[doc = "< MOS65XXX WDC 65816, 8-bit m/x"]
-pub const CS_MODE_MOS65XX_65816: cs_mode = cs_mode(16);
-#[doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"]
-pub const CS_MODE_MOS65XX_65816_LONG_M: cs_mode = cs_mode(32);
-#[doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"]
-pub const CS_MODE_MOS65XX_65816_LONG_X: cs_mode = cs_mode(64);
-pub const CS_MODE_MOS65XX_65816_LONG_MX: cs_mode = cs_mode(96);
+impl cs_mode {
+    #[doc = "< little-endian mode (default mode)"]
+    pub const CS_MODE_LITTLE_ENDIAN: cs_mode = cs_mode(0);
+}
+impl cs_mode {
+    #[doc = "< 32-bit ARM"]
+    pub const CS_MODE_ARM: cs_mode = cs_mode(0);
+}
+impl cs_mode {
+    #[doc = "< 16-bit mode (X86)"]
+    pub const CS_MODE_16: cs_mode = cs_mode(2);
+}
+impl cs_mode {
+    #[doc = "< 32-bit mode (X86)"]
+    pub const CS_MODE_32: cs_mode = cs_mode(4);
+}
+impl cs_mode {
+    #[doc = "< 64-bit mode (X86, PPC)"]
+    pub const CS_MODE_64: cs_mode = cs_mode(8);
+}
+impl cs_mode {
+    #[doc = "< ARM's Thumb mode, including Thumb-2"]
+    pub const CS_MODE_THUMB: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< ARM's Cortex-M series"]
+    pub const CS_MODE_MCLASS: cs_mode = cs_mode(32);
+}
+impl cs_mode {
+    #[doc = "< ARMv8 A32 encodings for ARM"]
+    pub const CS_MODE_V8: cs_mode = cs_mode(64);
+}
+impl cs_mode {
+    #[doc = "< MicroMips mode (MIPS)"]
+    pub const CS_MODE_MICRO: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< Mips III ISA"]
+    pub const CS_MODE_MIPS3: cs_mode = cs_mode(32);
+}
+impl cs_mode {
+    #[doc = "< Mips32r6 ISA"]
+    pub const CS_MODE_MIPS32R6: cs_mode = cs_mode(64);
+}
+impl cs_mode {
+    #[doc = "< Mips II ISA"]
+    pub const CS_MODE_MIPS2: cs_mode = cs_mode(128);
+}
+impl cs_mode {
+    #[doc = "< SparcV9 mode (Sparc)"]
+    pub const CS_MODE_V9: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< Quad Processing eXtensions mode (PPC)"]
+    pub const CS_MODE_QPX: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< Signal Processing Engine mode (PPC)"]
+    pub const CS_MODE_SPE: cs_mode = cs_mode(32);
+}
+impl cs_mode {
+    #[doc = "< Book-E mode (PPC)"]
+    pub const CS_MODE_BOOKE: cs_mode = cs_mode(64);
+}
+impl cs_mode {
+    #[doc = "< M68K 68000 mode"]
+    pub const CS_MODE_M68K_000: cs_mode = cs_mode(2);
+}
+impl cs_mode {
+    #[doc = "< M68K 68010 mode"]
+    pub const CS_MODE_M68K_010: cs_mode = cs_mode(4);
+}
+impl cs_mode {
+    #[doc = "< M68K 68020 mode"]
+    pub const CS_MODE_M68K_020: cs_mode = cs_mode(8);
+}
+impl cs_mode {
+    #[doc = "< M68K 68030 mode"]
+    pub const CS_MODE_M68K_030: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< M68K 68040 mode"]
+    pub const CS_MODE_M68K_040: cs_mode = cs_mode(32);
+}
+impl cs_mode {
+    #[doc = "< M68K 68060 mode"]
+    pub const CS_MODE_M68K_060: cs_mode = cs_mode(64);
+}
+impl cs_mode {
+    #[doc = "< big-endian mode"]
+    pub const CS_MODE_BIG_ENDIAN: cs_mode = cs_mode(2147483648);
+}
+impl cs_mode {
+    #[doc = "< Mips32 ISA (Mips)"]
+    pub const CS_MODE_MIPS32: cs_mode = cs_mode(4);
+}
+impl cs_mode {
+    #[doc = "< Mips64 ISA (Mips)"]
+    pub const CS_MODE_MIPS64: cs_mode = cs_mode(8);
+}
+impl cs_mode {
+    #[doc = "< M680X Hitachi 6301,6303 mode"]
+    pub const CS_MODE_M680X_6301: cs_mode = cs_mode(2);
+}
+impl cs_mode {
+    #[doc = "< M680X Hitachi 6309 mode"]
+    pub const CS_MODE_M680X_6309: cs_mode = cs_mode(4);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola 6800,6802 mode"]
+    pub const CS_MODE_M680X_6800: cs_mode = cs_mode(8);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola 6801,6803 mode"]
+    pub const CS_MODE_M680X_6801: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola/Freescale 6805 mode"]
+    pub const CS_MODE_M680X_6805: cs_mode = cs_mode(32);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola/Freescale/NXP 68HC08 mode"]
+    pub const CS_MODE_M680X_6808: cs_mode = cs_mode(64);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola 6809 mode"]
+    pub const CS_MODE_M680X_6809: cs_mode = cs_mode(128);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola/Freescale/NXP 68HC11 mode"]
+    pub const CS_MODE_M680X_6811: cs_mode = cs_mode(256);
+}
+impl cs_mode {
+    #[doc = "< M680X Motorola/Freescale/NXP CPU12\n< used on M68HC12/HCS12"]
+    pub const CS_MODE_M680X_CPU12: cs_mode = cs_mode(512);
+}
+impl cs_mode {
+    #[doc = "< M680X Freescale/NXP HCS08 mode"]
+    pub const CS_MODE_M680X_HCS08: cs_mode = cs_mode(1024);
+}
+impl cs_mode {
+    #[doc = "< Classic BPF mode (default)"]
+    pub const CS_MODE_BPF_CLASSIC: cs_mode = cs_mode(0);
+}
+impl cs_mode {
+    #[doc = "< Extended BPF mode"]
+    pub const CS_MODE_BPF_EXTENDED: cs_mode = cs_mode(1);
+}
+impl cs_mode {
+    #[doc = "< RISCV RV32G"]
+    pub const CS_MODE_RISCV32: cs_mode = cs_mode(1);
+}
+impl cs_mode {
+    #[doc = "< RISCV RV64G"]
+    pub const CS_MODE_RISCV64: cs_mode = cs_mode(2);
+}
+impl cs_mode {
+    #[doc = "< RISCV compressed instructure mode"]
+    pub const CS_MODE_RISCVC: cs_mode = cs_mode(4);
+}
+impl cs_mode {
+    #[doc = "< MOS65XXX MOS 6502"]
+    pub const CS_MODE_MOS65XX_6502: cs_mode = cs_mode(2);
+}
+impl cs_mode {
+    #[doc = "< MOS65XXX WDC 65c02"]
+    pub const CS_MODE_MOS65XX_65C02: cs_mode = cs_mode(4);
+}
+impl cs_mode {
+    #[doc = "< MOS65XXX WDC W65c02"]
+    pub const CS_MODE_MOS65XX_W65C02: cs_mode = cs_mode(8);
+}
+impl cs_mode {
+    #[doc = "< MOS65XXX WDC 65816, 8-bit m/x"]
+    pub const CS_MODE_MOS65XX_65816: cs_mode = cs_mode(16);
+}
+impl cs_mode {
+    #[doc = "< MOS65XXX WDC 65816, 16-bit m, 8-bit x"]
+    pub const CS_MODE_MOS65XX_65816_LONG_M: cs_mode = cs_mode(32);
+}
+impl cs_mode {
+    #[doc = "< MOS65XXX WDC 65816, 8-bit m, 16-bit x"]
+    pub const CS_MODE_MOS65XX_65816_LONG_X: cs_mode = cs_mode(64);
+}
+impl cs_mode {
+    pub const CS_MODE_MOS65XX_65816_LONG_MX: cs_mode = cs_mode(96);
+}
 impl ::core::ops::BitOr<cs_mode> for cs_mode {
     type Output = Self;
     #[inline]
@@ -169,7 +254,7 @@ impl ::core::ops::BitAndAssign for cs_mode {
         self.0 &= rhs.0;
     }
 }
-#[repr(C)]
+#[repr(transparent)]
 #[doc = " Mode type"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub struct cs_mode(pub libc::c_uint);
@@ -189,10 +274,9 @@ pub type cs_vsnprintf_t = ::core::option::Option<
         ap: *mut __va_list_tag,
     ) -> libc::c_int,
 >;
-#[doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()"]
-#[doc = " By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."]
+#[doc = " User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()\n By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf()."]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_opt_mem {
     pub malloc: cs_malloc_t,
     pub calloc: cs_calloc_t,
@@ -200,28 +284,15 @@ pub struct cs_opt_mem {
     pub free: cs_free_t,
     pub vsnprintf: cs_vsnprintf_t,
 }
-impl Clone for cs_opt_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-#[doc = " Customize mnemonic for instructions with alternative name."]
-#[doc = " To reset existing customized instruction to its default mnemonic,"]
-#[doc = " call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value"]
-#[doc = " for @mnemonic."]
+#[doc = " Customize mnemonic for instructions with alternative name.\n To reset existing customized instruction to its default mnemonic,\n call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value\n for @mnemonic."]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_opt_mnem {
     #[doc = " ID of instruction to be customized."]
     pub id: libc::c_uint,
     #[doc = " Customized instruction mnemonic."]
     pub mnemonic: *const libc::c_char,
 }
-impl Clone for cs_opt_mnem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(u32)]
 #[doc = " Runtime option for the disassembled engine"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -245,26 +316,42 @@ pub enum cs_opt_type {
     #[doc = "< print immediate operands in unsigned form"]
     CS_OPT_UNSIGNED = 8,
 }
-pub mod cs_opt_value {
-    #[doc = " Runtime option value (associated with option type above)"]
-    pub type Type = libc::c_uint;
+impl cs_opt_value {
     #[doc = "< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED."]
-    pub const CS_OPT_OFF: Type = 0;
+    pub const CS_OPT_OFF: cs_opt_value = cs_opt_value(0);
+}
+impl cs_opt_value {
     #[doc = "< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA)."]
-    pub const CS_OPT_ON: Type = 3;
+    pub const CS_OPT_ON: cs_opt_value = cs_opt_value(3);
+}
+impl cs_opt_value {
     #[doc = "< Default asm syntax (CS_OPT_SYNTAX)."]
-    pub const CS_OPT_SYNTAX_DEFAULT: Type = 0;
+    pub const CS_OPT_SYNTAX_DEFAULT: cs_opt_value = cs_opt_value(0);
+}
+impl cs_opt_value {
     #[doc = "< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX)."]
-    pub const CS_OPT_SYNTAX_INTEL: Type = 1;
+    pub const CS_OPT_SYNTAX_INTEL: cs_opt_value = cs_opt_value(1);
+}
+impl cs_opt_value {
     #[doc = "< X86 ATT asm syntax (CS_OPT_SYNTAX)."]
-    pub const CS_OPT_SYNTAX_ATT: Type = 2;
+    pub const CS_OPT_SYNTAX_ATT: cs_opt_value = cs_opt_value(2);
+}
+impl cs_opt_value {
     #[doc = "< Prints register name with only number (CS_OPT_SYNTAX)"]
-    pub const CS_OPT_SYNTAX_NOREGNAME: Type = 3;
+    pub const CS_OPT_SYNTAX_NOREGNAME: cs_opt_value = cs_opt_value(3);
+}
+impl cs_opt_value {
     #[doc = "< X86 Intel Masm syntax (CS_OPT_SYNTAX)."]
-    pub const CS_OPT_SYNTAX_MASM: Type = 4;
+    pub const CS_OPT_SYNTAX_MASM: cs_opt_value = cs_opt_value(4);
+}
+impl cs_opt_value {
     #[doc = "< MOS65XX use $ as hex prefix"]
-    pub const CS_OPT_SYNTAX_MOTOROLA: Type = 5;
+    pub const CS_OPT_SYNTAX_MOTOROLA: cs_opt_value = cs_opt_value(5);
 }
+#[repr(transparent)]
+#[doc = " Runtime option value (associated with option type above)"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct cs_opt_value(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " Common instruction operand types - to be consistent across all architectures."]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -280,12 +367,18 @@ pub enum cs_op_type {
     #[doc = "< Floating-Point operand."]
     CS_OP_FP = 4,
 }
-#[doc = "< Uninitialized/invalid access type."]
-pub const CS_AC_INVALID: cs_ac_type = cs_ac_type(0);
-#[doc = "< Operand read from memory or register."]
-pub const CS_AC_READ: cs_ac_type = cs_ac_type(1);
-#[doc = "< Operand write to memory or register."]
-pub const CS_AC_WRITE: cs_ac_type = cs_ac_type(2);
+impl cs_ac_type {
+    #[doc = "< Uninitialized/invalid access type."]
+    pub const CS_AC_INVALID: cs_ac_type = cs_ac_type(0);
+}
+impl cs_ac_type {
+    #[doc = "< Operand read from memory or register."]
+    pub const CS_AC_READ: cs_ac_type = cs_ac_type(1);
+}
+impl cs_ac_type {
+    #[doc = "< Operand write to memory or register."]
+    pub const CS_AC_WRITE: cs_ac_type = cs_ac_type(2);
+}
 impl ::core::ops::BitOr<cs_ac_type> for cs_ac_type {
     type Output = Self;
     #[inline]
@@ -312,43 +405,47 @@ impl ::core::ops::BitAndAssign for cs_ac_type {
         self.0 &= rhs.0;
     }
 }
-#[repr(C)]
-#[doc = " Common instruction operand access types - to be consistent across all architectures."]
-#[doc = " It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"]
+#[repr(transparent)]
+#[doc = " Common instruction operand access types - to be consistent across all architectures.\n It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub struct cs_ac_type(pub libc::c_uint);
-pub mod cs_group_type {
-    #[doc = " Common instruction groups - to be consistent across all architectures."]
-    pub type Type = libc::c_uint;
+impl cs_group_type {
     #[doc = "< uninitialized/invalid group."]
-    pub const CS_GRP_INVALID: Type = 0;
+    pub const CS_GRP_INVALID: cs_group_type = cs_group_type(0);
+}
+impl cs_group_type {
     #[doc = "< all jump instructions (conditional+direct+indirect jumps)"]
-    pub const CS_GRP_JUMP: Type = 1;
+    pub const CS_GRP_JUMP: cs_group_type = cs_group_type(1);
+}
+impl cs_group_type {
     #[doc = "< all call instructions"]
-    pub const CS_GRP_CALL: Type = 2;
+    pub const CS_GRP_CALL: cs_group_type = cs_group_type(2);
+}
+impl cs_group_type {
     #[doc = "< all return instructions"]
-    pub const CS_GRP_RET: Type = 3;
+    pub const CS_GRP_RET: cs_group_type = cs_group_type(3);
+}
+impl cs_group_type {
     #[doc = "< all interrupt instructions (int+syscall)"]
-    pub const CS_GRP_INT: Type = 4;
+    pub const CS_GRP_INT: cs_group_type = cs_group_type(4);
+}
+impl cs_group_type {
     #[doc = "< all interrupt return instructions"]
-    pub const CS_GRP_IRET: Type = 5;
+    pub const CS_GRP_IRET: cs_group_type = cs_group_type(5);
+}
+impl cs_group_type {
     #[doc = "< all privileged instructions"]
-    pub const CS_GRP_PRIVILEGE: Type = 6;
+    pub const CS_GRP_PRIVILEGE: cs_group_type = cs_group_type(6);
+}
+impl cs_group_type {
     #[doc = "< all relative branching instructions"]
-    pub const CS_GRP_BRANCH_RELATIVE: Type = 7;
-}
-#[doc = "User-defined callback function for SKIPDATA option."]
-#[doc = "See tests/test_skipdata.c for sample code demonstrating this API."]
-#[doc = ""]
-#[doc = "@code: the input buffer containing code to be disassembled."]
-#[doc = "This is the same buffer passed to cs_disasm()."]
-#[doc = "@code_size: size (in bytes) of the above @code buffer."]
-#[doc = "@offset: the position of the currently-examining byte in the input"]
-#[doc = "buffer @code mentioned above."]
-#[doc = "@user_data: user-data passed to cs_option() via @user_data field in"]
-#[doc = "cs_opt_skipdata struct below."]
-#[doc = ""]
-#[doc = "@return: return number of bytes to skip, or 0 to immediately stop disassembling."]
+    pub const CS_GRP_BRANCH_RELATIVE: cs_group_type = cs_group_type(7);
+}
+#[repr(transparent)]
+#[doc = " Common instruction groups - to be consistent across all architectures."]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct cs_group_type(pub libc::c_uint);
+#[doc = "User-defined callback function for SKIPDATA option.\nSee tests/test_skipdata.c for sample code demonstrating this API.\n\n@code: the input buffer containing code to be disassembled.\nThis is the same buffer passed to cs_disasm().\n@code_size: size (in bytes) of the above @code buffer.\n@offset: the position of the currently-examining byte in the input\nbuffer @code mentioned above.\n@user_data: user-data passed to cs_option() via @user_data field in\ncs_opt_skipdata struct below.\n\n@return: return number of bytes to skip, or 0 to immediately stop disassembling."]
 pub type cs_skipdata_cb_t = ::core::option::Option<
     unsafe extern "C" fn(
         code: *const u8,
@@ -359,42 +456,15 @@ pub type cs_skipdata_cb_t = ::core::option::Option<
 >;
 #[doc = " User-customized setup for SKIPDATA option"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_opt_skipdata {
-    #[doc = " Capstone considers data to skip as special \"instructions\"."]
-    #[doc = " User can specify the string for this instruction's \"mnemonic\" here."]
-    #[doc = " By default (if @mnemonic is NULL), Capstone use \".byte\"."]
+    #[doc = " Capstone considers data to skip as special \"instructions\".\n User can specify the string for this instruction's \"mnemonic\" here.\n By default (if @mnemonic is NULL), Capstone use \".byte\"."]
     pub mnemonic: *const libc::c_char,
-    #[doc = " User-defined callback function to be called when Capstone hits data."]
-    #[doc = " If the returned value from this callback is positive (>0), Capstone"]
-    #[doc = " will skip exactly that number of bytes & continue. Otherwise, if"]
-    #[doc = " the callback returns 0, Capstone stops disassembling and returns"]
-    #[doc = " immediately from cs_disasm()"]
-    #[doc = " NOTE: if this callback pointer is NULL, Capstone would skip a number"]
-    #[doc = " of bytes depending on architectures, as following:"]
-    #[doc = " Arm:     2 bytes (Thumb mode) or 4 bytes."]
-    #[doc = " Arm64:   4 bytes."]
-    #[doc = " Mips:    4 bytes."]
-    #[doc = " M680x:   1 byte."]
-    #[doc = " PowerPC: 4 bytes."]
-    #[doc = " Sparc:   4 bytes."]
-    #[doc = " SystemZ: 2 bytes."]
-    #[doc = " X86:     1 bytes."]
-    #[doc = " XCore:   2 bytes."]
-    #[doc = " EVM:     1 bytes."]
-    #[doc = " RISCV:   4 bytes."]
-    #[doc = " WASM:    1 bytes."]
-    #[doc = " MOS65XX: 1 bytes."]
-    #[doc = " BPF:     8 bytes."]
+    #[doc = " User-defined callback function to be called when Capstone hits data.\n If the returned value from this callback is positive (>0), Capstone\n will skip exactly that number of bytes & continue. Otherwise, if\n the callback returns 0, Capstone stops disassembling and returns\n immediately from cs_disasm()\n NOTE: if this callback pointer is NULL, Capstone would skip a number\n of bytes depending on architectures, as following:\n Arm:     2 bytes (Thumb mode) or 4 bytes.\n Arm64:   4 bytes.\n Mips:    4 bytes.\n M680x:   1 byte.\n PowerPC: 4 bytes.\n Sparc:   4 bytes.\n SystemZ: 2 bytes.\n X86:     1 bytes.\n XCore:   2 bytes.\n EVM:     1 bytes.\n RISCV:   4 bytes.\n WASM:    1 bytes.\n MOS65XX: 1 bytes.\n BPF:     8 bytes."]
     pub callback: cs_skipdata_cb_t,
     #[doc = " User-defined data to be passed to @callback function pointer."]
     pub user_data: *mut libc::c_void,
 }
-impl Clone for cs_opt_skipdata {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(u32)]
 #[doc = " ARM shift type"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -620,8 +690,7 @@ pub enum arm_sysreg {
     ARM_SYSREG_SPSR_HYP = 325,
 }
 #[repr(u32)]
-#[doc = " The memory barrier constants map directly to the 4-bit encoding of"]
-#[doc = " the option field for Memory Barrier operations."]
+#[doc = " The memory barrier constants map directly to the 4-bit encoding of\n the option field for Memory Barrier operations."]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum arm_mem_barrier {
     ARM_MB_INVALID = 0,
@@ -742,154 +811,385 @@ pub enum arm_vectordata_type {
     ARM_VECTORDATA_F16U32 = 41,
     ARM_VECTORDATA_U32F16 = 42,
 }
-pub mod arm_reg {
-    #[doc = " ARM registers"]
-    pub type Type = libc::c_uint;
-    pub const ARM_REG_INVALID: Type = 0;
-    pub const ARM_REG_APSR: Type = 1;
-    pub const ARM_REG_APSR_NZCV: Type = 2;
-    pub const ARM_REG_CPSR: Type = 3;
-    pub const ARM_REG_FPEXC: Type = 4;
-    pub const ARM_REG_FPINST: Type = 5;
-    pub const ARM_REG_FPSCR: Type = 6;
-    pub const ARM_REG_FPSCR_NZCV: Type = 7;
-    pub const ARM_REG_FPSID: Type = 8;
-    pub const ARM_REG_ITSTATE: Type = 9;
-    pub const ARM_REG_LR: Type = 10;
-    pub const ARM_REG_PC: Type = 11;
-    pub const ARM_REG_SP: Type = 12;
-    pub const ARM_REG_SPSR: Type = 13;
-    pub const ARM_REG_D0: Type = 14;
-    pub const ARM_REG_D1: Type = 15;
-    pub const ARM_REG_D2: Type = 16;
-    pub const ARM_REG_D3: Type = 17;
-    pub const ARM_REG_D4: Type = 18;
-    pub const ARM_REG_D5: Type = 19;
-    pub const ARM_REG_D6: Type = 20;
-    pub const ARM_REG_D7: Type = 21;
-    pub const ARM_REG_D8: Type = 22;
-    pub const ARM_REG_D9: Type = 23;
-    pub const ARM_REG_D10: Type = 24;
-    pub const ARM_REG_D11: Type = 25;
-    pub const ARM_REG_D12: Type = 26;
-    pub const ARM_REG_D13: Type = 27;
-    pub const ARM_REG_D14: Type = 28;
-    pub const ARM_REG_D15: Type = 29;
-    pub const ARM_REG_D16: Type = 30;
-    pub const ARM_REG_D17: Type = 31;
-    pub const ARM_REG_D18: Type = 32;
-    pub const ARM_REG_D19: Type = 33;
-    pub const ARM_REG_D20: Type = 34;
-    pub const ARM_REG_D21: Type = 35;
-    pub const ARM_REG_D22: Type = 36;
-    pub const ARM_REG_D23: Type = 37;
-    pub const ARM_REG_D24: Type = 38;
-    pub const ARM_REG_D25: Type = 39;
-    pub const ARM_REG_D26: Type = 40;
-    pub const ARM_REG_D27: Type = 41;
-    pub const ARM_REG_D28: Type = 42;
-    pub const ARM_REG_D29: Type = 43;
-    pub const ARM_REG_D30: Type = 44;
-    pub const ARM_REG_D31: Type = 45;
-    pub const ARM_REG_FPINST2: Type = 46;
-    pub const ARM_REG_MVFR0: Type = 47;
-    pub const ARM_REG_MVFR1: Type = 48;
-    pub const ARM_REG_MVFR2: Type = 49;
-    pub const ARM_REG_Q0: Type = 50;
-    pub const ARM_REG_Q1: Type = 51;
-    pub const ARM_REG_Q2: Type = 52;
-    pub const ARM_REG_Q3: Type = 53;
-    pub const ARM_REG_Q4: Type = 54;
-    pub const ARM_REG_Q5: Type = 55;
-    pub const ARM_REG_Q6: Type = 56;
-    pub const ARM_REG_Q7: Type = 57;
-    pub const ARM_REG_Q8: Type = 58;
-    pub const ARM_REG_Q9: Type = 59;
-    pub const ARM_REG_Q10: Type = 60;
-    pub const ARM_REG_Q11: Type = 61;
-    pub const ARM_REG_Q12: Type = 62;
-    pub const ARM_REG_Q13: Type = 63;
-    pub const ARM_REG_Q14: Type = 64;
-    pub const ARM_REG_Q15: Type = 65;
-    pub const ARM_REG_R0: Type = 66;
-    pub const ARM_REG_R1: Type = 67;
-    pub const ARM_REG_R2: Type = 68;
-    pub const ARM_REG_R3: Type = 69;
-    pub const ARM_REG_R4: Type = 70;
-    pub const ARM_REG_R5: Type = 71;
-    pub const ARM_REG_R6: Type = 72;
-    pub const ARM_REG_R7: Type = 73;
-    pub const ARM_REG_R8: Type = 74;
-    pub const ARM_REG_R9: Type = 75;
-    pub const ARM_REG_R10: Type = 76;
-    pub const ARM_REG_R11: Type = 77;
-    pub const ARM_REG_R12: Type = 78;
-    pub const ARM_REG_S0: Type = 79;
-    pub const ARM_REG_S1: Type = 80;
-    pub const ARM_REG_S2: Type = 81;
-    pub const ARM_REG_S3: Type = 82;
-    pub const ARM_REG_S4: Type = 83;
-    pub const ARM_REG_S5: Type = 84;
-    pub const ARM_REG_S6: Type = 85;
-    pub const ARM_REG_S7: Type = 86;
-    pub const ARM_REG_S8: Type = 87;
-    pub const ARM_REG_S9: Type = 88;
-    pub const ARM_REG_S10: Type = 89;
-    pub const ARM_REG_S11: Type = 90;
-    pub const ARM_REG_S12: Type = 91;
-    pub const ARM_REG_S13: Type = 92;
-    pub const ARM_REG_S14: Type = 93;
-    pub const ARM_REG_S15: Type = 94;
-    pub const ARM_REG_S16: Type = 95;
-    pub const ARM_REG_S17: Type = 96;
-    pub const ARM_REG_S18: Type = 97;
-    pub const ARM_REG_S19: Type = 98;
-    pub const ARM_REG_S20: Type = 99;
-    pub const ARM_REG_S21: Type = 100;
-    pub const ARM_REG_S22: Type = 101;
-    pub const ARM_REG_S23: Type = 102;
-    pub const ARM_REG_S24: Type = 103;
-    pub const ARM_REG_S25: Type = 104;
-    pub const ARM_REG_S26: Type = 105;
-    pub const ARM_REG_S27: Type = 106;
-    pub const ARM_REG_S28: Type = 107;
-    pub const ARM_REG_S29: Type = 108;
-    pub const ARM_REG_S30: Type = 109;
-    pub const ARM_REG_S31: Type = 110;
-    pub const ARM_REG_ENDING: Type = 111;
-    pub const ARM_REG_R13: Type = 12;
-    pub const ARM_REG_R14: Type = 10;
-    pub const ARM_REG_R15: Type = 11;
-    pub const ARM_REG_SB: Type = 75;
-    pub const ARM_REG_SL: Type = 76;
-    pub const ARM_REG_FP: Type = 77;
-    pub const ARM_REG_IP: Type = 78;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with ARM_OP_MEM operand type above"]
+impl arm_reg {
+    pub const ARM_REG_INVALID: arm_reg = arm_reg(0);
+}
+impl arm_reg {
+    pub const ARM_REG_APSR: arm_reg = arm_reg(1);
+}
+impl arm_reg {
+    pub const ARM_REG_APSR_NZCV: arm_reg = arm_reg(2);
+}
+impl arm_reg {
+    pub const ARM_REG_CPSR: arm_reg = arm_reg(3);
+}
+impl arm_reg {
+    pub const ARM_REG_FPEXC: arm_reg = arm_reg(4);
+}
+impl arm_reg {
+    pub const ARM_REG_FPINST: arm_reg = arm_reg(5);
+}
+impl arm_reg {
+    pub const ARM_REG_FPSCR: arm_reg = arm_reg(6);
+}
+impl arm_reg {
+    pub const ARM_REG_FPSCR_NZCV: arm_reg = arm_reg(7);
+}
+impl arm_reg {
+    pub const ARM_REG_FPSID: arm_reg = arm_reg(8);
+}
+impl arm_reg {
+    pub const ARM_REG_ITSTATE: arm_reg = arm_reg(9);
+}
+impl arm_reg {
+    pub const ARM_REG_LR: arm_reg = arm_reg(10);
+}
+impl arm_reg {
+    pub const ARM_REG_PC: arm_reg = arm_reg(11);
+}
+impl arm_reg {
+    pub const ARM_REG_SP: arm_reg = arm_reg(12);
+}
+impl arm_reg {
+    pub const ARM_REG_SPSR: arm_reg = arm_reg(13);
+}
+impl arm_reg {
+    pub const ARM_REG_D0: arm_reg = arm_reg(14);
+}
+impl arm_reg {
+    pub const ARM_REG_D1: arm_reg = arm_reg(15);
+}
+impl arm_reg {
+    pub const ARM_REG_D2: arm_reg = arm_reg(16);
+}
+impl arm_reg {
+    pub const ARM_REG_D3: arm_reg = arm_reg(17);
+}
+impl arm_reg {
+    pub const ARM_REG_D4: arm_reg = arm_reg(18);
+}
+impl arm_reg {
+    pub const ARM_REG_D5: arm_reg = arm_reg(19);
+}
+impl arm_reg {
+    pub const ARM_REG_D6: arm_reg = arm_reg(20);
+}
+impl arm_reg {
+    pub const ARM_REG_D7: arm_reg = arm_reg(21);
+}
+impl arm_reg {
+    pub const ARM_REG_D8: arm_reg = arm_reg(22);
+}
+impl arm_reg {
+    pub const ARM_REG_D9: arm_reg = arm_reg(23);
+}
+impl arm_reg {
+    pub const ARM_REG_D10: arm_reg = arm_reg(24);
+}
+impl arm_reg {
+    pub const ARM_REG_D11: arm_reg = arm_reg(25);
+}
+impl arm_reg {
+    pub const ARM_REG_D12: arm_reg = arm_reg(26);
+}
+impl arm_reg {
+    pub const ARM_REG_D13: arm_reg = arm_reg(27);
+}
+impl arm_reg {
+    pub const ARM_REG_D14: arm_reg = arm_reg(28);
+}
+impl arm_reg {
+    pub const ARM_REG_D15: arm_reg = arm_reg(29);
+}
+impl arm_reg {
+    pub const ARM_REG_D16: arm_reg = arm_reg(30);
+}
+impl arm_reg {
+    pub const ARM_REG_D17: arm_reg = arm_reg(31);
+}
+impl arm_reg {
+    pub const ARM_REG_D18: arm_reg = arm_reg(32);
+}
+impl arm_reg {
+    pub const ARM_REG_D19: arm_reg = arm_reg(33);
+}
+impl arm_reg {
+    pub const ARM_REG_D20: arm_reg = arm_reg(34);
+}
+impl arm_reg {
+    pub const ARM_REG_D21: arm_reg = arm_reg(35);
+}
+impl arm_reg {
+    pub const ARM_REG_D22: arm_reg = arm_reg(36);
+}
+impl arm_reg {
+    pub const ARM_REG_D23: arm_reg = arm_reg(37);
+}
+impl arm_reg {
+    pub const ARM_REG_D24: arm_reg = arm_reg(38);
+}
+impl arm_reg {
+    pub const ARM_REG_D25: arm_reg = arm_reg(39);
+}
+impl arm_reg {
+    pub const ARM_REG_D26: arm_reg = arm_reg(40);
+}
+impl arm_reg {
+    pub const ARM_REG_D27: arm_reg = arm_reg(41);
+}
+impl arm_reg {
+    pub const ARM_REG_D28: arm_reg = arm_reg(42);
+}
+impl arm_reg {
+    pub const ARM_REG_D29: arm_reg = arm_reg(43);
+}
+impl arm_reg {
+    pub const ARM_REG_D30: arm_reg = arm_reg(44);
+}
+impl arm_reg {
+    pub const ARM_REG_D31: arm_reg = arm_reg(45);
+}
+impl arm_reg {
+    pub const ARM_REG_FPINST2: arm_reg = arm_reg(46);
+}
+impl arm_reg {
+    pub const ARM_REG_MVFR0: arm_reg = arm_reg(47);
+}
+impl arm_reg {
+    pub const ARM_REG_MVFR1: arm_reg = arm_reg(48);
+}
+impl arm_reg {
+    pub const ARM_REG_MVFR2: arm_reg = arm_reg(49);
+}
+impl arm_reg {
+    pub const ARM_REG_Q0: arm_reg = arm_reg(50);
+}
+impl arm_reg {
+    pub const ARM_REG_Q1: arm_reg = arm_reg(51);
+}
+impl arm_reg {
+    pub const ARM_REG_Q2: arm_reg = arm_reg(52);
+}
+impl arm_reg {
+    pub const ARM_REG_Q3: arm_reg = arm_reg(53);
+}
+impl arm_reg {
+    pub const ARM_REG_Q4: arm_reg = arm_reg(54);
+}
+impl arm_reg {
+    pub const ARM_REG_Q5: arm_reg = arm_reg(55);
+}
+impl arm_reg {
+    pub const ARM_REG_Q6: arm_reg = arm_reg(56);
+}
+impl arm_reg {
+    pub const ARM_REG_Q7: arm_reg = arm_reg(57);
+}
+impl arm_reg {
+    pub const ARM_REG_Q8: arm_reg = arm_reg(58);
+}
+impl arm_reg {
+    pub const ARM_REG_Q9: arm_reg = arm_reg(59);
+}
+impl arm_reg {
+    pub const ARM_REG_Q10: arm_reg = arm_reg(60);
+}
+impl arm_reg {
+    pub const ARM_REG_Q11: arm_reg = arm_reg(61);
+}
+impl arm_reg {
+    pub const ARM_REG_Q12: arm_reg = arm_reg(62);
+}
+impl arm_reg {
+    pub const ARM_REG_Q13: arm_reg = arm_reg(63);
+}
+impl arm_reg {
+    pub const ARM_REG_Q14: arm_reg = arm_reg(64);
+}
+impl arm_reg {
+    pub const ARM_REG_Q15: arm_reg = arm_reg(65);
+}
+impl arm_reg {
+    pub const ARM_REG_R0: arm_reg = arm_reg(66);
+}
+impl arm_reg {
+    pub const ARM_REG_R1: arm_reg = arm_reg(67);
+}
+impl arm_reg {
+    pub const ARM_REG_R2: arm_reg = arm_reg(68);
+}
+impl arm_reg {
+    pub const ARM_REG_R3: arm_reg = arm_reg(69);
+}
+impl arm_reg {
+    pub const ARM_REG_R4: arm_reg = arm_reg(70);
+}
+impl arm_reg {
+    pub const ARM_REG_R5: arm_reg = arm_reg(71);
+}
+impl arm_reg {
+    pub const ARM_REG_R6: arm_reg = arm_reg(72);
+}
+impl arm_reg {
+    pub const ARM_REG_R7: arm_reg = arm_reg(73);
+}
+impl arm_reg {
+    pub const ARM_REG_R8: arm_reg = arm_reg(74);
+}
+impl arm_reg {
+    pub const ARM_REG_R9: arm_reg = arm_reg(75);
+}
+impl arm_reg {
+    pub const ARM_REG_R10: arm_reg = arm_reg(76);
+}
+impl arm_reg {
+    pub const ARM_REG_R11: arm_reg = arm_reg(77);
+}
+impl arm_reg {
+    pub const ARM_REG_R12: arm_reg = arm_reg(78);
+}
+impl arm_reg {
+    pub const ARM_REG_S0: arm_reg = arm_reg(79);
+}
+impl arm_reg {
+    pub const ARM_REG_S1: arm_reg = arm_reg(80);
+}
+impl arm_reg {
+    pub const ARM_REG_S2: arm_reg = arm_reg(81);
+}
+impl arm_reg {
+    pub const ARM_REG_S3: arm_reg = arm_reg(82);
+}
+impl arm_reg {
+    pub const ARM_REG_S4: arm_reg = arm_reg(83);
+}
+impl arm_reg {
+    pub const ARM_REG_S5: arm_reg = arm_reg(84);
+}
+impl arm_reg {
+    pub const ARM_REG_S6: arm_reg = arm_reg(85);
+}
+impl arm_reg {
+    pub const ARM_REG_S7: arm_reg = arm_reg(86);
+}
+impl arm_reg {
+    pub const ARM_REG_S8: arm_reg = arm_reg(87);
+}
+impl arm_reg {
+    pub const ARM_REG_S9: arm_reg = arm_reg(88);
+}
+impl arm_reg {
+    pub const ARM_REG_S10: arm_reg = arm_reg(89);
+}
+impl arm_reg {
+    pub const ARM_REG_S11: arm_reg = arm_reg(90);
+}
+impl arm_reg {
+    pub const ARM_REG_S12: arm_reg = arm_reg(91);
+}
+impl arm_reg {
+    pub const ARM_REG_S13: arm_reg = arm_reg(92);
+}
+impl arm_reg {
+    pub const ARM_REG_S14: arm_reg = arm_reg(93);
+}
+impl arm_reg {
+    pub const ARM_REG_S15: arm_reg = arm_reg(94);
+}
+impl arm_reg {
+    pub const ARM_REG_S16: arm_reg = arm_reg(95);
+}
+impl arm_reg {
+    pub const ARM_REG_S17: arm_reg = arm_reg(96);
+}
+impl arm_reg {
+    pub const ARM_REG_S18: arm_reg = arm_reg(97);
+}
+impl arm_reg {
+    pub const ARM_REG_S19: arm_reg = arm_reg(98);
+}
+impl arm_reg {
+    pub const ARM_REG_S20: arm_reg = arm_reg(99);
+}
+impl arm_reg {
+    pub const ARM_REG_S21: arm_reg = arm_reg(100);
+}
+impl arm_reg {
+    pub const ARM_REG_S22: arm_reg = arm_reg(101);
+}
+impl arm_reg {
+    pub const ARM_REG_S23: arm_reg = arm_reg(102);
+}
+impl arm_reg {
+    pub const ARM_REG_S24: arm_reg = arm_reg(103);
+}
+impl arm_reg {
+    pub const ARM_REG_S25: arm_reg = arm_reg(104);
+}
+impl arm_reg {
+    pub const ARM_REG_S26: arm_reg = arm_reg(105);
+}
+impl arm_reg {
+    pub const ARM_REG_S27: arm_reg = arm_reg(106);
+}
+impl arm_reg {
+    pub const ARM_REG_S28: arm_reg = arm_reg(107);
+}
+impl arm_reg {
+    pub const ARM_REG_S29: arm_reg = arm_reg(108);
+}
+impl arm_reg {
+    pub const ARM_REG_S30: arm_reg = arm_reg(109);
+}
+impl arm_reg {
+    pub const ARM_REG_S31: arm_reg = arm_reg(110);
+}
+impl arm_reg {
+    pub const ARM_REG_ENDING: arm_reg = arm_reg(111);
+}
+impl arm_reg {
+    pub const ARM_REG_R13: arm_reg = arm_reg(12);
+}
+impl arm_reg {
+    pub const ARM_REG_R14: arm_reg = arm_reg(10);
+}
+impl arm_reg {
+    pub const ARM_REG_R15: arm_reg = arm_reg(11);
+}
+impl arm_reg {
+    pub const ARM_REG_SB: arm_reg = arm_reg(75);
+}
+impl arm_reg {
+    pub const ARM_REG_SL: arm_reg = arm_reg(76);
+}
+impl arm_reg {
+    pub const ARM_REG_FP: arm_reg = arm_reg(77);
+}
+impl arm_reg {
+    pub const ARM_REG_IP: arm_reg = arm_reg(78);
+}
+#[repr(transparent)]
+#[doc = " ARM registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct arm_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with ARM_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct arm_op_mem {
     #[doc = "< base register"]
-    pub base: arm_reg::Type,
+    pub base: arm_reg,
     #[doc = "< index register"]
-    pub index: arm_reg::Type,
+    pub index: arm_reg,
     #[doc = "< scale for index register (can be 1, or -1)"]
     pub scale: libc::c_int,
     #[doc = "< displacement/offset value"]
     pub disp: libc::c_int,
-    #[doc = " left-shift on index register, or 0 if irrelevant"]
-    #[doc = " NOTE: this value can also be fetched via operand.shift.value"]
+    #[doc = " left-shift on index register, or 0 if irrelevant\n NOTE: this value can also be fetched via operand.shift.value"]
     pub lshift: libc::c_int,
 }
-impl Clone for arm_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_arm_op {
     #[doc = "< Vector Index for some vector operands (or -1 if irrelevant)"]
     pub vector_index: libc::c_int,
@@ -897,30 +1197,21 @@ pub struct cs_arm_op {
     #[doc = "< operand type"]
     pub type_: arm_op_type,
     pub __bindgen_anon_1: cs_arm_op__bindgen_ty_2,
-    #[doc = " in some instructions, an operand can be subtracted or added to"]
-    #[doc = " the base register,"]
-    #[doc = " if TRUE, this operand is subtracted. otherwise, it is added."]
+    #[doc = " in some instructions, an operand can be subtracted or added to\n the base register,\n if TRUE, this operand is subtracted. otherwise, it is added."]
     pub subtracted: bool,
-    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)"]
-    #[doc = " This field is combined of cs_ac_type."]
-    #[doc = " NOTE: this field is irrelevant if engine is compiled in DIET mode."]
+    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
     pub access: u8,
     #[doc = " Neon lane index for NEON instructions (or -1 if irrelevant)"]
     pub neon_lane: i8,
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_arm_op__bindgen_ty_1 {
     pub type_: arm_shifter,
     pub value: libc::c_uint,
 }
-impl Clone for cs_arm_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_arm_op__bindgen_ty_2 {
     #[doc = "< register value for REG/SYSREG operand"]
     pub reg: libc::c_int,
@@ -933,29 +1224,19 @@ pub union cs_arm_op__bindgen_ty_2 {
     #[doc = "< SETEND instruction's operand type"]
     pub setend: arm_setend_type,
 }
-impl Clone for cs_arm_op__bindgen_ty_2 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_arm_op__bindgen_ty_2 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_arm_op__bindgen_ty_2 {{ union }}")
     }
 }
-impl Clone for cs_arm_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_arm_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?}, access: {:?}, neon_lane: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted , self . access , self . neon_lane)
+        write ! (f , "cs_arm_op {{ vector_index: {:?}, shift: {:?}, type: {:?}, __bindgen_anon_1: {:?}, subtracted: {:?} }}" , self . vector_index , self . shift , self . type_ , self . __bindgen_anon_1 , self . subtracted)
     }
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_arm {
     #[doc = "< User-mode registers to be loaded (for LDM/STM instructions)"]
     pub usermode: bool,
@@ -975,20 +1256,14 @@ pub struct cs_arm {
     pub writeback: bool,
     #[doc = "< Option for some memory barrier instructions"]
     pub mem_barrier: arm_mem_barrier,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_arm_op; 36usize],
 }
-impl Clone for cs_arm {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_arm {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, mem_barrier: {:?}, op_count: {:?}, operands: [...] }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . mem_barrier , self . op_count)
+        write ! (f , "cs_arm {{ usermode: {:?}, vector_size: {:?}, vector_data: {:?}, cps_mode: {:?}, cps_flag: {:?}, cc: {:?}, update_flags: {:?}, writeback: {:?}, mem_barrier: {:?}, operands: {:?} }}" , self . usermode , self . vector_size , self . vector_data , self . cps_mode , self . cps_flag , self . cc , self . update_flags , self . writeback , self . mem_barrier , self . operands)
     }
 }
 #[repr(u32)]
@@ -1469,55 +1744,133 @@ pub enum arm_insn {
     ARM_INS_YIELD = 471,
     ARM_INS_ENDING = 472,
 }
-pub mod arm_insn_group {
-    #[doc = " Group of ARM instructions"]
-    pub type Type = libc::c_uint;
+impl arm_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const ARM_GRP_INVALID: Type = 0;
+    pub const ARM_GRP_INVALID: arm_insn_group = arm_insn_group(0);
+}
+impl arm_insn_group {
     #[doc = "< = CS_GRP_JUMP"]
-    pub const ARM_GRP_JUMP: Type = 1;
+    pub const ARM_GRP_JUMP: arm_insn_group = arm_insn_group(1);
+}
+impl arm_insn_group {
     #[doc = "< = CS_GRP_CALL"]
-    pub const ARM_GRP_CALL: Type = 2;
+    pub const ARM_GRP_CALL: arm_insn_group = arm_insn_group(2);
+}
+impl arm_insn_group {
     #[doc = "< = CS_GRP_INT"]
-    pub const ARM_GRP_INT: Type = 4;
+    pub const ARM_GRP_INT: arm_insn_group = arm_insn_group(4);
+}
+impl arm_insn_group {
     #[doc = "< = CS_GRP_PRIVILEGE"]
-    pub const ARM_GRP_PRIVILEGE: Type = 6;
+    pub const ARM_GRP_PRIVILEGE: arm_insn_group = arm_insn_group(6);
+}
+impl arm_insn_group {
     #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
-    pub const ARM_GRP_BRANCH_RELATIVE: Type = 7;
-    pub const ARM_GRP_CRYPTO: Type = 128;
-    pub const ARM_GRP_DATABARRIER: Type = 129;
-    pub const ARM_GRP_DIVIDE: Type = 130;
-    pub const ARM_GRP_FPARMV8: Type = 131;
-    pub const ARM_GRP_MULTPRO: Type = 132;
-    pub const ARM_GRP_NEON: Type = 133;
-    pub const ARM_GRP_T2EXTRACTPACK: Type = 134;
-    pub const ARM_GRP_THUMB2DSP: Type = 135;
-    pub const ARM_GRP_TRUSTZONE: Type = 136;
-    pub const ARM_GRP_V4T: Type = 137;
-    pub const ARM_GRP_V5T: Type = 138;
-    pub const ARM_GRP_V5TE: Type = 139;
-    pub const ARM_GRP_V6: Type = 140;
-    pub const ARM_GRP_V6T2: Type = 141;
-    pub const ARM_GRP_V7: Type = 142;
-    pub const ARM_GRP_V8: Type = 143;
-    pub const ARM_GRP_VFP2: Type = 144;
-    pub const ARM_GRP_VFP3: Type = 145;
-    pub const ARM_GRP_VFP4: Type = 146;
-    pub const ARM_GRP_ARM: Type = 147;
-    pub const ARM_GRP_MCLASS: Type = 148;
-    pub const ARM_GRP_NOTMCLASS: Type = 149;
-    pub const ARM_GRP_THUMB: Type = 150;
-    pub const ARM_GRP_THUMB1ONLY: Type = 151;
-    pub const ARM_GRP_THUMB2: Type = 152;
-    pub const ARM_GRP_PREV8: Type = 153;
-    pub const ARM_GRP_FPVMLX: Type = 154;
-    pub const ARM_GRP_MULOPS: Type = 155;
-    pub const ARM_GRP_CRC: Type = 156;
-    pub const ARM_GRP_DPVFP: Type = 157;
-    pub const ARM_GRP_V6M: Type = 158;
-    pub const ARM_GRP_VIRTUALIZATION: Type = 159;
-    pub const ARM_GRP_ENDING: Type = 160;
+    pub const ARM_GRP_BRANCH_RELATIVE: arm_insn_group = arm_insn_group(7);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_CRYPTO: arm_insn_group = arm_insn_group(128);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_DATABARRIER: arm_insn_group = arm_insn_group(129);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_DIVIDE: arm_insn_group = arm_insn_group(130);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_FPARMV8: arm_insn_group = arm_insn_group(131);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_MULTPRO: arm_insn_group = arm_insn_group(132);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_NEON: arm_insn_group = arm_insn_group(133);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_T2EXTRACTPACK: arm_insn_group = arm_insn_group(134);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_THUMB2DSP: arm_insn_group = arm_insn_group(135);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_TRUSTZONE: arm_insn_group = arm_insn_group(136);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V4T: arm_insn_group = arm_insn_group(137);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V5T: arm_insn_group = arm_insn_group(138);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V5TE: arm_insn_group = arm_insn_group(139);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V6: arm_insn_group = arm_insn_group(140);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V6T2: arm_insn_group = arm_insn_group(141);
 }
+impl arm_insn_group {
+    pub const ARM_GRP_V7: arm_insn_group = arm_insn_group(142);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V8: arm_insn_group = arm_insn_group(143);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_VFP2: arm_insn_group = arm_insn_group(144);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_VFP3: arm_insn_group = arm_insn_group(145);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_VFP4: arm_insn_group = arm_insn_group(146);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_ARM: arm_insn_group = arm_insn_group(147);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_MCLASS: arm_insn_group = arm_insn_group(148);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_NOTMCLASS: arm_insn_group = arm_insn_group(149);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_THUMB: arm_insn_group = arm_insn_group(150);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_THUMB1ONLY: arm_insn_group = arm_insn_group(151);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_THUMB2: arm_insn_group = arm_insn_group(152);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_PREV8: arm_insn_group = arm_insn_group(153);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_FPVMLX: arm_insn_group = arm_insn_group(154);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_MULOPS: arm_insn_group = arm_insn_group(155);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_CRC: arm_insn_group = arm_insn_group(156);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_DPVFP: arm_insn_group = arm_insn_group(157);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_V6M: arm_insn_group = arm_insn_group(158);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_VIRTUALIZATION: arm_insn_group = arm_insn_group(159);
+}
+impl arm_insn_group {
+    pub const ARM_GRP_ENDING: arm_insn_group = arm_insn_group(160);
+}
+#[repr(transparent)]
+#[doc = " Group of ARM instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct arm_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " ARM64 shift type"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -1581,7 +1934,9 @@ pub enum arm64_cc {
     #[doc = "< Always (unconditional):   Always (unconditional)"]
     ARM64_CC_NV = 16,
 }
-pub const ARM64_SYSREG_DBGDTRTX_EL0: arm64_sysreg = arm64_sysreg::ARM64_SYSREG_DBGDTRRX_EL0;
+impl arm64_sysreg {
+    pub const ARM64_SYSREG_DBGDTRTX_EL0: arm64_sysreg = arm64_sysreg::ARM64_SYSREG_DBGDTRRX_EL0;
+}
 #[repr(u32)]
 #[doc = " System registers"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -2641,636 +2996,1239 @@ pub enum arm64_prefetch_op {
     ARM64_PRFM_PSTL3KEEP = 21,
     ARM64_PRFM_PSTL3STRM = 22,
 }
-pub mod arm64_reg {
-    #[doc = " ARM64 registers"]
-    pub type Type = libc::c_uint;
-    pub const ARM64_REG_INVALID: Type = 0;
-    pub const ARM64_REG_FFR: Type = 1;
-    pub const ARM64_REG_FP: Type = 2;
-    pub const ARM64_REG_LR: Type = 3;
-    pub const ARM64_REG_NZCV: Type = 4;
-    pub const ARM64_REG_SP: Type = 5;
-    pub const ARM64_REG_WSP: Type = 6;
-    pub const ARM64_REG_WZR: Type = 7;
-    pub const ARM64_REG_XZR: Type = 8;
-    pub const ARM64_REG_B0: Type = 9;
-    pub const ARM64_REG_B1: Type = 10;
-    pub const ARM64_REG_B2: Type = 11;
-    pub const ARM64_REG_B3: Type = 12;
-    pub const ARM64_REG_B4: Type = 13;
-    pub const ARM64_REG_B5: Type = 14;
-    pub const ARM64_REG_B6: Type = 15;
-    pub const ARM64_REG_B7: Type = 16;
-    pub const ARM64_REG_B8: Type = 17;
-    pub const ARM64_REG_B9: Type = 18;
-    pub const ARM64_REG_B10: Type = 19;
-    pub const ARM64_REG_B11: Type = 20;
-    pub const ARM64_REG_B12: Type = 21;
-    pub const ARM64_REG_B13: Type = 22;
-    pub const ARM64_REG_B14: Type = 23;
-    pub const ARM64_REG_B15: Type = 24;
-    pub const ARM64_REG_B16: Type = 25;
-    pub const ARM64_REG_B17: Type = 26;
-    pub const ARM64_REG_B18: Type = 27;
-    pub const ARM64_REG_B19: Type = 28;
-    pub const ARM64_REG_B20: Type = 29;
-    pub const ARM64_REG_B21: Type = 30;
-    pub const ARM64_REG_B22: Type = 31;
-    pub const ARM64_REG_B23: Type = 32;
-    pub const ARM64_REG_B24: Type = 33;
-    pub const ARM64_REG_B25: Type = 34;
-    pub const ARM64_REG_B26: Type = 35;
-    pub const ARM64_REG_B27: Type = 36;
-    pub const ARM64_REG_B28: Type = 37;
-    pub const ARM64_REG_B29: Type = 38;
-    pub const ARM64_REG_B30: Type = 39;
-    pub const ARM64_REG_B31: Type = 40;
-    pub const ARM64_REG_D0: Type = 41;
-    pub const ARM64_REG_D1: Type = 42;
-    pub const ARM64_REG_D2: Type = 43;
-    pub const ARM64_REG_D3: Type = 44;
-    pub const ARM64_REG_D4: Type = 45;
-    pub const ARM64_REG_D5: Type = 46;
-    pub const ARM64_REG_D6: Type = 47;
-    pub const ARM64_REG_D7: Type = 48;
-    pub const ARM64_REG_D8: Type = 49;
-    pub const ARM64_REG_D9: Type = 50;
-    pub const ARM64_REG_D10: Type = 51;
-    pub const ARM64_REG_D11: Type = 52;
-    pub const ARM64_REG_D12: Type = 53;
-    pub const ARM64_REG_D13: Type = 54;
-    pub const ARM64_REG_D14: Type = 55;
-    pub const ARM64_REG_D15: Type = 56;
-    pub const ARM64_REG_D16: Type = 57;
-    pub const ARM64_REG_D17: Type = 58;
-    pub const ARM64_REG_D18: Type = 59;
-    pub const ARM64_REG_D19: Type = 60;
-    pub const ARM64_REG_D20: Type = 61;
-    pub const ARM64_REG_D21: Type = 62;
-    pub const ARM64_REG_D22: Type = 63;
-    pub const ARM64_REG_D23: Type = 64;
-    pub const ARM64_REG_D24: Type = 65;
-    pub const ARM64_REG_D25: Type = 66;
-    pub const ARM64_REG_D26: Type = 67;
-    pub const ARM64_REG_D27: Type = 68;
-    pub const ARM64_REG_D28: Type = 69;
-    pub const ARM64_REG_D29: Type = 70;
-    pub const ARM64_REG_D30: Type = 71;
-    pub const ARM64_REG_D31: Type = 72;
-    pub const ARM64_REG_H0: Type = 73;
-    pub const ARM64_REG_H1: Type = 74;
-    pub const ARM64_REG_H2: Type = 75;
-    pub const ARM64_REG_H3: Type = 76;
-    pub const ARM64_REG_H4: Type = 77;
-    pub const ARM64_REG_H5: Type = 78;
-    pub const ARM64_REG_H6: Type = 79;
-    pub const ARM64_REG_H7: Type = 80;
-    pub const ARM64_REG_H8: Type = 81;
-    pub const ARM64_REG_H9: Type = 82;
-    pub const ARM64_REG_H10: Type = 83;
-    pub const ARM64_REG_H11: Type = 84;
-    pub const ARM64_REG_H12: Type = 85;
-    pub const ARM64_REG_H13: Type = 86;
-    pub const ARM64_REG_H14: Type = 87;
-    pub const ARM64_REG_H15: Type = 88;
-    pub const ARM64_REG_H16: Type = 89;
-    pub const ARM64_REG_H17: Type = 90;
-    pub const ARM64_REG_H18: Type = 91;
-    pub const ARM64_REG_H19: Type = 92;
-    pub const ARM64_REG_H20: Type = 93;
-    pub const ARM64_REG_H21: Type = 94;
-    pub const ARM64_REG_H22: Type = 95;
-    pub const ARM64_REG_H23: Type = 96;
-    pub const ARM64_REG_H24: Type = 97;
-    pub const ARM64_REG_H25: Type = 98;
-    pub const ARM64_REG_H26: Type = 99;
-    pub const ARM64_REG_H27: Type = 100;
-    pub const ARM64_REG_H28: Type = 101;
-    pub const ARM64_REG_H29: Type = 102;
-    pub const ARM64_REG_H30: Type = 103;
-    pub const ARM64_REG_H31: Type = 104;
-    pub const ARM64_REG_P0: Type = 105;
-    pub const ARM64_REG_P1: Type = 106;
-    pub const ARM64_REG_P2: Type = 107;
-    pub const ARM64_REG_P3: Type = 108;
-    pub const ARM64_REG_P4: Type = 109;
-    pub const ARM64_REG_P5: Type = 110;
-    pub const ARM64_REG_P6: Type = 111;
-    pub const ARM64_REG_P7: Type = 112;
-    pub const ARM64_REG_P8: Type = 113;
-    pub const ARM64_REG_P9: Type = 114;
-    pub const ARM64_REG_P10: Type = 115;
-    pub const ARM64_REG_P11: Type = 116;
-    pub const ARM64_REG_P12: Type = 117;
-    pub const ARM64_REG_P13: Type = 118;
-    pub const ARM64_REG_P14: Type = 119;
-    pub const ARM64_REG_P15: Type = 120;
-    pub const ARM64_REG_Q0: Type = 121;
-    pub const ARM64_REG_Q1: Type = 122;
-    pub const ARM64_REG_Q2: Type = 123;
-    pub const ARM64_REG_Q3: Type = 124;
-    pub const ARM64_REG_Q4: Type = 125;
-    pub const ARM64_REG_Q5: Type = 126;
-    pub const ARM64_REG_Q6: Type = 127;
-    pub const ARM64_REG_Q7: Type = 128;
-    pub const ARM64_REG_Q8: Type = 129;
-    pub const ARM64_REG_Q9: Type = 130;
-    pub const ARM64_REG_Q10: Type = 131;
-    pub const ARM64_REG_Q11: Type = 132;
-    pub const ARM64_REG_Q12: Type = 133;
-    pub const ARM64_REG_Q13: Type = 134;
-    pub const ARM64_REG_Q14: Type = 135;
-    pub const ARM64_REG_Q15: Type = 136;
-    pub const ARM64_REG_Q16: Type = 137;
-    pub const ARM64_REG_Q17: Type = 138;
-    pub const ARM64_REG_Q18: Type = 139;
-    pub const ARM64_REG_Q19: Type = 140;
-    pub const ARM64_REG_Q20: Type = 141;
-    pub const ARM64_REG_Q21: Type = 142;
-    pub const ARM64_REG_Q22: Type = 143;
-    pub const ARM64_REG_Q23: Type = 144;
-    pub const ARM64_REG_Q24: Type = 145;
-    pub const ARM64_REG_Q25: Type = 146;
-    pub const ARM64_REG_Q26: Type = 147;
-    pub const ARM64_REG_Q27: Type = 148;
-    pub const ARM64_REG_Q28: Type = 149;
-    pub const ARM64_REG_Q29: Type = 150;
-    pub const ARM64_REG_Q30: Type = 151;
-    pub const ARM64_REG_Q31: Type = 152;
-    pub const ARM64_REG_S0: Type = 153;
-    pub const ARM64_REG_S1: Type = 154;
-    pub const ARM64_REG_S2: Type = 155;
-    pub const ARM64_REG_S3: Type = 156;
-    pub const ARM64_REG_S4: Type = 157;
-    pub const ARM64_REG_S5: Type = 158;
-    pub const ARM64_REG_S6: Type = 159;
-    pub const ARM64_REG_S7: Type = 160;
-    pub const ARM64_REG_S8: Type = 161;
-    pub const ARM64_REG_S9: Type = 162;
-    pub const ARM64_REG_S10: Type = 163;
-    pub const ARM64_REG_S11: Type = 164;
-    pub const ARM64_REG_S12: Type = 165;
-    pub const ARM64_REG_S13: Type = 166;
-    pub const ARM64_REG_S14: Type = 167;
-    pub const ARM64_REG_S15: Type = 168;
-    pub const ARM64_REG_S16: Type = 169;
-    pub const ARM64_REG_S17: Type = 170;
-    pub const ARM64_REG_S18: Type = 171;
-    pub const ARM64_REG_S19: Type = 172;
-    pub const ARM64_REG_S20: Type = 173;
-    pub const ARM64_REG_S21: Type = 174;
-    pub const ARM64_REG_S22: Type = 175;
-    pub const ARM64_REG_S23: Type = 176;
-    pub const ARM64_REG_S24: Type = 177;
-    pub const ARM64_REG_S25: Type = 178;
-    pub const ARM64_REG_S26: Type = 179;
-    pub const ARM64_REG_S27: Type = 180;
-    pub const ARM64_REG_S28: Type = 181;
-    pub const ARM64_REG_S29: Type = 182;
-    pub const ARM64_REG_S30: Type = 183;
-    pub const ARM64_REG_S31: Type = 184;
-    pub const ARM64_REG_W0: Type = 185;
-    pub const ARM64_REG_W1: Type = 186;
-    pub const ARM64_REG_W2: Type = 187;
-    pub const ARM64_REG_W3: Type = 188;
-    pub const ARM64_REG_W4: Type = 189;
-    pub const ARM64_REG_W5: Type = 190;
-    pub const ARM64_REG_W6: Type = 191;
-    pub const ARM64_REG_W7: Type = 192;
-    pub const ARM64_REG_W8: Type = 193;
-    pub const ARM64_REG_W9: Type = 194;
-    pub const ARM64_REG_W10: Type = 195;
-    pub const ARM64_REG_W11: Type = 196;
-    pub const ARM64_REG_W12: Type = 197;
-    pub const ARM64_REG_W13: Type = 198;
-    pub const ARM64_REG_W14: Type = 199;
-    pub const ARM64_REG_W15: Type = 200;
-    pub const ARM64_REG_W16: Type = 201;
-    pub const ARM64_REG_W17: Type = 202;
-    pub const ARM64_REG_W18: Type = 203;
-    pub const ARM64_REG_W19: Type = 204;
-    pub const ARM64_REG_W20: Type = 205;
-    pub const ARM64_REG_W21: Type = 206;
-    pub const ARM64_REG_W22: Type = 207;
-    pub const ARM64_REG_W23: Type = 208;
-    pub const ARM64_REG_W24: Type = 209;
-    pub const ARM64_REG_W25: Type = 210;
-    pub const ARM64_REG_W26: Type = 211;
-    pub const ARM64_REG_W27: Type = 212;
-    pub const ARM64_REG_W28: Type = 213;
-    pub const ARM64_REG_W29: Type = 214;
-    pub const ARM64_REG_W30: Type = 215;
-    pub const ARM64_REG_X0: Type = 216;
-    pub const ARM64_REG_X1: Type = 217;
-    pub const ARM64_REG_X2: Type = 218;
-    pub const ARM64_REG_X3: Type = 219;
-    pub const ARM64_REG_X4: Type = 220;
-    pub const ARM64_REG_X5: Type = 221;
-    pub const ARM64_REG_X6: Type = 222;
-    pub const ARM64_REG_X7: Type = 223;
-    pub const ARM64_REG_X8: Type = 224;
-    pub const ARM64_REG_X9: Type = 225;
-    pub const ARM64_REG_X10: Type = 226;
-    pub const ARM64_REG_X11: Type = 227;
-    pub const ARM64_REG_X12: Type = 228;
-    pub const ARM64_REG_X13: Type = 229;
-    pub const ARM64_REG_X14: Type = 230;
-    pub const ARM64_REG_X15: Type = 231;
-    pub const ARM64_REG_X16: Type = 232;
-    pub const ARM64_REG_X17: Type = 233;
-    pub const ARM64_REG_X18: Type = 234;
-    pub const ARM64_REG_X19: Type = 235;
-    pub const ARM64_REG_X20: Type = 236;
-    pub const ARM64_REG_X21: Type = 237;
-    pub const ARM64_REG_X22: Type = 238;
-    pub const ARM64_REG_X23: Type = 239;
-    pub const ARM64_REG_X24: Type = 240;
-    pub const ARM64_REG_X25: Type = 241;
-    pub const ARM64_REG_X26: Type = 242;
-    pub const ARM64_REG_X27: Type = 243;
-    pub const ARM64_REG_X28: Type = 244;
-    pub const ARM64_REG_Z0: Type = 245;
-    pub const ARM64_REG_Z1: Type = 246;
-    pub const ARM64_REG_Z2: Type = 247;
-    pub const ARM64_REG_Z3: Type = 248;
-    pub const ARM64_REG_Z4: Type = 249;
-    pub const ARM64_REG_Z5: Type = 250;
-    pub const ARM64_REG_Z6: Type = 251;
-    pub const ARM64_REG_Z7: Type = 252;
-    pub const ARM64_REG_Z8: Type = 253;
-    pub const ARM64_REG_Z9: Type = 254;
-    pub const ARM64_REG_Z10: Type = 255;
-    pub const ARM64_REG_Z11: Type = 256;
-    pub const ARM64_REG_Z12: Type = 257;
-    pub const ARM64_REG_Z13: Type = 258;
-    pub const ARM64_REG_Z14: Type = 259;
-    pub const ARM64_REG_Z15: Type = 260;
-    pub const ARM64_REG_Z16: Type = 261;
-    pub const ARM64_REG_Z17: Type = 262;
-    pub const ARM64_REG_Z18: Type = 263;
-    pub const ARM64_REG_Z19: Type = 264;
-    pub const ARM64_REG_Z20: Type = 265;
-    pub const ARM64_REG_Z21: Type = 266;
-    pub const ARM64_REG_Z22: Type = 267;
-    pub const ARM64_REG_Z23: Type = 268;
-    pub const ARM64_REG_Z24: Type = 269;
-    pub const ARM64_REG_Z25: Type = 270;
-    pub const ARM64_REG_Z26: Type = 271;
-    pub const ARM64_REG_Z27: Type = 272;
-    pub const ARM64_REG_Z28: Type = 273;
-    pub const ARM64_REG_Z29: Type = 274;
-    pub const ARM64_REG_Z30: Type = 275;
-    pub const ARM64_REG_Z31: Type = 276;
-    pub const ARM64_REG_V0: Type = 277;
-    pub const ARM64_REG_V1: Type = 278;
-    pub const ARM64_REG_V2: Type = 279;
-    pub const ARM64_REG_V3: Type = 280;
-    pub const ARM64_REG_V4: Type = 281;
-    pub const ARM64_REG_V5: Type = 282;
-    pub const ARM64_REG_V6: Type = 283;
-    pub const ARM64_REG_V7: Type = 284;
-    pub const ARM64_REG_V8: Type = 285;
-    pub const ARM64_REG_V9: Type = 286;
-    pub const ARM64_REG_V10: Type = 287;
-    pub const ARM64_REG_V11: Type = 288;
-    pub const ARM64_REG_V12: Type = 289;
-    pub const ARM64_REG_V13: Type = 290;
-    pub const ARM64_REG_V14: Type = 291;
-    pub const ARM64_REG_V15: Type = 292;
-    pub const ARM64_REG_V16: Type = 293;
-    pub const ARM64_REG_V17: Type = 294;
-    pub const ARM64_REG_V18: Type = 295;
-    pub const ARM64_REG_V19: Type = 296;
-    pub const ARM64_REG_V20: Type = 297;
-    pub const ARM64_REG_V21: Type = 298;
-    pub const ARM64_REG_V22: Type = 299;
-    pub const ARM64_REG_V23: Type = 300;
-    pub const ARM64_REG_V24: Type = 301;
-    pub const ARM64_REG_V25: Type = 302;
-    pub const ARM64_REG_V26: Type = 303;
-    pub const ARM64_REG_V27: Type = 304;
-    pub const ARM64_REG_V28: Type = 305;
-    pub const ARM64_REG_V29: Type = 306;
-    pub const ARM64_REG_V30: Type = 307;
-    pub const ARM64_REG_V31: Type = 308;
-    pub const ARM64_REG_ENDING: Type = 309;
-    pub const ARM64_REG_IP0: Type = 232;
-    pub const ARM64_REG_IP1: Type = 233;
-    pub const ARM64_REG_X29: Type = 2;
-    pub const ARM64_REG_X30: Type = 3;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with ARM64_OP_MEM operand type above"]
-#[repr(C)]
-#[derive(Debug, Copy)]
-pub struct arm64_op_mem {
-    #[doc = "< base register"]
-    pub base: arm64_reg::Type,
-    #[doc = "< index register"]
-    pub index: arm64_reg::Type,
-    #[doc = "< displacement/offset value"]
-    pub disp: i32,
+impl arm64_reg {
+    pub const ARM64_REG_INVALID: arm64_reg = arm64_reg(0);
 }
-impl Clone for arm64_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
+impl arm64_reg {
+    pub const ARM64_REG_FFR: arm64_reg = arm64_reg(1);
 }
-#[doc = " Instruction operand"]
-#[repr(C)]
-#[derive(Copy)]
-pub struct cs_arm64_op {
-    #[doc = "< Vector Index for some vector operands (or -1 if irrelevant)"]
-    pub vector_index: libc::c_int,
-    #[doc = "< Vector Arrangement Specifier"]
-    pub vas: arm64_vas,
-    pub shift: cs_arm64_op__bindgen_ty_1,
-    #[doc = "< extender type of this operand"]
-    pub ext: arm64_extender,
-    #[doc = "< operand type"]
-    pub type_: arm64_op_type,
-    pub __bindgen_anon_1: cs_arm64_op__bindgen_ty_2,
-    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)"]
-    #[doc = " This field is combined of cs_ac_type."]
-    #[doc = " NOTE: this field is irrelevant if engine is compiled in DIET mode."]
-    pub access: u8,
+impl arm64_reg {
+    pub const ARM64_REG_FP: arm64_reg = arm64_reg(2);
 }
-#[repr(C)]
-#[derive(Debug, Copy)]
-pub struct cs_arm64_op__bindgen_ty_1 {
-    #[doc = "< shifter type of this operand"]
-    pub type_: arm64_shifter,
-    #[doc = "< shifter value of this operand"]
-    pub value: libc::c_uint,
+impl arm64_reg {
+    pub const ARM64_REG_LR: arm64_reg = arm64_reg(3);
 }
-impl Clone for cs_arm64_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
+impl arm64_reg {
+    pub const ARM64_REG_NZCV: arm64_reg = arm64_reg(4);
 }
-#[repr(C)]
-#[derive(Copy)]
-pub union cs_arm64_op__bindgen_ty_2 {
-    #[doc = "< register value for REG operand"]
-    pub reg: arm64_reg::Type,
-    #[doc = "< immediate value, or index for C-IMM or IMM operand"]
-    pub imm: i64,
-    #[doc = "< floating point value for FP operand"]
-    pub fp: f64,
-    #[doc = "< base/index/scale/disp value for MEM operand"]
-    pub mem: arm64_op_mem,
-    #[doc = "< PState field of MSR instruction."]
-    pub pstate: arm64_pstate,
-    #[doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)"]
-    pub sys: arm64_sys_op,
-    #[doc = "< PRFM operation."]
-    pub prefetch: arm64_prefetch_op,
-    #[doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."]
-    pub barrier: arm64_barrier_op,
+impl arm64_reg {
+    pub const ARM64_REG_SP: arm64_reg = arm64_reg(5);
 }
-impl Clone for cs_arm64_op__bindgen_ty_2 {
-    fn clone(&self) -> Self {
-        *self
-    }
+impl arm64_reg {
+    pub const ARM64_REG_WSP: arm64_reg = arm64_reg(6);
 }
-impl ::core::fmt::Debug for cs_arm64_op__bindgen_ty_2 {
-    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write!(f, "cs_arm64_op__bindgen_ty_2 {{ union }}")
-    }
+impl arm64_reg {
+    pub const ARM64_REG_WZR: arm64_reg = arm64_reg(7);
 }
-impl Clone for cs_arm64_op {
-    fn clone(&self) -> Self {
-        *self
-    }
+impl arm64_reg {
+    pub const ARM64_REG_XZR: arm64_reg = arm64_reg(8);
 }
-impl ::core::fmt::Debug for cs_arm64_op {
-    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . __bindgen_anon_1 , self . access)
-    }
+impl arm64_reg {
+    pub const ARM64_REG_B0: arm64_reg = arm64_reg(9);
 }
-#[doc = " Instruction structure"]
-#[repr(C)]
-#[derive(Copy)]
-pub struct cs_arm64 {
-    #[doc = "< conditional code for this insn"]
-    pub cc: arm64_cc,
-    #[doc = "< does this insn update flags?"]
-    pub update_flags: bool,
-    #[doc = "< does this insn request writeback? 'True' means 'yes'"]
-    pub writeback: bool,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
-    pub op_count: u8,
-    #[doc = "< operands for this instruction."]
-    pub operands: [cs_arm64_op; 8usize],
+impl arm64_reg {
+    pub const ARM64_REG_B1: arm64_reg = arm64_reg(10);
 }
-impl Clone for cs_arm64 {
-    fn clone(&self) -> Self {
-        *self
-    }
+impl arm64_reg {
+    pub const ARM64_REG_B2: arm64_reg = arm64_reg(11);
 }
-impl ::core::fmt::Debug for cs_arm64 {
-    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, op_count: {:?}, operands: {:?} }}" , self . cc , self . update_flags , self . writeback , self . op_count , self . operands)
-    }
+impl arm64_reg {
+    pub const ARM64_REG_B3: arm64_reg = arm64_reg(12);
 }
-#[repr(u32)]
-#[doc = " ARM64 instruction"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum arm64_insn {
-    ARM64_INS_INVALID = 0,
-    ARM64_INS_ABS = 1,
-    ARM64_INS_ADC = 2,
-    ARM64_INS_ADCS = 3,
-    ARM64_INS_ADD = 4,
-    ARM64_INS_ADDHN = 5,
-    ARM64_INS_ADDHN2 = 6,
-    ARM64_INS_ADDP = 7,
-    ARM64_INS_ADDPL = 8,
-    ARM64_INS_ADDS = 9,
-    ARM64_INS_ADDV = 10,
-    ARM64_INS_ADDVL = 11,
-    ARM64_INS_ADR = 12,
-    ARM64_INS_ADRP = 13,
-    ARM64_INS_AESD = 14,
-    ARM64_INS_AESE = 15,
-    ARM64_INS_AESIMC = 16,
-    ARM64_INS_AESMC = 17,
-    ARM64_INS_AND = 18,
-    ARM64_INS_ANDS = 19,
-    ARM64_INS_ANDV = 20,
-    ARM64_INS_ASR = 21,
-    ARM64_INS_ASRD = 22,
-    ARM64_INS_ASRR = 23,
-    ARM64_INS_ASRV = 24,
-    ARM64_INS_AUTDA = 25,
-    ARM64_INS_AUTDB = 26,
-    ARM64_INS_AUTDZA = 27,
-    ARM64_INS_AUTDZB = 28,
-    ARM64_INS_AUTIA = 29,
-    ARM64_INS_AUTIA1716 = 30,
-    ARM64_INS_AUTIASP = 31,
-    ARM64_INS_AUTIAZ = 32,
-    ARM64_INS_AUTIB = 33,
-    ARM64_INS_AUTIB1716 = 34,
-    ARM64_INS_AUTIBSP = 35,
-    ARM64_INS_AUTIBZ = 36,
-    ARM64_INS_AUTIZA = 37,
-    ARM64_INS_AUTIZB = 38,
-    ARM64_INS_B = 39,
-    ARM64_INS_BCAX = 40,
-    ARM64_INS_BFM = 41,
-    ARM64_INS_BIC = 42,
-    ARM64_INS_BICS = 43,
-    ARM64_INS_BIF = 44,
-    ARM64_INS_BIT = 45,
-    ARM64_INS_BL = 46,
-    ARM64_INS_BLR = 47,
-    ARM64_INS_BLRAA = 48,
-    ARM64_INS_BLRAAZ = 49,
-    ARM64_INS_BLRAB = 50,
-    ARM64_INS_BLRABZ = 51,
-    ARM64_INS_BR = 52,
-    ARM64_INS_BRAA = 53,
-    ARM64_INS_BRAAZ = 54,
-    ARM64_INS_BRAB = 55,
-    ARM64_INS_BRABZ = 56,
-    ARM64_INS_BRK = 57,
-    ARM64_INS_BRKA = 58,
-    ARM64_INS_BRKAS = 59,
-    ARM64_INS_BRKB = 60,
-    ARM64_INS_BRKBS = 61,
-    ARM64_INS_BRKN = 62,
-    ARM64_INS_BRKNS = 63,
-    ARM64_INS_BRKPA = 64,
-    ARM64_INS_BRKPAS = 65,
-    ARM64_INS_BRKPB = 66,
-    ARM64_INS_BRKPBS = 67,
-    ARM64_INS_BSL = 68,
-    ARM64_INS_CAS = 69,
-    ARM64_INS_CASA = 70,
-    ARM64_INS_CASAB = 71,
-    ARM64_INS_CASAH = 72,
-    ARM64_INS_CASAL = 73,
-    ARM64_INS_CASALB = 74,
-    ARM64_INS_CASALH = 75,
-    ARM64_INS_CASB = 76,
-    ARM64_INS_CASH = 77,
-    ARM64_INS_CASL = 78,
-    ARM64_INS_CASLB = 79,
-    ARM64_INS_CASLH = 80,
-    ARM64_INS_CASP = 81,
-    ARM64_INS_CASPA = 82,
-    ARM64_INS_CASPAL = 83,
-    ARM64_INS_CASPL = 84,
-    ARM64_INS_CBNZ = 85,
-    ARM64_INS_CBZ = 86,
-    ARM64_INS_CCMN = 87,
-    ARM64_INS_CCMP = 88,
-    ARM64_INS_CFINV = 89,
-    ARM64_INS_CINC = 90,
-    ARM64_INS_CINV = 91,
-    ARM64_INS_CLASTA = 92,
-    ARM64_INS_CLASTB = 93,
-    ARM64_INS_CLREX = 94,
-    ARM64_INS_CLS = 95,
-    ARM64_INS_CLZ = 96,
-    ARM64_INS_CMEQ = 97,
-    ARM64_INS_CMGE = 98,
-    ARM64_INS_CMGT = 99,
-    ARM64_INS_CMHI = 100,
-    ARM64_INS_CMHS = 101,
-    ARM64_INS_CMLE = 102,
-    ARM64_INS_CMLO = 103,
-    ARM64_INS_CMLS = 104,
-    ARM64_INS_CMLT = 105,
-    ARM64_INS_CMN = 106,
-    ARM64_INS_CMP = 107,
-    ARM64_INS_CMPEQ = 108,
-    ARM64_INS_CMPGE = 109,
-    ARM64_INS_CMPGT = 110,
-    ARM64_INS_CMPHI = 111,
-    ARM64_INS_CMPHS = 112,
-    ARM64_INS_CMPLE = 113,
-    ARM64_INS_CMPLO = 114,
-    ARM64_INS_CMPLS = 115,
-    ARM64_INS_CMPLT = 116,
-    ARM64_INS_CMPNE = 117,
-    ARM64_INS_CMTST = 118,
-    ARM64_INS_CNEG = 119,
-    ARM64_INS_CNOT = 120,
-    ARM64_INS_CNT = 121,
-    ARM64_INS_CNTB = 122,
-    ARM64_INS_CNTD = 123,
-    ARM64_INS_CNTH = 124,
-    ARM64_INS_CNTP = 125,
-    ARM64_INS_CNTW = 126,
-    ARM64_INS_COMPACT = 127,
-    ARM64_INS_CPY = 128,
-    ARM64_INS_CRC32B = 129,
-    ARM64_INS_CRC32CB = 130,
-    ARM64_INS_CRC32CH = 131,
-    ARM64_INS_CRC32CW = 132,
-    ARM64_INS_CRC32CX = 133,
-    ARM64_INS_CRC32H = 134,
-    ARM64_INS_CRC32W = 135,
-    ARM64_INS_CRC32X = 136,
-    ARM64_INS_CSDB = 137,
-    ARM64_INS_CSEL = 138,
-    ARM64_INS_CSET = 139,
-    ARM64_INS_CSETM = 140,
-    ARM64_INS_CSINC = 141,
-    ARM64_INS_CSINV = 142,
-    ARM64_INS_CSNEG = 143,
-    ARM64_INS_CTERMEQ = 144,
-    ARM64_INS_CTERMNE = 145,
-    ARM64_INS_DCPS1 = 146,
-    ARM64_INS_DCPS2 = 147,
-    ARM64_INS_DCPS3 = 148,
-    ARM64_INS_DECB = 149,
-    ARM64_INS_DECD = 150,
-    ARM64_INS_DECH = 151,
-    ARM64_INS_DECP = 152,
-    ARM64_INS_DECW = 153,
-    ARM64_INS_DMB = 154,
-    ARM64_INS_DRPS = 155,
-    ARM64_INS_DSB = 156,
-    ARM64_INS_DUP = 157,
-    ARM64_INS_DUPM = 158,
-    ARM64_INS_EON = 159,
-    ARM64_INS_EOR = 160,
-    ARM64_INS_EOR3 = 161,
-    ARM64_INS_EORS = 162,
-    ARM64_INS_EORV = 163,
-    ARM64_INS_ERET = 164,
-    ARM64_INS_ERETAA = 165,
-    ARM64_INS_ERETAB = 166,
-    ARM64_INS_ESB = 167,
-    ARM64_INS_EXT = 168,
-    ARM64_INS_EXTR = 169,
-    ARM64_INS_FABD = 170,
-    ARM64_INS_FABS = 171,
-    ARM64_INS_FACGE = 172,
-    ARM64_INS_FACGT = 173,
-    ARM64_INS_FACLE = 174,
-    ARM64_INS_FACLT = 175,
-    ARM64_INS_FADD = 176,
-    ARM64_INS_FADDA = 177,
-    ARM64_INS_FADDP = 178,
-    ARM64_INS_FADDV = 179,
-    ARM64_INS_FCADD = 180,
-    ARM64_INS_FCCMP = 181,
-    ARM64_INS_FCCMPE = 182,
-    ARM64_INS_FCMEQ = 183,
-    ARM64_INS_FCMGE = 184,
-    ARM64_INS_FCMGT = 185,
-    ARM64_INS_FCMLA = 186,
-    ARM64_INS_FCMLE = 187,
-    ARM64_INS_FCMLT = 188,
-    ARM64_INS_FCMNE = 189,
-    ARM64_INS_FCMP = 190,
-    ARM64_INS_FCMPE = 191,
-    ARM64_INS_FCMUO = 192,
+impl arm64_reg {
+    pub const ARM64_REG_B4: arm64_reg = arm64_reg(13);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B5: arm64_reg = arm64_reg(14);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B6: arm64_reg = arm64_reg(15);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B7: arm64_reg = arm64_reg(16);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B8: arm64_reg = arm64_reg(17);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B9: arm64_reg = arm64_reg(18);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B10: arm64_reg = arm64_reg(19);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B11: arm64_reg = arm64_reg(20);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B12: arm64_reg = arm64_reg(21);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B13: arm64_reg = arm64_reg(22);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B14: arm64_reg = arm64_reg(23);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B15: arm64_reg = arm64_reg(24);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B16: arm64_reg = arm64_reg(25);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B17: arm64_reg = arm64_reg(26);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B18: arm64_reg = arm64_reg(27);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B19: arm64_reg = arm64_reg(28);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B20: arm64_reg = arm64_reg(29);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B21: arm64_reg = arm64_reg(30);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B22: arm64_reg = arm64_reg(31);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B23: arm64_reg = arm64_reg(32);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B24: arm64_reg = arm64_reg(33);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B25: arm64_reg = arm64_reg(34);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B26: arm64_reg = arm64_reg(35);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B27: arm64_reg = arm64_reg(36);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B28: arm64_reg = arm64_reg(37);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B29: arm64_reg = arm64_reg(38);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B30: arm64_reg = arm64_reg(39);
+}
+impl arm64_reg {
+    pub const ARM64_REG_B31: arm64_reg = arm64_reg(40);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D0: arm64_reg = arm64_reg(41);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D1: arm64_reg = arm64_reg(42);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D2: arm64_reg = arm64_reg(43);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D3: arm64_reg = arm64_reg(44);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D4: arm64_reg = arm64_reg(45);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D5: arm64_reg = arm64_reg(46);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D6: arm64_reg = arm64_reg(47);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D7: arm64_reg = arm64_reg(48);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D8: arm64_reg = arm64_reg(49);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D9: arm64_reg = arm64_reg(50);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D10: arm64_reg = arm64_reg(51);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D11: arm64_reg = arm64_reg(52);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D12: arm64_reg = arm64_reg(53);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D13: arm64_reg = arm64_reg(54);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D14: arm64_reg = arm64_reg(55);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D15: arm64_reg = arm64_reg(56);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D16: arm64_reg = arm64_reg(57);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D17: arm64_reg = arm64_reg(58);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D18: arm64_reg = arm64_reg(59);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D19: arm64_reg = arm64_reg(60);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D20: arm64_reg = arm64_reg(61);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D21: arm64_reg = arm64_reg(62);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D22: arm64_reg = arm64_reg(63);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D23: arm64_reg = arm64_reg(64);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D24: arm64_reg = arm64_reg(65);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D25: arm64_reg = arm64_reg(66);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D26: arm64_reg = arm64_reg(67);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D27: arm64_reg = arm64_reg(68);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D28: arm64_reg = arm64_reg(69);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D29: arm64_reg = arm64_reg(70);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D30: arm64_reg = arm64_reg(71);
+}
+impl arm64_reg {
+    pub const ARM64_REG_D31: arm64_reg = arm64_reg(72);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H0: arm64_reg = arm64_reg(73);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H1: arm64_reg = arm64_reg(74);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H2: arm64_reg = arm64_reg(75);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H3: arm64_reg = arm64_reg(76);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H4: arm64_reg = arm64_reg(77);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H5: arm64_reg = arm64_reg(78);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H6: arm64_reg = arm64_reg(79);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H7: arm64_reg = arm64_reg(80);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H8: arm64_reg = arm64_reg(81);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H9: arm64_reg = arm64_reg(82);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H10: arm64_reg = arm64_reg(83);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H11: arm64_reg = arm64_reg(84);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H12: arm64_reg = arm64_reg(85);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H13: arm64_reg = arm64_reg(86);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H14: arm64_reg = arm64_reg(87);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H15: arm64_reg = arm64_reg(88);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H16: arm64_reg = arm64_reg(89);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H17: arm64_reg = arm64_reg(90);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H18: arm64_reg = arm64_reg(91);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H19: arm64_reg = arm64_reg(92);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H20: arm64_reg = arm64_reg(93);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H21: arm64_reg = arm64_reg(94);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H22: arm64_reg = arm64_reg(95);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H23: arm64_reg = arm64_reg(96);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H24: arm64_reg = arm64_reg(97);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H25: arm64_reg = arm64_reg(98);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H26: arm64_reg = arm64_reg(99);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H27: arm64_reg = arm64_reg(100);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H28: arm64_reg = arm64_reg(101);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H29: arm64_reg = arm64_reg(102);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H30: arm64_reg = arm64_reg(103);
+}
+impl arm64_reg {
+    pub const ARM64_REG_H31: arm64_reg = arm64_reg(104);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P0: arm64_reg = arm64_reg(105);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P1: arm64_reg = arm64_reg(106);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P2: arm64_reg = arm64_reg(107);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P3: arm64_reg = arm64_reg(108);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P4: arm64_reg = arm64_reg(109);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P5: arm64_reg = arm64_reg(110);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P6: arm64_reg = arm64_reg(111);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P7: arm64_reg = arm64_reg(112);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P8: arm64_reg = arm64_reg(113);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P9: arm64_reg = arm64_reg(114);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P10: arm64_reg = arm64_reg(115);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P11: arm64_reg = arm64_reg(116);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P12: arm64_reg = arm64_reg(117);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P13: arm64_reg = arm64_reg(118);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P14: arm64_reg = arm64_reg(119);
+}
+impl arm64_reg {
+    pub const ARM64_REG_P15: arm64_reg = arm64_reg(120);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q0: arm64_reg = arm64_reg(121);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q1: arm64_reg = arm64_reg(122);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q2: arm64_reg = arm64_reg(123);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q3: arm64_reg = arm64_reg(124);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q4: arm64_reg = arm64_reg(125);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q5: arm64_reg = arm64_reg(126);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q6: arm64_reg = arm64_reg(127);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q7: arm64_reg = arm64_reg(128);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q8: arm64_reg = arm64_reg(129);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q9: arm64_reg = arm64_reg(130);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q10: arm64_reg = arm64_reg(131);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q11: arm64_reg = arm64_reg(132);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q12: arm64_reg = arm64_reg(133);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q13: arm64_reg = arm64_reg(134);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q14: arm64_reg = arm64_reg(135);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q15: arm64_reg = arm64_reg(136);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q16: arm64_reg = arm64_reg(137);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q17: arm64_reg = arm64_reg(138);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q18: arm64_reg = arm64_reg(139);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q19: arm64_reg = arm64_reg(140);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q20: arm64_reg = arm64_reg(141);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q21: arm64_reg = arm64_reg(142);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q22: arm64_reg = arm64_reg(143);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q23: arm64_reg = arm64_reg(144);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q24: arm64_reg = arm64_reg(145);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q25: arm64_reg = arm64_reg(146);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q26: arm64_reg = arm64_reg(147);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q27: arm64_reg = arm64_reg(148);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q28: arm64_reg = arm64_reg(149);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q29: arm64_reg = arm64_reg(150);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q30: arm64_reg = arm64_reg(151);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Q31: arm64_reg = arm64_reg(152);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S0: arm64_reg = arm64_reg(153);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S1: arm64_reg = arm64_reg(154);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S2: arm64_reg = arm64_reg(155);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S3: arm64_reg = arm64_reg(156);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S4: arm64_reg = arm64_reg(157);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S5: arm64_reg = arm64_reg(158);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S6: arm64_reg = arm64_reg(159);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S7: arm64_reg = arm64_reg(160);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S8: arm64_reg = arm64_reg(161);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S9: arm64_reg = arm64_reg(162);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S10: arm64_reg = arm64_reg(163);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S11: arm64_reg = arm64_reg(164);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S12: arm64_reg = arm64_reg(165);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S13: arm64_reg = arm64_reg(166);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S14: arm64_reg = arm64_reg(167);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S15: arm64_reg = arm64_reg(168);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S16: arm64_reg = arm64_reg(169);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S17: arm64_reg = arm64_reg(170);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S18: arm64_reg = arm64_reg(171);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S19: arm64_reg = arm64_reg(172);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S20: arm64_reg = arm64_reg(173);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S21: arm64_reg = arm64_reg(174);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S22: arm64_reg = arm64_reg(175);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S23: arm64_reg = arm64_reg(176);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S24: arm64_reg = arm64_reg(177);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S25: arm64_reg = arm64_reg(178);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S26: arm64_reg = arm64_reg(179);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S27: arm64_reg = arm64_reg(180);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S28: arm64_reg = arm64_reg(181);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S29: arm64_reg = arm64_reg(182);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S30: arm64_reg = arm64_reg(183);
+}
+impl arm64_reg {
+    pub const ARM64_REG_S31: arm64_reg = arm64_reg(184);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W0: arm64_reg = arm64_reg(185);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W1: arm64_reg = arm64_reg(186);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W2: arm64_reg = arm64_reg(187);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W3: arm64_reg = arm64_reg(188);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W4: arm64_reg = arm64_reg(189);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W5: arm64_reg = arm64_reg(190);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W6: arm64_reg = arm64_reg(191);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W7: arm64_reg = arm64_reg(192);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W8: arm64_reg = arm64_reg(193);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W9: arm64_reg = arm64_reg(194);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W10: arm64_reg = arm64_reg(195);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W11: arm64_reg = arm64_reg(196);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W12: arm64_reg = arm64_reg(197);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W13: arm64_reg = arm64_reg(198);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W14: arm64_reg = arm64_reg(199);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W15: arm64_reg = arm64_reg(200);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W16: arm64_reg = arm64_reg(201);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W17: arm64_reg = arm64_reg(202);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W18: arm64_reg = arm64_reg(203);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W19: arm64_reg = arm64_reg(204);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W20: arm64_reg = arm64_reg(205);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W21: arm64_reg = arm64_reg(206);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W22: arm64_reg = arm64_reg(207);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W23: arm64_reg = arm64_reg(208);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W24: arm64_reg = arm64_reg(209);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W25: arm64_reg = arm64_reg(210);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W26: arm64_reg = arm64_reg(211);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W27: arm64_reg = arm64_reg(212);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W28: arm64_reg = arm64_reg(213);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W29: arm64_reg = arm64_reg(214);
+}
+impl arm64_reg {
+    pub const ARM64_REG_W30: arm64_reg = arm64_reg(215);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X0: arm64_reg = arm64_reg(216);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X1: arm64_reg = arm64_reg(217);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X2: arm64_reg = arm64_reg(218);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X3: arm64_reg = arm64_reg(219);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X4: arm64_reg = arm64_reg(220);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X5: arm64_reg = arm64_reg(221);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X6: arm64_reg = arm64_reg(222);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X7: arm64_reg = arm64_reg(223);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X8: arm64_reg = arm64_reg(224);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X9: arm64_reg = arm64_reg(225);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X10: arm64_reg = arm64_reg(226);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X11: arm64_reg = arm64_reg(227);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X12: arm64_reg = arm64_reg(228);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X13: arm64_reg = arm64_reg(229);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X14: arm64_reg = arm64_reg(230);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X15: arm64_reg = arm64_reg(231);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X16: arm64_reg = arm64_reg(232);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X17: arm64_reg = arm64_reg(233);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X18: arm64_reg = arm64_reg(234);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X19: arm64_reg = arm64_reg(235);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X20: arm64_reg = arm64_reg(236);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X21: arm64_reg = arm64_reg(237);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X22: arm64_reg = arm64_reg(238);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X23: arm64_reg = arm64_reg(239);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X24: arm64_reg = arm64_reg(240);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X25: arm64_reg = arm64_reg(241);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X26: arm64_reg = arm64_reg(242);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X27: arm64_reg = arm64_reg(243);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X28: arm64_reg = arm64_reg(244);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z0: arm64_reg = arm64_reg(245);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z1: arm64_reg = arm64_reg(246);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z2: arm64_reg = arm64_reg(247);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z3: arm64_reg = arm64_reg(248);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z4: arm64_reg = arm64_reg(249);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z5: arm64_reg = arm64_reg(250);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z6: arm64_reg = arm64_reg(251);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z7: arm64_reg = arm64_reg(252);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z8: arm64_reg = arm64_reg(253);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z9: arm64_reg = arm64_reg(254);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z10: arm64_reg = arm64_reg(255);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z11: arm64_reg = arm64_reg(256);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z12: arm64_reg = arm64_reg(257);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z13: arm64_reg = arm64_reg(258);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z14: arm64_reg = arm64_reg(259);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z15: arm64_reg = arm64_reg(260);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z16: arm64_reg = arm64_reg(261);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z17: arm64_reg = arm64_reg(262);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z18: arm64_reg = arm64_reg(263);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z19: arm64_reg = arm64_reg(264);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z20: arm64_reg = arm64_reg(265);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z21: arm64_reg = arm64_reg(266);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z22: arm64_reg = arm64_reg(267);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z23: arm64_reg = arm64_reg(268);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z24: arm64_reg = arm64_reg(269);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z25: arm64_reg = arm64_reg(270);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z26: arm64_reg = arm64_reg(271);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z27: arm64_reg = arm64_reg(272);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z28: arm64_reg = arm64_reg(273);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z29: arm64_reg = arm64_reg(274);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z30: arm64_reg = arm64_reg(275);
+}
+impl arm64_reg {
+    pub const ARM64_REG_Z31: arm64_reg = arm64_reg(276);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V0: arm64_reg = arm64_reg(277);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V1: arm64_reg = arm64_reg(278);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V2: arm64_reg = arm64_reg(279);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V3: arm64_reg = arm64_reg(280);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V4: arm64_reg = arm64_reg(281);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V5: arm64_reg = arm64_reg(282);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V6: arm64_reg = arm64_reg(283);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V7: arm64_reg = arm64_reg(284);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V8: arm64_reg = arm64_reg(285);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V9: arm64_reg = arm64_reg(286);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V10: arm64_reg = arm64_reg(287);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V11: arm64_reg = arm64_reg(288);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V12: arm64_reg = arm64_reg(289);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V13: arm64_reg = arm64_reg(290);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V14: arm64_reg = arm64_reg(291);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V15: arm64_reg = arm64_reg(292);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V16: arm64_reg = arm64_reg(293);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V17: arm64_reg = arm64_reg(294);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V18: arm64_reg = arm64_reg(295);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V19: arm64_reg = arm64_reg(296);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V20: arm64_reg = arm64_reg(297);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V21: arm64_reg = arm64_reg(298);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V22: arm64_reg = arm64_reg(299);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V23: arm64_reg = arm64_reg(300);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V24: arm64_reg = arm64_reg(301);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V25: arm64_reg = arm64_reg(302);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V26: arm64_reg = arm64_reg(303);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V27: arm64_reg = arm64_reg(304);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V28: arm64_reg = arm64_reg(305);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V29: arm64_reg = arm64_reg(306);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V30: arm64_reg = arm64_reg(307);
+}
+impl arm64_reg {
+    pub const ARM64_REG_V31: arm64_reg = arm64_reg(308);
+}
+impl arm64_reg {
+    pub const ARM64_REG_ENDING: arm64_reg = arm64_reg(309);
+}
+impl arm64_reg {
+    pub const ARM64_REG_IP0: arm64_reg = arm64_reg(232);
+}
+impl arm64_reg {
+    pub const ARM64_REG_IP1: arm64_reg = arm64_reg(233);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X29: arm64_reg = arm64_reg(2);
+}
+impl arm64_reg {
+    pub const ARM64_REG_X30: arm64_reg = arm64_reg(3);
+}
+#[repr(transparent)]
+#[doc = " ARM64 registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct arm64_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with ARM64_OP_MEM operand type above"]
+#[repr(C)]
+#[derive(Debug, Copy, Clone)]
+pub struct arm64_op_mem {
+    #[doc = "< base register"]
+    pub base: arm64_reg,
+    #[doc = "< index register"]
+    pub index: arm64_reg,
+    #[doc = "< displacement/offset value"]
+    pub disp: i32,
+}
+#[doc = " Instruction operand"]
+#[repr(C)]
+#[derive(Copy, Clone)]
+pub struct cs_arm64_op {
+    #[doc = "< Vector Index for some vector operands (or -1 if irrelevant)"]
+    pub vector_index: libc::c_int,
+    #[doc = "< Vector Arrangement Specifier"]
+    pub vas: arm64_vas,
+    pub shift: cs_arm64_op__bindgen_ty_1,
+    #[doc = "< extender type of this operand"]
+    pub ext: arm64_extender,
+    #[doc = "< operand type"]
+    pub type_: arm64_op_type,
+    pub __bindgen_anon_1: cs_arm64_op__bindgen_ty_2,
+    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
+    pub access: u8,
+}
+#[repr(C)]
+#[derive(Debug, Copy, Clone)]
+pub struct cs_arm64_op__bindgen_ty_1 {
+    #[doc = "< shifter type of this operand"]
+    pub type_: arm64_shifter,
+    #[doc = "< shifter value of this operand"]
+    pub value: libc::c_uint,
+}
+#[repr(C)]
+#[derive(Copy, Clone)]
+pub union cs_arm64_op__bindgen_ty_2 {
+    #[doc = "< register value for REG operand"]
+    pub reg: arm64_reg,
+    #[doc = "< immediate value, or index for C-IMM or IMM operand"]
+    pub imm: i64,
+    #[doc = "< floating point value for FP operand"]
+    pub fp: f64,
+    #[doc = "< base/index/scale/disp value for MEM operand"]
+    pub mem: arm64_op_mem,
+    #[doc = "< PState field of MSR instruction."]
+    pub pstate: arm64_pstate,
+    #[doc = "< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)"]
+    pub sys: arm64_sys_op,
+    #[doc = "< PRFM operation."]
+    pub prefetch: arm64_prefetch_op,
+    #[doc = "< Memory barrier operation (ISB/DMB/DSB instructions)."]
+    pub barrier: arm64_barrier_op,
+}
+impl ::core::fmt::Debug for cs_arm64_op__bindgen_ty_2 {
+    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
+        write!(f, "cs_arm64_op__bindgen_ty_2 {{ union }}")
+    }
+}
+impl ::core::fmt::Debug for cs_arm64_op {
+    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
+        write ! (f , "cs_arm64_op {{ vector_index: {:?}, vas: {:?}, shift: {:?}, ext: {:?}, type: {:?}, __bindgen_anon_1: {:?} }}" , self . vector_index , self . vas , self . shift , self . ext , self . type_ , self . __bindgen_anon_1)
+    }
+}
+#[doc = " Instruction structure"]
+#[repr(C)]
+#[derive(Copy, Clone)]
+pub struct cs_arm64 {
+    #[doc = "< conditional code for this insn"]
+    pub cc: arm64_cc,
+    #[doc = "< does this insn update flags?"]
+    pub update_flags: bool,
+    #[doc = "< does this insn request writeback? 'True' means 'yes'"]
+    pub writeback: bool,
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
+    pub op_count: u8,
+    #[doc = "< operands for this instruction."]
+    pub operands: [cs_arm64_op; 8usize],
+}
+impl ::core::fmt::Debug for cs_arm64 {
+    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
+        write!(
+            f,
+            "cs_arm64 {{ cc: {:?}, update_flags: {:?}, writeback: {:?}, operands: {:?} }}",
+            self.cc, self.update_flags, self.writeback, self.operands
+        )
+    }
+}
+#[repr(u32)]
+#[doc = " ARM64 instruction"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub enum arm64_insn {
+    ARM64_INS_INVALID = 0,
+    ARM64_INS_ABS = 1,
+    ARM64_INS_ADC = 2,
+    ARM64_INS_ADCS = 3,
+    ARM64_INS_ADD = 4,
+    ARM64_INS_ADDHN = 5,
+    ARM64_INS_ADDHN2 = 6,
+    ARM64_INS_ADDP = 7,
+    ARM64_INS_ADDPL = 8,
+    ARM64_INS_ADDS = 9,
+    ARM64_INS_ADDV = 10,
+    ARM64_INS_ADDVL = 11,
+    ARM64_INS_ADR = 12,
+    ARM64_INS_ADRP = 13,
+    ARM64_INS_AESD = 14,
+    ARM64_INS_AESE = 15,
+    ARM64_INS_AESIMC = 16,
+    ARM64_INS_AESMC = 17,
+    ARM64_INS_AND = 18,
+    ARM64_INS_ANDS = 19,
+    ARM64_INS_ANDV = 20,
+    ARM64_INS_ASR = 21,
+    ARM64_INS_ASRD = 22,
+    ARM64_INS_ASRR = 23,
+    ARM64_INS_ASRV = 24,
+    ARM64_INS_AUTDA = 25,
+    ARM64_INS_AUTDB = 26,
+    ARM64_INS_AUTDZA = 27,
+    ARM64_INS_AUTDZB = 28,
+    ARM64_INS_AUTIA = 29,
+    ARM64_INS_AUTIA1716 = 30,
+    ARM64_INS_AUTIASP = 31,
+    ARM64_INS_AUTIAZ = 32,
+    ARM64_INS_AUTIB = 33,
+    ARM64_INS_AUTIB1716 = 34,
+    ARM64_INS_AUTIBSP = 35,
+    ARM64_INS_AUTIBZ = 36,
+    ARM64_INS_AUTIZA = 37,
+    ARM64_INS_AUTIZB = 38,
+    ARM64_INS_B = 39,
+    ARM64_INS_BCAX = 40,
+    ARM64_INS_BFM = 41,
+    ARM64_INS_BIC = 42,
+    ARM64_INS_BICS = 43,
+    ARM64_INS_BIF = 44,
+    ARM64_INS_BIT = 45,
+    ARM64_INS_BL = 46,
+    ARM64_INS_BLR = 47,
+    ARM64_INS_BLRAA = 48,
+    ARM64_INS_BLRAAZ = 49,
+    ARM64_INS_BLRAB = 50,
+    ARM64_INS_BLRABZ = 51,
+    ARM64_INS_BR = 52,
+    ARM64_INS_BRAA = 53,
+    ARM64_INS_BRAAZ = 54,
+    ARM64_INS_BRAB = 55,
+    ARM64_INS_BRABZ = 56,
+    ARM64_INS_BRK = 57,
+    ARM64_INS_BRKA = 58,
+    ARM64_INS_BRKAS = 59,
+    ARM64_INS_BRKB = 60,
+    ARM64_INS_BRKBS = 61,
+    ARM64_INS_BRKN = 62,
+    ARM64_INS_BRKNS = 63,
+    ARM64_INS_BRKPA = 64,
+    ARM64_INS_BRKPAS = 65,
+    ARM64_INS_BRKPB = 66,
+    ARM64_INS_BRKPBS = 67,
+    ARM64_INS_BSL = 68,
+    ARM64_INS_CAS = 69,
+    ARM64_INS_CASA = 70,
+    ARM64_INS_CASAB = 71,
+    ARM64_INS_CASAH = 72,
+    ARM64_INS_CASAL = 73,
+    ARM64_INS_CASALB = 74,
+    ARM64_INS_CASALH = 75,
+    ARM64_INS_CASB = 76,
+    ARM64_INS_CASH = 77,
+    ARM64_INS_CASL = 78,
+    ARM64_INS_CASLB = 79,
+    ARM64_INS_CASLH = 80,
+    ARM64_INS_CASP = 81,
+    ARM64_INS_CASPA = 82,
+    ARM64_INS_CASPAL = 83,
+    ARM64_INS_CASPL = 84,
+    ARM64_INS_CBNZ = 85,
+    ARM64_INS_CBZ = 86,
+    ARM64_INS_CCMN = 87,
+    ARM64_INS_CCMP = 88,
+    ARM64_INS_CFINV = 89,
+    ARM64_INS_CINC = 90,
+    ARM64_INS_CINV = 91,
+    ARM64_INS_CLASTA = 92,
+    ARM64_INS_CLASTB = 93,
+    ARM64_INS_CLREX = 94,
+    ARM64_INS_CLS = 95,
+    ARM64_INS_CLZ = 96,
+    ARM64_INS_CMEQ = 97,
+    ARM64_INS_CMGE = 98,
+    ARM64_INS_CMGT = 99,
+    ARM64_INS_CMHI = 100,
+    ARM64_INS_CMHS = 101,
+    ARM64_INS_CMLE = 102,
+    ARM64_INS_CMLO = 103,
+    ARM64_INS_CMLS = 104,
+    ARM64_INS_CMLT = 105,
+    ARM64_INS_CMN = 106,
+    ARM64_INS_CMP = 107,
+    ARM64_INS_CMPEQ = 108,
+    ARM64_INS_CMPGE = 109,
+    ARM64_INS_CMPGT = 110,
+    ARM64_INS_CMPHI = 111,
+    ARM64_INS_CMPHS = 112,
+    ARM64_INS_CMPLE = 113,
+    ARM64_INS_CMPLO = 114,
+    ARM64_INS_CMPLS = 115,
+    ARM64_INS_CMPLT = 116,
+    ARM64_INS_CMPNE = 117,
+    ARM64_INS_CMTST = 118,
+    ARM64_INS_CNEG = 119,
+    ARM64_INS_CNOT = 120,
+    ARM64_INS_CNT = 121,
+    ARM64_INS_CNTB = 122,
+    ARM64_INS_CNTD = 123,
+    ARM64_INS_CNTH = 124,
+    ARM64_INS_CNTP = 125,
+    ARM64_INS_CNTW = 126,
+    ARM64_INS_COMPACT = 127,
+    ARM64_INS_CPY = 128,
+    ARM64_INS_CRC32B = 129,
+    ARM64_INS_CRC32CB = 130,
+    ARM64_INS_CRC32CH = 131,
+    ARM64_INS_CRC32CW = 132,
+    ARM64_INS_CRC32CX = 133,
+    ARM64_INS_CRC32H = 134,
+    ARM64_INS_CRC32W = 135,
+    ARM64_INS_CRC32X = 136,
+    ARM64_INS_CSDB = 137,
+    ARM64_INS_CSEL = 138,
+    ARM64_INS_CSET = 139,
+    ARM64_INS_CSETM = 140,
+    ARM64_INS_CSINC = 141,
+    ARM64_INS_CSINV = 142,
+    ARM64_INS_CSNEG = 143,
+    ARM64_INS_CTERMEQ = 144,
+    ARM64_INS_CTERMNE = 145,
+    ARM64_INS_DCPS1 = 146,
+    ARM64_INS_DCPS2 = 147,
+    ARM64_INS_DCPS3 = 148,
+    ARM64_INS_DECB = 149,
+    ARM64_INS_DECD = 150,
+    ARM64_INS_DECH = 151,
+    ARM64_INS_DECP = 152,
+    ARM64_INS_DECW = 153,
+    ARM64_INS_DMB = 154,
+    ARM64_INS_DRPS = 155,
+    ARM64_INS_DSB = 156,
+    ARM64_INS_DUP = 157,
+    ARM64_INS_DUPM = 158,
+    ARM64_INS_EON = 159,
+    ARM64_INS_EOR = 160,
+    ARM64_INS_EOR3 = 161,
+    ARM64_INS_EORS = 162,
+    ARM64_INS_EORV = 163,
+    ARM64_INS_ERET = 164,
+    ARM64_INS_ERETAA = 165,
+    ARM64_INS_ERETAB = 166,
+    ARM64_INS_ESB = 167,
+    ARM64_INS_EXT = 168,
+    ARM64_INS_EXTR = 169,
+    ARM64_INS_FABD = 170,
+    ARM64_INS_FABS = 171,
+    ARM64_INS_FACGE = 172,
+    ARM64_INS_FACGT = 173,
+    ARM64_INS_FACLE = 174,
+    ARM64_INS_FACLT = 175,
+    ARM64_INS_FADD = 176,
+    ARM64_INS_FADDA = 177,
+    ARM64_INS_FADDP = 178,
+    ARM64_INS_FADDV = 179,
+    ARM64_INS_FCADD = 180,
+    ARM64_INS_FCCMP = 181,
+    ARM64_INS_FCCMPE = 182,
+    ARM64_INS_FCMEQ = 183,
+    ARM64_INS_FCMGE = 184,
+    ARM64_INS_FCMGT = 185,
+    ARM64_INS_FCMLA = 186,
+    ARM64_INS_FCMLE = 187,
+    ARM64_INS_FCMLT = 188,
+    ARM64_INS_FCMNE = 189,
+    ARM64_INS_FCMP = 190,
+    ARM64_INS_FCMPE = 191,
+    ARM64_INS_FCMUO = 192,
     ARM64_INS_FCPY = 193,
     ARM64_INS_FCSEL = 194,
     ARM64_INS_FCVT = 195,
@@ -4030,92 +4988,240 @@ pub enum arm64_insn {
     ARM64_INS_TLBI = 949,
     ARM64_INS_ENDING = 950,
 }
-pub mod arm64_insn_group {
-    #[doc = " Group of ARM64 instructions"]
-    pub type Type = libc::c_uint;
+impl arm64_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const ARM64_GRP_INVALID: Type = 0;
+    pub const ARM64_GRP_INVALID: arm64_insn_group = arm64_insn_group(0);
+}
+impl arm64_insn_group {
     #[doc = "< = CS_GRP_JUMP"]
-    pub const ARM64_GRP_JUMP: Type = 1;
-    pub const ARM64_GRP_CALL: Type = 2;
-    pub const ARM64_GRP_RET: Type = 3;
-    pub const ARM64_GRP_INT: Type = 4;
+    pub const ARM64_GRP_JUMP: arm64_insn_group = arm64_insn_group(1);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_CALL: arm64_insn_group = arm64_insn_group(2);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_RET: arm64_insn_group = arm64_insn_group(3);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_INT: arm64_insn_group = arm64_insn_group(4);
+}
+impl arm64_insn_group {
     #[doc = "< = CS_GRP_PRIVILEGE"]
-    pub const ARM64_GRP_PRIVILEGE: Type = 6;
+    pub const ARM64_GRP_PRIVILEGE: arm64_insn_group = arm64_insn_group(6);
+}
+impl arm64_insn_group {
     #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
-    pub const ARM64_GRP_BRANCH_RELATIVE: Type = 7;
-    pub const ARM64_GRP_PAC: Type = 8;
-    pub const ARM64_GRP_CRYPTO: Type = 128;
-    pub const ARM64_GRP_FPARMV8: Type = 129;
-    pub const ARM64_GRP_NEON: Type = 130;
-    pub const ARM64_GRP_CRC: Type = 131;
-    pub const ARM64_GRP_AES: Type = 132;
-    pub const ARM64_GRP_DOTPROD: Type = 133;
-    pub const ARM64_GRP_FULLFP16: Type = 134;
-    pub const ARM64_GRP_LSE: Type = 135;
-    pub const ARM64_GRP_RCPC: Type = 136;
-    pub const ARM64_GRP_RDM: Type = 137;
-    pub const ARM64_GRP_SHA2: Type = 138;
-    pub const ARM64_GRP_SHA3: Type = 139;
-    pub const ARM64_GRP_SM4: Type = 140;
-    pub const ARM64_GRP_SVE: Type = 141;
-    pub const ARM64_GRP_V8_1A: Type = 142;
-    pub const ARM64_GRP_V8_3A: Type = 143;
-    pub const ARM64_GRP_V8_4A: Type = 144;
-    pub const ARM64_GRP_ENDING: Type = 145;
-}
-pub mod m68k_reg {
-    #[doc = " M68K registers and special registers"]
-    pub type Type = libc::c_uint;
-    pub const M68K_REG_INVALID: Type = 0;
-    pub const M68K_REG_D0: Type = 1;
-    pub const M68K_REG_D1: Type = 2;
-    pub const M68K_REG_D2: Type = 3;
-    pub const M68K_REG_D3: Type = 4;
-    pub const M68K_REG_D4: Type = 5;
-    pub const M68K_REG_D5: Type = 6;
-    pub const M68K_REG_D6: Type = 7;
-    pub const M68K_REG_D7: Type = 8;
-    pub const M68K_REG_A0: Type = 9;
-    pub const M68K_REG_A1: Type = 10;
-    pub const M68K_REG_A2: Type = 11;
-    pub const M68K_REG_A3: Type = 12;
-    pub const M68K_REG_A4: Type = 13;
-    pub const M68K_REG_A5: Type = 14;
-    pub const M68K_REG_A6: Type = 15;
-    pub const M68K_REG_A7: Type = 16;
-    pub const M68K_REG_FP0: Type = 17;
-    pub const M68K_REG_FP1: Type = 18;
-    pub const M68K_REG_FP2: Type = 19;
-    pub const M68K_REG_FP3: Type = 20;
-    pub const M68K_REG_FP4: Type = 21;
-    pub const M68K_REG_FP5: Type = 22;
-    pub const M68K_REG_FP6: Type = 23;
-    pub const M68K_REG_FP7: Type = 24;
-    pub const M68K_REG_PC: Type = 25;
-    pub const M68K_REG_SR: Type = 26;
-    pub const M68K_REG_CCR: Type = 27;
-    pub const M68K_REG_SFC: Type = 28;
-    pub const M68K_REG_DFC: Type = 29;
-    pub const M68K_REG_USP: Type = 30;
-    pub const M68K_REG_VBR: Type = 31;
-    pub const M68K_REG_CACR: Type = 32;
-    pub const M68K_REG_CAAR: Type = 33;
-    pub const M68K_REG_MSP: Type = 34;
-    pub const M68K_REG_ISP: Type = 35;
-    pub const M68K_REG_TC: Type = 36;
-    pub const M68K_REG_ITT0: Type = 37;
-    pub const M68K_REG_ITT1: Type = 38;
-    pub const M68K_REG_DTT0: Type = 39;
-    pub const M68K_REG_DTT1: Type = 40;
-    pub const M68K_REG_MMUSR: Type = 41;
-    pub const M68K_REG_URP: Type = 42;
-    pub const M68K_REG_SRP: Type = 43;
-    pub const M68K_REG_FPCR: Type = 44;
-    pub const M68K_REG_FPSR: Type = 45;
-    pub const M68K_REG_FPIAR: Type = 46;
-    pub const M68K_REG_ENDING: Type = 47;
+    pub const ARM64_GRP_BRANCH_RELATIVE: arm64_insn_group = arm64_insn_group(7);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_PAC: arm64_insn_group = arm64_insn_group(8);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_CRYPTO: arm64_insn_group = arm64_insn_group(128);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_FPARMV8: arm64_insn_group = arm64_insn_group(129);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_NEON: arm64_insn_group = arm64_insn_group(130);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_CRC: arm64_insn_group = arm64_insn_group(131);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_AES: arm64_insn_group = arm64_insn_group(132);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_DOTPROD: arm64_insn_group = arm64_insn_group(133);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_FULLFP16: arm64_insn_group = arm64_insn_group(134);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_LSE: arm64_insn_group = arm64_insn_group(135);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_RCPC: arm64_insn_group = arm64_insn_group(136);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_RDM: arm64_insn_group = arm64_insn_group(137);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_SHA2: arm64_insn_group = arm64_insn_group(138);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_SHA3: arm64_insn_group = arm64_insn_group(139);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_SM4: arm64_insn_group = arm64_insn_group(140);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_SVE: arm64_insn_group = arm64_insn_group(141);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_V8_1A: arm64_insn_group = arm64_insn_group(142);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_V8_3A: arm64_insn_group = arm64_insn_group(143);
+}
+impl arm64_insn_group {
+    pub const ARM64_GRP_V8_4A: arm64_insn_group = arm64_insn_group(144);
 }
+impl arm64_insn_group {
+    pub const ARM64_GRP_ENDING: arm64_insn_group = arm64_insn_group(145);
+}
+#[repr(transparent)]
+#[doc = " Group of ARM64 instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct arm64_insn_group(pub libc::c_uint);
+impl m68k_reg {
+    pub const M68K_REG_INVALID: m68k_reg = m68k_reg(0);
+}
+impl m68k_reg {
+    pub const M68K_REG_D0: m68k_reg = m68k_reg(1);
+}
+impl m68k_reg {
+    pub const M68K_REG_D1: m68k_reg = m68k_reg(2);
+}
+impl m68k_reg {
+    pub const M68K_REG_D2: m68k_reg = m68k_reg(3);
+}
+impl m68k_reg {
+    pub const M68K_REG_D3: m68k_reg = m68k_reg(4);
+}
+impl m68k_reg {
+    pub const M68K_REG_D4: m68k_reg = m68k_reg(5);
+}
+impl m68k_reg {
+    pub const M68K_REG_D5: m68k_reg = m68k_reg(6);
+}
+impl m68k_reg {
+    pub const M68K_REG_D6: m68k_reg = m68k_reg(7);
+}
+impl m68k_reg {
+    pub const M68K_REG_D7: m68k_reg = m68k_reg(8);
+}
+impl m68k_reg {
+    pub const M68K_REG_A0: m68k_reg = m68k_reg(9);
+}
+impl m68k_reg {
+    pub const M68K_REG_A1: m68k_reg = m68k_reg(10);
+}
+impl m68k_reg {
+    pub const M68K_REG_A2: m68k_reg = m68k_reg(11);
+}
+impl m68k_reg {
+    pub const M68K_REG_A3: m68k_reg = m68k_reg(12);
+}
+impl m68k_reg {
+    pub const M68K_REG_A4: m68k_reg = m68k_reg(13);
+}
+impl m68k_reg {
+    pub const M68K_REG_A5: m68k_reg = m68k_reg(14);
+}
+impl m68k_reg {
+    pub const M68K_REG_A6: m68k_reg = m68k_reg(15);
+}
+impl m68k_reg {
+    pub const M68K_REG_A7: m68k_reg = m68k_reg(16);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP0: m68k_reg = m68k_reg(17);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP1: m68k_reg = m68k_reg(18);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP2: m68k_reg = m68k_reg(19);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP3: m68k_reg = m68k_reg(20);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP4: m68k_reg = m68k_reg(21);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP5: m68k_reg = m68k_reg(22);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP6: m68k_reg = m68k_reg(23);
+}
+impl m68k_reg {
+    pub const M68K_REG_FP7: m68k_reg = m68k_reg(24);
+}
+impl m68k_reg {
+    pub const M68K_REG_PC: m68k_reg = m68k_reg(25);
+}
+impl m68k_reg {
+    pub const M68K_REG_SR: m68k_reg = m68k_reg(26);
+}
+impl m68k_reg {
+    pub const M68K_REG_CCR: m68k_reg = m68k_reg(27);
+}
+impl m68k_reg {
+    pub const M68K_REG_SFC: m68k_reg = m68k_reg(28);
+}
+impl m68k_reg {
+    pub const M68K_REG_DFC: m68k_reg = m68k_reg(29);
+}
+impl m68k_reg {
+    pub const M68K_REG_USP: m68k_reg = m68k_reg(30);
+}
+impl m68k_reg {
+    pub const M68K_REG_VBR: m68k_reg = m68k_reg(31);
+}
+impl m68k_reg {
+    pub const M68K_REG_CACR: m68k_reg = m68k_reg(32);
+}
+impl m68k_reg {
+    pub const M68K_REG_CAAR: m68k_reg = m68k_reg(33);
+}
+impl m68k_reg {
+    pub const M68K_REG_MSP: m68k_reg = m68k_reg(34);
+}
+impl m68k_reg {
+    pub const M68K_REG_ISP: m68k_reg = m68k_reg(35);
+}
+impl m68k_reg {
+    pub const M68K_REG_TC: m68k_reg = m68k_reg(36);
+}
+impl m68k_reg {
+    pub const M68K_REG_ITT0: m68k_reg = m68k_reg(37);
+}
+impl m68k_reg {
+    pub const M68K_REG_ITT1: m68k_reg = m68k_reg(38);
+}
+impl m68k_reg {
+    pub const M68K_REG_DTT0: m68k_reg = m68k_reg(39);
+}
+impl m68k_reg {
+    pub const M68K_REG_DTT1: m68k_reg = m68k_reg(40);
+}
+impl m68k_reg {
+    pub const M68K_REG_MMUSR: m68k_reg = m68k_reg(41);
+}
+impl m68k_reg {
+    pub const M68K_REG_URP: m68k_reg = m68k_reg(42);
+}
+impl m68k_reg {
+    pub const M68K_REG_SRP: m68k_reg = m68k_reg(43);
+}
+impl m68k_reg {
+    pub const M68K_REG_FPCR: m68k_reg = m68k_reg(44);
+}
+impl m68k_reg {
+    pub const M68K_REG_FPSR: m68k_reg = m68k_reg(45);
+}
+impl m68k_reg {
+    pub const M68K_REG_FPIAR: m68k_reg = m68k_reg(46);
+}
+impl m68k_reg {
+    pub const M68K_REG_ENDING: m68k_reg = m68k_reg(47);
+}
+#[repr(transparent)]
+#[doc = " M68K registers and special registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct m68k_reg(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " M68K Addressing Modes"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -4184,17 +5290,16 @@ pub enum m68k_op_type {
     #[doc = "< Branch displacement"]
     M68K_OP_BR_DISP = 8,
 }
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with M68K_OP_MEM operand type above"]
+#[doc = " Instruction's operand referring to memory\n This is associated with M68K_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct m68k_op_mem {
     #[doc = "< base register (or M68K_REG_INVALID if irrelevant)"]
-    pub base_reg: m68k_reg::Type,
+    pub base_reg: m68k_reg,
     #[doc = "< index register (or M68K_REG_INVALID if irrelevant)"]
-    pub index_reg: m68k_reg::Type,
+    pub index_reg: m68k_reg,
     #[doc = "< indirect base register (or M68K_REG_INVALID if irrelevant)"]
-    pub in_base_reg: m68k_reg::Type,
+    pub in_base_reg: m68k_reg,
     #[doc = "< indirect displacement"]
     pub in_disp: u32,
     #[doc = "< other displacement"]
@@ -4212,11 +5317,6 @@ pub struct m68k_op_mem {
     #[doc = "< 0 = w, 1 = l"]
     pub index_size: u8,
 }
-impl Clone for m68k_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(u32)]
 #[doc = " Operand type for instruction's operands"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -4231,33 +5331,23 @@ pub enum m68k_op_br_disp_size {
     M68K_OP_BR_DISP_SIZE_LONG = 4,
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct m68k_op_br_disp {
     #[doc = "< displacement value"]
     pub disp: i32,
     #[doc = "< Size from m68k_op_br_disp_size type above"]
     pub disp_size: u8,
 }
-impl Clone for m68k_op_br_disp {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Register pair in one operand."]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_m68k_op_reg_pair {
-    pub reg_0: m68k_reg::Type,
-    pub reg_1: m68k_reg::Type,
-}
-impl Clone for cs_m68k_op_reg_pair {
-    fn clone(&self) -> Self {
-        *self
-    }
+    pub reg_0: m68k_reg,
+    pub reg_1: m68k_reg,
 }
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_m68k_op {
     pub __bindgen_anon_1: cs_m68k_op__bindgen_ty_1,
     #[doc = "< data when operand is targeting memory"]
@@ -4271,7 +5361,7 @@ pub struct cs_m68k_op {
     pub address_mode: m68k_address_mode,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_m68k_op__bindgen_ty_1 {
     #[doc = "< immediate value for IMM operand"]
     pub imm: u64,
@@ -4280,28 +5370,18 @@ pub union cs_m68k_op__bindgen_ty_1 {
     #[doc = "< float imm"]
     pub simm: f32,
     #[doc = "< register value for REG operand"]
-    pub reg: m68k_reg::Type,
+    pub reg: m68k_reg,
     #[doc = "< register pair in one operand"]
     pub reg_pair: cs_m68k_op_reg_pair,
 }
-impl Clone for cs_m68k_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_m68k_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_m68k_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_m68k_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_m68k_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, register_bits: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . register_bits , self . type_ , self . address_mode)
+        write ! (f , "cs_m68k_op {{ __bindgen_anon_1: {:?}, mem: {:?}, br_disp: {:?}, type: {:?}, address_mode: {:?} }}" , self . __bindgen_anon_1 , self . mem , self . br_disp , self . type_ , self . address_mode)
     }
 }
 #[repr(u32)]
@@ -4340,32 +5420,22 @@ pub enum m68k_size_type {
 }
 #[doc = " Operation size of the current instruction (NOT the actually size of instruction)"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct m68k_op_size {
     pub type_: m68k_size_type,
     pub __bindgen_anon_1: m68k_op_size__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union m68k_op_size__bindgen_ty_1 {
     pub cpu_size: m68k_cpu_size,
     pub fpu_size: m68k_fpu_size,
 }
-impl Clone for m68k_op_size__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for m68k_op_size__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "m68k_op_size__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for m68k_op_size {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for m68k_op_size {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -4377,7 +5447,7 @@ impl ::core::fmt::Debug for m68k_op_size {
 }
 #[doc = " The M68K instruction and it's operands"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_m68k {
     #[doc = "< operands for this instruction."]
     pub operands: [cs_m68k_op; 4usize],
@@ -4386,17 +5456,12 @@ pub struct cs_m68k {
     #[doc = "< number of operands for the instruction"]
     pub op_count: u8,
 }
-impl Clone for cs_m68k {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_m68k {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_m68k {{ operands: {:?}, op_size: {:?}, op_count: {:?} }}",
-            self.operands, self.op_size, self.op_count
+            "cs_m68k {{ operands: {:?}, op_size: {:?} }}",
+            self.operands, self.op_size
         )
     }
 }
@@ -4781,266 +5846,619 @@ pub enum m68k_insn {
     M68K_INS_UNPK = 374,
     M68K_INS_ENDING = 375,
 }
-#[repr(u32)]
-#[doc = " Group of M68K instructions"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum m68k_group_type {
-    #[doc = "< CS_GRUP_INVALID"]
-    M68K_GRP_INVALID = 0,
-    #[doc = "< = CS_GRP_JUMP"]
-    M68K_GRP_JUMP = 1,
-    #[doc = "< = CS_GRP_RET"]
-    M68K_GRP_RET = 3,
-    #[doc = "< = CS_GRP_IRET"]
-    M68K_GRP_IRET = 5,
-    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
-    M68K_GRP_BRANCH_RELATIVE = 7,
-    M68K_GRP_ENDING = 8,
+impl m68k_group_type {
+    #[doc = "< CS_GRUP_INVALID"]
+    pub const M68K_GRP_INVALID: m68k_group_type = m68k_group_type(0);
+}
+impl m68k_group_type {
+    #[doc = "< = CS_GRP_JUMP"]
+    pub const M68K_GRP_JUMP: m68k_group_type = m68k_group_type(1);
+}
+impl m68k_group_type {
+    #[doc = "< = CS_GRP_RET"]
+    pub const M68K_GRP_RET: m68k_group_type = m68k_group_type(3);
+}
+impl m68k_group_type {
+    #[doc = "< = CS_GRP_IRET"]
+    pub const M68K_GRP_IRET: m68k_group_type = m68k_group_type(5);
+}
+impl m68k_group_type {
+    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
+    pub const M68K_GRP_BRANCH_RELATIVE: m68k_group_type = m68k_group_type(7);
+}
+impl m68k_group_type {
+    pub const M68K_GRP_ENDING: m68k_group_type = m68k_group_type(8);
+}
+#[repr(transparent)]
+#[doc = " Group of M68K instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct m68k_group_type(pub libc::c_uint);
+#[repr(u32)]
+#[doc = " Operand type for instruction's operands"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub enum mips_op_type {
+    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
+    MIPS_OP_INVALID = 0,
+    #[doc = "< = CS_OP_REG (Register operand)."]
+    MIPS_OP_REG = 1,
+    #[doc = "< = CS_OP_IMM (Immediate operand)."]
+    MIPS_OP_IMM = 2,
+    #[doc = "< = CS_OP_MEM (Memory operand)."]
+    MIPS_OP_MEM = 3,
+}
+impl mips_reg {
+    pub const MIPS_REG_INVALID: mips_reg = mips_reg(0);
+}
+impl mips_reg {
+    pub const MIPS_REG_PC: mips_reg = mips_reg(1);
+}
+impl mips_reg {
+    pub const MIPS_REG_0: mips_reg = mips_reg(2);
+}
+impl mips_reg {
+    pub const MIPS_REG_1: mips_reg = mips_reg(3);
+}
+impl mips_reg {
+    pub const MIPS_REG_2: mips_reg = mips_reg(4);
+}
+impl mips_reg {
+    pub const MIPS_REG_3: mips_reg = mips_reg(5);
+}
+impl mips_reg {
+    pub const MIPS_REG_4: mips_reg = mips_reg(6);
+}
+impl mips_reg {
+    pub const MIPS_REG_5: mips_reg = mips_reg(7);
+}
+impl mips_reg {
+    pub const MIPS_REG_6: mips_reg = mips_reg(8);
+}
+impl mips_reg {
+    pub const MIPS_REG_7: mips_reg = mips_reg(9);
+}
+impl mips_reg {
+    pub const MIPS_REG_8: mips_reg = mips_reg(10);
+}
+impl mips_reg {
+    pub const MIPS_REG_9: mips_reg = mips_reg(11);
+}
+impl mips_reg {
+    pub const MIPS_REG_10: mips_reg = mips_reg(12);
+}
+impl mips_reg {
+    pub const MIPS_REG_11: mips_reg = mips_reg(13);
+}
+impl mips_reg {
+    pub const MIPS_REG_12: mips_reg = mips_reg(14);
+}
+impl mips_reg {
+    pub const MIPS_REG_13: mips_reg = mips_reg(15);
+}
+impl mips_reg {
+    pub const MIPS_REG_14: mips_reg = mips_reg(16);
+}
+impl mips_reg {
+    pub const MIPS_REG_15: mips_reg = mips_reg(17);
+}
+impl mips_reg {
+    pub const MIPS_REG_16: mips_reg = mips_reg(18);
+}
+impl mips_reg {
+    pub const MIPS_REG_17: mips_reg = mips_reg(19);
+}
+impl mips_reg {
+    pub const MIPS_REG_18: mips_reg = mips_reg(20);
+}
+impl mips_reg {
+    pub const MIPS_REG_19: mips_reg = mips_reg(21);
+}
+impl mips_reg {
+    pub const MIPS_REG_20: mips_reg = mips_reg(22);
+}
+impl mips_reg {
+    pub const MIPS_REG_21: mips_reg = mips_reg(23);
+}
+impl mips_reg {
+    pub const MIPS_REG_22: mips_reg = mips_reg(24);
+}
+impl mips_reg {
+    pub const MIPS_REG_23: mips_reg = mips_reg(25);
+}
+impl mips_reg {
+    pub const MIPS_REG_24: mips_reg = mips_reg(26);
+}
+impl mips_reg {
+    pub const MIPS_REG_25: mips_reg = mips_reg(27);
+}
+impl mips_reg {
+    pub const MIPS_REG_26: mips_reg = mips_reg(28);
+}
+impl mips_reg {
+    pub const MIPS_REG_27: mips_reg = mips_reg(29);
+}
+impl mips_reg {
+    pub const MIPS_REG_28: mips_reg = mips_reg(30);
+}
+impl mips_reg {
+    pub const MIPS_REG_29: mips_reg = mips_reg(31);
+}
+impl mips_reg {
+    pub const MIPS_REG_30: mips_reg = mips_reg(32);
+}
+impl mips_reg {
+    pub const MIPS_REG_31: mips_reg = mips_reg(33);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPCCOND: mips_reg = mips_reg(34);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPCARRY: mips_reg = mips_reg(35);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPEFI: mips_reg = mips_reg(36);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPOUTFLAG: mips_reg = mips_reg(37);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPOUTFLAG16_19: mips_reg = mips_reg(38);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPOUTFLAG20: mips_reg = mips_reg(39);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPOUTFLAG21: mips_reg = mips_reg(40);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPOUTFLAG22: mips_reg = mips_reg(41);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPOUTFLAG23: mips_reg = mips_reg(42);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPPOS: mips_reg = mips_reg(43);
+}
+impl mips_reg {
+    pub const MIPS_REG_DSPSCOUNT: mips_reg = mips_reg(44);
+}
+impl mips_reg {
+    pub const MIPS_REG_AC0: mips_reg = mips_reg(45);
+}
+impl mips_reg {
+    pub const MIPS_REG_AC1: mips_reg = mips_reg(46);
+}
+impl mips_reg {
+    pub const MIPS_REG_AC2: mips_reg = mips_reg(47);
+}
+impl mips_reg {
+    pub const MIPS_REG_AC3: mips_reg = mips_reg(48);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC0: mips_reg = mips_reg(49);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC1: mips_reg = mips_reg(50);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC2: mips_reg = mips_reg(51);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC3: mips_reg = mips_reg(52);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC4: mips_reg = mips_reg(53);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC5: mips_reg = mips_reg(54);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC6: mips_reg = mips_reg(55);
+}
+impl mips_reg {
+    pub const MIPS_REG_CC7: mips_reg = mips_reg(56);
+}
+impl mips_reg {
+    pub const MIPS_REG_F0: mips_reg = mips_reg(57);
+}
+impl mips_reg {
+    pub const MIPS_REG_F1: mips_reg = mips_reg(58);
+}
+impl mips_reg {
+    pub const MIPS_REG_F2: mips_reg = mips_reg(59);
+}
+impl mips_reg {
+    pub const MIPS_REG_F3: mips_reg = mips_reg(60);
+}
+impl mips_reg {
+    pub const MIPS_REG_F4: mips_reg = mips_reg(61);
+}
+impl mips_reg {
+    pub const MIPS_REG_F5: mips_reg = mips_reg(62);
+}
+impl mips_reg {
+    pub const MIPS_REG_F6: mips_reg = mips_reg(63);
+}
+impl mips_reg {
+    pub const MIPS_REG_F7: mips_reg = mips_reg(64);
+}
+impl mips_reg {
+    pub const MIPS_REG_F8: mips_reg = mips_reg(65);
+}
+impl mips_reg {
+    pub const MIPS_REG_F9: mips_reg = mips_reg(66);
+}
+impl mips_reg {
+    pub const MIPS_REG_F10: mips_reg = mips_reg(67);
+}
+impl mips_reg {
+    pub const MIPS_REG_F11: mips_reg = mips_reg(68);
+}
+impl mips_reg {
+    pub const MIPS_REG_F12: mips_reg = mips_reg(69);
+}
+impl mips_reg {
+    pub const MIPS_REG_F13: mips_reg = mips_reg(70);
+}
+impl mips_reg {
+    pub const MIPS_REG_F14: mips_reg = mips_reg(71);
+}
+impl mips_reg {
+    pub const MIPS_REG_F15: mips_reg = mips_reg(72);
+}
+impl mips_reg {
+    pub const MIPS_REG_F16: mips_reg = mips_reg(73);
+}
+impl mips_reg {
+    pub const MIPS_REG_F17: mips_reg = mips_reg(74);
+}
+impl mips_reg {
+    pub const MIPS_REG_F18: mips_reg = mips_reg(75);
+}
+impl mips_reg {
+    pub const MIPS_REG_F19: mips_reg = mips_reg(76);
+}
+impl mips_reg {
+    pub const MIPS_REG_F20: mips_reg = mips_reg(77);
+}
+impl mips_reg {
+    pub const MIPS_REG_F21: mips_reg = mips_reg(78);
+}
+impl mips_reg {
+    pub const MIPS_REG_F22: mips_reg = mips_reg(79);
+}
+impl mips_reg {
+    pub const MIPS_REG_F23: mips_reg = mips_reg(80);
+}
+impl mips_reg {
+    pub const MIPS_REG_F24: mips_reg = mips_reg(81);
+}
+impl mips_reg {
+    pub const MIPS_REG_F25: mips_reg = mips_reg(82);
+}
+impl mips_reg {
+    pub const MIPS_REG_F26: mips_reg = mips_reg(83);
+}
+impl mips_reg {
+    pub const MIPS_REG_F27: mips_reg = mips_reg(84);
+}
+impl mips_reg {
+    pub const MIPS_REG_F28: mips_reg = mips_reg(85);
+}
+impl mips_reg {
+    pub const MIPS_REG_F29: mips_reg = mips_reg(86);
+}
+impl mips_reg {
+    pub const MIPS_REG_F30: mips_reg = mips_reg(87);
+}
+impl mips_reg {
+    pub const MIPS_REG_F31: mips_reg = mips_reg(88);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC0: mips_reg = mips_reg(89);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC1: mips_reg = mips_reg(90);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC2: mips_reg = mips_reg(91);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC3: mips_reg = mips_reg(92);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC4: mips_reg = mips_reg(93);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC5: mips_reg = mips_reg(94);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC6: mips_reg = mips_reg(95);
+}
+impl mips_reg {
+    pub const MIPS_REG_FCC7: mips_reg = mips_reg(96);
+}
+impl mips_reg {
+    pub const MIPS_REG_W0: mips_reg = mips_reg(97);
+}
+impl mips_reg {
+    pub const MIPS_REG_W1: mips_reg = mips_reg(98);
+}
+impl mips_reg {
+    pub const MIPS_REG_W2: mips_reg = mips_reg(99);
 }
-#[repr(u32)]
-#[doc = " Operand type for instruction's operands"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum mips_op_type {
-    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
-    MIPS_OP_INVALID = 0,
-    #[doc = "< = CS_OP_REG (Register operand)."]
-    MIPS_OP_REG = 1,
-    #[doc = "< = CS_OP_IMM (Immediate operand)."]
-    MIPS_OP_IMM = 2,
-    #[doc = "< = CS_OP_MEM (Memory operand)."]
-    MIPS_OP_MEM = 3,
+impl mips_reg {
+    pub const MIPS_REG_W3: mips_reg = mips_reg(100);
+}
+impl mips_reg {
+    pub const MIPS_REG_W4: mips_reg = mips_reg(101);
+}
+impl mips_reg {
+    pub const MIPS_REG_W5: mips_reg = mips_reg(102);
+}
+impl mips_reg {
+    pub const MIPS_REG_W6: mips_reg = mips_reg(103);
+}
+impl mips_reg {
+    pub const MIPS_REG_W7: mips_reg = mips_reg(104);
+}
+impl mips_reg {
+    pub const MIPS_REG_W8: mips_reg = mips_reg(105);
+}
+impl mips_reg {
+    pub const MIPS_REG_W9: mips_reg = mips_reg(106);
+}
+impl mips_reg {
+    pub const MIPS_REG_W10: mips_reg = mips_reg(107);
+}
+impl mips_reg {
+    pub const MIPS_REG_W11: mips_reg = mips_reg(108);
+}
+impl mips_reg {
+    pub const MIPS_REG_W12: mips_reg = mips_reg(109);
+}
+impl mips_reg {
+    pub const MIPS_REG_W13: mips_reg = mips_reg(110);
+}
+impl mips_reg {
+    pub const MIPS_REG_W14: mips_reg = mips_reg(111);
+}
+impl mips_reg {
+    pub const MIPS_REG_W15: mips_reg = mips_reg(112);
+}
+impl mips_reg {
+    pub const MIPS_REG_W16: mips_reg = mips_reg(113);
+}
+impl mips_reg {
+    pub const MIPS_REG_W17: mips_reg = mips_reg(114);
+}
+impl mips_reg {
+    pub const MIPS_REG_W18: mips_reg = mips_reg(115);
+}
+impl mips_reg {
+    pub const MIPS_REG_W19: mips_reg = mips_reg(116);
+}
+impl mips_reg {
+    pub const MIPS_REG_W20: mips_reg = mips_reg(117);
+}
+impl mips_reg {
+    pub const MIPS_REG_W21: mips_reg = mips_reg(118);
+}
+impl mips_reg {
+    pub const MIPS_REG_W22: mips_reg = mips_reg(119);
+}
+impl mips_reg {
+    pub const MIPS_REG_W23: mips_reg = mips_reg(120);
+}
+impl mips_reg {
+    pub const MIPS_REG_W24: mips_reg = mips_reg(121);
+}
+impl mips_reg {
+    pub const MIPS_REG_W25: mips_reg = mips_reg(122);
+}
+impl mips_reg {
+    pub const MIPS_REG_W26: mips_reg = mips_reg(123);
+}
+impl mips_reg {
+    pub const MIPS_REG_W27: mips_reg = mips_reg(124);
+}
+impl mips_reg {
+    pub const MIPS_REG_W28: mips_reg = mips_reg(125);
+}
+impl mips_reg {
+    pub const MIPS_REG_W29: mips_reg = mips_reg(126);
+}
+impl mips_reg {
+    pub const MIPS_REG_W30: mips_reg = mips_reg(127);
+}
+impl mips_reg {
+    pub const MIPS_REG_W31: mips_reg = mips_reg(128);
+}
+impl mips_reg {
+    pub const MIPS_REG_HI: mips_reg = mips_reg(129);
+}
+impl mips_reg {
+    pub const MIPS_REG_LO: mips_reg = mips_reg(130);
+}
+impl mips_reg {
+    pub const MIPS_REG_P0: mips_reg = mips_reg(131);
+}
+impl mips_reg {
+    pub const MIPS_REG_P1: mips_reg = mips_reg(132);
+}
+impl mips_reg {
+    pub const MIPS_REG_P2: mips_reg = mips_reg(133);
+}
+impl mips_reg {
+    pub const MIPS_REG_MPL0: mips_reg = mips_reg(134);
+}
+impl mips_reg {
+    pub const MIPS_REG_MPL1: mips_reg = mips_reg(135);
+}
+impl mips_reg {
+    pub const MIPS_REG_MPL2: mips_reg = mips_reg(136);
+}
+impl mips_reg {
+    pub const MIPS_REG_ENDING: mips_reg = mips_reg(137);
+}
+impl mips_reg {
+    pub const MIPS_REG_ZERO: mips_reg = mips_reg(2);
+}
+impl mips_reg {
+    pub const MIPS_REG_AT: mips_reg = mips_reg(3);
+}
+impl mips_reg {
+    pub const MIPS_REG_V0: mips_reg = mips_reg(4);
+}
+impl mips_reg {
+    pub const MIPS_REG_V1: mips_reg = mips_reg(5);
+}
+impl mips_reg {
+    pub const MIPS_REG_A0: mips_reg = mips_reg(6);
+}
+impl mips_reg {
+    pub const MIPS_REG_A1: mips_reg = mips_reg(7);
+}
+impl mips_reg {
+    pub const MIPS_REG_A2: mips_reg = mips_reg(8);
 }
-pub mod mips_reg {
-    #[doc = " MIPS registers"]
-    pub type Type = libc::c_uint;
-    pub const MIPS_REG_INVALID: Type = 0;
-    pub const MIPS_REG_PC: Type = 1;
-    pub const MIPS_REG_0: Type = 2;
-    pub const MIPS_REG_1: Type = 3;
-    pub const MIPS_REG_2: Type = 4;
-    pub const MIPS_REG_3: Type = 5;
-    pub const MIPS_REG_4: Type = 6;
-    pub const MIPS_REG_5: Type = 7;
-    pub const MIPS_REG_6: Type = 8;
-    pub const MIPS_REG_7: Type = 9;
-    pub const MIPS_REG_8: Type = 10;
-    pub const MIPS_REG_9: Type = 11;
-    pub const MIPS_REG_10: Type = 12;
-    pub const MIPS_REG_11: Type = 13;
-    pub const MIPS_REG_12: Type = 14;
-    pub const MIPS_REG_13: Type = 15;
-    pub const MIPS_REG_14: Type = 16;
-    pub const MIPS_REG_15: Type = 17;
-    pub const MIPS_REG_16: Type = 18;
-    pub const MIPS_REG_17: Type = 19;
-    pub const MIPS_REG_18: Type = 20;
-    pub const MIPS_REG_19: Type = 21;
-    pub const MIPS_REG_20: Type = 22;
-    pub const MIPS_REG_21: Type = 23;
-    pub const MIPS_REG_22: Type = 24;
-    pub const MIPS_REG_23: Type = 25;
-    pub const MIPS_REG_24: Type = 26;
-    pub const MIPS_REG_25: Type = 27;
-    pub const MIPS_REG_26: Type = 28;
-    pub const MIPS_REG_27: Type = 29;
-    pub const MIPS_REG_28: Type = 30;
-    pub const MIPS_REG_29: Type = 31;
-    pub const MIPS_REG_30: Type = 32;
-    pub const MIPS_REG_31: Type = 33;
-    pub const MIPS_REG_DSPCCOND: Type = 34;
-    pub const MIPS_REG_DSPCARRY: Type = 35;
-    pub const MIPS_REG_DSPEFI: Type = 36;
-    pub const MIPS_REG_DSPOUTFLAG: Type = 37;
-    pub const MIPS_REG_DSPOUTFLAG16_19: Type = 38;
-    pub const MIPS_REG_DSPOUTFLAG20: Type = 39;
-    pub const MIPS_REG_DSPOUTFLAG21: Type = 40;
-    pub const MIPS_REG_DSPOUTFLAG22: Type = 41;
-    pub const MIPS_REG_DSPOUTFLAG23: Type = 42;
-    pub const MIPS_REG_DSPPOS: Type = 43;
-    pub const MIPS_REG_DSPSCOUNT: Type = 44;
-    pub const MIPS_REG_AC0: Type = 45;
-    pub const MIPS_REG_AC1: Type = 46;
-    pub const MIPS_REG_AC2: Type = 47;
-    pub const MIPS_REG_AC3: Type = 48;
-    pub const MIPS_REG_CC0: Type = 49;
-    pub const MIPS_REG_CC1: Type = 50;
-    pub const MIPS_REG_CC2: Type = 51;
-    pub const MIPS_REG_CC3: Type = 52;
-    pub const MIPS_REG_CC4: Type = 53;
-    pub const MIPS_REG_CC5: Type = 54;
-    pub const MIPS_REG_CC6: Type = 55;
-    pub const MIPS_REG_CC7: Type = 56;
-    pub const MIPS_REG_F0: Type = 57;
-    pub const MIPS_REG_F1: Type = 58;
-    pub const MIPS_REG_F2: Type = 59;
-    pub const MIPS_REG_F3: Type = 60;
-    pub const MIPS_REG_F4: Type = 61;
-    pub const MIPS_REG_F5: Type = 62;
-    pub const MIPS_REG_F6: Type = 63;
-    pub const MIPS_REG_F7: Type = 64;
-    pub const MIPS_REG_F8: Type = 65;
-    pub const MIPS_REG_F9: Type = 66;
-    pub const MIPS_REG_F10: Type = 67;
-    pub const MIPS_REG_F11: Type = 68;
-    pub const MIPS_REG_F12: Type = 69;
-    pub const MIPS_REG_F13: Type = 70;
-    pub const MIPS_REG_F14: Type = 71;
-    pub const MIPS_REG_F15: Type = 72;
-    pub const MIPS_REG_F16: Type = 73;
-    pub const MIPS_REG_F17: Type = 74;
-    pub const MIPS_REG_F18: Type = 75;
-    pub const MIPS_REG_F19: Type = 76;
-    pub const MIPS_REG_F20: Type = 77;
-    pub const MIPS_REG_F21: Type = 78;
-    pub const MIPS_REG_F22: Type = 79;
-    pub const MIPS_REG_F23: Type = 80;
-    pub const MIPS_REG_F24: Type = 81;
-    pub const MIPS_REG_F25: Type = 82;
-    pub const MIPS_REG_F26: Type = 83;
-    pub const MIPS_REG_F27: Type = 84;
-    pub const MIPS_REG_F28: Type = 85;
-    pub const MIPS_REG_F29: Type = 86;
-    pub const MIPS_REG_F30: Type = 87;
-    pub const MIPS_REG_F31: Type = 88;
-    pub const MIPS_REG_FCC0: Type = 89;
-    pub const MIPS_REG_FCC1: Type = 90;
-    pub const MIPS_REG_FCC2: Type = 91;
-    pub const MIPS_REG_FCC3: Type = 92;
-    pub const MIPS_REG_FCC4: Type = 93;
-    pub const MIPS_REG_FCC5: Type = 94;
-    pub const MIPS_REG_FCC6: Type = 95;
-    pub const MIPS_REG_FCC7: Type = 96;
-    pub const MIPS_REG_W0: Type = 97;
-    pub const MIPS_REG_W1: Type = 98;
-    pub const MIPS_REG_W2: Type = 99;
-    pub const MIPS_REG_W3: Type = 100;
-    pub const MIPS_REG_W4: Type = 101;
-    pub const MIPS_REG_W5: Type = 102;
-    pub const MIPS_REG_W6: Type = 103;
-    pub const MIPS_REG_W7: Type = 104;
-    pub const MIPS_REG_W8: Type = 105;
-    pub const MIPS_REG_W9: Type = 106;
-    pub const MIPS_REG_W10: Type = 107;
-    pub const MIPS_REG_W11: Type = 108;
-    pub const MIPS_REG_W12: Type = 109;
-    pub const MIPS_REG_W13: Type = 110;
-    pub const MIPS_REG_W14: Type = 111;
-    pub const MIPS_REG_W15: Type = 112;
-    pub const MIPS_REG_W16: Type = 113;
-    pub const MIPS_REG_W17: Type = 114;
-    pub const MIPS_REG_W18: Type = 115;
-    pub const MIPS_REG_W19: Type = 116;
-    pub const MIPS_REG_W20: Type = 117;
-    pub const MIPS_REG_W21: Type = 118;
-    pub const MIPS_REG_W22: Type = 119;
-    pub const MIPS_REG_W23: Type = 120;
-    pub const MIPS_REG_W24: Type = 121;
-    pub const MIPS_REG_W25: Type = 122;
-    pub const MIPS_REG_W26: Type = 123;
-    pub const MIPS_REG_W27: Type = 124;
-    pub const MIPS_REG_W28: Type = 125;
-    pub const MIPS_REG_W29: Type = 126;
-    pub const MIPS_REG_W30: Type = 127;
-    pub const MIPS_REG_W31: Type = 128;
-    pub const MIPS_REG_HI: Type = 129;
-    pub const MIPS_REG_LO: Type = 130;
-    pub const MIPS_REG_P0: Type = 131;
-    pub const MIPS_REG_P1: Type = 132;
-    pub const MIPS_REG_P2: Type = 133;
-    pub const MIPS_REG_MPL0: Type = 134;
-    pub const MIPS_REG_MPL1: Type = 135;
-    pub const MIPS_REG_MPL2: Type = 136;
-    pub const MIPS_REG_ENDING: Type = 137;
-    pub const MIPS_REG_ZERO: Type = 2;
-    pub const MIPS_REG_AT: Type = 3;
-    pub const MIPS_REG_V0: Type = 4;
-    pub const MIPS_REG_V1: Type = 5;
-    pub const MIPS_REG_A0: Type = 6;
-    pub const MIPS_REG_A1: Type = 7;
-    pub const MIPS_REG_A2: Type = 8;
-    pub const MIPS_REG_A3: Type = 9;
-    pub const MIPS_REG_T0: Type = 10;
-    pub const MIPS_REG_T1: Type = 11;
-    pub const MIPS_REG_T2: Type = 12;
-    pub const MIPS_REG_T3: Type = 13;
-    pub const MIPS_REG_T4: Type = 14;
-    pub const MIPS_REG_T5: Type = 15;
-    pub const MIPS_REG_T6: Type = 16;
-    pub const MIPS_REG_T7: Type = 17;
-    pub const MIPS_REG_S0: Type = 18;
-    pub const MIPS_REG_S1: Type = 19;
-    pub const MIPS_REG_S2: Type = 20;
-    pub const MIPS_REG_S3: Type = 21;
-    pub const MIPS_REG_S4: Type = 22;
-    pub const MIPS_REG_S5: Type = 23;
-    pub const MIPS_REG_S6: Type = 24;
-    pub const MIPS_REG_S7: Type = 25;
-    pub const MIPS_REG_T8: Type = 26;
-    pub const MIPS_REG_T9: Type = 27;
-    pub const MIPS_REG_K0: Type = 28;
-    pub const MIPS_REG_K1: Type = 29;
-    pub const MIPS_REG_GP: Type = 30;
-    pub const MIPS_REG_SP: Type = 31;
-    pub const MIPS_REG_FP: Type = 32;
-    pub const MIPS_REG_S8: Type = 32;
-    pub const MIPS_REG_RA: Type = 33;
-    pub const MIPS_REG_HI0: Type = 45;
-    pub const MIPS_REG_HI1: Type = 46;
-    pub const MIPS_REG_HI2: Type = 47;
-    pub const MIPS_REG_HI3: Type = 48;
-    pub const MIPS_REG_LO0: Type = 45;
-    pub const MIPS_REG_LO1: Type = 46;
-    pub const MIPS_REG_LO2: Type = 47;
-    pub const MIPS_REG_LO3: Type = 48;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with MIPS_OP_MEM operand type above"]
+impl mips_reg {
+    pub const MIPS_REG_A3: mips_reg = mips_reg(9);
+}
+impl mips_reg {
+    pub const MIPS_REG_T0: mips_reg = mips_reg(10);
+}
+impl mips_reg {
+    pub const MIPS_REG_T1: mips_reg = mips_reg(11);
+}
+impl mips_reg {
+    pub const MIPS_REG_T2: mips_reg = mips_reg(12);
+}
+impl mips_reg {
+    pub const MIPS_REG_T3: mips_reg = mips_reg(13);
+}
+impl mips_reg {
+    pub const MIPS_REG_T4: mips_reg = mips_reg(14);
+}
+impl mips_reg {
+    pub const MIPS_REG_T5: mips_reg = mips_reg(15);
+}
+impl mips_reg {
+    pub const MIPS_REG_T6: mips_reg = mips_reg(16);
+}
+impl mips_reg {
+    pub const MIPS_REG_T7: mips_reg = mips_reg(17);
+}
+impl mips_reg {
+    pub const MIPS_REG_S0: mips_reg = mips_reg(18);
+}
+impl mips_reg {
+    pub const MIPS_REG_S1: mips_reg = mips_reg(19);
+}
+impl mips_reg {
+    pub const MIPS_REG_S2: mips_reg = mips_reg(20);
+}
+impl mips_reg {
+    pub const MIPS_REG_S3: mips_reg = mips_reg(21);
+}
+impl mips_reg {
+    pub const MIPS_REG_S4: mips_reg = mips_reg(22);
+}
+impl mips_reg {
+    pub const MIPS_REG_S5: mips_reg = mips_reg(23);
+}
+impl mips_reg {
+    pub const MIPS_REG_S6: mips_reg = mips_reg(24);
+}
+impl mips_reg {
+    pub const MIPS_REG_S7: mips_reg = mips_reg(25);
+}
+impl mips_reg {
+    pub const MIPS_REG_T8: mips_reg = mips_reg(26);
+}
+impl mips_reg {
+    pub const MIPS_REG_T9: mips_reg = mips_reg(27);
+}
+impl mips_reg {
+    pub const MIPS_REG_K0: mips_reg = mips_reg(28);
+}
+impl mips_reg {
+    pub const MIPS_REG_K1: mips_reg = mips_reg(29);
+}
+impl mips_reg {
+    pub const MIPS_REG_GP: mips_reg = mips_reg(30);
+}
+impl mips_reg {
+    pub const MIPS_REG_SP: mips_reg = mips_reg(31);
+}
+impl mips_reg {
+    pub const MIPS_REG_FP: mips_reg = mips_reg(32);
+}
+impl mips_reg {
+    pub const MIPS_REG_S8: mips_reg = mips_reg(32);
+}
+impl mips_reg {
+    pub const MIPS_REG_RA: mips_reg = mips_reg(33);
+}
+impl mips_reg {
+    pub const MIPS_REG_HI0: mips_reg = mips_reg(45);
+}
+impl mips_reg {
+    pub const MIPS_REG_HI1: mips_reg = mips_reg(46);
+}
+impl mips_reg {
+    pub const MIPS_REG_HI2: mips_reg = mips_reg(47);
+}
+impl mips_reg {
+    pub const MIPS_REG_HI3: mips_reg = mips_reg(48);
+}
+impl mips_reg {
+    pub const MIPS_REG_LO0: mips_reg = mips_reg(45);
+}
+impl mips_reg {
+    pub const MIPS_REG_LO1: mips_reg = mips_reg(46);
+}
+impl mips_reg {
+    pub const MIPS_REG_LO2: mips_reg = mips_reg(47);
+}
+impl mips_reg {
+    pub const MIPS_REG_LO3: mips_reg = mips_reg(48);
+}
+#[repr(transparent)]
+#[doc = " MIPS registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct mips_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with MIPS_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct mips_op_mem {
     #[doc = "< base register"]
-    pub base: mips_reg::Type,
+    pub base: mips_reg,
     #[doc = "< displacement/offset value"]
     pub disp: i64,
 }
-impl Clone for mips_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_mips_op {
     #[doc = "< operand type"]
     pub type_: mips_op_type,
     pub __bindgen_anon_1: cs_mips_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_mips_op__bindgen_ty_1 {
     #[doc = "< register id for REG operand"]
-    pub reg: mips_reg::Type,
+    pub reg: mips_reg,
     #[doc = "< immediate value for IMM operand"]
     pub imm: i64,
     #[doc = "< base/index/scale/disp value for MEM operand"]
     pub mem: mips_op_mem,
 }
-impl Clone for cs_mips_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_mips_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_mips_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_mips_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_mips_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -5052,26 +6470,16 @@ impl ::core::fmt::Debug for cs_mips_op {
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_mips {
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_mips_op; 10usize],
 }
-impl Clone for cs_mips {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_mips {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write!(
-            f,
-            "cs_mips {{ op_count: {:?}, operands: {:?} }}",
-            self.op_count, self.operands
-        )
+        write!(f, "cs_mips {{ operands: {:?} }}", self.operands)
     }
 }
 #[repr(u32)]
@@ -5706,391 +7114,950 @@ pub enum mips_insn {
     MIPS_INS_JR_HB = 625,
     MIPS_INS_ENDING = 626,
 }
-pub mod mips_insn_group {
-    #[doc = " Group of MIPS instructions"]
-    pub type Type = libc::c_uint;
-    #[doc = "< = CS_GRP_INVALID"]
-    pub const MIPS_GRP_INVALID: Type = 0;
-    #[doc = "< = CS_GRP_JUMP"]
-    pub const MIPS_GRP_JUMP: Type = 1;
-    #[doc = "< = CS_GRP_CALL"]
-    pub const MIPS_GRP_CALL: Type = 2;
-    #[doc = "< = CS_GRP_RET"]
-    pub const MIPS_GRP_RET: Type = 3;
-    #[doc = "< = CS_GRP_INT"]
-    pub const MIPS_GRP_INT: Type = 4;
-    #[doc = "< = CS_GRP_IRET"]
-    pub const MIPS_GRP_IRET: Type = 5;
-    #[doc = "< = CS_GRP_PRIVILEGE"]
-    pub const MIPS_GRP_PRIVILEGE: Type = 6;
-    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
-    pub const MIPS_GRP_BRANCH_RELATIVE: Type = 7;
-    pub const MIPS_GRP_BITCOUNT: Type = 128;
-    pub const MIPS_GRP_DSP: Type = 129;
-    pub const MIPS_GRP_DSPR2: Type = 130;
-    pub const MIPS_GRP_FPIDX: Type = 131;
-    pub const MIPS_GRP_MSA: Type = 132;
-    pub const MIPS_GRP_MIPS32R2: Type = 133;
-    pub const MIPS_GRP_MIPS64: Type = 134;
-    pub const MIPS_GRP_MIPS64R2: Type = 135;
-    pub const MIPS_GRP_SEINREG: Type = 136;
-    pub const MIPS_GRP_STDENC: Type = 137;
-    pub const MIPS_GRP_SWAP: Type = 138;
-    pub const MIPS_GRP_MICROMIPS: Type = 139;
-    pub const MIPS_GRP_MIPS16MODE: Type = 140;
-    pub const MIPS_GRP_FP64BIT: Type = 141;
-    pub const MIPS_GRP_NONANSFPMATH: Type = 142;
-    pub const MIPS_GRP_NOTFP64BIT: Type = 143;
-    pub const MIPS_GRP_NOTINMICROMIPS: Type = 144;
-    pub const MIPS_GRP_NOTNACL: Type = 145;
-    pub const MIPS_GRP_NOTMIPS32R6: Type = 146;
-    pub const MIPS_GRP_NOTMIPS64R6: Type = 147;
-    pub const MIPS_GRP_CNMIPS: Type = 148;
-    pub const MIPS_GRP_MIPS32: Type = 149;
-    pub const MIPS_GRP_MIPS32R6: Type = 150;
-    pub const MIPS_GRP_MIPS64R6: Type = 151;
-    pub const MIPS_GRP_MIPS2: Type = 152;
-    pub const MIPS_GRP_MIPS3: Type = 153;
-    pub const MIPS_GRP_MIPS3_32: Type = 154;
-    pub const MIPS_GRP_MIPS3_32R2: Type = 155;
-    pub const MIPS_GRP_MIPS4_32: Type = 156;
-    pub const MIPS_GRP_MIPS4_32R2: Type = 157;
-    pub const MIPS_GRP_MIPS5_32R2: Type = 158;
-    pub const MIPS_GRP_GP32BIT: Type = 159;
-    pub const MIPS_GRP_GP64BIT: Type = 160;
-    pub const MIPS_GRP_ENDING: Type = 161;
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_INVALID"]
+    pub const MIPS_GRP_INVALID: mips_insn_group = mips_insn_group(0);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_JUMP"]
+    pub const MIPS_GRP_JUMP: mips_insn_group = mips_insn_group(1);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_CALL"]
+    pub const MIPS_GRP_CALL: mips_insn_group = mips_insn_group(2);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_RET"]
+    pub const MIPS_GRP_RET: mips_insn_group = mips_insn_group(3);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_INT"]
+    pub const MIPS_GRP_INT: mips_insn_group = mips_insn_group(4);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_IRET"]
+    pub const MIPS_GRP_IRET: mips_insn_group = mips_insn_group(5);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_PRIVILEGE"]
+    pub const MIPS_GRP_PRIVILEGE: mips_insn_group = mips_insn_group(6);
+}
+impl mips_insn_group {
+    #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
+    pub const MIPS_GRP_BRANCH_RELATIVE: mips_insn_group = mips_insn_group(7);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_BITCOUNT: mips_insn_group = mips_insn_group(128);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_DSP: mips_insn_group = mips_insn_group(129);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_DSPR2: mips_insn_group = mips_insn_group(130);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_FPIDX: mips_insn_group = mips_insn_group(131);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MSA: mips_insn_group = mips_insn_group(132);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS32R2: mips_insn_group = mips_insn_group(133);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS64: mips_insn_group = mips_insn_group(134);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS64R2: mips_insn_group = mips_insn_group(135);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_SEINREG: mips_insn_group = mips_insn_group(136);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_STDENC: mips_insn_group = mips_insn_group(137);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_SWAP: mips_insn_group = mips_insn_group(138);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MICROMIPS: mips_insn_group = mips_insn_group(139);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS16MODE: mips_insn_group = mips_insn_group(140);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_FP64BIT: mips_insn_group = mips_insn_group(141);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_NONANSFPMATH: mips_insn_group = mips_insn_group(142);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_NOTFP64BIT: mips_insn_group = mips_insn_group(143);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_NOTINMICROMIPS: mips_insn_group = mips_insn_group(144);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_NOTNACL: mips_insn_group = mips_insn_group(145);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_NOTMIPS32R6: mips_insn_group = mips_insn_group(146);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_NOTMIPS64R6: mips_insn_group = mips_insn_group(147);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_CNMIPS: mips_insn_group = mips_insn_group(148);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS32: mips_insn_group = mips_insn_group(149);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS32R6: mips_insn_group = mips_insn_group(150);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS64R6: mips_insn_group = mips_insn_group(151);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS2: mips_insn_group = mips_insn_group(152);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS3: mips_insn_group = mips_insn_group(153);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS3_32: mips_insn_group = mips_insn_group(154);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS3_32R2: mips_insn_group = mips_insn_group(155);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS4_32: mips_insn_group = mips_insn_group(156);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS4_32R2: mips_insn_group = mips_insn_group(157);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_MIPS5_32R2: mips_insn_group = mips_insn_group(158);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_GP32BIT: mips_insn_group = mips_insn_group(159);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_GP64BIT: mips_insn_group = mips_insn_group(160);
+}
+impl mips_insn_group {
+    pub const MIPS_GRP_ENDING: mips_insn_group = mips_insn_group(161);
+}
+#[repr(transparent)]
+#[doc = " Group of MIPS instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct mips_insn_group(pub libc::c_uint);
+#[repr(u32)]
+#[doc = " PPC branch codes for some branch instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub enum ppc_bc {
+    PPC_BC_INVALID = 0,
+    PPC_BC_LT = 12,
+    PPC_BC_LE = 36,
+    PPC_BC_EQ = 76,
+    PPC_BC_GE = 4,
+    PPC_BC_GT = 44,
+    PPC_BC_NE = 68,
+    PPC_BC_UN = 108,
+    PPC_BC_NU = 100,
+    #[doc = "< summary overflow"]
+    PPC_BC_SO = 140,
+    #[doc = "< not summary overflow"]
+    PPC_BC_NS = 132,
+}
+#[repr(u32)]
+#[doc = " PPC branch hint for some branch instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub enum ppc_bh {
+    #[doc = "< no hint"]
+    PPC_BH_INVALID = 0,
+    #[doc = "< PLUS hint"]
+    PPC_BH_PLUS = 1,
+    #[doc = "< MINUS hint"]
+    PPC_BH_MINUS = 2,
+}
+#[repr(u32)]
+#[doc = " Operand type for instruction's operands"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub enum ppc_op_type {
+    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
+    PPC_OP_INVALID = 0,
+    #[doc = "< = CS_OP_REG (Register operand)."]
+    PPC_OP_REG = 1,
+    #[doc = "< = CS_OP_IMM (Immediate operand)."]
+    PPC_OP_IMM = 2,
+    #[doc = "< = CS_OP_MEM (Memory operand)."]
+    PPC_OP_MEM = 3,
+    #[doc = "< Condition Register field"]
+    PPC_OP_CRX = 64,
+}
+impl ppc_reg {
+    pub const PPC_REG_INVALID: ppc_reg = ppc_reg(0);
+}
+impl ppc_reg {
+    pub const PPC_REG_CARRY: ppc_reg = ppc_reg(2);
+}
+impl ppc_reg {
+    pub const PPC_REG_CTR: ppc_reg = ppc_reg(3);
+}
+impl ppc_reg {
+    pub const PPC_REG_LR: ppc_reg = ppc_reg(5);
+}
+impl ppc_reg {
+    pub const PPC_REG_RM: ppc_reg = ppc_reg(6);
+}
+impl ppc_reg {
+    pub const PPC_REG_VRSAVE: ppc_reg = ppc_reg(8);
+}
+impl ppc_reg {
+    pub const PPC_REG_XER: ppc_reg = ppc_reg(9);
+}
+impl ppc_reg {
+    pub const PPC_REG_ZERO: ppc_reg = ppc_reg(10);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR0: ppc_reg = ppc_reg(12);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR1: ppc_reg = ppc_reg(13);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR2: ppc_reg = ppc_reg(14);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR3: ppc_reg = ppc_reg(15);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR4: ppc_reg = ppc_reg(16);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR5: ppc_reg = ppc_reg(17);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR6: ppc_reg = ppc_reg(18);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR7: ppc_reg = ppc_reg(19);
+}
+impl ppc_reg {
+    pub const PPC_REG_CTR8: ppc_reg = ppc_reg(20);
+}
+impl ppc_reg {
+    pub const PPC_REG_F0: ppc_reg = ppc_reg(21);
+}
+impl ppc_reg {
+    pub const PPC_REG_F1: ppc_reg = ppc_reg(22);
+}
+impl ppc_reg {
+    pub const PPC_REG_F2: ppc_reg = ppc_reg(23);
+}
+impl ppc_reg {
+    pub const PPC_REG_F3: ppc_reg = ppc_reg(24);
+}
+impl ppc_reg {
+    pub const PPC_REG_F4: ppc_reg = ppc_reg(25);
+}
+impl ppc_reg {
+    pub const PPC_REG_F5: ppc_reg = ppc_reg(26);
+}
+impl ppc_reg {
+    pub const PPC_REG_F6: ppc_reg = ppc_reg(27);
+}
+impl ppc_reg {
+    pub const PPC_REG_F7: ppc_reg = ppc_reg(28);
+}
+impl ppc_reg {
+    pub const PPC_REG_F8: ppc_reg = ppc_reg(29);
+}
+impl ppc_reg {
+    pub const PPC_REG_F9: ppc_reg = ppc_reg(30);
+}
+impl ppc_reg {
+    pub const PPC_REG_F10: ppc_reg = ppc_reg(31);
+}
+impl ppc_reg {
+    pub const PPC_REG_F11: ppc_reg = ppc_reg(32);
+}
+impl ppc_reg {
+    pub const PPC_REG_F12: ppc_reg = ppc_reg(33);
+}
+impl ppc_reg {
+    pub const PPC_REG_F13: ppc_reg = ppc_reg(34);
+}
+impl ppc_reg {
+    pub const PPC_REG_F14: ppc_reg = ppc_reg(35);
+}
+impl ppc_reg {
+    pub const PPC_REG_F15: ppc_reg = ppc_reg(36);
+}
+impl ppc_reg {
+    pub const PPC_REG_F16: ppc_reg = ppc_reg(37);
+}
+impl ppc_reg {
+    pub const PPC_REG_F17: ppc_reg = ppc_reg(38);
+}
+impl ppc_reg {
+    pub const PPC_REG_F18: ppc_reg = ppc_reg(39);
+}
+impl ppc_reg {
+    pub const PPC_REG_F19: ppc_reg = ppc_reg(40);
+}
+impl ppc_reg {
+    pub const PPC_REG_F20: ppc_reg = ppc_reg(41);
+}
+impl ppc_reg {
+    pub const PPC_REG_F21: ppc_reg = ppc_reg(42);
+}
+impl ppc_reg {
+    pub const PPC_REG_F22: ppc_reg = ppc_reg(43);
+}
+impl ppc_reg {
+    pub const PPC_REG_F23: ppc_reg = ppc_reg(44);
+}
+impl ppc_reg {
+    pub const PPC_REG_F24: ppc_reg = ppc_reg(45);
+}
+impl ppc_reg {
+    pub const PPC_REG_F25: ppc_reg = ppc_reg(46);
+}
+impl ppc_reg {
+    pub const PPC_REG_F26: ppc_reg = ppc_reg(47);
+}
+impl ppc_reg {
+    pub const PPC_REG_F27: ppc_reg = ppc_reg(48);
+}
+impl ppc_reg {
+    pub const PPC_REG_F28: ppc_reg = ppc_reg(49);
+}
+impl ppc_reg {
+    pub const PPC_REG_F29: ppc_reg = ppc_reg(50);
+}
+impl ppc_reg {
+    pub const PPC_REG_F30: ppc_reg = ppc_reg(51);
+}
+impl ppc_reg {
+    pub const PPC_REG_F31: ppc_reg = ppc_reg(52);
+}
+impl ppc_reg {
+    pub const PPC_REG_LR8: ppc_reg = ppc_reg(54);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q0: ppc_reg = ppc_reg(55);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q1: ppc_reg = ppc_reg(56);
 }
-#[repr(u32)]
-#[doc = " PPC branch codes for some branch instructions"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum ppc_bc {
-    PPC_BC_INVALID = 0,
-    PPC_BC_LT = 12,
-    PPC_BC_LE = 36,
-    PPC_BC_EQ = 76,
-    PPC_BC_GE = 4,
-    PPC_BC_GT = 44,
-    PPC_BC_NE = 68,
-    PPC_BC_UN = 108,
-    PPC_BC_NU = 100,
-    #[doc = "< summary overflow"]
-    PPC_BC_SO = 140,
-    #[doc = "< not summary overflow"]
-    PPC_BC_NS = 132,
+impl ppc_reg {
+    pub const PPC_REG_Q2: ppc_reg = ppc_reg(57);
 }
-#[repr(u32)]
-#[doc = " PPC branch hint for some branch instructions"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum ppc_bh {
-    #[doc = "< no hint"]
-    PPC_BH_INVALID = 0,
-    #[doc = "< PLUS hint"]
-    PPC_BH_PLUS = 1,
-    #[doc = "< MINUS hint"]
-    PPC_BH_MINUS = 2,
+impl ppc_reg {
+    pub const PPC_REG_Q3: ppc_reg = ppc_reg(58);
 }
-#[repr(u32)]
-#[doc = " Operand type for instruction's operands"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum ppc_op_type {
-    #[doc = "< = CS_OP_INVALID (Uninitialized)."]
-    PPC_OP_INVALID = 0,
-    #[doc = "< = CS_OP_REG (Register operand)."]
-    PPC_OP_REG = 1,
-    #[doc = "< = CS_OP_IMM (Immediate operand)."]
-    PPC_OP_IMM = 2,
-    #[doc = "< = CS_OP_MEM (Memory operand)."]
-    PPC_OP_MEM = 3,
-    #[doc = "< Condition Register field"]
-    PPC_OP_CRX = 64,
+impl ppc_reg {
+    pub const PPC_REG_Q4: ppc_reg = ppc_reg(59);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q5: ppc_reg = ppc_reg(60);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q6: ppc_reg = ppc_reg(61);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q7: ppc_reg = ppc_reg(62);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q8: ppc_reg = ppc_reg(63);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q9: ppc_reg = ppc_reg(64);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q10: ppc_reg = ppc_reg(65);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q11: ppc_reg = ppc_reg(66);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q12: ppc_reg = ppc_reg(67);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q13: ppc_reg = ppc_reg(68);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q14: ppc_reg = ppc_reg(69);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q15: ppc_reg = ppc_reg(70);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q16: ppc_reg = ppc_reg(71);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q17: ppc_reg = ppc_reg(72);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q18: ppc_reg = ppc_reg(73);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q19: ppc_reg = ppc_reg(74);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q20: ppc_reg = ppc_reg(75);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q21: ppc_reg = ppc_reg(76);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q22: ppc_reg = ppc_reg(77);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q23: ppc_reg = ppc_reg(78);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q24: ppc_reg = ppc_reg(79);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q25: ppc_reg = ppc_reg(80);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q26: ppc_reg = ppc_reg(81);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q27: ppc_reg = ppc_reg(82);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q28: ppc_reg = ppc_reg(83);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q29: ppc_reg = ppc_reg(84);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q30: ppc_reg = ppc_reg(85);
+}
+impl ppc_reg {
+    pub const PPC_REG_Q31: ppc_reg = ppc_reg(86);
+}
+impl ppc_reg {
+    pub const PPC_REG_R0: ppc_reg = ppc_reg(87);
+}
+impl ppc_reg {
+    pub const PPC_REG_R1: ppc_reg = ppc_reg(88);
+}
+impl ppc_reg {
+    pub const PPC_REG_R2: ppc_reg = ppc_reg(89);
+}
+impl ppc_reg {
+    pub const PPC_REG_R3: ppc_reg = ppc_reg(90);
+}
+impl ppc_reg {
+    pub const PPC_REG_R4: ppc_reg = ppc_reg(91);
+}
+impl ppc_reg {
+    pub const PPC_REG_R5: ppc_reg = ppc_reg(92);
+}
+impl ppc_reg {
+    pub const PPC_REG_R6: ppc_reg = ppc_reg(93);
+}
+impl ppc_reg {
+    pub const PPC_REG_R7: ppc_reg = ppc_reg(94);
+}
+impl ppc_reg {
+    pub const PPC_REG_R8: ppc_reg = ppc_reg(95);
+}
+impl ppc_reg {
+    pub const PPC_REG_R9: ppc_reg = ppc_reg(96);
+}
+impl ppc_reg {
+    pub const PPC_REG_R10: ppc_reg = ppc_reg(97);
+}
+impl ppc_reg {
+    pub const PPC_REG_R11: ppc_reg = ppc_reg(98);
+}
+impl ppc_reg {
+    pub const PPC_REG_R12: ppc_reg = ppc_reg(99);
+}
+impl ppc_reg {
+    pub const PPC_REG_R13: ppc_reg = ppc_reg(100);
+}
+impl ppc_reg {
+    pub const PPC_REG_R14: ppc_reg = ppc_reg(101);
+}
+impl ppc_reg {
+    pub const PPC_REG_R15: ppc_reg = ppc_reg(102);
+}
+impl ppc_reg {
+    pub const PPC_REG_R16: ppc_reg = ppc_reg(103);
+}
+impl ppc_reg {
+    pub const PPC_REG_R17: ppc_reg = ppc_reg(104);
+}
+impl ppc_reg {
+    pub const PPC_REG_R18: ppc_reg = ppc_reg(105);
+}
+impl ppc_reg {
+    pub const PPC_REG_R19: ppc_reg = ppc_reg(106);
+}
+impl ppc_reg {
+    pub const PPC_REG_R20: ppc_reg = ppc_reg(107);
+}
+impl ppc_reg {
+    pub const PPC_REG_R21: ppc_reg = ppc_reg(108);
+}
+impl ppc_reg {
+    pub const PPC_REG_R22: ppc_reg = ppc_reg(109);
+}
+impl ppc_reg {
+    pub const PPC_REG_R23: ppc_reg = ppc_reg(110);
+}
+impl ppc_reg {
+    pub const PPC_REG_R24: ppc_reg = ppc_reg(111);
+}
+impl ppc_reg {
+    pub const PPC_REG_R25: ppc_reg = ppc_reg(112);
+}
+impl ppc_reg {
+    pub const PPC_REG_R26: ppc_reg = ppc_reg(113);
+}
+impl ppc_reg {
+    pub const PPC_REG_R27: ppc_reg = ppc_reg(114);
+}
+impl ppc_reg {
+    pub const PPC_REG_R28: ppc_reg = ppc_reg(115);
+}
+impl ppc_reg {
+    pub const PPC_REG_R29: ppc_reg = ppc_reg(116);
+}
+impl ppc_reg {
+    pub const PPC_REG_R30: ppc_reg = ppc_reg(117);
+}
+impl ppc_reg {
+    pub const PPC_REG_R31: ppc_reg = ppc_reg(118);
+}
+impl ppc_reg {
+    pub const PPC_REG_V0: ppc_reg = ppc_reg(151);
+}
+impl ppc_reg {
+    pub const PPC_REG_V1: ppc_reg = ppc_reg(152);
+}
+impl ppc_reg {
+    pub const PPC_REG_V2: ppc_reg = ppc_reg(153);
+}
+impl ppc_reg {
+    pub const PPC_REG_V3: ppc_reg = ppc_reg(154);
+}
+impl ppc_reg {
+    pub const PPC_REG_V4: ppc_reg = ppc_reg(155);
+}
+impl ppc_reg {
+    pub const PPC_REG_V5: ppc_reg = ppc_reg(156);
+}
+impl ppc_reg {
+    pub const PPC_REG_V6: ppc_reg = ppc_reg(157);
+}
+impl ppc_reg {
+    pub const PPC_REG_V7: ppc_reg = ppc_reg(158);
+}
+impl ppc_reg {
+    pub const PPC_REG_V8: ppc_reg = ppc_reg(159);
+}
+impl ppc_reg {
+    pub const PPC_REG_V9: ppc_reg = ppc_reg(160);
+}
+impl ppc_reg {
+    pub const PPC_REG_V10: ppc_reg = ppc_reg(161);
+}
+impl ppc_reg {
+    pub const PPC_REG_V11: ppc_reg = ppc_reg(162);
+}
+impl ppc_reg {
+    pub const PPC_REG_V12: ppc_reg = ppc_reg(163);
+}
+impl ppc_reg {
+    pub const PPC_REG_V13: ppc_reg = ppc_reg(164);
+}
+impl ppc_reg {
+    pub const PPC_REG_V14: ppc_reg = ppc_reg(165);
+}
+impl ppc_reg {
+    pub const PPC_REG_V15: ppc_reg = ppc_reg(166);
+}
+impl ppc_reg {
+    pub const PPC_REG_V16: ppc_reg = ppc_reg(167);
+}
+impl ppc_reg {
+    pub const PPC_REG_V17: ppc_reg = ppc_reg(168);
+}
+impl ppc_reg {
+    pub const PPC_REG_V18: ppc_reg = ppc_reg(169);
+}
+impl ppc_reg {
+    pub const PPC_REG_V19: ppc_reg = ppc_reg(170);
 }
-pub mod ppc_reg {
-    #[doc = " PPC registers"]
-    pub type Type = libc::c_uint;
-    pub const PPC_REG_INVALID: Type = 0;
-    pub const PPC_REG_CARRY: Type = 2;
-    pub const PPC_REG_CTR: Type = 3;
-    pub const PPC_REG_LR: Type = 5;
-    pub const PPC_REG_RM: Type = 6;
-    pub const PPC_REG_VRSAVE: Type = 8;
-    pub const PPC_REG_XER: Type = 9;
-    pub const PPC_REG_ZERO: Type = 10;
-    pub const PPC_REG_CR0: Type = 12;
-    pub const PPC_REG_CR1: Type = 13;
-    pub const PPC_REG_CR2: Type = 14;
-    pub const PPC_REG_CR3: Type = 15;
-    pub const PPC_REG_CR4: Type = 16;
-    pub const PPC_REG_CR5: Type = 17;
-    pub const PPC_REG_CR6: Type = 18;
-    pub const PPC_REG_CR7: Type = 19;
-    pub const PPC_REG_CTR8: Type = 20;
-    pub const PPC_REG_F0: Type = 21;
-    pub const PPC_REG_F1: Type = 22;
-    pub const PPC_REG_F2: Type = 23;
-    pub const PPC_REG_F3: Type = 24;
-    pub const PPC_REG_F4: Type = 25;
-    pub const PPC_REG_F5: Type = 26;
-    pub const PPC_REG_F6: Type = 27;
-    pub const PPC_REG_F7: Type = 28;
-    pub const PPC_REG_F8: Type = 29;
-    pub const PPC_REG_F9: Type = 30;
-    pub const PPC_REG_F10: Type = 31;
-    pub const PPC_REG_F11: Type = 32;
-    pub const PPC_REG_F12: Type = 33;
-    pub const PPC_REG_F13: Type = 34;
-    pub const PPC_REG_F14: Type = 35;
-    pub const PPC_REG_F15: Type = 36;
-    pub const PPC_REG_F16: Type = 37;
-    pub const PPC_REG_F17: Type = 38;
-    pub const PPC_REG_F18: Type = 39;
-    pub const PPC_REG_F19: Type = 40;
-    pub const PPC_REG_F20: Type = 41;
-    pub const PPC_REG_F21: Type = 42;
-    pub const PPC_REG_F22: Type = 43;
-    pub const PPC_REG_F23: Type = 44;
-    pub const PPC_REG_F24: Type = 45;
-    pub const PPC_REG_F25: Type = 46;
-    pub const PPC_REG_F26: Type = 47;
-    pub const PPC_REG_F27: Type = 48;
-    pub const PPC_REG_F28: Type = 49;
-    pub const PPC_REG_F29: Type = 50;
-    pub const PPC_REG_F30: Type = 51;
-    pub const PPC_REG_F31: Type = 52;
-    pub const PPC_REG_LR8: Type = 54;
-    pub const PPC_REG_Q0: Type = 55;
-    pub const PPC_REG_Q1: Type = 56;
-    pub const PPC_REG_Q2: Type = 57;
-    pub const PPC_REG_Q3: Type = 58;
-    pub const PPC_REG_Q4: Type = 59;
-    pub const PPC_REG_Q5: Type = 60;
-    pub const PPC_REG_Q6: Type = 61;
-    pub const PPC_REG_Q7: Type = 62;
-    pub const PPC_REG_Q8: Type = 63;
-    pub const PPC_REG_Q9: Type = 64;
-    pub const PPC_REG_Q10: Type = 65;
-    pub const PPC_REG_Q11: Type = 66;
-    pub const PPC_REG_Q12: Type = 67;
-    pub const PPC_REG_Q13: Type = 68;
-    pub const PPC_REG_Q14: Type = 69;
-    pub const PPC_REG_Q15: Type = 70;
-    pub const PPC_REG_Q16: Type = 71;
-    pub const PPC_REG_Q17: Type = 72;
-    pub const PPC_REG_Q18: Type = 73;
-    pub const PPC_REG_Q19: Type = 74;
-    pub const PPC_REG_Q20: Type = 75;
-    pub const PPC_REG_Q21: Type = 76;
-    pub const PPC_REG_Q22: Type = 77;
-    pub const PPC_REG_Q23: Type = 78;
-    pub const PPC_REG_Q24: Type = 79;
-    pub const PPC_REG_Q25: Type = 80;
-    pub const PPC_REG_Q26: Type = 81;
-    pub const PPC_REG_Q27: Type = 82;
-    pub const PPC_REG_Q28: Type = 83;
-    pub const PPC_REG_Q29: Type = 84;
-    pub const PPC_REG_Q30: Type = 85;
-    pub const PPC_REG_Q31: Type = 86;
-    pub const PPC_REG_R0: Type = 87;
-    pub const PPC_REG_R1: Type = 88;
-    pub const PPC_REG_R2: Type = 89;
-    pub const PPC_REG_R3: Type = 90;
-    pub const PPC_REG_R4: Type = 91;
-    pub const PPC_REG_R5: Type = 92;
-    pub const PPC_REG_R6: Type = 93;
-    pub const PPC_REG_R7: Type = 94;
-    pub const PPC_REG_R8: Type = 95;
-    pub const PPC_REG_R9: Type = 96;
-    pub const PPC_REG_R10: Type = 97;
-    pub const PPC_REG_R11: Type = 98;
-    pub const PPC_REG_R12: Type = 99;
-    pub const PPC_REG_R13: Type = 100;
-    pub const PPC_REG_R14: Type = 101;
-    pub const PPC_REG_R15: Type = 102;
-    pub const PPC_REG_R16: Type = 103;
-    pub const PPC_REG_R17: Type = 104;
-    pub const PPC_REG_R18: Type = 105;
-    pub const PPC_REG_R19: Type = 106;
-    pub const PPC_REG_R20: Type = 107;
-    pub const PPC_REG_R21: Type = 108;
-    pub const PPC_REG_R22: Type = 109;
-    pub const PPC_REG_R23: Type = 110;
-    pub const PPC_REG_R24: Type = 111;
-    pub const PPC_REG_R25: Type = 112;
-    pub const PPC_REG_R26: Type = 113;
-    pub const PPC_REG_R27: Type = 114;
-    pub const PPC_REG_R28: Type = 115;
-    pub const PPC_REG_R29: Type = 116;
-    pub const PPC_REG_R30: Type = 117;
-    pub const PPC_REG_R31: Type = 118;
-    pub const PPC_REG_V0: Type = 151;
-    pub const PPC_REG_V1: Type = 152;
-    pub const PPC_REG_V2: Type = 153;
-    pub const PPC_REG_V3: Type = 154;
-    pub const PPC_REG_V4: Type = 155;
-    pub const PPC_REG_V5: Type = 156;
-    pub const PPC_REG_V6: Type = 157;
-    pub const PPC_REG_V7: Type = 158;
-    pub const PPC_REG_V8: Type = 159;
-    pub const PPC_REG_V9: Type = 160;
-    pub const PPC_REG_V10: Type = 161;
-    pub const PPC_REG_V11: Type = 162;
-    pub const PPC_REG_V12: Type = 163;
-    pub const PPC_REG_V13: Type = 164;
-    pub const PPC_REG_V14: Type = 165;
-    pub const PPC_REG_V15: Type = 166;
-    pub const PPC_REG_V16: Type = 167;
-    pub const PPC_REG_V17: Type = 168;
-    pub const PPC_REG_V18: Type = 169;
-    pub const PPC_REG_V19: Type = 170;
-    pub const PPC_REG_V20: Type = 171;
-    pub const PPC_REG_V21: Type = 172;
-    pub const PPC_REG_V22: Type = 173;
-    pub const PPC_REG_V23: Type = 174;
-    pub const PPC_REG_V24: Type = 175;
-    pub const PPC_REG_V25: Type = 176;
-    pub const PPC_REG_V26: Type = 177;
-    pub const PPC_REG_V27: Type = 178;
-    pub const PPC_REG_V28: Type = 179;
-    pub const PPC_REG_V29: Type = 180;
-    pub const PPC_REG_V30: Type = 181;
-    pub const PPC_REG_V31: Type = 182;
-    pub const PPC_REG_VS0: Type = 215;
-    pub const PPC_REG_VS1: Type = 216;
-    pub const PPC_REG_VS2: Type = 217;
-    pub const PPC_REG_VS3: Type = 218;
-    pub const PPC_REG_VS4: Type = 219;
-    pub const PPC_REG_VS5: Type = 220;
-    pub const PPC_REG_VS6: Type = 221;
-    pub const PPC_REG_VS7: Type = 222;
-    pub const PPC_REG_VS8: Type = 223;
-    pub const PPC_REG_VS9: Type = 224;
-    pub const PPC_REG_VS10: Type = 225;
-    pub const PPC_REG_VS11: Type = 226;
-    pub const PPC_REG_VS12: Type = 227;
-    pub const PPC_REG_VS13: Type = 228;
-    pub const PPC_REG_VS14: Type = 229;
-    pub const PPC_REG_VS15: Type = 230;
-    pub const PPC_REG_VS16: Type = 231;
-    pub const PPC_REG_VS17: Type = 232;
-    pub const PPC_REG_VS18: Type = 233;
-    pub const PPC_REG_VS19: Type = 234;
-    pub const PPC_REG_VS20: Type = 235;
-    pub const PPC_REG_VS21: Type = 236;
-    pub const PPC_REG_VS22: Type = 237;
-    pub const PPC_REG_VS23: Type = 238;
-    pub const PPC_REG_VS24: Type = 239;
-    pub const PPC_REG_VS25: Type = 240;
-    pub const PPC_REG_VS26: Type = 241;
-    pub const PPC_REG_VS27: Type = 242;
-    pub const PPC_REG_VS28: Type = 243;
-    pub const PPC_REG_VS29: Type = 244;
-    pub const PPC_REG_VS30: Type = 245;
-    pub const PPC_REG_VS31: Type = 246;
-    pub const PPC_REG_VS32: Type = 247;
-    pub const PPC_REG_VS33: Type = 248;
-    pub const PPC_REG_VS34: Type = 249;
-    pub const PPC_REG_VS35: Type = 250;
-    pub const PPC_REG_VS36: Type = 251;
-    pub const PPC_REG_VS37: Type = 252;
-    pub const PPC_REG_VS38: Type = 253;
-    pub const PPC_REG_VS39: Type = 254;
-    pub const PPC_REG_VS40: Type = 255;
-    pub const PPC_REG_VS41: Type = 256;
-    pub const PPC_REG_VS42: Type = 257;
-    pub const PPC_REG_VS43: Type = 258;
-    pub const PPC_REG_VS44: Type = 259;
-    pub const PPC_REG_VS45: Type = 260;
-    pub const PPC_REG_VS46: Type = 261;
-    pub const PPC_REG_VS47: Type = 262;
-    pub const PPC_REG_VS48: Type = 263;
-    pub const PPC_REG_VS49: Type = 264;
-    pub const PPC_REG_VS50: Type = 265;
-    pub const PPC_REG_VS51: Type = 266;
-    pub const PPC_REG_VS52: Type = 267;
-    pub const PPC_REG_VS53: Type = 268;
-    pub const PPC_REG_VS54: Type = 269;
-    pub const PPC_REG_VS55: Type = 270;
-    pub const PPC_REG_VS56: Type = 271;
-    pub const PPC_REG_VS57: Type = 272;
-    pub const PPC_REG_VS58: Type = 273;
-    pub const PPC_REG_VS59: Type = 274;
-    pub const PPC_REG_VS60: Type = 275;
-    pub const PPC_REG_VS61: Type = 276;
-    pub const PPC_REG_VS62: Type = 277;
-    pub const PPC_REG_VS63: Type = 278;
-    pub const PPC_REG_CR0EQ: Type = 312;
-    pub const PPC_REG_CR1EQ: Type = 313;
-    pub const PPC_REG_CR2EQ: Type = 314;
-    pub const PPC_REG_CR3EQ: Type = 315;
-    pub const PPC_REG_CR4EQ: Type = 316;
-    pub const PPC_REG_CR5EQ: Type = 317;
-    pub const PPC_REG_CR6EQ: Type = 318;
-    pub const PPC_REG_CR7EQ: Type = 319;
-    pub const PPC_REG_CR0GT: Type = 320;
-    pub const PPC_REG_CR1GT: Type = 321;
-    pub const PPC_REG_CR2GT: Type = 322;
-    pub const PPC_REG_CR3GT: Type = 323;
-    pub const PPC_REG_CR4GT: Type = 324;
-    pub const PPC_REG_CR5GT: Type = 325;
-    pub const PPC_REG_CR6GT: Type = 326;
-    pub const PPC_REG_CR7GT: Type = 327;
-    pub const PPC_REG_CR0LT: Type = 328;
-    pub const PPC_REG_CR1LT: Type = 329;
-    pub const PPC_REG_CR2LT: Type = 330;
-    pub const PPC_REG_CR3LT: Type = 331;
-    pub const PPC_REG_CR4LT: Type = 332;
-    pub const PPC_REG_CR5LT: Type = 333;
-    pub const PPC_REG_CR6LT: Type = 334;
-    pub const PPC_REG_CR7LT: Type = 335;
-    pub const PPC_REG_CR0UN: Type = 336;
-    pub const PPC_REG_CR1UN: Type = 337;
-    pub const PPC_REG_CR2UN: Type = 338;
-    pub const PPC_REG_CR3UN: Type = 339;
-    pub const PPC_REG_CR4UN: Type = 340;
-    pub const PPC_REG_CR5UN: Type = 341;
-    pub const PPC_REG_CR6UN: Type = 342;
-    pub const PPC_REG_CR7UN: Type = 343;
-    pub const PPC_REG_ENDING: Type = 344;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with PPC_OP_MEM operand type above"]
+impl ppc_reg {
+    pub const PPC_REG_V20: ppc_reg = ppc_reg(171);
+}
+impl ppc_reg {
+    pub const PPC_REG_V21: ppc_reg = ppc_reg(172);
+}
+impl ppc_reg {
+    pub const PPC_REG_V22: ppc_reg = ppc_reg(173);
+}
+impl ppc_reg {
+    pub const PPC_REG_V23: ppc_reg = ppc_reg(174);
+}
+impl ppc_reg {
+    pub const PPC_REG_V24: ppc_reg = ppc_reg(175);
+}
+impl ppc_reg {
+    pub const PPC_REG_V25: ppc_reg = ppc_reg(176);
+}
+impl ppc_reg {
+    pub const PPC_REG_V26: ppc_reg = ppc_reg(177);
+}
+impl ppc_reg {
+    pub const PPC_REG_V27: ppc_reg = ppc_reg(178);
+}
+impl ppc_reg {
+    pub const PPC_REG_V28: ppc_reg = ppc_reg(179);
+}
+impl ppc_reg {
+    pub const PPC_REG_V29: ppc_reg = ppc_reg(180);
+}
+impl ppc_reg {
+    pub const PPC_REG_V30: ppc_reg = ppc_reg(181);
+}
+impl ppc_reg {
+    pub const PPC_REG_V31: ppc_reg = ppc_reg(182);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS0: ppc_reg = ppc_reg(215);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS1: ppc_reg = ppc_reg(216);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS2: ppc_reg = ppc_reg(217);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS3: ppc_reg = ppc_reg(218);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS4: ppc_reg = ppc_reg(219);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS5: ppc_reg = ppc_reg(220);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS6: ppc_reg = ppc_reg(221);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS7: ppc_reg = ppc_reg(222);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS8: ppc_reg = ppc_reg(223);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS9: ppc_reg = ppc_reg(224);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS10: ppc_reg = ppc_reg(225);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS11: ppc_reg = ppc_reg(226);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS12: ppc_reg = ppc_reg(227);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS13: ppc_reg = ppc_reg(228);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS14: ppc_reg = ppc_reg(229);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS15: ppc_reg = ppc_reg(230);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS16: ppc_reg = ppc_reg(231);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS17: ppc_reg = ppc_reg(232);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS18: ppc_reg = ppc_reg(233);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS19: ppc_reg = ppc_reg(234);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS20: ppc_reg = ppc_reg(235);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS21: ppc_reg = ppc_reg(236);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS22: ppc_reg = ppc_reg(237);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS23: ppc_reg = ppc_reg(238);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS24: ppc_reg = ppc_reg(239);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS25: ppc_reg = ppc_reg(240);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS26: ppc_reg = ppc_reg(241);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS27: ppc_reg = ppc_reg(242);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS28: ppc_reg = ppc_reg(243);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS29: ppc_reg = ppc_reg(244);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS30: ppc_reg = ppc_reg(245);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS31: ppc_reg = ppc_reg(246);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS32: ppc_reg = ppc_reg(247);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS33: ppc_reg = ppc_reg(248);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS34: ppc_reg = ppc_reg(249);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS35: ppc_reg = ppc_reg(250);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS36: ppc_reg = ppc_reg(251);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS37: ppc_reg = ppc_reg(252);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS38: ppc_reg = ppc_reg(253);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS39: ppc_reg = ppc_reg(254);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS40: ppc_reg = ppc_reg(255);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS41: ppc_reg = ppc_reg(256);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS42: ppc_reg = ppc_reg(257);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS43: ppc_reg = ppc_reg(258);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS44: ppc_reg = ppc_reg(259);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS45: ppc_reg = ppc_reg(260);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS46: ppc_reg = ppc_reg(261);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS47: ppc_reg = ppc_reg(262);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS48: ppc_reg = ppc_reg(263);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS49: ppc_reg = ppc_reg(264);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS50: ppc_reg = ppc_reg(265);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS51: ppc_reg = ppc_reg(266);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS52: ppc_reg = ppc_reg(267);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS53: ppc_reg = ppc_reg(268);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS54: ppc_reg = ppc_reg(269);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS55: ppc_reg = ppc_reg(270);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS56: ppc_reg = ppc_reg(271);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS57: ppc_reg = ppc_reg(272);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS58: ppc_reg = ppc_reg(273);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS59: ppc_reg = ppc_reg(274);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS60: ppc_reg = ppc_reg(275);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS61: ppc_reg = ppc_reg(276);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS62: ppc_reg = ppc_reg(277);
+}
+impl ppc_reg {
+    pub const PPC_REG_VS63: ppc_reg = ppc_reg(278);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR0EQ: ppc_reg = ppc_reg(312);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR1EQ: ppc_reg = ppc_reg(313);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR2EQ: ppc_reg = ppc_reg(314);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR3EQ: ppc_reg = ppc_reg(315);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR4EQ: ppc_reg = ppc_reg(316);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR5EQ: ppc_reg = ppc_reg(317);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR6EQ: ppc_reg = ppc_reg(318);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR7EQ: ppc_reg = ppc_reg(319);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR0GT: ppc_reg = ppc_reg(320);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR1GT: ppc_reg = ppc_reg(321);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR2GT: ppc_reg = ppc_reg(322);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR3GT: ppc_reg = ppc_reg(323);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR4GT: ppc_reg = ppc_reg(324);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR5GT: ppc_reg = ppc_reg(325);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR6GT: ppc_reg = ppc_reg(326);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR7GT: ppc_reg = ppc_reg(327);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR0LT: ppc_reg = ppc_reg(328);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR1LT: ppc_reg = ppc_reg(329);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR2LT: ppc_reg = ppc_reg(330);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR3LT: ppc_reg = ppc_reg(331);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR4LT: ppc_reg = ppc_reg(332);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR5LT: ppc_reg = ppc_reg(333);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR6LT: ppc_reg = ppc_reg(334);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR7LT: ppc_reg = ppc_reg(335);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR0UN: ppc_reg = ppc_reg(336);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR1UN: ppc_reg = ppc_reg(337);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR2UN: ppc_reg = ppc_reg(338);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR3UN: ppc_reg = ppc_reg(339);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR4UN: ppc_reg = ppc_reg(340);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR5UN: ppc_reg = ppc_reg(341);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR6UN: ppc_reg = ppc_reg(342);
+}
+impl ppc_reg {
+    pub const PPC_REG_CR7UN: ppc_reg = ppc_reg(343);
+}
+impl ppc_reg {
+    pub const PPC_REG_ENDING: ppc_reg = ppc_reg(344);
+}
+#[repr(transparent)]
+#[doc = " PPC registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct ppc_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with PPC_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct ppc_op_mem {
     #[doc = "< base register"]
-    pub base: ppc_reg::Type,
+    pub base: ppc_reg,
     #[doc = "< displacement/offset value"]
     pub disp: i32,
 }
-impl Clone for ppc_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct ppc_op_crx {
     pub scale: libc::c_uint,
-    pub reg: ppc_reg::Type,
+    pub reg: ppc_reg,
     pub cond: ppc_bc,
 }
-impl Clone for ppc_op_crx {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_ppc_op {
     #[doc = "< operand type"]
     pub type_: ppc_op_type,
     pub __bindgen_anon_1: cs_ppc_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_ppc_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
-    pub reg: ppc_reg::Type,
+    pub reg: ppc_reg,
     #[doc = "< immediate value for IMM operand"]
     pub imm: i64,
     #[doc = "< base/disp value for MEM operand"]
@@ -6098,21 +8065,11 @@ pub union cs_ppc_op__bindgen_ty_1 {
     #[doc = "< operand with condition register"]
     pub crx: ppc_op_crx,
 }
-impl Clone for cs_ppc_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_ppc_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_ppc_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_ppc_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_ppc_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -6124,7 +8081,7 @@ impl ::core::fmt::Debug for cs_ppc_op {
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_ppc {
     #[doc = " branch code for branch instructions"]
     pub bc: ppc_bc,
@@ -6132,23 +8089,17 @@ pub struct cs_ppc {
     pub bh: ppc_bh,
     #[doc = " if update_cr0 = True, then this 'dot' insn updates CR0"]
     pub update_cr0: bool,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_ppc_op; 8usize],
 }
-impl Clone for cs_ppc {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_ppc {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, op_count: {:?}, operands: {:?} }}",
-            self.bc, self.bh, self.update_cr0, self.op_count, self.operands
+            "cs_ppc {{ bc: {:?}, bh: {:?}, update_cr0: {:?}, operands: {:?} }}",
+            self.bc, self.bh, self.update_cr0, self.operands
         )
     }
 }
@@ -7847,29 +9798,63 @@ pub enum ppc_insn {
     PPC_INS_XXSWAPD = 1688,
     PPC_INS_ENDING = 1689,
 }
-pub mod ppc_insn_group {
-    #[doc = " Group of PPC instructions"]
-    pub type Type = libc::c_uint;
-    #[doc = "< = CS_GRP_INVALID"]
-    pub const PPC_GRP_INVALID: Type = 0;
-    #[doc = "< = CS_GRP_JUMP"]
-    pub const PPC_GRP_JUMP: Type = 1;
-    pub const PPC_GRP_ALTIVEC: Type = 128;
-    pub const PPC_GRP_MODE32: Type = 129;
-    pub const PPC_GRP_MODE64: Type = 130;
-    pub const PPC_GRP_BOOKE: Type = 131;
-    pub const PPC_GRP_NOTBOOKE: Type = 132;
-    pub const PPC_GRP_SPE: Type = 133;
-    pub const PPC_GRP_VSX: Type = 134;
-    pub const PPC_GRP_E500: Type = 135;
-    pub const PPC_GRP_PPC4XX: Type = 136;
-    pub const PPC_GRP_PPC6XX: Type = 137;
-    pub const PPC_GRP_ICBT: Type = 138;
-    pub const PPC_GRP_P8ALTIVEC: Type = 139;
-    pub const PPC_GRP_P8VECTOR: Type = 140;
-    pub const PPC_GRP_QPX: Type = 141;
-    pub const PPC_GRP_ENDING: Type = 142;
+impl ppc_insn_group {
+    #[doc = "< = CS_GRP_INVALID"]
+    pub const PPC_GRP_INVALID: ppc_insn_group = ppc_insn_group(0);
+}
+impl ppc_insn_group {
+    #[doc = "< = CS_GRP_JUMP"]
+    pub const PPC_GRP_JUMP: ppc_insn_group = ppc_insn_group(1);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_ALTIVEC: ppc_insn_group = ppc_insn_group(128);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_MODE32: ppc_insn_group = ppc_insn_group(129);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_MODE64: ppc_insn_group = ppc_insn_group(130);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_BOOKE: ppc_insn_group = ppc_insn_group(131);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_NOTBOOKE: ppc_insn_group = ppc_insn_group(132);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_SPE: ppc_insn_group = ppc_insn_group(133);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_VSX: ppc_insn_group = ppc_insn_group(134);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_E500: ppc_insn_group = ppc_insn_group(135);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_PPC4XX: ppc_insn_group = ppc_insn_group(136);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_PPC6XX: ppc_insn_group = ppc_insn_group(137);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_ICBT: ppc_insn_group = ppc_insn_group(138);
 }
+impl ppc_insn_group {
+    pub const PPC_GRP_P8ALTIVEC: ppc_insn_group = ppc_insn_group(139);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_P8VECTOR: ppc_insn_group = ppc_insn_group(140);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_QPX: ppc_insn_group = ppc_insn_group(141);
+}
+impl ppc_insn_group {
+    pub const PPC_GRP_ENDING: ppc_insn_group = ppc_insn_group(142);
+}
+#[repr(transparent)]
+#[doc = " Group of PPC instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct ppc_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " Enums corresponding to Sparc condition codes, both icc's and fcc's."]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -7967,153 +9952,317 @@ pub enum sparc_op_type {
     #[doc = "< = CS_OP_MEM (Memory operand)."]
     SPARC_OP_MEM = 3,
 }
-pub mod sparc_reg {
-    #[doc = " SPARC registers"]
-    pub type Type = libc::c_uint;
-    pub const SPARC_REG_INVALID: Type = 0;
-    pub const SPARC_REG_F0: Type = 1;
-    pub const SPARC_REG_F1: Type = 2;
-    pub const SPARC_REG_F2: Type = 3;
-    pub const SPARC_REG_F3: Type = 4;
-    pub const SPARC_REG_F4: Type = 5;
-    pub const SPARC_REG_F5: Type = 6;
-    pub const SPARC_REG_F6: Type = 7;
-    pub const SPARC_REG_F7: Type = 8;
-    pub const SPARC_REG_F8: Type = 9;
-    pub const SPARC_REG_F9: Type = 10;
-    pub const SPARC_REG_F10: Type = 11;
-    pub const SPARC_REG_F11: Type = 12;
-    pub const SPARC_REG_F12: Type = 13;
-    pub const SPARC_REG_F13: Type = 14;
-    pub const SPARC_REG_F14: Type = 15;
-    pub const SPARC_REG_F15: Type = 16;
-    pub const SPARC_REG_F16: Type = 17;
-    pub const SPARC_REG_F17: Type = 18;
-    pub const SPARC_REG_F18: Type = 19;
-    pub const SPARC_REG_F19: Type = 20;
-    pub const SPARC_REG_F20: Type = 21;
-    pub const SPARC_REG_F21: Type = 22;
-    pub const SPARC_REG_F22: Type = 23;
-    pub const SPARC_REG_F23: Type = 24;
-    pub const SPARC_REG_F24: Type = 25;
-    pub const SPARC_REG_F25: Type = 26;
-    pub const SPARC_REG_F26: Type = 27;
-    pub const SPARC_REG_F27: Type = 28;
-    pub const SPARC_REG_F28: Type = 29;
-    pub const SPARC_REG_F29: Type = 30;
-    pub const SPARC_REG_F30: Type = 31;
-    pub const SPARC_REG_F31: Type = 32;
-    pub const SPARC_REG_F32: Type = 33;
-    pub const SPARC_REG_F34: Type = 34;
-    pub const SPARC_REG_F36: Type = 35;
-    pub const SPARC_REG_F38: Type = 36;
-    pub const SPARC_REG_F40: Type = 37;
-    pub const SPARC_REG_F42: Type = 38;
-    pub const SPARC_REG_F44: Type = 39;
-    pub const SPARC_REG_F46: Type = 40;
-    pub const SPARC_REG_F48: Type = 41;
-    pub const SPARC_REG_F50: Type = 42;
-    pub const SPARC_REG_F52: Type = 43;
-    pub const SPARC_REG_F54: Type = 44;
-    pub const SPARC_REG_F56: Type = 45;
-    pub const SPARC_REG_F58: Type = 46;
-    pub const SPARC_REG_F60: Type = 47;
-    pub const SPARC_REG_F62: Type = 48;
-    pub const SPARC_REG_FCC0: Type = 49;
-    pub const SPARC_REG_FCC1: Type = 50;
-    pub const SPARC_REG_FCC2: Type = 51;
-    pub const SPARC_REG_FCC3: Type = 52;
-    pub const SPARC_REG_FP: Type = 53;
-    pub const SPARC_REG_G0: Type = 54;
-    pub const SPARC_REG_G1: Type = 55;
-    pub const SPARC_REG_G2: Type = 56;
-    pub const SPARC_REG_G3: Type = 57;
-    pub const SPARC_REG_G4: Type = 58;
-    pub const SPARC_REG_G5: Type = 59;
-    pub const SPARC_REG_G6: Type = 60;
-    pub const SPARC_REG_G7: Type = 61;
-    pub const SPARC_REG_I0: Type = 62;
-    pub const SPARC_REG_I1: Type = 63;
-    pub const SPARC_REG_I2: Type = 64;
-    pub const SPARC_REG_I3: Type = 65;
-    pub const SPARC_REG_I4: Type = 66;
-    pub const SPARC_REG_I5: Type = 67;
-    pub const SPARC_REG_I7: Type = 68;
-    pub const SPARC_REG_ICC: Type = 69;
-    pub const SPARC_REG_L0: Type = 70;
-    pub const SPARC_REG_L1: Type = 71;
-    pub const SPARC_REG_L2: Type = 72;
-    pub const SPARC_REG_L3: Type = 73;
-    pub const SPARC_REG_L4: Type = 74;
-    pub const SPARC_REG_L5: Type = 75;
-    pub const SPARC_REG_L6: Type = 76;
-    pub const SPARC_REG_L7: Type = 77;
-    pub const SPARC_REG_O0: Type = 78;
-    pub const SPARC_REG_O1: Type = 79;
-    pub const SPARC_REG_O2: Type = 80;
-    pub const SPARC_REG_O3: Type = 81;
-    pub const SPARC_REG_O4: Type = 82;
-    pub const SPARC_REG_O5: Type = 83;
-    pub const SPARC_REG_O7: Type = 84;
-    pub const SPARC_REG_SP: Type = 85;
-    pub const SPARC_REG_Y: Type = 86;
-    pub const SPARC_REG_XCC: Type = 87;
-    pub const SPARC_REG_ENDING: Type = 88;
-    pub const SPARC_REG_O6: Type = 85;
-    pub const SPARC_REG_I6: Type = 53;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with SPARC_OP_MEM operand type above"]
+impl sparc_reg {
+    pub const SPARC_REG_INVALID: sparc_reg = sparc_reg(0);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F0: sparc_reg = sparc_reg(1);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F1: sparc_reg = sparc_reg(2);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F2: sparc_reg = sparc_reg(3);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F3: sparc_reg = sparc_reg(4);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F4: sparc_reg = sparc_reg(5);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F5: sparc_reg = sparc_reg(6);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F6: sparc_reg = sparc_reg(7);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F7: sparc_reg = sparc_reg(8);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F8: sparc_reg = sparc_reg(9);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F9: sparc_reg = sparc_reg(10);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F10: sparc_reg = sparc_reg(11);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F11: sparc_reg = sparc_reg(12);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F12: sparc_reg = sparc_reg(13);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F13: sparc_reg = sparc_reg(14);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F14: sparc_reg = sparc_reg(15);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F15: sparc_reg = sparc_reg(16);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F16: sparc_reg = sparc_reg(17);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F17: sparc_reg = sparc_reg(18);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F18: sparc_reg = sparc_reg(19);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F19: sparc_reg = sparc_reg(20);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F20: sparc_reg = sparc_reg(21);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F21: sparc_reg = sparc_reg(22);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F22: sparc_reg = sparc_reg(23);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F23: sparc_reg = sparc_reg(24);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F24: sparc_reg = sparc_reg(25);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F25: sparc_reg = sparc_reg(26);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F26: sparc_reg = sparc_reg(27);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F27: sparc_reg = sparc_reg(28);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F28: sparc_reg = sparc_reg(29);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F29: sparc_reg = sparc_reg(30);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F30: sparc_reg = sparc_reg(31);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F31: sparc_reg = sparc_reg(32);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F32: sparc_reg = sparc_reg(33);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F34: sparc_reg = sparc_reg(34);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F36: sparc_reg = sparc_reg(35);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F38: sparc_reg = sparc_reg(36);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F40: sparc_reg = sparc_reg(37);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F42: sparc_reg = sparc_reg(38);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F44: sparc_reg = sparc_reg(39);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F46: sparc_reg = sparc_reg(40);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F48: sparc_reg = sparc_reg(41);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F50: sparc_reg = sparc_reg(42);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F52: sparc_reg = sparc_reg(43);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F54: sparc_reg = sparc_reg(44);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F56: sparc_reg = sparc_reg(45);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F58: sparc_reg = sparc_reg(46);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F60: sparc_reg = sparc_reg(47);
+}
+impl sparc_reg {
+    pub const SPARC_REG_F62: sparc_reg = sparc_reg(48);
+}
+impl sparc_reg {
+    pub const SPARC_REG_FCC0: sparc_reg = sparc_reg(49);
+}
+impl sparc_reg {
+    pub const SPARC_REG_FCC1: sparc_reg = sparc_reg(50);
+}
+impl sparc_reg {
+    pub const SPARC_REG_FCC2: sparc_reg = sparc_reg(51);
+}
+impl sparc_reg {
+    pub const SPARC_REG_FCC3: sparc_reg = sparc_reg(52);
+}
+impl sparc_reg {
+    pub const SPARC_REG_FP: sparc_reg = sparc_reg(53);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G0: sparc_reg = sparc_reg(54);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G1: sparc_reg = sparc_reg(55);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G2: sparc_reg = sparc_reg(56);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G3: sparc_reg = sparc_reg(57);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G4: sparc_reg = sparc_reg(58);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G5: sparc_reg = sparc_reg(59);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G6: sparc_reg = sparc_reg(60);
+}
+impl sparc_reg {
+    pub const SPARC_REG_G7: sparc_reg = sparc_reg(61);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I0: sparc_reg = sparc_reg(62);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I1: sparc_reg = sparc_reg(63);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I2: sparc_reg = sparc_reg(64);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I3: sparc_reg = sparc_reg(65);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I4: sparc_reg = sparc_reg(66);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I5: sparc_reg = sparc_reg(67);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I7: sparc_reg = sparc_reg(68);
+}
+impl sparc_reg {
+    pub const SPARC_REG_ICC: sparc_reg = sparc_reg(69);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L0: sparc_reg = sparc_reg(70);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L1: sparc_reg = sparc_reg(71);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L2: sparc_reg = sparc_reg(72);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L3: sparc_reg = sparc_reg(73);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L4: sparc_reg = sparc_reg(74);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L5: sparc_reg = sparc_reg(75);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L6: sparc_reg = sparc_reg(76);
+}
+impl sparc_reg {
+    pub const SPARC_REG_L7: sparc_reg = sparc_reg(77);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O0: sparc_reg = sparc_reg(78);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O1: sparc_reg = sparc_reg(79);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O2: sparc_reg = sparc_reg(80);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O3: sparc_reg = sparc_reg(81);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O4: sparc_reg = sparc_reg(82);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O5: sparc_reg = sparc_reg(83);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O7: sparc_reg = sparc_reg(84);
+}
+impl sparc_reg {
+    pub const SPARC_REG_SP: sparc_reg = sparc_reg(85);
+}
+impl sparc_reg {
+    pub const SPARC_REG_Y: sparc_reg = sparc_reg(86);
+}
+impl sparc_reg {
+    pub const SPARC_REG_XCC: sparc_reg = sparc_reg(87);
+}
+impl sparc_reg {
+    pub const SPARC_REG_ENDING: sparc_reg = sparc_reg(88);
+}
+impl sparc_reg {
+    pub const SPARC_REG_O6: sparc_reg = sparc_reg(85);
+}
+impl sparc_reg {
+    pub const SPARC_REG_I6: sparc_reg = sparc_reg(53);
+}
+#[repr(transparent)]
+#[doc = " SPARC registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct sparc_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with SPARC_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct sparc_op_mem {
-    #[doc = "< base register, can be safely interpreted as"]
-    #[doc = "< a value of type `sparc_reg`, but it is only"]
-    #[doc = "< one byte wide"]
+    #[doc = "< base register, can be safely interpreted as\n< a value of type `sparc_reg`, but it is only\n< one byte wide"]
     pub base: u8,
     #[doc = "< index register, same conditions apply here"]
     pub index: u8,
     #[doc = "< displacement/offset value"]
     pub disp: i32,
 }
-impl Clone for sparc_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_sparc_op {
     #[doc = "< operand type"]
     pub type_: sparc_op_type,
     pub __bindgen_anon_1: cs_sparc_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_sparc_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
-    pub reg: sparc_reg::Type,
+    pub reg: sparc_reg,
     #[doc = "< immediate value for IMM operand"]
     pub imm: i64,
     #[doc = "< base/disp value for MEM operand"]
     pub mem: sparc_op_mem,
 }
-impl Clone for cs_sparc_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_sparc_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_sparc_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_sparc_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_sparc_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -8125,29 +10274,23 @@ impl ::core::fmt::Debug for cs_sparc_op {
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_sparc {
     #[doc = "< code condition for this insn"]
     pub cc: sparc_cc,
     #[doc = "< branch hint: encoding as bitwise OR of sparc_hint."]
     pub hint: sparc_hint,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_sparc_op; 4usize],
 }
-impl Clone for cs_sparc {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_sparc {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_sparc {{ cc: {:?}, hint: {:?}, op_count: {:?}, operands: {:?} }}",
-            self.cc, self.hint, self.op_count, self.operands
+            "cs_sparc {{ cc: {:?}, hint: {:?}, operands: {:?} }}",
+            self.cc, self.hint, self.operands
         )
     }
 }
@@ -8436,22 +10579,42 @@ pub enum sparc_insn {
     SPARC_INS_RETL = 278,
     SPARC_INS_ENDING = 279,
 }
-pub mod sparc_insn_group {
-    #[doc = " Group of SPARC instructions"]
-    pub type Type = libc::c_uint;
+impl sparc_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const SPARC_GRP_INVALID: Type = 0;
+    pub const SPARC_GRP_INVALID: sparc_insn_group = sparc_insn_group(0);
+}
+impl sparc_insn_group {
     #[doc = "< = CS_GRP_JUMP"]
-    pub const SPARC_GRP_JUMP: Type = 1;
-    pub const SPARC_GRP_HARDQUAD: Type = 128;
-    pub const SPARC_GRP_V9: Type = 129;
-    pub const SPARC_GRP_VIS: Type = 130;
-    pub const SPARC_GRP_VIS2: Type = 131;
-    pub const SPARC_GRP_VIS3: Type = 132;
-    pub const SPARC_GRP_32BIT: Type = 133;
-    pub const SPARC_GRP_64BIT: Type = 134;
-    pub const SPARC_GRP_ENDING: Type = 135;
+    pub const SPARC_GRP_JUMP: sparc_insn_group = sparc_insn_group(1);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_HARDQUAD: sparc_insn_group = sparc_insn_group(128);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_V9: sparc_insn_group = sparc_insn_group(129);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_VIS: sparc_insn_group = sparc_insn_group(130);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_VIS2: sparc_insn_group = sparc_insn_group(131);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_VIS3: sparc_insn_group = sparc_insn_group(132);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_32BIT: sparc_insn_group = sparc_insn_group(133);
 }
+impl sparc_insn_group {
+    pub const SPARC_GRP_64BIT: sparc_insn_group = sparc_insn_group(134);
+}
+impl sparc_insn_group {
+    pub const SPARC_GRP_ENDING: sparc_insn_group = sparc_insn_group(135);
+}
+#[repr(transparent)]
+#[doc = " Group of SPARC instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct sparc_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " Enums corresponding to SystemZ condition codes"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -8488,136 +10651,369 @@ pub enum sysz_op_type {
     #[doc = "< Access register operand."]
     SYSZ_OP_ACREG = 64,
 }
-pub mod sysz_reg {
-    #[doc = " SystemZ registers"]
-    pub type Type = libc::c_uint;
-    pub const SYSZ_REG_INVALID: Type = 0;
-    pub const SYSZ_REG_0: Type = 1;
-    pub const SYSZ_REG_1: Type = 2;
-    pub const SYSZ_REG_2: Type = 3;
-    pub const SYSZ_REG_3: Type = 4;
-    pub const SYSZ_REG_4: Type = 5;
-    pub const SYSZ_REG_5: Type = 6;
-    pub const SYSZ_REG_6: Type = 7;
-    pub const SYSZ_REG_7: Type = 8;
-    pub const SYSZ_REG_8: Type = 9;
-    pub const SYSZ_REG_9: Type = 10;
-    pub const SYSZ_REG_10: Type = 11;
-    pub const SYSZ_REG_11: Type = 12;
-    pub const SYSZ_REG_12: Type = 13;
-    pub const SYSZ_REG_13: Type = 14;
-    pub const SYSZ_REG_14: Type = 15;
-    pub const SYSZ_REG_15: Type = 16;
-    pub const SYSZ_REG_CC: Type = 17;
-    pub const SYSZ_REG_F0: Type = 18;
-    pub const SYSZ_REG_F1: Type = 19;
-    pub const SYSZ_REG_F2: Type = 20;
-    pub const SYSZ_REG_F3: Type = 21;
-    pub const SYSZ_REG_F4: Type = 22;
-    pub const SYSZ_REG_F5: Type = 23;
-    pub const SYSZ_REG_F6: Type = 24;
-    pub const SYSZ_REG_F7: Type = 25;
-    pub const SYSZ_REG_F8: Type = 26;
-    pub const SYSZ_REG_F9: Type = 27;
-    pub const SYSZ_REG_F10: Type = 28;
-    pub const SYSZ_REG_F11: Type = 29;
-    pub const SYSZ_REG_F12: Type = 30;
-    pub const SYSZ_REG_F13: Type = 31;
-    pub const SYSZ_REG_F14: Type = 32;
-    pub const SYSZ_REG_F15: Type = 33;
-    pub const SYSZ_REG_R0L: Type = 34;
-    pub const SYSZ_REG_A0: Type = 35;
-    pub const SYSZ_REG_A1: Type = 36;
-    pub const SYSZ_REG_A2: Type = 37;
-    pub const SYSZ_REG_A3: Type = 38;
-    pub const SYSZ_REG_A4: Type = 39;
-    pub const SYSZ_REG_A5: Type = 40;
-    pub const SYSZ_REG_A6: Type = 41;
-    pub const SYSZ_REG_A7: Type = 42;
-    pub const SYSZ_REG_A8: Type = 43;
-    pub const SYSZ_REG_A9: Type = 44;
-    pub const SYSZ_REG_A10: Type = 45;
-    pub const SYSZ_REG_A11: Type = 46;
-    pub const SYSZ_REG_A12: Type = 47;
-    pub const SYSZ_REG_A13: Type = 48;
-    pub const SYSZ_REG_A14: Type = 49;
-    pub const SYSZ_REG_A15: Type = 50;
-    pub const SYSZ_REG_C0: Type = 51;
-    pub const SYSZ_REG_C1: Type = 52;
-    pub const SYSZ_REG_C2: Type = 53;
-    pub const SYSZ_REG_C3: Type = 54;
-    pub const SYSZ_REG_C4: Type = 55;
-    pub const SYSZ_REG_C5: Type = 56;
-    pub const SYSZ_REG_C6: Type = 57;
-    pub const SYSZ_REG_C7: Type = 58;
-    pub const SYSZ_REG_C8: Type = 59;
-    pub const SYSZ_REG_C9: Type = 60;
-    pub const SYSZ_REG_C10: Type = 61;
-    pub const SYSZ_REG_C11: Type = 62;
-    pub const SYSZ_REG_C12: Type = 63;
-    pub const SYSZ_REG_C13: Type = 64;
-    pub const SYSZ_REG_C14: Type = 65;
-    pub const SYSZ_REG_C15: Type = 66;
-    pub const SYSZ_REG_V0: Type = 67;
-    pub const SYSZ_REG_V1: Type = 68;
-    pub const SYSZ_REG_V2: Type = 69;
-    pub const SYSZ_REG_V3: Type = 70;
-    pub const SYSZ_REG_V4: Type = 71;
-    pub const SYSZ_REG_V5: Type = 72;
-    pub const SYSZ_REG_V6: Type = 73;
-    pub const SYSZ_REG_V7: Type = 74;
-    pub const SYSZ_REG_V8: Type = 75;
-    pub const SYSZ_REG_V9: Type = 76;
-    pub const SYSZ_REG_V10: Type = 77;
-    pub const SYSZ_REG_V11: Type = 78;
-    pub const SYSZ_REG_V12: Type = 79;
-    pub const SYSZ_REG_V13: Type = 80;
-    pub const SYSZ_REG_V14: Type = 81;
-    pub const SYSZ_REG_V15: Type = 82;
-    pub const SYSZ_REG_V16: Type = 83;
-    pub const SYSZ_REG_V17: Type = 84;
-    pub const SYSZ_REG_V18: Type = 85;
-    pub const SYSZ_REG_V19: Type = 86;
-    pub const SYSZ_REG_V20: Type = 87;
-    pub const SYSZ_REG_V21: Type = 88;
-    pub const SYSZ_REG_V22: Type = 89;
-    pub const SYSZ_REG_V23: Type = 90;
-    pub const SYSZ_REG_V24: Type = 91;
-    pub const SYSZ_REG_V25: Type = 92;
-    pub const SYSZ_REG_V26: Type = 93;
-    pub const SYSZ_REG_V27: Type = 94;
-    pub const SYSZ_REG_V28: Type = 95;
-    pub const SYSZ_REG_V29: Type = 96;
-    pub const SYSZ_REG_V30: Type = 97;
-    pub const SYSZ_REG_V31: Type = 98;
-    pub const SYSZ_REG_F16: Type = 99;
-    pub const SYSZ_REG_F17: Type = 100;
-    pub const SYSZ_REG_F18: Type = 101;
-    pub const SYSZ_REG_F19: Type = 102;
-    pub const SYSZ_REG_F20: Type = 103;
-    pub const SYSZ_REG_F21: Type = 104;
-    pub const SYSZ_REG_F22: Type = 105;
-    pub const SYSZ_REG_F23: Type = 106;
-    pub const SYSZ_REG_F24: Type = 107;
-    pub const SYSZ_REG_F25: Type = 108;
-    pub const SYSZ_REG_F26: Type = 109;
-    pub const SYSZ_REG_F27: Type = 110;
-    pub const SYSZ_REG_F28: Type = 111;
-    pub const SYSZ_REG_F29: Type = 112;
-    pub const SYSZ_REG_F30: Type = 113;
-    pub const SYSZ_REG_F31: Type = 114;
-    pub const SYSZ_REG_F0Q: Type = 115;
-    pub const SYSZ_REG_F4Q: Type = 116;
-    pub const SYSZ_REG_ENDING: Type = 117;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with SYSZ_OP_MEM operand type above"]
+impl sysz_reg {
+    pub const SYSZ_REG_INVALID: sysz_reg = sysz_reg(0);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_0: sysz_reg = sysz_reg(1);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_1: sysz_reg = sysz_reg(2);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_2: sysz_reg = sysz_reg(3);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_3: sysz_reg = sysz_reg(4);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_4: sysz_reg = sysz_reg(5);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_5: sysz_reg = sysz_reg(6);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_6: sysz_reg = sysz_reg(7);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_7: sysz_reg = sysz_reg(8);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_8: sysz_reg = sysz_reg(9);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_9: sysz_reg = sysz_reg(10);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_10: sysz_reg = sysz_reg(11);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_11: sysz_reg = sysz_reg(12);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_12: sysz_reg = sysz_reg(13);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_13: sysz_reg = sysz_reg(14);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_14: sysz_reg = sysz_reg(15);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_15: sysz_reg = sysz_reg(16);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_CC: sysz_reg = sysz_reg(17);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F0: sysz_reg = sysz_reg(18);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F1: sysz_reg = sysz_reg(19);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F2: sysz_reg = sysz_reg(20);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F3: sysz_reg = sysz_reg(21);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F4: sysz_reg = sysz_reg(22);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F5: sysz_reg = sysz_reg(23);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F6: sysz_reg = sysz_reg(24);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F7: sysz_reg = sysz_reg(25);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F8: sysz_reg = sysz_reg(26);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F9: sysz_reg = sysz_reg(27);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F10: sysz_reg = sysz_reg(28);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F11: sysz_reg = sysz_reg(29);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F12: sysz_reg = sysz_reg(30);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F13: sysz_reg = sysz_reg(31);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F14: sysz_reg = sysz_reg(32);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F15: sysz_reg = sysz_reg(33);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_R0L: sysz_reg = sysz_reg(34);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A0: sysz_reg = sysz_reg(35);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A1: sysz_reg = sysz_reg(36);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A2: sysz_reg = sysz_reg(37);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A3: sysz_reg = sysz_reg(38);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A4: sysz_reg = sysz_reg(39);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A5: sysz_reg = sysz_reg(40);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A6: sysz_reg = sysz_reg(41);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A7: sysz_reg = sysz_reg(42);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A8: sysz_reg = sysz_reg(43);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A9: sysz_reg = sysz_reg(44);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A10: sysz_reg = sysz_reg(45);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A11: sysz_reg = sysz_reg(46);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A12: sysz_reg = sysz_reg(47);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A13: sysz_reg = sysz_reg(48);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A14: sysz_reg = sysz_reg(49);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_A15: sysz_reg = sysz_reg(50);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C0: sysz_reg = sysz_reg(51);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C1: sysz_reg = sysz_reg(52);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C2: sysz_reg = sysz_reg(53);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C3: sysz_reg = sysz_reg(54);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C4: sysz_reg = sysz_reg(55);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C5: sysz_reg = sysz_reg(56);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C6: sysz_reg = sysz_reg(57);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C7: sysz_reg = sysz_reg(58);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C8: sysz_reg = sysz_reg(59);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C9: sysz_reg = sysz_reg(60);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C10: sysz_reg = sysz_reg(61);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C11: sysz_reg = sysz_reg(62);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C12: sysz_reg = sysz_reg(63);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C13: sysz_reg = sysz_reg(64);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C14: sysz_reg = sysz_reg(65);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_C15: sysz_reg = sysz_reg(66);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V0: sysz_reg = sysz_reg(67);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V1: sysz_reg = sysz_reg(68);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V2: sysz_reg = sysz_reg(69);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V3: sysz_reg = sysz_reg(70);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V4: sysz_reg = sysz_reg(71);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V5: sysz_reg = sysz_reg(72);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V6: sysz_reg = sysz_reg(73);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V7: sysz_reg = sysz_reg(74);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V8: sysz_reg = sysz_reg(75);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V9: sysz_reg = sysz_reg(76);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V10: sysz_reg = sysz_reg(77);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V11: sysz_reg = sysz_reg(78);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V12: sysz_reg = sysz_reg(79);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V13: sysz_reg = sysz_reg(80);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V14: sysz_reg = sysz_reg(81);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V15: sysz_reg = sysz_reg(82);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V16: sysz_reg = sysz_reg(83);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V17: sysz_reg = sysz_reg(84);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V18: sysz_reg = sysz_reg(85);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V19: sysz_reg = sysz_reg(86);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V20: sysz_reg = sysz_reg(87);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V21: sysz_reg = sysz_reg(88);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V22: sysz_reg = sysz_reg(89);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V23: sysz_reg = sysz_reg(90);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V24: sysz_reg = sysz_reg(91);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V25: sysz_reg = sysz_reg(92);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V26: sysz_reg = sysz_reg(93);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V27: sysz_reg = sysz_reg(94);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V28: sysz_reg = sysz_reg(95);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V29: sysz_reg = sysz_reg(96);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V30: sysz_reg = sysz_reg(97);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_V31: sysz_reg = sysz_reg(98);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F16: sysz_reg = sysz_reg(99);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F17: sysz_reg = sysz_reg(100);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F18: sysz_reg = sysz_reg(101);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F19: sysz_reg = sysz_reg(102);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F20: sysz_reg = sysz_reg(103);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F21: sysz_reg = sysz_reg(104);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F22: sysz_reg = sysz_reg(105);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F23: sysz_reg = sysz_reg(106);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F24: sysz_reg = sysz_reg(107);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F25: sysz_reg = sysz_reg(108);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F26: sysz_reg = sysz_reg(109);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F27: sysz_reg = sysz_reg(110);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F28: sysz_reg = sysz_reg(111);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F29: sysz_reg = sysz_reg(112);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F30: sysz_reg = sysz_reg(113);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F31: sysz_reg = sysz_reg(114);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F0Q: sysz_reg = sysz_reg(115);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_F4Q: sysz_reg = sysz_reg(116);
+}
+impl sysz_reg {
+    pub const SYSZ_REG_ENDING: sysz_reg = sysz_reg(117);
+}
+#[repr(transparent)]
+#[doc = " SystemZ registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct sysz_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with SYSZ_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct sysz_op_mem {
-    #[doc = "< base register, can be safely interpreted as"]
-    #[doc = "< a value of type `sysz_reg`, but it is only"]
-    #[doc = "< one byte wide"]
+    #[doc = "< base register, can be safely interpreted as\n< a value of type `sysz_reg`, but it is only\n< one byte wide"]
     pub base: u8,
     #[doc = "< index register, same conditions apply here"]
     pub index: u8,
@@ -8626,44 +11022,29 @@ pub struct sysz_op_mem {
     #[doc = "< displacement/offset value"]
     pub disp: i64,
 }
-impl Clone for sysz_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_sysz_op {
     #[doc = "< operand type"]
     pub type_: sysz_op_type,
     pub __bindgen_anon_1: cs_sysz_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_sysz_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
-    pub reg: sysz_reg::Type,
+    pub reg: sysz_reg,
     #[doc = "< immediate value for IMM operand"]
     pub imm: i64,
     #[doc = "< base/disp value for MEM operand"]
     pub mem: sysz_op_mem,
 }
-impl Clone for cs_sysz_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_sysz_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_sysz_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_sysz_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_sysz_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -8674,27 +11055,21 @@ impl ::core::fmt::Debug for cs_sysz_op {
     }
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_sysz {
     #[doc = "< Code condition"]
     pub cc: sysz_cc,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_sysz_op; 6usize],
 }
-impl Clone for cs_sysz {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_sysz {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_sysz {{ cc: {:?}, op_count: {:?}, operands: {:?} }}",
-            self.cc, self.op_count, self.operands
+            "cs_sysz {{ cc: {:?}, operands: {:?} }}",
+            self.cc, self.operands
         )
     }
 }
@@ -11050,295 +13425,853 @@ pub enum sysz_insn {
     SYSZ_INS_ZAP = 2345,
     SYSZ_INS_ENDING = 2346,
 }
-pub mod sysz_insn_group {
-    #[doc = " Group of SystemZ instructions"]
-    pub type Type = libc::c_uint;
-    #[doc = "< = CS_GRP_INVALID"]
-    pub const SYSZ_GRP_INVALID: Type = 0;
-    #[doc = "< = CS_GRP_JUMP"]
-    pub const SYSZ_GRP_JUMP: Type = 1;
-    pub const SYSZ_GRP_DISTINCTOPS: Type = 128;
-    pub const SYSZ_GRP_FPEXTENSION: Type = 129;
-    pub const SYSZ_GRP_HIGHWORD: Type = 130;
-    pub const SYSZ_GRP_INTERLOCKEDACCESS1: Type = 131;
-    pub const SYSZ_GRP_LOADSTOREONCOND: Type = 132;
-    pub const SYSZ_GRP_DFPPACKEDCONVERSION: Type = 133;
-    pub const SYSZ_GRP_DFPZONEDCONVERSION: Type = 134;
-    pub const SYSZ_GRP_ENHANCEDDAT2: Type = 135;
-    pub const SYSZ_GRP_EXECUTIONHINT: Type = 136;
-    pub const SYSZ_GRP_GUARDEDSTORAGE: Type = 137;
-    pub const SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE: Type = 138;
-    pub const SYSZ_GRP_LOADANDTRAP: Type = 139;
-    pub const SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE: Type = 140;
-    pub const SYSZ_GRP_LOADSTOREONCOND2: Type = 141;
-    pub const SYSZ_GRP_MESSAGESECURITYASSIST3: Type = 142;
-    pub const SYSZ_GRP_MESSAGESECURITYASSIST4: Type = 143;
-    pub const SYSZ_GRP_MESSAGESECURITYASSIST5: Type = 144;
-    pub const SYSZ_GRP_MESSAGESECURITYASSIST7: Type = 145;
-    pub const SYSZ_GRP_MESSAGESECURITYASSIST8: Type = 146;
-    pub const SYSZ_GRP_MISCELLANEOUSEXTENSIONS: Type = 147;
-    pub const SYSZ_GRP_MISCELLANEOUSEXTENSIONS2: Type = 148;
-    pub const SYSZ_GRP_NOVECTOR: Type = 149;
-    pub const SYSZ_GRP_POPULATIONCOUNT: Type = 150;
-    pub const SYSZ_GRP_PROCESSORASSIST: Type = 151;
-    pub const SYSZ_GRP_RESETREFERENCEBITSMULTIPLE: Type = 152;
-    pub const SYSZ_GRP_TRANSACTIONALEXECUTION: Type = 153;
-    pub const SYSZ_GRP_VECTOR: Type = 154;
-    pub const SYSZ_GRP_VECTORENHANCEMENTS1: Type = 155;
-    pub const SYSZ_GRP_VECTORPACKEDDECIMAL: Type = 156;
-    pub const SYSZ_GRP_ENDING: Type = 157;
-}
-pub mod x86_reg {
-    #[doc = " X86 registers"]
-    pub type Type = libc::c_uint;
-    pub const X86_REG_INVALID: Type = 0;
-    pub const X86_REG_AH: Type = 1;
-    pub const X86_REG_AL: Type = 2;
-    pub const X86_REG_AX: Type = 3;
-    pub const X86_REG_BH: Type = 4;
-    pub const X86_REG_BL: Type = 5;
-    pub const X86_REG_BP: Type = 6;
-    pub const X86_REG_BPL: Type = 7;
-    pub const X86_REG_BX: Type = 8;
-    pub const X86_REG_CH: Type = 9;
-    pub const X86_REG_CL: Type = 10;
-    pub const X86_REG_CS: Type = 11;
-    pub const X86_REG_CX: Type = 12;
-    pub const X86_REG_DH: Type = 13;
-    pub const X86_REG_DI: Type = 14;
-    pub const X86_REG_DIL: Type = 15;
-    pub const X86_REG_DL: Type = 16;
-    pub const X86_REG_DS: Type = 17;
-    pub const X86_REG_DX: Type = 18;
-    pub const X86_REG_EAX: Type = 19;
-    pub const X86_REG_EBP: Type = 20;
-    pub const X86_REG_EBX: Type = 21;
-    pub const X86_REG_ECX: Type = 22;
-    pub const X86_REG_EDI: Type = 23;
-    pub const X86_REG_EDX: Type = 24;
-    pub const X86_REG_EFLAGS: Type = 25;
-    pub const X86_REG_EIP: Type = 26;
-    pub const X86_REG_EIZ: Type = 27;
-    pub const X86_REG_ES: Type = 28;
-    pub const X86_REG_ESI: Type = 29;
-    pub const X86_REG_ESP: Type = 30;
-    pub const X86_REG_FPSW: Type = 31;
-    pub const X86_REG_FS: Type = 32;
-    pub const X86_REG_GS: Type = 33;
-    pub const X86_REG_IP: Type = 34;
-    pub const X86_REG_RAX: Type = 35;
-    pub const X86_REG_RBP: Type = 36;
-    pub const X86_REG_RBX: Type = 37;
-    pub const X86_REG_RCX: Type = 38;
-    pub const X86_REG_RDI: Type = 39;
-    pub const X86_REG_RDX: Type = 40;
-    pub const X86_REG_RIP: Type = 41;
-    pub const X86_REG_RIZ: Type = 42;
-    pub const X86_REG_RSI: Type = 43;
-    pub const X86_REG_RSP: Type = 44;
-    pub const X86_REG_SI: Type = 45;
-    pub const X86_REG_SIL: Type = 46;
-    pub const X86_REG_SP: Type = 47;
-    pub const X86_REG_SPL: Type = 48;
-    pub const X86_REG_SS: Type = 49;
-    pub const X86_REG_CR0: Type = 50;
-    pub const X86_REG_CR1: Type = 51;
-    pub const X86_REG_CR2: Type = 52;
-    pub const X86_REG_CR3: Type = 53;
-    pub const X86_REG_CR4: Type = 54;
-    pub const X86_REG_CR5: Type = 55;
-    pub const X86_REG_CR6: Type = 56;
-    pub const X86_REG_CR7: Type = 57;
-    pub const X86_REG_CR8: Type = 58;
-    pub const X86_REG_CR9: Type = 59;
-    pub const X86_REG_CR10: Type = 60;
-    pub const X86_REG_CR11: Type = 61;
-    pub const X86_REG_CR12: Type = 62;
-    pub const X86_REG_CR13: Type = 63;
-    pub const X86_REG_CR14: Type = 64;
-    pub const X86_REG_CR15: Type = 65;
-    pub const X86_REG_DR0: Type = 66;
-    pub const X86_REG_DR1: Type = 67;
-    pub const X86_REG_DR2: Type = 68;
-    pub const X86_REG_DR3: Type = 69;
-    pub const X86_REG_DR4: Type = 70;
-    pub const X86_REG_DR5: Type = 71;
-    pub const X86_REG_DR6: Type = 72;
-    pub const X86_REG_DR7: Type = 73;
-    pub const X86_REG_DR8: Type = 74;
-    pub const X86_REG_DR9: Type = 75;
-    pub const X86_REG_DR10: Type = 76;
-    pub const X86_REG_DR11: Type = 77;
-    pub const X86_REG_DR12: Type = 78;
-    pub const X86_REG_DR13: Type = 79;
-    pub const X86_REG_DR14: Type = 80;
-    pub const X86_REG_DR15: Type = 81;
-    pub const X86_REG_FP0: Type = 82;
-    pub const X86_REG_FP1: Type = 83;
-    pub const X86_REG_FP2: Type = 84;
-    pub const X86_REG_FP3: Type = 85;
-    pub const X86_REG_FP4: Type = 86;
-    pub const X86_REG_FP5: Type = 87;
-    pub const X86_REG_FP6: Type = 88;
-    pub const X86_REG_FP7: Type = 89;
-    pub const X86_REG_K0: Type = 90;
-    pub const X86_REG_K1: Type = 91;
-    pub const X86_REG_K2: Type = 92;
-    pub const X86_REG_K3: Type = 93;
-    pub const X86_REG_K4: Type = 94;
-    pub const X86_REG_K5: Type = 95;
-    pub const X86_REG_K6: Type = 96;
-    pub const X86_REG_K7: Type = 97;
-    pub const X86_REG_MM0: Type = 98;
-    pub const X86_REG_MM1: Type = 99;
-    pub const X86_REG_MM2: Type = 100;
-    pub const X86_REG_MM3: Type = 101;
-    pub const X86_REG_MM4: Type = 102;
-    pub const X86_REG_MM5: Type = 103;
-    pub const X86_REG_MM6: Type = 104;
-    pub const X86_REG_MM7: Type = 105;
-    pub const X86_REG_R8: Type = 106;
-    pub const X86_REG_R9: Type = 107;
-    pub const X86_REG_R10: Type = 108;
-    pub const X86_REG_R11: Type = 109;
-    pub const X86_REG_R12: Type = 110;
-    pub const X86_REG_R13: Type = 111;
-    pub const X86_REG_R14: Type = 112;
-    pub const X86_REG_R15: Type = 113;
-    pub const X86_REG_ST0: Type = 114;
-    pub const X86_REG_ST1: Type = 115;
-    pub const X86_REG_ST2: Type = 116;
-    pub const X86_REG_ST3: Type = 117;
-    pub const X86_REG_ST4: Type = 118;
-    pub const X86_REG_ST5: Type = 119;
-    pub const X86_REG_ST6: Type = 120;
-    pub const X86_REG_ST7: Type = 121;
-    pub const X86_REG_XMM0: Type = 122;
-    pub const X86_REG_XMM1: Type = 123;
-    pub const X86_REG_XMM2: Type = 124;
-    pub const X86_REG_XMM3: Type = 125;
-    pub const X86_REG_XMM4: Type = 126;
-    pub const X86_REG_XMM5: Type = 127;
-    pub const X86_REG_XMM6: Type = 128;
-    pub const X86_REG_XMM7: Type = 129;
-    pub const X86_REG_XMM8: Type = 130;
-    pub const X86_REG_XMM9: Type = 131;
-    pub const X86_REG_XMM10: Type = 132;
-    pub const X86_REG_XMM11: Type = 133;
-    pub const X86_REG_XMM12: Type = 134;
-    pub const X86_REG_XMM13: Type = 135;
-    pub const X86_REG_XMM14: Type = 136;
-    pub const X86_REG_XMM15: Type = 137;
-    pub const X86_REG_XMM16: Type = 138;
-    pub const X86_REG_XMM17: Type = 139;
-    pub const X86_REG_XMM18: Type = 140;
-    pub const X86_REG_XMM19: Type = 141;
-    pub const X86_REG_XMM20: Type = 142;
-    pub const X86_REG_XMM21: Type = 143;
-    pub const X86_REG_XMM22: Type = 144;
-    pub const X86_REG_XMM23: Type = 145;
-    pub const X86_REG_XMM24: Type = 146;
-    pub const X86_REG_XMM25: Type = 147;
-    pub const X86_REG_XMM26: Type = 148;
-    pub const X86_REG_XMM27: Type = 149;
-    pub const X86_REG_XMM28: Type = 150;
-    pub const X86_REG_XMM29: Type = 151;
-    pub const X86_REG_XMM30: Type = 152;
-    pub const X86_REG_XMM31: Type = 153;
-    pub const X86_REG_YMM0: Type = 154;
-    pub const X86_REG_YMM1: Type = 155;
-    pub const X86_REG_YMM2: Type = 156;
-    pub const X86_REG_YMM3: Type = 157;
-    pub const X86_REG_YMM4: Type = 158;
-    pub const X86_REG_YMM5: Type = 159;
-    pub const X86_REG_YMM6: Type = 160;
-    pub const X86_REG_YMM7: Type = 161;
-    pub const X86_REG_YMM8: Type = 162;
-    pub const X86_REG_YMM9: Type = 163;
-    pub const X86_REG_YMM10: Type = 164;
-    pub const X86_REG_YMM11: Type = 165;
-    pub const X86_REG_YMM12: Type = 166;
-    pub const X86_REG_YMM13: Type = 167;
-    pub const X86_REG_YMM14: Type = 168;
-    pub const X86_REG_YMM15: Type = 169;
-    pub const X86_REG_YMM16: Type = 170;
-    pub const X86_REG_YMM17: Type = 171;
-    pub const X86_REG_YMM18: Type = 172;
-    pub const X86_REG_YMM19: Type = 173;
-    pub const X86_REG_YMM20: Type = 174;
-    pub const X86_REG_YMM21: Type = 175;
-    pub const X86_REG_YMM22: Type = 176;
-    pub const X86_REG_YMM23: Type = 177;
-    pub const X86_REG_YMM24: Type = 178;
-    pub const X86_REG_YMM25: Type = 179;
-    pub const X86_REG_YMM26: Type = 180;
-    pub const X86_REG_YMM27: Type = 181;
-    pub const X86_REG_YMM28: Type = 182;
-    pub const X86_REG_YMM29: Type = 183;
-    pub const X86_REG_YMM30: Type = 184;
-    pub const X86_REG_YMM31: Type = 185;
-    pub const X86_REG_ZMM0: Type = 186;
-    pub const X86_REG_ZMM1: Type = 187;
-    pub const X86_REG_ZMM2: Type = 188;
-    pub const X86_REG_ZMM3: Type = 189;
-    pub const X86_REG_ZMM4: Type = 190;
-    pub const X86_REG_ZMM5: Type = 191;
-    pub const X86_REG_ZMM6: Type = 192;
-    pub const X86_REG_ZMM7: Type = 193;
-    pub const X86_REG_ZMM8: Type = 194;
-    pub const X86_REG_ZMM9: Type = 195;
-    pub const X86_REG_ZMM10: Type = 196;
-    pub const X86_REG_ZMM11: Type = 197;
-    pub const X86_REG_ZMM12: Type = 198;
-    pub const X86_REG_ZMM13: Type = 199;
-    pub const X86_REG_ZMM14: Type = 200;
-    pub const X86_REG_ZMM15: Type = 201;
-    pub const X86_REG_ZMM16: Type = 202;
-    pub const X86_REG_ZMM17: Type = 203;
-    pub const X86_REG_ZMM18: Type = 204;
-    pub const X86_REG_ZMM19: Type = 205;
-    pub const X86_REG_ZMM20: Type = 206;
-    pub const X86_REG_ZMM21: Type = 207;
-    pub const X86_REG_ZMM22: Type = 208;
-    pub const X86_REG_ZMM23: Type = 209;
-    pub const X86_REG_ZMM24: Type = 210;
-    pub const X86_REG_ZMM25: Type = 211;
-    pub const X86_REG_ZMM26: Type = 212;
-    pub const X86_REG_ZMM27: Type = 213;
-    pub const X86_REG_ZMM28: Type = 214;
-    pub const X86_REG_ZMM29: Type = 215;
-    pub const X86_REG_ZMM30: Type = 216;
-    pub const X86_REG_ZMM31: Type = 217;
-    pub const X86_REG_R8B: Type = 218;
-    pub const X86_REG_R9B: Type = 219;
-    pub const X86_REG_R10B: Type = 220;
-    pub const X86_REG_R11B: Type = 221;
-    pub const X86_REG_R12B: Type = 222;
-    pub const X86_REG_R13B: Type = 223;
-    pub const X86_REG_R14B: Type = 224;
-    pub const X86_REG_R15B: Type = 225;
-    pub const X86_REG_R8D: Type = 226;
-    pub const X86_REG_R9D: Type = 227;
-    pub const X86_REG_R10D: Type = 228;
-    pub const X86_REG_R11D: Type = 229;
-    pub const X86_REG_R12D: Type = 230;
-    pub const X86_REG_R13D: Type = 231;
-    pub const X86_REG_R14D: Type = 232;
-    pub const X86_REG_R15D: Type = 233;
-    pub const X86_REG_R8W: Type = 234;
-    pub const X86_REG_R9W: Type = 235;
-    pub const X86_REG_R10W: Type = 236;
-    pub const X86_REG_R11W: Type = 237;
-    pub const X86_REG_R12W: Type = 238;
-    pub const X86_REG_R13W: Type = 239;
-    pub const X86_REG_R14W: Type = 240;
-    pub const X86_REG_R15W: Type = 241;
-    pub const X86_REG_BND0: Type = 242;
-    pub const X86_REG_BND1: Type = 243;
-    pub const X86_REG_BND2: Type = 244;
-    pub const X86_REG_BND3: Type = 245;
-    pub const X86_REG_ENDING: Type = 246;
+impl sysz_insn_group {
+    #[doc = "< = CS_GRP_INVALID"]
+    pub const SYSZ_GRP_INVALID: sysz_insn_group = sysz_insn_group(0);
+}
+impl sysz_insn_group {
+    #[doc = "< = CS_GRP_JUMP"]
+    pub const SYSZ_GRP_JUMP: sysz_insn_group = sysz_insn_group(1);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_DISTINCTOPS: sysz_insn_group = sysz_insn_group(128);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_FPEXTENSION: sysz_insn_group = sysz_insn_group(129);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_HIGHWORD: sysz_insn_group = sysz_insn_group(130);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_INTERLOCKEDACCESS1: sysz_insn_group = sysz_insn_group(131);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_LOADSTOREONCOND: sysz_insn_group = sysz_insn_group(132);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_DFPPACKEDCONVERSION: sysz_insn_group = sysz_insn_group(133);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_DFPZONEDCONVERSION: sysz_insn_group = sysz_insn_group(134);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_ENHANCEDDAT2: sysz_insn_group = sysz_insn_group(135);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_EXECUTIONHINT: sysz_insn_group = sysz_insn_group(136);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_GUARDEDSTORAGE: sysz_insn_group = sysz_insn_group(137);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_INSERTREFERENCEBITSMULTIPLE: sysz_insn_group = sysz_insn_group(138);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_LOADANDTRAP: sysz_insn_group = sysz_insn_group(139);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_LOADANDZERORIGHTMOSTBYTE: sysz_insn_group = sysz_insn_group(140);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_LOADSTOREONCOND2: sysz_insn_group = sysz_insn_group(141);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MESSAGESECURITYASSIST3: sysz_insn_group = sysz_insn_group(142);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MESSAGESECURITYASSIST4: sysz_insn_group = sysz_insn_group(143);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MESSAGESECURITYASSIST5: sysz_insn_group = sysz_insn_group(144);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MESSAGESECURITYASSIST7: sysz_insn_group = sysz_insn_group(145);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MESSAGESECURITYASSIST8: sysz_insn_group = sysz_insn_group(146);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MISCELLANEOUSEXTENSIONS: sysz_insn_group = sysz_insn_group(147);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_MISCELLANEOUSEXTENSIONS2: sysz_insn_group = sysz_insn_group(148);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_NOVECTOR: sysz_insn_group = sysz_insn_group(149);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_POPULATIONCOUNT: sysz_insn_group = sysz_insn_group(150);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_PROCESSORASSIST: sysz_insn_group = sysz_insn_group(151);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_RESETREFERENCEBITSMULTIPLE: sysz_insn_group = sysz_insn_group(152);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_TRANSACTIONALEXECUTION: sysz_insn_group = sysz_insn_group(153);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_VECTOR: sysz_insn_group = sysz_insn_group(154);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_VECTORENHANCEMENTS1: sysz_insn_group = sysz_insn_group(155);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_VECTORPACKEDDECIMAL: sysz_insn_group = sysz_insn_group(156);
+}
+impl sysz_insn_group {
+    pub const SYSZ_GRP_ENDING: sysz_insn_group = sysz_insn_group(157);
+}
+#[repr(transparent)]
+#[doc = " Group of SystemZ instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct sysz_insn_group(pub libc::c_uint);
+impl x86_reg {
+    pub const X86_REG_INVALID: x86_reg = x86_reg(0);
+}
+impl x86_reg {
+    pub const X86_REG_AH: x86_reg = x86_reg(1);
+}
+impl x86_reg {
+    pub const X86_REG_AL: x86_reg = x86_reg(2);
+}
+impl x86_reg {
+    pub const X86_REG_AX: x86_reg = x86_reg(3);
+}
+impl x86_reg {
+    pub const X86_REG_BH: x86_reg = x86_reg(4);
+}
+impl x86_reg {
+    pub const X86_REG_BL: x86_reg = x86_reg(5);
+}
+impl x86_reg {
+    pub const X86_REG_BP: x86_reg = x86_reg(6);
+}
+impl x86_reg {
+    pub const X86_REG_BPL: x86_reg = x86_reg(7);
+}
+impl x86_reg {
+    pub const X86_REG_BX: x86_reg = x86_reg(8);
+}
+impl x86_reg {
+    pub const X86_REG_CH: x86_reg = x86_reg(9);
+}
+impl x86_reg {
+    pub const X86_REG_CL: x86_reg = x86_reg(10);
+}
+impl x86_reg {
+    pub const X86_REG_CS: x86_reg = x86_reg(11);
+}
+impl x86_reg {
+    pub const X86_REG_CX: x86_reg = x86_reg(12);
+}
+impl x86_reg {
+    pub const X86_REG_DH: x86_reg = x86_reg(13);
+}
+impl x86_reg {
+    pub const X86_REG_DI: x86_reg = x86_reg(14);
+}
+impl x86_reg {
+    pub const X86_REG_DIL: x86_reg = x86_reg(15);
+}
+impl x86_reg {
+    pub const X86_REG_DL: x86_reg = x86_reg(16);
+}
+impl x86_reg {
+    pub const X86_REG_DS: x86_reg = x86_reg(17);
+}
+impl x86_reg {
+    pub const X86_REG_DX: x86_reg = x86_reg(18);
+}
+impl x86_reg {
+    pub const X86_REG_EAX: x86_reg = x86_reg(19);
+}
+impl x86_reg {
+    pub const X86_REG_EBP: x86_reg = x86_reg(20);
+}
+impl x86_reg {
+    pub const X86_REG_EBX: x86_reg = x86_reg(21);
+}
+impl x86_reg {
+    pub const X86_REG_ECX: x86_reg = x86_reg(22);
+}
+impl x86_reg {
+    pub const X86_REG_EDI: x86_reg = x86_reg(23);
+}
+impl x86_reg {
+    pub const X86_REG_EDX: x86_reg = x86_reg(24);
+}
+impl x86_reg {
+    pub const X86_REG_EFLAGS: x86_reg = x86_reg(25);
+}
+impl x86_reg {
+    pub const X86_REG_EIP: x86_reg = x86_reg(26);
+}
+impl x86_reg {
+    pub const X86_REG_EIZ: x86_reg = x86_reg(27);
+}
+impl x86_reg {
+    pub const X86_REG_ES: x86_reg = x86_reg(28);
+}
+impl x86_reg {
+    pub const X86_REG_ESI: x86_reg = x86_reg(29);
+}
+impl x86_reg {
+    pub const X86_REG_ESP: x86_reg = x86_reg(30);
+}
+impl x86_reg {
+    pub const X86_REG_FPSW: x86_reg = x86_reg(31);
+}
+impl x86_reg {
+    pub const X86_REG_FS: x86_reg = x86_reg(32);
+}
+impl x86_reg {
+    pub const X86_REG_GS: x86_reg = x86_reg(33);
+}
+impl x86_reg {
+    pub const X86_REG_IP: x86_reg = x86_reg(34);
+}
+impl x86_reg {
+    pub const X86_REG_RAX: x86_reg = x86_reg(35);
+}
+impl x86_reg {
+    pub const X86_REG_RBP: x86_reg = x86_reg(36);
+}
+impl x86_reg {
+    pub const X86_REG_RBX: x86_reg = x86_reg(37);
+}
+impl x86_reg {
+    pub const X86_REG_RCX: x86_reg = x86_reg(38);
+}
+impl x86_reg {
+    pub const X86_REG_RDI: x86_reg = x86_reg(39);
+}
+impl x86_reg {
+    pub const X86_REG_RDX: x86_reg = x86_reg(40);
+}
+impl x86_reg {
+    pub const X86_REG_RIP: x86_reg = x86_reg(41);
+}
+impl x86_reg {
+    pub const X86_REG_RIZ: x86_reg = x86_reg(42);
+}
+impl x86_reg {
+    pub const X86_REG_RSI: x86_reg = x86_reg(43);
+}
+impl x86_reg {
+    pub const X86_REG_RSP: x86_reg = x86_reg(44);
+}
+impl x86_reg {
+    pub const X86_REG_SI: x86_reg = x86_reg(45);
+}
+impl x86_reg {
+    pub const X86_REG_SIL: x86_reg = x86_reg(46);
+}
+impl x86_reg {
+    pub const X86_REG_SP: x86_reg = x86_reg(47);
+}
+impl x86_reg {
+    pub const X86_REG_SPL: x86_reg = x86_reg(48);
+}
+impl x86_reg {
+    pub const X86_REG_SS: x86_reg = x86_reg(49);
+}
+impl x86_reg {
+    pub const X86_REG_CR0: x86_reg = x86_reg(50);
+}
+impl x86_reg {
+    pub const X86_REG_CR1: x86_reg = x86_reg(51);
+}
+impl x86_reg {
+    pub const X86_REG_CR2: x86_reg = x86_reg(52);
+}
+impl x86_reg {
+    pub const X86_REG_CR3: x86_reg = x86_reg(53);
+}
+impl x86_reg {
+    pub const X86_REG_CR4: x86_reg = x86_reg(54);
+}
+impl x86_reg {
+    pub const X86_REG_CR5: x86_reg = x86_reg(55);
+}
+impl x86_reg {
+    pub const X86_REG_CR6: x86_reg = x86_reg(56);
+}
+impl x86_reg {
+    pub const X86_REG_CR7: x86_reg = x86_reg(57);
+}
+impl x86_reg {
+    pub const X86_REG_CR8: x86_reg = x86_reg(58);
+}
+impl x86_reg {
+    pub const X86_REG_CR9: x86_reg = x86_reg(59);
+}
+impl x86_reg {
+    pub const X86_REG_CR10: x86_reg = x86_reg(60);
+}
+impl x86_reg {
+    pub const X86_REG_CR11: x86_reg = x86_reg(61);
+}
+impl x86_reg {
+    pub const X86_REG_CR12: x86_reg = x86_reg(62);
+}
+impl x86_reg {
+    pub const X86_REG_CR13: x86_reg = x86_reg(63);
+}
+impl x86_reg {
+    pub const X86_REG_CR14: x86_reg = x86_reg(64);
+}
+impl x86_reg {
+    pub const X86_REG_CR15: x86_reg = x86_reg(65);
+}
+impl x86_reg {
+    pub const X86_REG_DR0: x86_reg = x86_reg(66);
+}
+impl x86_reg {
+    pub const X86_REG_DR1: x86_reg = x86_reg(67);
+}
+impl x86_reg {
+    pub const X86_REG_DR2: x86_reg = x86_reg(68);
+}
+impl x86_reg {
+    pub const X86_REG_DR3: x86_reg = x86_reg(69);
+}
+impl x86_reg {
+    pub const X86_REG_DR4: x86_reg = x86_reg(70);
+}
+impl x86_reg {
+    pub const X86_REG_DR5: x86_reg = x86_reg(71);
+}
+impl x86_reg {
+    pub const X86_REG_DR6: x86_reg = x86_reg(72);
+}
+impl x86_reg {
+    pub const X86_REG_DR7: x86_reg = x86_reg(73);
+}
+impl x86_reg {
+    pub const X86_REG_DR8: x86_reg = x86_reg(74);
+}
+impl x86_reg {
+    pub const X86_REG_DR9: x86_reg = x86_reg(75);
+}
+impl x86_reg {
+    pub const X86_REG_DR10: x86_reg = x86_reg(76);
+}
+impl x86_reg {
+    pub const X86_REG_DR11: x86_reg = x86_reg(77);
+}
+impl x86_reg {
+    pub const X86_REG_DR12: x86_reg = x86_reg(78);
+}
+impl x86_reg {
+    pub const X86_REG_DR13: x86_reg = x86_reg(79);
+}
+impl x86_reg {
+    pub const X86_REG_DR14: x86_reg = x86_reg(80);
+}
+impl x86_reg {
+    pub const X86_REG_DR15: x86_reg = x86_reg(81);
+}
+impl x86_reg {
+    pub const X86_REG_FP0: x86_reg = x86_reg(82);
+}
+impl x86_reg {
+    pub const X86_REG_FP1: x86_reg = x86_reg(83);
+}
+impl x86_reg {
+    pub const X86_REG_FP2: x86_reg = x86_reg(84);
+}
+impl x86_reg {
+    pub const X86_REG_FP3: x86_reg = x86_reg(85);
+}
+impl x86_reg {
+    pub const X86_REG_FP4: x86_reg = x86_reg(86);
+}
+impl x86_reg {
+    pub const X86_REG_FP5: x86_reg = x86_reg(87);
+}
+impl x86_reg {
+    pub const X86_REG_FP6: x86_reg = x86_reg(88);
+}
+impl x86_reg {
+    pub const X86_REG_FP7: x86_reg = x86_reg(89);
+}
+impl x86_reg {
+    pub const X86_REG_K0: x86_reg = x86_reg(90);
+}
+impl x86_reg {
+    pub const X86_REG_K1: x86_reg = x86_reg(91);
+}
+impl x86_reg {
+    pub const X86_REG_K2: x86_reg = x86_reg(92);
+}
+impl x86_reg {
+    pub const X86_REG_K3: x86_reg = x86_reg(93);
+}
+impl x86_reg {
+    pub const X86_REG_K4: x86_reg = x86_reg(94);
+}
+impl x86_reg {
+    pub const X86_REG_K5: x86_reg = x86_reg(95);
+}
+impl x86_reg {
+    pub const X86_REG_K6: x86_reg = x86_reg(96);
+}
+impl x86_reg {
+    pub const X86_REG_K7: x86_reg = x86_reg(97);
+}
+impl x86_reg {
+    pub const X86_REG_MM0: x86_reg = x86_reg(98);
+}
+impl x86_reg {
+    pub const X86_REG_MM1: x86_reg = x86_reg(99);
+}
+impl x86_reg {
+    pub const X86_REG_MM2: x86_reg = x86_reg(100);
+}
+impl x86_reg {
+    pub const X86_REG_MM3: x86_reg = x86_reg(101);
+}
+impl x86_reg {
+    pub const X86_REG_MM4: x86_reg = x86_reg(102);
+}
+impl x86_reg {
+    pub const X86_REG_MM5: x86_reg = x86_reg(103);
+}
+impl x86_reg {
+    pub const X86_REG_MM6: x86_reg = x86_reg(104);
+}
+impl x86_reg {
+    pub const X86_REG_MM7: x86_reg = x86_reg(105);
+}
+impl x86_reg {
+    pub const X86_REG_R8: x86_reg = x86_reg(106);
+}
+impl x86_reg {
+    pub const X86_REG_R9: x86_reg = x86_reg(107);
+}
+impl x86_reg {
+    pub const X86_REG_R10: x86_reg = x86_reg(108);
+}
+impl x86_reg {
+    pub const X86_REG_R11: x86_reg = x86_reg(109);
+}
+impl x86_reg {
+    pub const X86_REG_R12: x86_reg = x86_reg(110);
+}
+impl x86_reg {
+    pub const X86_REG_R13: x86_reg = x86_reg(111);
+}
+impl x86_reg {
+    pub const X86_REG_R14: x86_reg = x86_reg(112);
+}
+impl x86_reg {
+    pub const X86_REG_R15: x86_reg = x86_reg(113);
+}
+impl x86_reg {
+    pub const X86_REG_ST0: x86_reg = x86_reg(114);
+}
+impl x86_reg {
+    pub const X86_REG_ST1: x86_reg = x86_reg(115);
+}
+impl x86_reg {
+    pub const X86_REG_ST2: x86_reg = x86_reg(116);
+}
+impl x86_reg {
+    pub const X86_REG_ST3: x86_reg = x86_reg(117);
+}
+impl x86_reg {
+    pub const X86_REG_ST4: x86_reg = x86_reg(118);
+}
+impl x86_reg {
+    pub const X86_REG_ST5: x86_reg = x86_reg(119);
+}
+impl x86_reg {
+    pub const X86_REG_ST6: x86_reg = x86_reg(120);
+}
+impl x86_reg {
+    pub const X86_REG_ST7: x86_reg = x86_reg(121);
+}
+impl x86_reg {
+    pub const X86_REG_XMM0: x86_reg = x86_reg(122);
+}
+impl x86_reg {
+    pub const X86_REG_XMM1: x86_reg = x86_reg(123);
+}
+impl x86_reg {
+    pub const X86_REG_XMM2: x86_reg = x86_reg(124);
+}
+impl x86_reg {
+    pub const X86_REG_XMM3: x86_reg = x86_reg(125);
+}
+impl x86_reg {
+    pub const X86_REG_XMM4: x86_reg = x86_reg(126);
+}
+impl x86_reg {
+    pub const X86_REG_XMM5: x86_reg = x86_reg(127);
+}
+impl x86_reg {
+    pub const X86_REG_XMM6: x86_reg = x86_reg(128);
+}
+impl x86_reg {
+    pub const X86_REG_XMM7: x86_reg = x86_reg(129);
+}
+impl x86_reg {
+    pub const X86_REG_XMM8: x86_reg = x86_reg(130);
+}
+impl x86_reg {
+    pub const X86_REG_XMM9: x86_reg = x86_reg(131);
+}
+impl x86_reg {
+    pub const X86_REG_XMM10: x86_reg = x86_reg(132);
+}
+impl x86_reg {
+    pub const X86_REG_XMM11: x86_reg = x86_reg(133);
+}
+impl x86_reg {
+    pub const X86_REG_XMM12: x86_reg = x86_reg(134);
+}
+impl x86_reg {
+    pub const X86_REG_XMM13: x86_reg = x86_reg(135);
+}
+impl x86_reg {
+    pub const X86_REG_XMM14: x86_reg = x86_reg(136);
+}
+impl x86_reg {
+    pub const X86_REG_XMM15: x86_reg = x86_reg(137);
+}
+impl x86_reg {
+    pub const X86_REG_XMM16: x86_reg = x86_reg(138);
+}
+impl x86_reg {
+    pub const X86_REG_XMM17: x86_reg = x86_reg(139);
+}
+impl x86_reg {
+    pub const X86_REG_XMM18: x86_reg = x86_reg(140);
+}
+impl x86_reg {
+    pub const X86_REG_XMM19: x86_reg = x86_reg(141);
+}
+impl x86_reg {
+    pub const X86_REG_XMM20: x86_reg = x86_reg(142);
+}
+impl x86_reg {
+    pub const X86_REG_XMM21: x86_reg = x86_reg(143);
+}
+impl x86_reg {
+    pub const X86_REG_XMM22: x86_reg = x86_reg(144);
+}
+impl x86_reg {
+    pub const X86_REG_XMM23: x86_reg = x86_reg(145);
+}
+impl x86_reg {
+    pub const X86_REG_XMM24: x86_reg = x86_reg(146);
+}
+impl x86_reg {
+    pub const X86_REG_XMM25: x86_reg = x86_reg(147);
+}
+impl x86_reg {
+    pub const X86_REG_XMM26: x86_reg = x86_reg(148);
+}
+impl x86_reg {
+    pub const X86_REG_XMM27: x86_reg = x86_reg(149);
+}
+impl x86_reg {
+    pub const X86_REG_XMM28: x86_reg = x86_reg(150);
+}
+impl x86_reg {
+    pub const X86_REG_XMM29: x86_reg = x86_reg(151);
+}
+impl x86_reg {
+    pub const X86_REG_XMM30: x86_reg = x86_reg(152);
+}
+impl x86_reg {
+    pub const X86_REG_XMM31: x86_reg = x86_reg(153);
+}
+impl x86_reg {
+    pub const X86_REG_YMM0: x86_reg = x86_reg(154);
+}
+impl x86_reg {
+    pub const X86_REG_YMM1: x86_reg = x86_reg(155);
+}
+impl x86_reg {
+    pub const X86_REG_YMM2: x86_reg = x86_reg(156);
+}
+impl x86_reg {
+    pub const X86_REG_YMM3: x86_reg = x86_reg(157);
+}
+impl x86_reg {
+    pub const X86_REG_YMM4: x86_reg = x86_reg(158);
+}
+impl x86_reg {
+    pub const X86_REG_YMM5: x86_reg = x86_reg(159);
+}
+impl x86_reg {
+    pub const X86_REG_YMM6: x86_reg = x86_reg(160);
+}
+impl x86_reg {
+    pub const X86_REG_YMM7: x86_reg = x86_reg(161);
+}
+impl x86_reg {
+    pub const X86_REG_YMM8: x86_reg = x86_reg(162);
+}
+impl x86_reg {
+    pub const X86_REG_YMM9: x86_reg = x86_reg(163);
+}
+impl x86_reg {
+    pub const X86_REG_YMM10: x86_reg = x86_reg(164);
+}
+impl x86_reg {
+    pub const X86_REG_YMM11: x86_reg = x86_reg(165);
+}
+impl x86_reg {
+    pub const X86_REG_YMM12: x86_reg = x86_reg(166);
+}
+impl x86_reg {
+    pub const X86_REG_YMM13: x86_reg = x86_reg(167);
+}
+impl x86_reg {
+    pub const X86_REG_YMM14: x86_reg = x86_reg(168);
+}
+impl x86_reg {
+    pub const X86_REG_YMM15: x86_reg = x86_reg(169);
+}
+impl x86_reg {
+    pub const X86_REG_YMM16: x86_reg = x86_reg(170);
+}
+impl x86_reg {
+    pub const X86_REG_YMM17: x86_reg = x86_reg(171);
+}
+impl x86_reg {
+    pub const X86_REG_YMM18: x86_reg = x86_reg(172);
+}
+impl x86_reg {
+    pub const X86_REG_YMM19: x86_reg = x86_reg(173);
+}
+impl x86_reg {
+    pub const X86_REG_YMM20: x86_reg = x86_reg(174);
+}
+impl x86_reg {
+    pub const X86_REG_YMM21: x86_reg = x86_reg(175);
+}
+impl x86_reg {
+    pub const X86_REG_YMM22: x86_reg = x86_reg(176);
+}
+impl x86_reg {
+    pub const X86_REG_YMM23: x86_reg = x86_reg(177);
+}
+impl x86_reg {
+    pub const X86_REG_YMM24: x86_reg = x86_reg(178);
+}
+impl x86_reg {
+    pub const X86_REG_YMM25: x86_reg = x86_reg(179);
+}
+impl x86_reg {
+    pub const X86_REG_YMM26: x86_reg = x86_reg(180);
+}
+impl x86_reg {
+    pub const X86_REG_YMM27: x86_reg = x86_reg(181);
+}
+impl x86_reg {
+    pub const X86_REG_YMM28: x86_reg = x86_reg(182);
+}
+impl x86_reg {
+    pub const X86_REG_YMM29: x86_reg = x86_reg(183);
+}
+impl x86_reg {
+    pub const X86_REG_YMM30: x86_reg = x86_reg(184);
+}
+impl x86_reg {
+    pub const X86_REG_YMM31: x86_reg = x86_reg(185);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM0: x86_reg = x86_reg(186);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM1: x86_reg = x86_reg(187);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM2: x86_reg = x86_reg(188);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM3: x86_reg = x86_reg(189);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM4: x86_reg = x86_reg(190);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM5: x86_reg = x86_reg(191);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM6: x86_reg = x86_reg(192);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM7: x86_reg = x86_reg(193);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM8: x86_reg = x86_reg(194);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM9: x86_reg = x86_reg(195);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM10: x86_reg = x86_reg(196);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM11: x86_reg = x86_reg(197);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM12: x86_reg = x86_reg(198);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM13: x86_reg = x86_reg(199);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM14: x86_reg = x86_reg(200);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM15: x86_reg = x86_reg(201);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM16: x86_reg = x86_reg(202);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM17: x86_reg = x86_reg(203);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM18: x86_reg = x86_reg(204);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM19: x86_reg = x86_reg(205);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM20: x86_reg = x86_reg(206);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM21: x86_reg = x86_reg(207);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM22: x86_reg = x86_reg(208);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM23: x86_reg = x86_reg(209);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM24: x86_reg = x86_reg(210);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM25: x86_reg = x86_reg(211);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM26: x86_reg = x86_reg(212);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM27: x86_reg = x86_reg(213);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM28: x86_reg = x86_reg(214);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM29: x86_reg = x86_reg(215);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM30: x86_reg = x86_reg(216);
+}
+impl x86_reg {
+    pub const X86_REG_ZMM31: x86_reg = x86_reg(217);
+}
+impl x86_reg {
+    pub const X86_REG_R8B: x86_reg = x86_reg(218);
+}
+impl x86_reg {
+    pub const X86_REG_R9B: x86_reg = x86_reg(219);
+}
+impl x86_reg {
+    pub const X86_REG_R10B: x86_reg = x86_reg(220);
+}
+impl x86_reg {
+    pub const X86_REG_R11B: x86_reg = x86_reg(221);
+}
+impl x86_reg {
+    pub const X86_REG_R12B: x86_reg = x86_reg(222);
+}
+impl x86_reg {
+    pub const X86_REG_R13B: x86_reg = x86_reg(223);
+}
+impl x86_reg {
+    pub const X86_REG_R14B: x86_reg = x86_reg(224);
+}
+impl x86_reg {
+    pub const X86_REG_R15B: x86_reg = x86_reg(225);
+}
+impl x86_reg {
+    pub const X86_REG_R8D: x86_reg = x86_reg(226);
+}
+impl x86_reg {
+    pub const X86_REG_R9D: x86_reg = x86_reg(227);
+}
+impl x86_reg {
+    pub const X86_REG_R10D: x86_reg = x86_reg(228);
+}
+impl x86_reg {
+    pub const X86_REG_R11D: x86_reg = x86_reg(229);
+}
+impl x86_reg {
+    pub const X86_REG_R12D: x86_reg = x86_reg(230);
+}
+impl x86_reg {
+    pub const X86_REG_R13D: x86_reg = x86_reg(231);
+}
+impl x86_reg {
+    pub const X86_REG_R14D: x86_reg = x86_reg(232);
+}
+impl x86_reg {
+    pub const X86_REG_R15D: x86_reg = x86_reg(233);
+}
+impl x86_reg {
+    pub const X86_REG_R8W: x86_reg = x86_reg(234);
+}
+impl x86_reg {
+    pub const X86_REG_R9W: x86_reg = x86_reg(235);
+}
+impl x86_reg {
+    pub const X86_REG_R10W: x86_reg = x86_reg(236);
+}
+impl x86_reg {
+    pub const X86_REG_R11W: x86_reg = x86_reg(237);
+}
+impl x86_reg {
+    pub const X86_REG_R12W: x86_reg = x86_reg(238);
+}
+impl x86_reg {
+    pub const X86_REG_R13W: x86_reg = x86_reg(239);
+}
+impl x86_reg {
+    pub const X86_REG_R14W: x86_reg = x86_reg(240);
+}
+impl x86_reg {
+    pub const X86_REG_R15W: x86_reg = x86_reg(241);
 }
+impl x86_reg {
+    pub const X86_REG_BND0: x86_reg = x86_reg(242);
+}
+impl x86_reg {
+    pub const X86_REG_BND1: x86_reg = x86_reg(243);
+}
+impl x86_reg {
+    pub const X86_REG_BND2: x86_reg = x86_reg(244);
+}
+impl x86_reg {
+    pub const X86_REG_BND3: x86_reg = x86_reg(245);
+}
+impl x86_reg {
+    pub const X86_REG_ENDING: x86_reg = x86_reg(246);
+}
+#[repr(transparent)]
+#[doc = " X86 registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct x86_reg(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " Operand type for instruction's operands"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -11451,7 +14384,9 @@ pub enum x86_avx_rm {
     #[doc = "< Round toward zero"]
     X86_AVX_RM_RZ = 4,
 }
-pub const X86_PREFIX_REPE: x86_prefix = x86_prefix::X86_PREFIX_REP;
+impl x86_prefix {
+    pub const X86_PREFIX_REPE: x86_prefix = x86_prefix::X86_PREFIX_REP;
+}
 #[repr(u32)]
 #[doc = " Instruction prefixes - to be used in cs_x86.prefix[]"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -11479,39 +14414,31 @@ pub enum x86_prefix {
     #[doc = "< address-size override (cs_x86.prefix[3]"]
     X86_PREFIX_ADDRSIZE = 103,
 }
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with X86_OP_MEM operand type above"]
+#[doc = " Instruction's operand referring to memory\n This is associated with X86_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct x86_op_mem {
     #[doc = "< segment register (or X86_REG_INVALID if irrelevant)"]
-    pub segment: x86_reg::Type,
+    pub segment: x86_reg,
     #[doc = "< base register (or X86_REG_INVALID if irrelevant)"]
-    pub base: x86_reg::Type,
+    pub base: x86_reg,
     #[doc = "< index register (or X86_REG_INVALID if irrelevant)"]
-    pub index: x86_reg::Type,
+    pub index: x86_reg,
     #[doc = "< scale for index register"]
     pub scale: libc::c_int,
     #[doc = "< displacement value"]
     pub disp: i64,
 }
-impl Clone for x86_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_x86_op {
     #[doc = "< operand type"]
     pub type_: x86_op_type,
     pub __bindgen_anon_1: cs_x86_op__bindgen_ty_1,
     #[doc = " size of this operand (in bytes)."]
     pub size: u8,
-    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)"]
-    #[doc = " This field is combined of cs_ac_type."]
-    #[doc = " NOTE: this field is irrelevant if engine is compiled in DIET mode."]
+    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
     pub access: u8,
     #[doc = " AVX broadcast type, or 0 if irrelevant"]
     pub avx_bcast: x86_avx_bcast,
@@ -11519,37 +14446,27 @@ pub struct cs_x86_op {
     pub avx_zero_opmask: bool,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_x86_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
-    pub reg: x86_reg::Type,
+    pub reg: x86_reg,
     #[doc = "< immediate value for IMM operand"]
     pub imm: i64,
     #[doc = "< base/index/scale/disp value for MEM operand"]
     pub mem: x86_op_mem,
 }
-impl Clone for cs_x86_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_x86_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_x86_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_x86_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_x86_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . size , self . access , self . avx_bcast , self . avx_zero_opmask)
+        write ! (f , "cs_x86_op {{ type: {:?}, __bindgen_anon_1: {:?}, avx_bcast: {:?}, avx_zero_opmask: {:?} }}" , self . type_ , self . __bindgen_anon_1 , self . avx_bcast , self . avx_zero_opmask)
     }
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_x86_encoding {
     #[doc = " ModR/M offset, or 0 when irrelevant"]
     pub modrm_offset: u8,
@@ -11560,26 +14477,13 @@ pub struct cs_x86_encoding {
     pub imm_offset: u8,
     pub imm_size: u8,
 }
-impl Clone for cs_x86_encoding {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_x86 {
-    #[doc = " Instruction prefix, which can be up to 4 bytes."]
-    #[doc = " A prefix byte gets value 0 when irrelevant."]
-    #[doc = " prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)"]
-    #[doc = " prefix[1] indicates segment override (irrelevant for x86_64):"]
-    #[doc = " See X86_PREFIX_CS/SS/DS/ES/FS/GS above."]
-    #[doc = " prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)"]
-    #[doc = " prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"]
+    #[doc = " Instruction prefix, which can be up to 4 bytes.\n A prefix byte gets value 0 when irrelevant.\n prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)\n prefix[1] indicates segment override (irrelevant for x86_64):\n See X86_PREFIX_CS/SS/DS/ES/FS/GS above.\n prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)\n prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)"]
     pub prefix: [u8; 4usize],
-    #[doc = " Instruction opcode, which can be from 1 to 4 bytes in size."]
-    #[doc = " This contains VEX opcode as well."]
-    #[doc = " An trailing opcode byte gets value 0 when irrelevant."]
+    #[doc = " Instruction opcode, which can be from 1 to 4 bytes in size.\n This contains VEX opcode as well.\n An trailing opcode byte gets value 0 when irrelevant."]
     pub opcode: [u8; 4usize],
     #[doc = " REX prefix: only a non-zero value is relevant for x86_64"]
     pub rex: u8,
@@ -11592,11 +14496,11 @@ pub struct cs_x86 {
     #[doc = " Displacement value, valid if encoding.disp_offset != 0"]
     pub disp: i64,
     #[doc = " SIB index register, or X86_REG_INVALID when irrelevant."]
-    pub sib_index: x86_reg::Type,
+    pub sib_index: x86_reg,
     #[doc = " SIB scale, only applicable if sib_index is valid."]
     pub sib_scale: i8,
     #[doc = " SIB base register, or X86_REG_INVALID when irrelevant."]
-    pub sib_base: x86_reg::Type,
+    pub sib_base: x86_reg,
     #[doc = " XOP Code Condition"]
     pub xop_cc: x86_xop_cc,
     #[doc = " SSE Code Condition"]
@@ -11608,8 +14512,7 @@ pub struct cs_x86 {
     #[doc = " AVX static rounding mode"]
     pub avx_rm: x86_avx_rm,
     pub __bindgen_anon_1: cs_x86__bindgen_ty_1,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_x86_op; 8usize],
@@ -11617,33 +14520,21 @@ pub struct cs_x86 {
     pub encoding: cs_x86_encoding,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_x86__bindgen_ty_1 {
-    #[doc = " EFLAGS updated by this instruction."]
-    #[doc = " This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"]
+    #[doc = " EFLAGS updated by this instruction.\n This can be formed from OR combination of X86_EFLAGS_* symbols in x86.h"]
     pub eflags: u64,
-    #[doc = " FPU_FLAGS updated by this instruction."]
-    #[doc = " This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"]
+    #[doc = " FPU_FLAGS updated by this instruction.\n This can be formed from OR combination of X86_FPU_FLAGS_* symbols in x86.h"]
     pub fpu_flags: u64,
 }
-impl Clone for cs_x86__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_x86__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_x86__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_x86 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_x86 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, rex: {:?}, addr_size: {:?}, modrm: {:?}, sib: {:?}, disp: {:?}, sib_index: {:?}, sib_scale: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, op_count: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . rex , self . addr_size , self . modrm , self . sib , self . disp , self . sib_index , self . sib_scale , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . op_count , self . operands , self . encoding)
+        write ! (f , "cs_x86 {{ prefix: {:?}, opcode: {:?}, sib_index: {:?}, sib_base: {:?}, xop_cc: {:?}, sse_cc: {:?}, avx_cc: {:?}, avx_sae: {:?}, avx_rm: {:?}, __bindgen_anon_1: {:?}, operands: {:?}, encoding: {:?} }}" , self . prefix , self . opcode , self . sib_index , self . sib_base , self . xop_cc , self . sse_cc , self . avx_cc , self . avx_sae , self . avx_rm , self . __bindgen_anon_1 , self . operands , self . encoding)
     }
 }
 #[repr(u32)]
@@ -13176,70 +16067,172 @@ pub enum x86_insn {
     X86_INS_XTEST = 1523,
     X86_INS_ENDING = 1524,
 }
-pub mod x86_insn_group {
-    #[doc = " Group of X86 instructions"]
-    pub type Type = libc::c_uint;
+impl x86_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const X86_GRP_INVALID: Type = 0;
+    pub const X86_GRP_INVALID: x86_insn_group = x86_insn_group(0);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_JUMP"]
-    pub const X86_GRP_JUMP: Type = 1;
+    pub const X86_GRP_JUMP: x86_insn_group = x86_insn_group(1);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_CALL"]
-    pub const X86_GRP_CALL: Type = 2;
+    pub const X86_GRP_CALL: x86_insn_group = x86_insn_group(2);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_RET"]
-    pub const X86_GRP_RET: Type = 3;
+    pub const X86_GRP_RET: x86_insn_group = x86_insn_group(3);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_INT"]
-    pub const X86_GRP_INT: Type = 4;
+    pub const X86_GRP_INT: x86_insn_group = x86_insn_group(4);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_IRET"]
-    pub const X86_GRP_IRET: Type = 5;
+    pub const X86_GRP_IRET: x86_insn_group = x86_insn_group(5);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_PRIVILEGE"]
-    pub const X86_GRP_PRIVILEGE: Type = 6;
+    pub const X86_GRP_PRIVILEGE: x86_insn_group = x86_insn_group(6);
+}
+impl x86_insn_group {
     #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
-    pub const X86_GRP_BRANCH_RELATIVE: Type = 7;
+    pub const X86_GRP_BRANCH_RELATIVE: x86_insn_group = x86_insn_group(7);
+}
+impl x86_insn_group {
     #[doc = "< all virtualization instructions (VT-x + AMD-V)"]
-    pub const X86_GRP_VM: Type = 128;
-    pub const X86_GRP_3DNOW: Type = 129;
-    pub const X86_GRP_AES: Type = 130;
-    pub const X86_GRP_ADX: Type = 131;
-    pub const X86_GRP_AVX: Type = 132;
-    pub const X86_GRP_AVX2: Type = 133;
-    pub const X86_GRP_AVX512: Type = 134;
-    pub const X86_GRP_BMI: Type = 135;
-    pub const X86_GRP_BMI2: Type = 136;
-    pub const X86_GRP_CMOV: Type = 137;
-    pub const X86_GRP_F16C: Type = 138;
-    pub const X86_GRP_FMA: Type = 139;
-    pub const X86_GRP_FMA4: Type = 140;
-    pub const X86_GRP_FSGSBASE: Type = 141;
-    pub const X86_GRP_HLE: Type = 142;
-    pub const X86_GRP_MMX: Type = 143;
-    pub const X86_GRP_MODE32: Type = 144;
-    pub const X86_GRP_MODE64: Type = 145;
-    pub const X86_GRP_RTM: Type = 146;
-    pub const X86_GRP_SHA: Type = 147;
-    pub const X86_GRP_SSE1: Type = 148;
-    pub const X86_GRP_SSE2: Type = 149;
-    pub const X86_GRP_SSE3: Type = 150;
-    pub const X86_GRP_SSE41: Type = 151;
-    pub const X86_GRP_SSE42: Type = 152;
-    pub const X86_GRP_SSE4A: Type = 153;
-    pub const X86_GRP_SSSE3: Type = 154;
-    pub const X86_GRP_PCLMUL: Type = 155;
-    pub const X86_GRP_XOP: Type = 156;
-    pub const X86_GRP_CDI: Type = 157;
-    pub const X86_GRP_ERI: Type = 158;
-    pub const X86_GRP_TBM: Type = 159;
-    pub const X86_GRP_16BITMODE: Type = 160;
-    pub const X86_GRP_NOT64BITMODE: Type = 161;
-    pub const X86_GRP_SGX: Type = 162;
-    pub const X86_GRP_DQI: Type = 163;
-    pub const X86_GRP_BWI: Type = 164;
-    pub const X86_GRP_PFI: Type = 165;
-    pub const X86_GRP_VLX: Type = 166;
-    pub const X86_GRP_SMAP: Type = 167;
-    pub const X86_GRP_NOVLX: Type = 168;
-    pub const X86_GRP_FPU: Type = 169;
-    pub const X86_GRP_ENDING: Type = 170;
+    pub const X86_GRP_VM: x86_insn_group = x86_insn_group(128);
+}
+impl x86_insn_group {
+    pub const X86_GRP_3DNOW: x86_insn_group = x86_insn_group(129);
+}
+impl x86_insn_group {
+    pub const X86_GRP_AES: x86_insn_group = x86_insn_group(130);
+}
+impl x86_insn_group {
+    pub const X86_GRP_ADX: x86_insn_group = x86_insn_group(131);
+}
+impl x86_insn_group {
+    pub const X86_GRP_AVX: x86_insn_group = x86_insn_group(132);
+}
+impl x86_insn_group {
+    pub const X86_GRP_AVX2: x86_insn_group = x86_insn_group(133);
+}
+impl x86_insn_group {
+    pub const X86_GRP_AVX512: x86_insn_group = x86_insn_group(134);
+}
+impl x86_insn_group {
+    pub const X86_GRP_BMI: x86_insn_group = x86_insn_group(135);
+}
+impl x86_insn_group {
+    pub const X86_GRP_BMI2: x86_insn_group = x86_insn_group(136);
+}
+impl x86_insn_group {
+    pub const X86_GRP_CMOV: x86_insn_group = x86_insn_group(137);
+}
+impl x86_insn_group {
+    pub const X86_GRP_F16C: x86_insn_group = x86_insn_group(138);
+}
+impl x86_insn_group {
+    pub const X86_GRP_FMA: x86_insn_group = x86_insn_group(139);
+}
+impl x86_insn_group {
+    pub const X86_GRP_FMA4: x86_insn_group = x86_insn_group(140);
+}
+impl x86_insn_group {
+    pub const X86_GRP_FSGSBASE: x86_insn_group = x86_insn_group(141);
+}
+impl x86_insn_group {
+    pub const X86_GRP_HLE: x86_insn_group = x86_insn_group(142);
+}
+impl x86_insn_group {
+    pub const X86_GRP_MMX: x86_insn_group = x86_insn_group(143);
+}
+impl x86_insn_group {
+    pub const X86_GRP_MODE32: x86_insn_group = x86_insn_group(144);
+}
+impl x86_insn_group {
+    pub const X86_GRP_MODE64: x86_insn_group = x86_insn_group(145);
+}
+impl x86_insn_group {
+    pub const X86_GRP_RTM: x86_insn_group = x86_insn_group(146);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SHA: x86_insn_group = x86_insn_group(147);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SSE1: x86_insn_group = x86_insn_group(148);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SSE2: x86_insn_group = x86_insn_group(149);
 }
+impl x86_insn_group {
+    pub const X86_GRP_SSE3: x86_insn_group = x86_insn_group(150);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SSE41: x86_insn_group = x86_insn_group(151);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SSE42: x86_insn_group = x86_insn_group(152);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SSE4A: x86_insn_group = x86_insn_group(153);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SSSE3: x86_insn_group = x86_insn_group(154);
+}
+impl x86_insn_group {
+    pub const X86_GRP_PCLMUL: x86_insn_group = x86_insn_group(155);
+}
+impl x86_insn_group {
+    pub const X86_GRP_XOP: x86_insn_group = x86_insn_group(156);
+}
+impl x86_insn_group {
+    pub const X86_GRP_CDI: x86_insn_group = x86_insn_group(157);
+}
+impl x86_insn_group {
+    pub const X86_GRP_ERI: x86_insn_group = x86_insn_group(158);
+}
+impl x86_insn_group {
+    pub const X86_GRP_TBM: x86_insn_group = x86_insn_group(159);
+}
+impl x86_insn_group {
+    pub const X86_GRP_16BITMODE: x86_insn_group = x86_insn_group(160);
+}
+impl x86_insn_group {
+    pub const X86_GRP_NOT64BITMODE: x86_insn_group = x86_insn_group(161);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SGX: x86_insn_group = x86_insn_group(162);
+}
+impl x86_insn_group {
+    pub const X86_GRP_DQI: x86_insn_group = x86_insn_group(163);
+}
+impl x86_insn_group {
+    pub const X86_GRP_BWI: x86_insn_group = x86_insn_group(164);
+}
+impl x86_insn_group {
+    pub const X86_GRP_PFI: x86_insn_group = x86_insn_group(165);
+}
+impl x86_insn_group {
+    pub const X86_GRP_VLX: x86_insn_group = x86_insn_group(166);
+}
+impl x86_insn_group {
+    pub const X86_GRP_SMAP: x86_insn_group = x86_insn_group(167);
+}
+impl x86_insn_group {
+    pub const X86_GRP_NOVLX: x86_insn_group = x86_insn_group(168);
+}
+impl x86_insn_group {
+    pub const X86_GRP_FPU: x86_insn_group = x86_insn_group(169);
+}
+impl x86_insn_group {
+    pub const X86_GRP_ENDING: x86_insn_group = x86_insn_group(170);
+}
+#[repr(transparent)]
+#[doc = " Group of X86 instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct x86_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " Operand type for instruction's operands"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -13253,47 +16246,98 @@ pub enum xcore_op_type {
     #[doc = "< = CS_OP_MEM (Memory operand)."]
     XCORE_OP_MEM = 3,
 }
-pub mod xcore_reg {
-    #[doc = " XCore registers"]
-    pub type Type = libc::c_uint;
-    pub const XCORE_REG_INVALID: Type = 0;
-    pub const XCORE_REG_CP: Type = 1;
-    pub const XCORE_REG_DP: Type = 2;
-    pub const XCORE_REG_LR: Type = 3;
-    pub const XCORE_REG_SP: Type = 4;
-    pub const XCORE_REG_R0: Type = 5;
-    pub const XCORE_REG_R1: Type = 6;
-    pub const XCORE_REG_R2: Type = 7;
-    pub const XCORE_REG_R3: Type = 8;
-    pub const XCORE_REG_R4: Type = 9;
-    pub const XCORE_REG_R5: Type = 10;
-    pub const XCORE_REG_R6: Type = 11;
-    pub const XCORE_REG_R7: Type = 12;
-    pub const XCORE_REG_R8: Type = 13;
-    pub const XCORE_REG_R9: Type = 14;
-    pub const XCORE_REG_R10: Type = 15;
-    pub const XCORE_REG_R11: Type = 16;
+impl xcore_reg {
+    pub const XCORE_REG_INVALID: xcore_reg = xcore_reg(0);
+}
+impl xcore_reg {
+    pub const XCORE_REG_CP: xcore_reg = xcore_reg(1);
+}
+impl xcore_reg {
+    pub const XCORE_REG_DP: xcore_reg = xcore_reg(2);
+}
+impl xcore_reg {
+    pub const XCORE_REG_LR: xcore_reg = xcore_reg(3);
+}
+impl xcore_reg {
+    pub const XCORE_REG_SP: xcore_reg = xcore_reg(4);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R0: xcore_reg = xcore_reg(5);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R1: xcore_reg = xcore_reg(6);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R2: xcore_reg = xcore_reg(7);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R3: xcore_reg = xcore_reg(8);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R4: xcore_reg = xcore_reg(9);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R5: xcore_reg = xcore_reg(10);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R6: xcore_reg = xcore_reg(11);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R7: xcore_reg = xcore_reg(12);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R8: xcore_reg = xcore_reg(13);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R9: xcore_reg = xcore_reg(14);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R10: xcore_reg = xcore_reg(15);
+}
+impl xcore_reg {
+    pub const XCORE_REG_R11: xcore_reg = xcore_reg(16);
+}
+impl xcore_reg {
     #[doc = "< pc"]
-    pub const XCORE_REG_PC: Type = 17;
+    pub const XCORE_REG_PC: xcore_reg = xcore_reg(17);
+}
+impl xcore_reg {
     #[doc = "< save pc"]
-    pub const XCORE_REG_SCP: Type = 18;
-    pub const XCORE_REG_SSR: Type = 19;
-    pub const XCORE_REG_ET: Type = 20;
-    pub const XCORE_REG_ED: Type = 21;
-    pub const XCORE_REG_SED: Type = 22;
-    pub const XCORE_REG_KEP: Type = 23;
-    pub const XCORE_REG_KSP: Type = 24;
-    pub const XCORE_REG_ID: Type = 25;
-    pub const XCORE_REG_ENDING: Type = 26;
-}
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with XCORE_OP_MEM operand type above"]
+    pub const XCORE_REG_SCP: xcore_reg = xcore_reg(18);
+}
+impl xcore_reg {
+    pub const XCORE_REG_SSR: xcore_reg = xcore_reg(19);
+}
+impl xcore_reg {
+    pub const XCORE_REG_ET: xcore_reg = xcore_reg(20);
+}
+impl xcore_reg {
+    pub const XCORE_REG_ED: xcore_reg = xcore_reg(21);
+}
+impl xcore_reg {
+    pub const XCORE_REG_SED: xcore_reg = xcore_reg(22);
+}
+impl xcore_reg {
+    pub const XCORE_REG_KEP: xcore_reg = xcore_reg(23);
+}
+impl xcore_reg {
+    pub const XCORE_REG_KSP: xcore_reg = xcore_reg(24);
+}
+impl xcore_reg {
+    pub const XCORE_REG_ID: xcore_reg = xcore_reg(25);
+}
+impl xcore_reg {
+    pub const XCORE_REG_ENDING: xcore_reg = xcore_reg(26);
+}
+#[repr(transparent)]
+#[doc = " XCore registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct xcore_reg(pub libc::c_uint);
+#[doc = " Instruction's operand referring to memory\n This is associated with XCORE_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct xcore_op_mem {
-    #[doc = "< base register, can be safely interpreted as"]
-    #[doc = "< a value of type `xcore_reg`, but it is only"]
-    #[doc = "< one byte wide"]
+    #[doc = "< base register, can be safely interpreted as\n< a value of type `xcore_reg`, but it is only\n< one byte wide"]
     pub base: u8,
     #[doc = "< index register, same conditions apply here"]
     pub index: u8,
@@ -13302,44 +16346,29 @@ pub struct xcore_op_mem {
     #[doc = "< +1: forward, -1: backward"]
     pub direct: libc::c_int,
 }
-impl Clone for xcore_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_xcore_op {
     #[doc = "< operand type"]
     pub type_: xcore_op_type,
     pub __bindgen_anon_1: cs_xcore_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_xcore_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
-    pub reg: xcore_reg::Type,
+    pub reg: xcore_reg,
     #[doc = "< immediate value for IMM operand"]
     pub imm: i32,
     #[doc = "< base/disp value for MEM operand"]
     pub mem: xcore_op_mem,
 }
-impl Clone for cs_xcore_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_xcore_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_xcore_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_xcore_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_xcore_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -13351,26 +16380,16 @@ impl ::core::fmt::Debug for cs_xcore_op {
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_xcore {
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_xcore_op; 8usize],
 }
-impl Clone for cs_xcore {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_xcore {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write!(
-            f,
-            "cs_xcore {{ op_count: {:?}, operands: {:?} }}",
-            self.op_count, self.operands
-        )
+        write!(f, "cs_xcore {{ operands: {:?} }}", self.operands)
     }
 }
 #[repr(u32)]
@@ -13500,15 +16519,21 @@ pub enum xcore_insn {
     XCORE_INS_ZEXT = 120,
     XCORE_INS_ENDING = 121,
 }
-pub mod xcore_insn_group {
-    #[doc = " Group of XCore instructions"]
-    pub type Type = libc::c_uint;
+impl xcore_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const XCORE_GRP_INVALID: Type = 0;
+    pub const XCORE_GRP_INVALID: xcore_insn_group = xcore_insn_group(0);
+}
+impl xcore_insn_group {
     #[doc = "< = CS_GRP_JUMP"]
-    pub const XCORE_GRP_JUMP: Type = 1;
-    pub const XCORE_GRP_ENDING: Type = 2;
+    pub const XCORE_GRP_JUMP: xcore_insn_group = xcore_insn_group(1);
 }
+impl xcore_insn_group {
+    pub const XCORE_GRP_ENDING: xcore_insn_group = xcore_insn_group(2);
+}
+#[repr(transparent)]
+#[doc = " Group of XCore instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct xcore_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum tms320c64x_op_type {
@@ -13546,7 +16571,7 @@ pub enum tms320c64x_mem_mod {
     TMS320C64X_MEM_MOD_POST = 3,
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct tms320c64x_op_mem {
     #[doc = "< base register"]
     pub base: libc::c_uint,
@@ -13563,20 +16588,15 @@ pub struct tms320c64x_op_mem {
     #[doc = "< modification"]
     pub modify: libc::c_uint,
 }
-impl Clone for tms320c64x_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_tms320c64x_op {
     #[doc = "< operand type"]
     pub type_: tms320c64x_op_type,
     pub __bindgen_anon_1: cs_tms320c64x_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_tms320c64x_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand or first register for REGPAIR operand"]
     pub reg: libc::c_uint,
@@ -13585,21 +16605,11 @@ pub union cs_tms320c64x_op__bindgen_ty_1 {
     #[doc = "< base/disp value for MEM operand"]
     pub mem: tms320c64x_op_mem,
 }
-impl Clone for cs_tms320c64x_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_tms320c64x_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_tms320c64x_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_tms320c64x_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_tms320c64x_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -13610,7 +16620,7 @@ impl ::core::fmt::Debug for cs_tms320c64x_op {
     }
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_tms320c64x {
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
@@ -13620,134 +16630,309 @@ pub struct cs_tms320c64x {
     pub parallel: libc::c_uint,
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_tms320c64x__bindgen_ty_1 {
     pub reg: libc::c_uint,
     pub zero: libc::c_uint,
 }
-impl Clone for cs_tms320c64x__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_tms320c64x__bindgen_ty_2 {
     pub unit: libc::c_uint,
     pub side: libc::c_uint,
     pub crosspath: libc::c_uint,
 }
-impl Clone for cs_tms320c64x__bindgen_ty_2 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
-impl Clone for cs_tms320c64x {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_tms320c64x {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_tms320c64x {{ op_count: {:?}, operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}" , self . op_count , self . operands , self . condition , self . funit , self . parallel)
+        write!(
+            f,
+            "cs_tms320c64x {{ operands: {:?}, condition: {:?}, funit: {:?}, parallel: {:?} }}",
+            self.operands, self.condition, self.funit, self.parallel
+        )
     }
 }
-pub mod tms320c64x_reg {
-    pub type Type = libc::c_uint;
-    pub const TMS320C64X_REG_INVALID: Type = 0;
-    pub const TMS320C64X_REG_AMR: Type = 1;
-    pub const TMS320C64X_REG_CSR: Type = 2;
-    pub const TMS320C64X_REG_DIER: Type = 3;
-    pub const TMS320C64X_REG_DNUM: Type = 4;
-    pub const TMS320C64X_REG_ECR: Type = 5;
-    pub const TMS320C64X_REG_GFPGFR: Type = 6;
-    pub const TMS320C64X_REG_GPLYA: Type = 7;
-    pub const TMS320C64X_REG_GPLYB: Type = 8;
-    pub const TMS320C64X_REG_ICR: Type = 9;
-    pub const TMS320C64X_REG_IER: Type = 10;
-    pub const TMS320C64X_REG_IERR: Type = 11;
-    pub const TMS320C64X_REG_ILC: Type = 12;
-    pub const TMS320C64X_REG_IRP: Type = 13;
-    pub const TMS320C64X_REG_ISR: Type = 14;
-    pub const TMS320C64X_REG_ISTP: Type = 15;
-    pub const TMS320C64X_REG_ITSR: Type = 16;
-    pub const TMS320C64X_REG_NRP: Type = 17;
-    pub const TMS320C64X_REG_NTSR: Type = 18;
-    pub const TMS320C64X_REG_REP: Type = 19;
-    pub const TMS320C64X_REG_RILC: Type = 20;
-    pub const TMS320C64X_REG_SSR: Type = 21;
-    pub const TMS320C64X_REG_TSCH: Type = 22;
-    pub const TMS320C64X_REG_TSCL: Type = 23;
-    pub const TMS320C64X_REG_TSR: Type = 24;
-    pub const TMS320C64X_REG_A0: Type = 25;
-    pub const TMS320C64X_REG_A1: Type = 26;
-    pub const TMS320C64X_REG_A2: Type = 27;
-    pub const TMS320C64X_REG_A3: Type = 28;
-    pub const TMS320C64X_REG_A4: Type = 29;
-    pub const TMS320C64X_REG_A5: Type = 30;
-    pub const TMS320C64X_REG_A6: Type = 31;
-    pub const TMS320C64X_REG_A7: Type = 32;
-    pub const TMS320C64X_REG_A8: Type = 33;
-    pub const TMS320C64X_REG_A9: Type = 34;
-    pub const TMS320C64X_REG_A10: Type = 35;
-    pub const TMS320C64X_REG_A11: Type = 36;
-    pub const TMS320C64X_REG_A12: Type = 37;
-    pub const TMS320C64X_REG_A13: Type = 38;
-    pub const TMS320C64X_REG_A14: Type = 39;
-    pub const TMS320C64X_REG_A15: Type = 40;
-    pub const TMS320C64X_REG_A16: Type = 41;
-    pub const TMS320C64X_REG_A17: Type = 42;
-    pub const TMS320C64X_REG_A18: Type = 43;
-    pub const TMS320C64X_REG_A19: Type = 44;
-    pub const TMS320C64X_REG_A20: Type = 45;
-    pub const TMS320C64X_REG_A21: Type = 46;
-    pub const TMS320C64X_REG_A22: Type = 47;
-    pub const TMS320C64X_REG_A23: Type = 48;
-    pub const TMS320C64X_REG_A24: Type = 49;
-    pub const TMS320C64X_REG_A25: Type = 50;
-    pub const TMS320C64X_REG_A26: Type = 51;
-    pub const TMS320C64X_REG_A27: Type = 52;
-    pub const TMS320C64X_REG_A28: Type = 53;
-    pub const TMS320C64X_REG_A29: Type = 54;
-    pub const TMS320C64X_REG_A30: Type = 55;
-    pub const TMS320C64X_REG_A31: Type = 56;
-    pub const TMS320C64X_REG_B0: Type = 57;
-    pub const TMS320C64X_REG_B1: Type = 58;
-    pub const TMS320C64X_REG_B2: Type = 59;
-    pub const TMS320C64X_REG_B3: Type = 60;
-    pub const TMS320C64X_REG_B4: Type = 61;
-    pub const TMS320C64X_REG_B5: Type = 62;
-    pub const TMS320C64X_REG_B6: Type = 63;
-    pub const TMS320C64X_REG_B7: Type = 64;
-    pub const TMS320C64X_REG_B8: Type = 65;
-    pub const TMS320C64X_REG_B9: Type = 66;
-    pub const TMS320C64X_REG_B10: Type = 67;
-    pub const TMS320C64X_REG_B11: Type = 68;
-    pub const TMS320C64X_REG_B12: Type = 69;
-    pub const TMS320C64X_REG_B13: Type = 70;
-    pub const TMS320C64X_REG_B14: Type = 71;
-    pub const TMS320C64X_REG_B15: Type = 72;
-    pub const TMS320C64X_REG_B16: Type = 73;
-    pub const TMS320C64X_REG_B17: Type = 74;
-    pub const TMS320C64X_REG_B18: Type = 75;
-    pub const TMS320C64X_REG_B19: Type = 76;
-    pub const TMS320C64X_REG_B20: Type = 77;
-    pub const TMS320C64X_REG_B21: Type = 78;
-    pub const TMS320C64X_REG_B22: Type = 79;
-    pub const TMS320C64X_REG_B23: Type = 80;
-    pub const TMS320C64X_REG_B24: Type = 81;
-    pub const TMS320C64X_REG_B25: Type = 82;
-    pub const TMS320C64X_REG_B26: Type = 83;
-    pub const TMS320C64X_REG_B27: Type = 84;
-    pub const TMS320C64X_REG_B28: Type = 85;
-    pub const TMS320C64X_REG_B29: Type = 86;
-    pub const TMS320C64X_REG_B30: Type = 87;
-    pub const TMS320C64X_REG_B31: Type = 88;
-    pub const TMS320C64X_REG_PCE1: Type = 89;
-    pub const TMS320C64X_REG_ENDING: Type = 90;
-    pub const TMS320C64X_REG_EFR: Type = 5;
-    pub const TMS320C64X_REG_IFR: Type = 14;
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_INVALID: tms320c64x_reg = tms320c64x_reg(0);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_AMR: tms320c64x_reg = tms320c64x_reg(1);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_CSR: tms320c64x_reg = tms320c64x_reg(2);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_DIER: tms320c64x_reg = tms320c64x_reg(3);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_DNUM: tms320c64x_reg = tms320c64x_reg(4);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ECR: tms320c64x_reg = tms320c64x_reg(5);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_GFPGFR: tms320c64x_reg = tms320c64x_reg(6);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_GPLYA: tms320c64x_reg = tms320c64x_reg(7);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_GPLYB: tms320c64x_reg = tms320c64x_reg(8);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ICR: tms320c64x_reg = tms320c64x_reg(9);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_IER: tms320c64x_reg = tms320c64x_reg(10);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_IERR: tms320c64x_reg = tms320c64x_reg(11);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ILC: tms320c64x_reg = tms320c64x_reg(12);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_IRP: tms320c64x_reg = tms320c64x_reg(13);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ISR: tms320c64x_reg = tms320c64x_reg(14);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ISTP: tms320c64x_reg = tms320c64x_reg(15);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ITSR: tms320c64x_reg = tms320c64x_reg(16);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_NRP: tms320c64x_reg = tms320c64x_reg(17);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_NTSR: tms320c64x_reg = tms320c64x_reg(18);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_REP: tms320c64x_reg = tms320c64x_reg(19);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_RILC: tms320c64x_reg = tms320c64x_reg(20);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_SSR: tms320c64x_reg = tms320c64x_reg(21);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_TSCH: tms320c64x_reg = tms320c64x_reg(22);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_TSCL: tms320c64x_reg = tms320c64x_reg(23);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_TSR: tms320c64x_reg = tms320c64x_reg(24);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A0: tms320c64x_reg = tms320c64x_reg(25);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A1: tms320c64x_reg = tms320c64x_reg(26);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A2: tms320c64x_reg = tms320c64x_reg(27);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A3: tms320c64x_reg = tms320c64x_reg(28);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A4: tms320c64x_reg = tms320c64x_reg(29);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A5: tms320c64x_reg = tms320c64x_reg(30);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A6: tms320c64x_reg = tms320c64x_reg(31);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A7: tms320c64x_reg = tms320c64x_reg(32);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A8: tms320c64x_reg = tms320c64x_reg(33);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A9: tms320c64x_reg = tms320c64x_reg(34);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A10: tms320c64x_reg = tms320c64x_reg(35);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A11: tms320c64x_reg = tms320c64x_reg(36);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A12: tms320c64x_reg = tms320c64x_reg(37);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A13: tms320c64x_reg = tms320c64x_reg(38);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A14: tms320c64x_reg = tms320c64x_reg(39);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A15: tms320c64x_reg = tms320c64x_reg(40);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A16: tms320c64x_reg = tms320c64x_reg(41);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A17: tms320c64x_reg = tms320c64x_reg(42);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A18: tms320c64x_reg = tms320c64x_reg(43);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A19: tms320c64x_reg = tms320c64x_reg(44);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A20: tms320c64x_reg = tms320c64x_reg(45);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A21: tms320c64x_reg = tms320c64x_reg(46);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A22: tms320c64x_reg = tms320c64x_reg(47);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A23: tms320c64x_reg = tms320c64x_reg(48);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A24: tms320c64x_reg = tms320c64x_reg(49);
 }
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A25: tms320c64x_reg = tms320c64x_reg(50);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A26: tms320c64x_reg = tms320c64x_reg(51);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A27: tms320c64x_reg = tms320c64x_reg(52);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A28: tms320c64x_reg = tms320c64x_reg(53);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A29: tms320c64x_reg = tms320c64x_reg(54);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A30: tms320c64x_reg = tms320c64x_reg(55);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_A31: tms320c64x_reg = tms320c64x_reg(56);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B0: tms320c64x_reg = tms320c64x_reg(57);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B1: tms320c64x_reg = tms320c64x_reg(58);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B2: tms320c64x_reg = tms320c64x_reg(59);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B3: tms320c64x_reg = tms320c64x_reg(60);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B4: tms320c64x_reg = tms320c64x_reg(61);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B5: tms320c64x_reg = tms320c64x_reg(62);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B6: tms320c64x_reg = tms320c64x_reg(63);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B7: tms320c64x_reg = tms320c64x_reg(64);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B8: tms320c64x_reg = tms320c64x_reg(65);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B9: tms320c64x_reg = tms320c64x_reg(66);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B10: tms320c64x_reg = tms320c64x_reg(67);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B11: tms320c64x_reg = tms320c64x_reg(68);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B12: tms320c64x_reg = tms320c64x_reg(69);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B13: tms320c64x_reg = tms320c64x_reg(70);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B14: tms320c64x_reg = tms320c64x_reg(71);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B15: tms320c64x_reg = tms320c64x_reg(72);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B16: tms320c64x_reg = tms320c64x_reg(73);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B17: tms320c64x_reg = tms320c64x_reg(74);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B18: tms320c64x_reg = tms320c64x_reg(75);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B19: tms320c64x_reg = tms320c64x_reg(76);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B20: tms320c64x_reg = tms320c64x_reg(77);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B21: tms320c64x_reg = tms320c64x_reg(78);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B22: tms320c64x_reg = tms320c64x_reg(79);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B23: tms320c64x_reg = tms320c64x_reg(80);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B24: tms320c64x_reg = tms320c64x_reg(81);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B25: tms320c64x_reg = tms320c64x_reg(82);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B26: tms320c64x_reg = tms320c64x_reg(83);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B27: tms320c64x_reg = tms320c64x_reg(84);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B28: tms320c64x_reg = tms320c64x_reg(85);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B29: tms320c64x_reg = tms320c64x_reg(86);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B30: tms320c64x_reg = tms320c64x_reg(87);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_B31: tms320c64x_reg = tms320c64x_reg(88);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_PCE1: tms320c64x_reg = tms320c64x_reg(89);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_ENDING: tms320c64x_reg = tms320c64x_reg(90);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_EFR: tms320c64x_reg = tms320c64x_reg(5);
+}
+impl tms320c64x_reg {
+    pub const TMS320C64X_REG_IFR: tms320c64x_reg = tms320c64x_reg(14);
+}
+#[repr(transparent)]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct tms320c64x_reg(pub libc::c_uint);
 #[repr(u32)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum tms320c64x_insn {
@@ -13898,19 +17083,35 @@ pub enum tms320c64x_insn {
     TMS320C64X_INS_ZERO = 144,
     TMS320C64X_INS_ENDING = 145,
 }
-pub mod tms320c64x_insn_group {
-    pub type Type = libc::c_uint;
+impl tms320c64x_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const TMS320C64X_GRP_INVALID: Type = 0;
+    pub const TMS320C64X_GRP_INVALID: tms320c64x_insn_group = tms320c64x_insn_group(0);
+}
+impl tms320c64x_insn_group {
     #[doc = "< = CS_GRP_JUMP"]
-    pub const TMS320C64X_GRP_JUMP: Type = 1;
-    pub const TMS320C64X_GRP_FUNIT_D: Type = 128;
-    pub const TMS320C64X_GRP_FUNIT_L: Type = 129;
-    pub const TMS320C64X_GRP_FUNIT_M: Type = 130;
-    pub const TMS320C64X_GRP_FUNIT_S: Type = 131;
-    pub const TMS320C64X_GRP_FUNIT_NO: Type = 132;
-    pub const TMS320C64X_GRP_ENDING: Type = 133;
+    pub const TMS320C64X_GRP_JUMP: tms320c64x_insn_group = tms320c64x_insn_group(1);
+}
+impl tms320c64x_insn_group {
+    pub const TMS320C64X_GRP_FUNIT_D: tms320c64x_insn_group = tms320c64x_insn_group(128);
+}
+impl tms320c64x_insn_group {
+    pub const TMS320C64X_GRP_FUNIT_L: tms320c64x_insn_group = tms320c64x_insn_group(129);
+}
+impl tms320c64x_insn_group {
+    pub const TMS320C64X_GRP_FUNIT_M: tms320c64x_insn_group = tms320c64x_insn_group(130);
 }
+impl tms320c64x_insn_group {
+    pub const TMS320C64X_GRP_FUNIT_S: tms320c64x_insn_group = tms320c64x_insn_group(131);
+}
+impl tms320c64x_insn_group {
+    pub const TMS320C64X_GRP_FUNIT_NO: tms320c64x_insn_group = tms320c64x_insn_group(132);
+}
+impl tms320c64x_insn_group {
+    pub const TMS320C64X_GRP_ENDING: tms320c64x_insn_group = tms320c64x_insn_group(133);
+}
+#[repr(transparent)]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct tms320c64x_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum tms320c64x_funit {
@@ -13921,55 +17122,101 @@ pub enum tms320c64x_funit {
     TMS320C64X_FUNIT_S = 4,
     TMS320C64X_FUNIT_NO = 5,
 }
-pub mod m680x_reg {
-    #[doc = " M680X registers and special registers"]
-    pub type Type = libc::c_uint;
-    pub const M680X_REG_INVALID: Type = 0;
+impl m680x_reg {
+    pub const M680X_REG_INVALID: m680x_reg = m680x_reg(0);
+}
+impl m680x_reg {
     #[doc = "< M6800/1/2/3/9, HD6301/9"]
-    pub const M680X_REG_A: Type = 1;
+    pub const M680X_REG_A: m680x_reg = m680x_reg(1);
+}
+impl m680x_reg {
     #[doc = "< M6800/1/2/3/9, HD6301/9"]
-    pub const M680X_REG_B: Type = 2;
+    pub const M680X_REG_B: m680x_reg = m680x_reg(2);
+}
+impl m680x_reg {
     #[doc = "< HD6309"]
-    pub const M680X_REG_E: Type = 3;
+    pub const M680X_REG_E: m680x_reg = m680x_reg(3);
+}
+impl m680x_reg {
     #[doc = "< HD6309"]
-    pub const M680X_REG_F: Type = 4;
+    pub const M680X_REG_F: m680x_reg = m680x_reg(4);
+}
+impl m680x_reg {
     #[doc = "< HD6309"]
-    pub const M680X_REG_0: Type = 5;
+    pub const M680X_REG_0: m680x_reg = m680x_reg(5);
+}
+impl m680x_reg {
     #[doc = "< M6801/3/9, HD6301/9"]
-    pub const M680X_REG_D: Type = 6;
+    pub const M680X_REG_D: m680x_reg = m680x_reg(6);
+}
+impl m680x_reg {
     #[doc = "< HD6309"]
-    pub const M680X_REG_W: Type = 7;
+    pub const M680X_REG_W: m680x_reg = m680x_reg(7);
+}
+impl m680x_reg {
     #[doc = "< M6800/1/2/3/9, M6301/9"]
-    pub const M680X_REG_CC: Type = 8;
+    pub const M680X_REG_CC: m680x_reg = m680x_reg(8);
+}
+impl m680x_reg {
     #[doc = "< M6809/M6309"]
-    pub const M680X_REG_DP: Type = 9;
+    pub const M680X_REG_DP: m680x_reg = m680x_reg(9);
+}
+impl m680x_reg {
     #[doc = "< M6309"]
-    pub const M680X_REG_MD: Type = 10;
+    pub const M680X_REG_MD: m680x_reg = m680x_reg(10);
+}
+impl m680x_reg {
     #[doc = "< M6808"]
-    pub const M680X_REG_HX: Type = 11;
+    pub const M680X_REG_HX: m680x_reg = m680x_reg(11);
+}
+impl m680x_reg {
     #[doc = "< M6808"]
-    pub const M680X_REG_H: Type = 12;
+    pub const M680X_REG_H: m680x_reg = m680x_reg(12);
+}
+impl m680x_reg {
     #[doc = "< M6800/1/2/3/9, M6301/9"]
-    pub const M680X_REG_X: Type = 13;
+    pub const M680X_REG_X: m680x_reg = m680x_reg(13);
+}
+impl m680x_reg {
     #[doc = "< M6809/M6309"]
-    pub const M680X_REG_Y: Type = 14;
+    pub const M680X_REG_Y: m680x_reg = m680x_reg(14);
+}
+impl m680x_reg {
     #[doc = "< M6809/M6309"]
-    pub const M680X_REG_S: Type = 15;
+    pub const M680X_REG_S: m680x_reg = m680x_reg(15);
+}
+impl m680x_reg {
     #[doc = "< M6809/M6309"]
-    pub const M680X_REG_U: Type = 16;
+    pub const M680X_REG_U: m680x_reg = m680x_reg(16);
+}
+impl m680x_reg {
     #[doc = "< M6309"]
-    pub const M680X_REG_V: Type = 17;
+    pub const M680X_REG_V: m680x_reg = m680x_reg(17);
+}
+impl m680x_reg {
     #[doc = "< M6309"]
-    pub const M680X_REG_Q: Type = 18;
+    pub const M680X_REG_Q: m680x_reg = m680x_reg(18);
+}
+impl m680x_reg {
     #[doc = "< M6800/1/2/3/9, M6301/9"]
-    pub const M680X_REG_PC: Type = 19;
+    pub const M680X_REG_PC: m680x_reg = m680x_reg(19);
+}
+impl m680x_reg {
     #[doc = "< CPU12"]
-    pub const M680X_REG_TMP2: Type = 20;
+    pub const M680X_REG_TMP2: m680x_reg = m680x_reg(20);
+}
+impl m680x_reg {
     #[doc = "< CPU12"]
-    pub const M680X_REG_TMP3: Type = 21;
+    pub const M680X_REG_TMP3: m680x_reg = m680x_reg(21);
+}
+impl m680x_reg {
     #[doc = "< <-- mark the end of the list of registers"]
-    pub const M680X_REG_ENDING: Type = 22;
+    pub const M680X_REG_ENDING: m680x_reg = m680x_reg(22);
 }
+#[repr(transparent)]
+#[doc = " M680X registers and special registers"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct m680x_reg(pub libc::c_uint);
 #[repr(u32)]
 #[doc = " Operand type for instruction's operands"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -13988,92 +17235,64 @@ pub enum m680x_op_type {
     M680X_OP_DIRECT = 5,
     #[doc = "< = Relative addressing operand."]
     M680X_OP_RELATIVE = 6,
-    #[doc = "< = constant operand (Displayed as number only)."]
-    #[doc = "< Used e.g. for a bit index or page number."]
+    #[doc = "< = constant operand (Displayed as number only).\n< Used e.g. for a bit index or page number."]
     M680X_OP_CONSTANT = 7,
 }
 #[doc = " Instruction's operand referring to indexed addressing"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct m680x_op_idx {
-    #[doc = "< base register (or M680X_REG_INVALID if"]
-    #[doc = "< irrelevant)"]
-    pub base_reg: m680x_reg::Type,
-    #[doc = "< offset register (or M680X_REG_INVALID if"]
-    #[doc = "< irrelevant)"]
-    pub offset_reg: m680x_reg::Type,
+    #[doc = "< base register (or M680X_REG_INVALID if\n< irrelevant)"]
+    pub base_reg: m680x_reg,
+    #[doc = "< offset register (or M680X_REG_INVALID if\n< irrelevant)"]
+    pub offset_reg: m680x_reg,
     #[doc = "< 5-,8- or 16-bit offset. See also offset_bits."]
     pub offset: i16,
-    #[doc = "< = offset addr. if base_reg == M680X_REG_PC."]
-    #[doc = "< calculated as offset + PC"]
+    #[doc = "< = offset addr. if base_reg == M680X_REG_PC.\n< calculated as offset + PC"]
     pub offset_addr: u16,
     #[doc = "< offset width in bits for indexed addressing"]
     pub offset_bits: u8,
-    #[doc = "< inc. or dec. value:"]
-    #[doc = "<    0: no inc-/decrement"]
-    #[doc = "<    1 .. 8: increment by 1 .. 8"]
-    #[doc = "<    -1 .. -8: decrement by 1 .. 8"]
-    #[doc = "< if flag M680X_IDX_POST_INC_DEC set it is post"]
-    #[doc = "< inc-/decrement otherwise pre inc-/decrement"]
+    #[doc = "< inc. or dec. value:\n<    0: no inc-/decrement\n<    1 .. 8: increment by 1 .. 8\n<    -1 .. -8: decrement by 1 .. 8\n< if flag M680X_IDX_POST_INC_DEC set it is post\n< inc-/decrement otherwise pre inc-/decrement"]
     pub inc_dec: i8,
     #[doc = "< 8-bit flags (see above)"]
     pub flags: u8,
 }
-impl Clone for m680x_op_idx {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction's memory operand referring to relative addressing (Bcc/LBcc)"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct m680x_op_rel {
-    #[doc = "< The absolute address."]
-    #[doc = "< calculated as PC + offset. PC is the first"]
-    #[doc = "< address after the instruction."]
+    #[doc = "< The absolute address.\n< calculated as PC + offset. PC is the first\n< address after the instruction."]
     pub address: u16,
     #[doc = "< the offset/displacement value"]
     pub offset: i16,
 }
-impl Clone for m680x_op_rel {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction's operand referring to extended addressing"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct m680x_op_ext {
     #[doc = "< The absolute address"]
     pub address: u16,
     #[doc = "< true if extended indirect addressing"]
     pub indirect: bool,
 }
-impl Clone for m680x_op_ext {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_m680x_op {
     pub type_: m680x_op_type,
     pub __bindgen_anon_1: cs_m680x_op__bindgen_ty_1,
     #[doc = "< size of this operand (in bytes)"]
     pub size: u8,
-    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)"]
-    #[doc = " This field is combined of cs_ac_type."]
-    #[doc = " NOTE: this field is irrelevant if engine is compiled in DIET"]
+    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET"]
     pub access: u8,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_m680x_op__bindgen_ty_1 {
     #[doc = "< immediate value for IMM operand"]
     pub imm: i32,
     #[doc = "< register value for REG operand"]
-    pub reg: m680x_reg::Type,
+    pub reg: m680x_reg,
     #[doc = "< Indexed addressing operand"]
     pub idx: m680x_op_idx,
     #[doc = "< Relative address. operand (Bcc/LBcc)"]
@@ -14085,54 +17304,61 @@ pub union cs_m680x_op__bindgen_ty_1 {
     #[doc = "< constant value (bit index, page nr.)"]
     pub const_val: u8,
 }
-impl Clone for cs_m680x_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_m680x_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_m680x_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_m680x_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_m680x_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?}, size: {:?}, access: {:?} }}",
-            self.type_, self.__bindgen_anon_1, self.size, self.access
+            "cs_m680x_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
+            self.type_, self.__bindgen_anon_1
         )
     }
 }
-#[repr(u32)]
-#[doc = " Group of M680X instructions"]
-#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
-pub enum m680x_group_type {
-    M680X_GRP_INVALID = 0,
+impl m680x_group_type {
+    pub const M680X_GRP_INVALID: m680x_group_type = m680x_group_type(0);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_JUMP"]
-    M680X_GRP_JUMP = 1,
+    pub const M680X_GRP_JUMP: m680x_group_type = m680x_group_type(1);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_CALL"]
-    M680X_GRP_CALL = 2,
+    pub const M680X_GRP_CALL: m680x_group_type = m680x_group_type(2);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_RET"]
-    M680X_GRP_RET = 3,
+    pub const M680X_GRP_RET: m680x_group_type = m680x_group_type(3);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_INT"]
-    M680X_GRP_INT = 4,
+    pub const M680X_GRP_INT: m680x_group_type = m680x_group_type(4);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_IRET"]
-    M680X_GRP_IRET = 5,
+    pub const M680X_GRP_IRET: m680x_group_type = m680x_group_type(5);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_PRIVILEDGE; not used"]
-    M680X_GRP_PRIV = 6,
+    pub const M680X_GRP_PRIV: m680x_group_type = m680x_group_type(6);
+}
+impl m680x_group_type {
     #[doc = "< = CS_GRP_BRANCH_RELATIVE"]
-    M680X_GRP_BRAREL = 7,
-    M680X_GRP_ENDING = 8,
+    pub const M680X_GRP_BRAREL: m680x_group_type = m680x_group_type(7);
 }
+impl m680x_group_type {
+    pub const M680X_GRP_ENDING: m680x_group_type = m680x_group_type(8);
+}
+#[repr(transparent)]
+#[doc = " Group of M680X instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct m680x_group_type(pub libc::c_uint);
 #[doc = " The M680X instruction and it's operands"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_m680x {
     #[doc = "< See: M680X instruction flags"]
     pub flags: u8,
@@ -14141,18 +17367,9 @@ pub struct cs_m680x {
     #[doc = "< operands for this insn."]
     pub operands: [cs_m680x_op; 9usize],
 }
-impl Clone for cs_m680x {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_m680x {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write!(
-            f,
-            "cs_m680x {{ flags: {:?}, op_count: {:?}, operands: {:?} }}",
-            self.flags, self.op_count, self.operands
-        )
+        write!(f, "cs_m680x {{ operands: {:?} }}", self.operands)
     }
 }
 #[repr(u32)]
@@ -14557,7 +17774,7 @@ pub enum m680x_insn {
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_evm {
     #[doc = "< number of items popped from the stack"]
     pub pop: libc::c_uchar,
@@ -14566,11 +17783,6 @@ pub struct cs_evm {
     #[doc = "< gas fee for the instruction"]
     pub fee: libc::c_uint,
 }
-impl Clone for cs_evm {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(u32)]
 #[doc = " EVM instruction"]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
@@ -14713,32 +17925,54 @@ pub enum evm_insn {
     EVM_INS_INVALID = 512,
     EVM_INS_ENDING = 513,
 }
-pub mod evm_insn_group {
-    #[doc = " Group of EVM instructions"]
-    pub type Type = libc::c_uint;
+impl evm_insn_group {
     #[doc = "< = CS_GRP_INVALID"]
-    pub const EVM_GRP_INVALID: Type = 0;
+    pub const EVM_GRP_INVALID: evm_insn_group = evm_insn_group(0);
+}
+impl evm_insn_group {
     #[doc = "< all jump instructions"]
-    pub const EVM_GRP_JUMP: Type = 1;
+    pub const EVM_GRP_JUMP: evm_insn_group = evm_insn_group(1);
+}
+impl evm_insn_group {
     #[doc = "< math instructions"]
-    pub const EVM_GRP_MATH: Type = 8;
+    pub const EVM_GRP_MATH: evm_insn_group = evm_insn_group(8);
+}
+impl evm_insn_group {
     #[doc = "< instructions write to stack"]
-    pub const EVM_GRP_STACK_WRITE: Type = 9;
+    pub const EVM_GRP_STACK_WRITE: evm_insn_group = evm_insn_group(9);
+}
+impl evm_insn_group {
     #[doc = "< instructions read from stack"]
-    pub const EVM_GRP_STACK_READ: Type = 10;
+    pub const EVM_GRP_STACK_READ: evm_insn_group = evm_insn_group(10);
+}
+impl evm_insn_group {
     #[doc = "< instructions write to memory"]
-    pub const EVM_GRP_MEM_WRITE: Type = 11;
+    pub const EVM_GRP_MEM_WRITE: evm_insn_group = evm_insn_group(11);
+}
+impl evm_insn_group {
     #[doc = "< instructions read from memory"]
-    pub const EVM_GRP_MEM_READ: Type = 12;
+    pub const EVM_GRP_MEM_READ: evm_insn_group = evm_insn_group(12);
+}
+impl evm_insn_group {
     #[doc = "< instructions write to storage"]
-    pub const EVM_GRP_STORE_WRITE: Type = 13;
+    pub const EVM_GRP_STORE_WRITE: evm_insn_group = evm_insn_group(13);
+}
+impl evm_insn_group {
     #[doc = "< instructions read from storage"]
-    pub const EVM_GRP_STORE_READ: Type = 14;
+    pub const EVM_GRP_STORE_READ: evm_insn_group = evm_insn_group(14);
+}
+impl evm_insn_group {
     #[doc = "< instructions halt execution"]
-    pub const EVM_GRP_HALT: Type = 15;
+    pub const EVM_GRP_HALT: evm_insn_group = evm_insn_group(15);
+}
+impl evm_insn_group {
     #[doc = "< <-- mark the end of the list of groups"]
-    pub const EVM_GRP_ENDING: Type = 16;
+    pub const EVM_GRP_ENDING: evm_insn_group = evm_insn_group(16);
 }
+#[repr(transparent)]
+#[doc = " Group of EVM instructions"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct evm_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum riscv_op_type {
@@ -14748,44 +17982,29 @@ pub enum riscv_op_type {
     RISCV_OP_MEM = 3,
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct riscv_op_mem {
     pub base: libc::c_uint,
     pub disp: i64,
 }
-impl Clone for riscv_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_riscv_op {
     pub type_: riscv_op_type,
     pub __bindgen_anon_1: cs_riscv_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_riscv_op__bindgen_ty_1 {
     pub reg: libc::c_uint,
     pub imm: i64,
     pub mem: riscv_op_mem,
 }
-impl Clone for cs_riscv_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_riscv_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_riscv_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_riscv_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_riscv_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -14796,160 +18015,417 @@ impl ::core::fmt::Debug for cs_riscv_op {
     }
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_riscv {
     pub need_effective_addr: bool,
     pub op_count: u8,
     pub operands: [cs_riscv_op; 8usize],
 }
-impl Clone for cs_riscv {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_riscv {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_riscv {{ need_effective_addr: {:?}, op_count: {:?}, operands: {:?} }}",
-            self.need_effective_addr, self.op_count, self.operands
+            "cs_riscv {{ need_effective_addr: {:?}, operands: {:?} }}",
+            self.need_effective_addr, self.operands
         )
     }
 }
-pub mod riscv_reg {
-    pub type Type = libc::c_uint;
-    pub const RISCV_REG_INVALID: Type = 0;
-    pub const RISCV_REG_X0: Type = 1;
-    pub const RISCV_REG_ZERO: Type = 1;
-    pub const RISCV_REG_X1: Type = 2;
-    pub const RISCV_REG_RA: Type = 2;
-    pub const RISCV_REG_X2: Type = 3;
-    pub const RISCV_REG_SP: Type = 3;
-    pub const RISCV_REG_X3: Type = 4;
-    pub const RISCV_REG_GP: Type = 4;
-    pub const RISCV_REG_X4: Type = 5;
-    pub const RISCV_REG_TP: Type = 5;
-    pub const RISCV_REG_X5: Type = 6;
-    pub const RISCV_REG_T0: Type = 6;
-    pub const RISCV_REG_X6: Type = 7;
-    pub const RISCV_REG_T1: Type = 7;
-    pub const RISCV_REG_X7: Type = 8;
-    pub const RISCV_REG_T2: Type = 8;
-    pub const RISCV_REG_X8: Type = 9;
-    pub const RISCV_REG_S0: Type = 9;
-    pub const RISCV_REG_FP: Type = 9;
-    pub const RISCV_REG_X9: Type = 10;
-    pub const RISCV_REG_S1: Type = 10;
-    pub const RISCV_REG_X10: Type = 11;
-    pub const RISCV_REG_A0: Type = 11;
-    pub const RISCV_REG_X11: Type = 12;
-    pub const RISCV_REG_A1: Type = 12;
-    pub const RISCV_REG_X12: Type = 13;
-    pub const RISCV_REG_A2: Type = 13;
-    pub const RISCV_REG_X13: Type = 14;
-    pub const RISCV_REG_A3: Type = 14;
-    pub const RISCV_REG_X14: Type = 15;
-    pub const RISCV_REG_A4: Type = 15;
-    pub const RISCV_REG_X15: Type = 16;
-    pub const RISCV_REG_A5: Type = 16;
-    pub const RISCV_REG_X16: Type = 17;
-    pub const RISCV_REG_A6: Type = 17;
-    pub const RISCV_REG_X17: Type = 18;
-    pub const RISCV_REG_A7: Type = 18;
-    pub const RISCV_REG_X18: Type = 19;
-    pub const RISCV_REG_S2: Type = 19;
-    pub const RISCV_REG_X19: Type = 20;
-    pub const RISCV_REG_S3: Type = 20;
-    pub const RISCV_REG_X20: Type = 21;
-    pub const RISCV_REG_S4: Type = 21;
-    pub const RISCV_REG_X21: Type = 22;
-    pub const RISCV_REG_S5: Type = 22;
-    pub const RISCV_REG_X22: Type = 23;
-    pub const RISCV_REG_S6: Type = 23;
-    pub const RISCV_REG_X23: Type = 24;
-    pub const RISCV_REG_S7: Type = 24;
-    pub const RISCV_REG_X24: Type = 25;
-    pub const RISCV_REG_S8: Type = 25;
-    pub const RISCV_REG_X25: Type = 26;
-    pub const RISCV_REG_S9: Type = 26;
-    pub const RISCV_REG_X26: Type = 27;
-    pub const RISCV_REG_S10: Type = 27;
-    pub const RISCV_REG_X27: Type = 28;
-    pub const RISCV_REG_S11: Type = 28;
-    pub const RISCV_REG_X28: Type = 29;
-    pub const RISCV_REG_T3: Type = 29;
-    pub const RISCV_REG_X29: Type = 30;
-    pub const RISCV_REG_T4: Type = 30;
-    pub const RISCV_REG_X30: Type = 31;
-    pub const RISCV_REG_T5: Type = 31;
-    pub const RISCV_REG_X31: Type = 32;
-    pub const RISCV_REG_T6: Type = 32;
-    pub const RISCV_REG_F0_32: Type = 33;
-    pub const RISCV_REG_F0_64: Type = 34;
-    pub const RISCV_REG_F1_32: Type = 35;
-    pub const RISCV_REG_F1_64: Type = 36;
-    pub const RISCV_REG_F2_32: Type = 37;
-    pub const RISCV_REG_F2_64: Type = 38;
-    pub const RISCV_REG_F3_32: Type = 39;
-    pub const RISCV_REG_F3_64: Type = 40;
-    pub const RISCV_REG_F4_32: Type = 41;
-    pub const RISCV_REG_F4_64: Type = 42;
-    pub const RISCV_REG_F5_32: Type = 43;
-    pub const RISCV_REG_F5_64: Type = 44;
-    pub const RISCV_REG_F6_32: Type = 45;
-    pub const RISCV_REG_F6_64: Type = 46;
-    pub const RISCV_REG_F7_32: Type = 47;
-    pub const RISCV_REG_F7_64: Type = 48;
-    pub const RISCV_REG_F8_32: Type = 49;
-    pub const RISCV_REG_F8_64: Type = 50;
-    pub const RISCV_REG_F9_32: Type = 51;
-    pub const RISCV_REG_F9_64: Type = 52;
-    pub const RISCV_REG_F10_32: Type = 53;
-    pub const RISCV_REG_F10_64: Type = 54;
-    pub const RISCV_REG_F11_32: Type = 55;
-    pub const RISCV_REG_F11_64: Type = 56;
-    pub const RISCV_REG_F12_32: Type = 57;
-    pub const RISCV_REG_F12_64: Type = 58;
-    pub const RISCV_REG_F13_32: Type = 59;
-    pub const RISCV_REG_F13_64: Type = 60;
-    pub const RISCV_REG_F14_32: Type = 61;
-    pub const RISCV_REG_F14_64: Type = 62;
-    pub const RISCV_REG_F15_32: Type = 63;
-    pub const RISCV_REG_F15_64: Type = 64;
-    pub const RISCV_REG_F16_32: Type = 65;
-    pub const RISCV_REG_F16_64: Type = 66;
-    pub const RISCV_REG_F17_32: Type = 67;
-    pub const RISCV_REG_F17_64: Type = 68;
-    pub const RISCV_REG_F18_32: Type = 69;
-    pub const RISCV_REG_F18_64: Type = 70;
-    pub const RISCV_REG_F19_32: Type = 71;
-    pub const RISCV_REG_F19_64: Type = 72;
-    pub const RISCV_REG_F20_32: Type = 73;
-    pub const RISCV_REG_F20_64: Type = 74;
-    pub const RISCV_REG_F21_32: Type = 75;
-    pub const RISCV_REG_F21_64: Type = 76;
-    pub const RISCV_REG_F22_32: Type = 77;
-    pub const RISCV_REG_F22_64: Type = 78;
-    pub const RISCV_REG_F23_32: Type = 79;
-    pub const RISCV_REG_F23_64: Type = 80;
-    pub const RISCV_REG_F24_32: Type = 81;
-    pub const RISCV_REG_F24_64: Type = 82;
-    pub const RISCV_REG_F25_32: Type = 83;
-    pub const RISCV_REG_F25_64: Type = 84;
-    pub const RISCV_REG_F26_32: Type = 85;
-    pub const RISCV_REG_F26_64: Type = 86;
-    pub const RISCV_REG_F27_32: Type = 87;
-    pub const RISCV_REG_F27_64: Type = 88;
-    pub const RISCV_REG_F28_32: Type = 89;
-    pub const RISCV_REG_F28_64: Type = 90;
-    pub const RISCV_REG_F29_32: Type = 91;
-    pub const RISCV_REG_F29_64: Type = 92;
-    pub const RISCV_REG_F30_32: Type = 93;
-    pub const RISCV_REG_F30_64: Type = 94;
-    pub const RISCV_REG_F31_32: Type = 95;
-    pub const RISCV_REG_F31_64: Type = 96;
-    pub const RISCV_REG_ENDING: Type = 97;
+impl riscv_reg {
+    pub const RISCV_REG_INVALID: riscv_reg = riscv_reg(0);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X0: riscv_reg = riscv_reg(1);
+}
+impl riscv_reg {
+    pub const RISCV_REG_ZERO: riscv_reg = riscv_reg(1);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X1: riscv_reg = riscv_reg(2);
+}
+impl riscv_reg {
+    pub const RISCV_REG_RA: riscv_reg = riscv_reg(2);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X2: riscv_reg = riscv_reg(3);
+}
+impl riscv_reg {
+    pub const RISCV_REG_SP: riscv_reg = riscv_reg(3);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X3: riscv_reg = riscv_reg(4);
+}
+impl riscv_reg {
+    pub const RISCV_REG_GP: riscv_reg = riscv_reg(4);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X4: riscv_reg = riscv_reg(5);
+}
+impl riscv_reg {
+    pub const RISCV_REG_TP: riscv_reg = riscv_reg(5);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X5: riscv_reg = riscv_reg(6);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T0: riscv_reg = riscv_reg(6);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X6: riscv_reg = riscv_reg(7);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T1: riscv_reg = riscv_reg(7);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X7: riscv_reg = riscv_reg(8);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T2: riscv_reg = riscv_reg(8);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X8: riscv_reg = riscv_reg(9);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S0: riscv_reg = riscv_reg(9);
+}
+impl riscv_reg {
+    pub const RISCV_REG_FP: riscv_reg = riscv_reg(9);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X9: riscv_reg = riscv_reg(10);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S1: riscv_reg = riscv_reg(10);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X10: riscv_reg = riscv_reg(11);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A0: riscv_reg = riscv_reg(11);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X11: riscv_reg = riscv_reg(12);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A1: riscv_reg = riscv_reg(12);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X12: riscv_reg = riscv_reg(13);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A2: riscv_reg = riscv_reg(13);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X13: riscv_reg = riscv_reg(14);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A3: riscv_reg = riscv_reg(14);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X14: riscv_reg = riscv_reg(15);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A4: riscv_reg = riscv_reg(15);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X15: riscv_reg = riscv_reg(16);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A5: riscv_reg = riscv_reg(16);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X16: riscv_reg = riscv_reg(17);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A6: riscv_reg = riscv_reg(17);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X17: riscv_reg = riscv_reg(18);
+}
+impl riscv_reg {
+    pub const RISCV_REG_A7: riscv_reg = riscv_reg(18);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X18: riscv_reg = riscv_reg(19);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S2: riscv_reg = riscv_reg(19);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X19: riscv_reg = riscv_reg(20);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S3: riscv_reg = riscv_reg(20);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X20: riscv_reg = riscv_reg(21);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S4: riscv_reg = riscv_reg(21);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X21: riscv_reg = riscv_reg(22);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S5: riscv_reg = riscv_reg(22);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X22: riscv_reg = riscv_reg(23);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S6: riscv_reg = riscv_reg(23);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X23: riscv_reg = riscv_reg(24);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S7: riscv_reg = riscv_reg(24);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X24: riscv_reg = riscv_reg(25);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S8: riscv_reg = riscv_reg(25);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X25: riscv_reg = riscv_reg(26);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S9: riscv_reg = riscv_reg(26);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X26: riscv_reg = riscv_reg(27);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S10: riscv_reg = riscv_reg(27);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X27: riscv_reg = riscv_reg(28);
+}
+impl riscv_reg {
+    pub const RISCV_REG_S11: riscv_reg = riscv_reg(28);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X28: riscv_reg = riscv_reg(29);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T3: riscv_reg = riscv_reg(29);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X29: riscv_reg = riscv_reg(30);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T4: riscv_reg = riscv_reg(30);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X30: riscv_reg = riscv_reg(31);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T5: riscv_reg = riscv_reg(31);
+}
+impl riscv_reg {
+    pub const RISCV_REG_X31: riscv_reg = riscv_reg(32);
+}
+impl riscv_reg {
+    pub const RISCV_REG_T6: riscv_reg = riscv_reg(32);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F0_32: riscv_reg = riscv_reg(33);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F0_64: riscv_reg = riscv_reg(34);
 }
+impl riscv_reg {
+    pub const RISCV_REG_F1_32: riscv_reg = riscv_reg(35);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F1_64: riscv_reg = riscv_reg(36);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F2_32: riscv_reg = riscv_reg(37);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F2_64: riscv_reg = riscv_reg(38);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F3_32: riscv_reg = riscv_reg(39);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F3_64: riscv_reg = riscv_reg(40);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F4_32: riscv_reg = riscv_reg(41);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F4_64: riscv_reg = riscv_reg(42);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F5_32: riscv_reg = riscv_reg(43);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F5_64: riscv_reg = riscv_reg(44);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F6_32: riscv_reg = riscv_reg(45);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F6_64: riscv_reg = riscv_reg(46);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F7_32: riscv_reg = riscv_reg(47);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F7_64: riscv_reg = riscv_reg(48);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F8_32: riscv_reg = riscv_reg(49);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F8_64: riscv_reg = riscv_reg(50);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F9_32: riscv_reg = riscv_reg(51);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F9_64: riscv_reg = riscv_reg(52);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F10_32: riscv_reg = riscv_reg(53);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F10_64: riscv_reg = riscv_reg(54);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F11_32: riscv_reg = riscv_reg(55);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F11_64: riscv_reg = riscv_reg(56);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F12_32: riscv_reg = riscv_reg(57);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F12_64: riscv_reg = riscv_reg(58);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F13_32: riscv_reg = riscv_reg(59);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F13_64: riscv_reg = riscv_reg(60);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F14_32: riscv_reg = riscv_reg(61);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F14_64: riscv_reg = riscv_reg(62);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F15_32: riscv_reg = riscv_reg(63);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F15_64: riscv_reg = riscv_reg(64);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F16_32: riscv_reg = riscv_reg(65);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F16_64: riscv_reg = riscv_reg(66);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F17_32: riscv_reg = riscv_reg(67);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F17_64: riscv_reg = riscv_reg(68);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F18_32: riscv_reg = riscv_reg(69);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F18_64: riscv_reg = riscv_reg(70);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F19_32: riscv_reg = riscv_reg(71);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F19_64: riscv_reg = riscv_reg(72);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F20_32: riscv_reg = riscv_reg(73);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F20_64: riscv_reg = riscv_reg(74);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F21_32: riscv_reg = riscv_reg(75);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F21_64: riscv_reg = riscv_reg(76);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F22_32: riscv_reg = riscv_reg(77);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F22_64: riscv_reg = riscv_reg(78);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F23_32: riscv_reg = riscv_reg(79);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F23_64: riscv_reg = riscv_reg(80);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F24_32: riscv_reg = riscv_reg(81);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F24_64: riscv_reg = riscv_reg(82);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F25_32: riscv_reg = riscv_reg(83);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F25_64: riscv_reg = riscv_reg(84);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F26_32: riscv_reg = riscv_reg(85);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F26_64: riscv_reg = riscv_reg(86);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F27_32: riscv_reg = riscv_reg(87);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F27_64: riscv_reg = riscv_reg(88);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F28_32: riscv_reg = riscv_reg(89);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F28_64: riscv_reg = riscv_reg(90);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F29_32: riscv_reg = riscv_reg(91);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F29_64: riscv_reg = riscv_reg(92);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F30_32: riscv_reg = riscv_reg(93);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F30_64: riscv_reg = riscv_reg(94);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F31_32: riscv_reg = riscv_reg(95);
+}
+impl riscv_reg {
+    pub const RISCV_REG_F31_64: riscv_reg = riscv_reg(96);
+}
+impl riscv_reg {
+    pub const RISCV_REG_ENDING: riscv_reg = riscv_reg(97);
+}
+#[repr(transparent)]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct riscv_reg(pub libc::c_uint);
 #[repr(u32)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum riscv_insn {
@@ -15228,19 +18704,39 @@ pub enum riscv_insn {
     RISCV_INS_XORI = 272,
     RISCV_INS_ENDING = 273,
 }
-pub mod riscv_insn_group {
-    pub type Type = libc::c_uint;
-    pub const RISCV_GRP_INVALID: Type = 0;
-    pub const RISCV_GRP_JUMP: Type = 1;
-    pub const RISCV_GRP_ISRV32: Type = 128;
-    pub const RISCV_GRP_ISRV64: Type = 129;
-    pub const RISCV_GRP_HASSTDEXTA: Type = 130;
-    pub const RISCV_GRP_HASSTDEXTC: Type = 131;
-    pub const RISCV_GRP_HASSTDEXTD: Type = 132;
-    pub const RISCV_GRP_HASSTDEXTF: Type = 133;
-    pub const RISCV_GRP_HASSTDEXTM: Type = 134;
-    pub const RISCV_GRP_ENDING: Type = 135;
+impl riscv_insn_group {
+    pub const RISCV_GRP_INVALID: riscv_insn_group = riscv_insn_group(0);
 }
+impl riscv_insn_group {
+    pub const RISCV_GRP_JUMP: riscv_insn_group = riscv_insn_group(1);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_ISRV32: riscv_insn_group = riscv_insn_group(128);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_ISRV64: riscv_insn_group = riscv_insn_group(129);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_HASSTDEXTA: riscv_insn_group = riscv_insn_group(130);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_HASSTDEXTC: riscv_insn_group = riscv_insn_group(131);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_HASSTDEXTD: riscv_insn_group = riscv_insn_group(132);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_HASSTDEXTF: riscv_insn_group = riscv_insn_group(133);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_HASSTDEXTM: riscv_insn_group = riscv_insn_group(134);
+}
+impl riscv_insn_group {
+    pub const RISCV_GRP_ENDING: riscv_insn_group = riscv_insn_group(135);
+}
+#[repr(transparent)]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct riscv_insn_group(pub libc::c_uint);
 #[repr(u32)]
 #[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
 pub enum wasm_op_type {
@@ -15255,26 +18751,21 @@ pub enum wasm_op_type {
     WASM_OP_BRTABLE = 8,
 }
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct cs_wasm_brtable {
     pub length: u32,
     pub address: u64,
     pub default_target: u32,
 }
-impl Clone for cs_wasm_brtable {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_wasm_op {
     pub type_: wasm_op_type,
     pub size: u32,
     pub __bindgen_anon_1: cs_wasm_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_wasm_op__bindgen_ty_1 {
     pub int7: i8,
     pub varuint32: u32,
@@ -15284,49 +18775,30 @@ pub union cs_wasm_op__bindgen_ty_1 {
     pub immediate: [u32; 2usize],
     pub brtable: cs_wasm_brtable,
 }
-impl Clone for cs_wasm_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_wasm_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_wasm_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_wasm_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_wasm_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_wasm_op {{ type: {:?}, size: {:?}, __bindgen_anon_1: {:?} }}",
-            self.type_, self.size, self.__bindgen_anon_1
+            "cs_wasm_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
+            self.type_, self.__bindgen_anon_1
         )
     }
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_wasm {
     pub op_count: u8,
     pub operands: [cs_wasm_op; 2usize],
 }
-impl Clone for cs_wasm {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_wasm {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write!(
-            f,
-            "cs_wasm {{ op_count: {:?}, operands: {:?} }}",
-            self.op_count, self.operands
-        )
+        write!(f, "cs_wasm {{ operands: {:?} }}", self.operands)
     }
 }
 #[repr(u32)]
@@ -15424,14 +18896,14 @@ pub enum mos65xx_op_type {
 }
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_mos65xx_op {
     #[doc = "< operand type"]
     pub type_: mos65xx_op_type,
     pub __bindgen_anon_1: cs_mos65xx_op__bindgen_ty_1,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_mos65xx_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
     pub reg: mos65xx_reg,
@@ -15440,21 +18912,11 @@ pub union cs_mos65xx_op__bindgen_ty_1 {
     #[doc = "< address for MEM operand"]
     pub mem: u32,
 }
-impl Clone for cs_mos65xx_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_mos65xx_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_mos65xx_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_mos65xx_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_mos65xx_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
@@ -15466,27 +18928,21 @@ impl ::core::fmt::Debug for cs_mos65xx_op {
 }
 #[doc = " The MOS65XX address mode and it's operands"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_mos65xx {
     pub am: mos65xx_address_mode,
     pub modifies_flags: bool,
-    #[doc = " Number of operands of this instruction,"]
-    #[doc = " or 0 when instruction has no operand."]
+    #[doc = " Number of operands of this instruction,\n or 0 when instruction has no operand."]
     pub op_count: u8,
     #[doc = "< operands for this instruction."]
     pub operands: [cs_mos65xx_op; 3usize],
 }
-impl Clone for cs_mos65xx {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_mos65xx {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, op_count: {:?}, operands: {:?} }}",
-            self.am, self.modifies_flags, self.op_count, self.operands
+            "cs_mos65xx {{ am: {:?}, modifies_flags: {:?}, operands: {:?} }}",
+            self.am, self.modifies_flags, self.operands
         )
     }
 }
@@ -15526,34 +18982,26 @@ pub enum bpf_reg {
     BPF_REG_R10 = 13,
     BPF_REG_ENDING = 14,
 }
-#[doc = " Instruction's operand referring to memory"]
-#[doc = " This is associated with BPF_OP_MEM operand type above"]
+#[doc = " Instruction's operand referring to memory\n This is associated with BPF_OP_MEM operand type above"]
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct bpf_op_mem {
     #[doc = "< base register"]
     pub base: bpf_reg,
     #[doc = "< offset value"]
     pub disp: u32,
 }
-impl Clone for bpf_op_mem {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 #[doc = " Instruction operand"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_bpf_op {
     pub type_: bpf_op_type,
     pub __bindgen_anon_1: cs_bpf_op__bindgen_ty_1,
-    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)"]
-    #[doc = " This field is combined of cs_ac_type."]
-    #[doc = " NOTE: this field is irrelevant if engine is compiled in DIET mode."]
+    #[doc = " How is this operand accessed? (READ, WRITE or READ|WRITE)\n This field is combined of cs_ac_type.\n NOTE: this field is irrelevant if engine is compiled in DIET mode."]
     pub access: u8,
 }
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_bpf_op__bindgen_ty_1 {
     #[doc = "< register value for REG operand"]
     pub reg: u8,
@@ -15570,58 +19018,35 @@ pub union cs_bpf_op__bindgen_ty_1 {
     #[doc = "< cBPF's extension (not eBPF)"]
     pub ext: u32,
 }
-impl Clone for cs_bpf_op__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_bpf_op__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_bpf_op__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_bpf_op {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_bpf_op {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(
             f,
-            "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?}, access: {:?} }}",
-            self.type_, self.__bindgen_anon_1, self.access
+            "cs_bpf_op {{ type: {:?}, __bindgen_anon_1: {:?} }}",
+            self.type_, self.__bindgen_anon_1
         )
     }
 }
 #[doc = " Instruction structure"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_bpf {
     pub op_count: u8,
     pub operands: [cs_bpf_op; 4usize],
 }
-impl Clone for cs_bpf {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_bpf {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write!(
-            f,
-            "cs_bpf {{ op_count: {:?}, operands: {:?} }}",
-            self.op_count, self.operands
-        )
+        write!(f, "cs_bpf {{ operands: {:?} }}", self.operands)
     }
 }
-#[doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON"]
-#[doc = " Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))"]
-#[doc = " by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c"]
-#[doc = " if cs_detail changes, in particular if a field is added after the union,"]
-#[doc = " then update arch/ARCH/ARCHDisassembler.c accordingly"]
+#[doc = " NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON\n Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))\n by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c\n if cs_detail changes, in particular if a field is added after the union,\n then update arch/ARCH/ARCHDisassembler.c accordingly"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub struct cs_detail {
     #[doc = "< list of implicit registers read by this insn"]
     pub regs_read: [u16; 16usize],
@@ -15639,7 +19064,7 @@ pub struct cs_detail {
 }
 #[doc = " Architecture-specific instruction info"]
 #[repr(C)]
-#[derive(Copy)]
+#[derive(Copy, Clone)]
 pub union cs_detail__bindgen_ty_1 {
     #[doc = "< X86 architecture, including 16-bit, 32-bit & 64-bit mode"]
     pub x86: cs_x86,
@@ -15674,223 +19099,129 @@ pub union cs_detail__bindgen_ty_1 {
     #[doc = "< RISCV architecture"]
     pub riscv: cs_riscv,
 }
-impl Clone for cs_detail__bindgen_ty_1 {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_detail__bindgen_ty_1 {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
         write!(f, "cs_detail__bindgen_ty_1 {{ union }}")
     }
 }
-impl Clone for cs_detail {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
 impl ::core::fmt::Debug for cs_detail {
     fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_detail {{ regs_read: {:?}, regs_read_count: {:?}, regs_write: {:?}, regs_write_count: {:?}, groups: {:?}, groups_count: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_read_count , self . regs_write , self . regs_write_count , self . groups , self . groups_count , self . __bindgen_anon_1)
+        write ! (f , "cs_detail {{ regs_read: {:?}, regs_write: {:?}, groups: {:?}, __bindgen_anon_1: {:?} }}" , self . regs_read , self . regs_write , self . groups , self . __bindgen_anon_1)
     }
 }
 #[doc = " Detail information of disassembled instruction"]
 #[repr(C)]
+#[derive(Debug)]
 pub struct cs_insn {
-    #[doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)"]
-    #[doc = " Find the instruction id in the '[ARCH]_insn' enum in the header file"]
-    #[doc = " of corresponding architecture, such as 'arm_insn' in arm.h for ARM,"]
-    #[doc = " 'x86_insn' in x86.h for X86, etc..."]
-    #[doc = " This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
-    #[doc = " NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."]
+    #[doc = " Instruction ID (basically a numeric ID for the instruction mnemonic)\n Find the instruction id in the '[ARCH]_insn' enum in the header file\n of corresponding architecture, such as 'arm_insn' in arm.h for ARM,\n 'x86_insn' in x86.h for X86, etc...\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF\n NOTE: in Skipdata mode, \"data\" instruction has 0 for this id field."]
     pub id: libc::c_uint,
-    #[doc = " Address (EIP) of this instruction"]
-    #[doc = " This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
+    #[doc = " Address (EIP) of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
     pub address: u64,
-    #[doc = " Size of this instruction"]
-    #[doc = " This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
+    #[doc = " Size of this instruction\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
     pub size: u16,
-    #[doc = " Machine bytes of this instruction, with number of bytes indicated by @size above"]
-    #[doc = " This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
+    #[doc = " Machine bytes of this instruction, with number of bytes indicated by @size above\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
     pub bytes: [u8; 24usize],
-    #[doc = " Ascii text of instruction mnemonic"]
-    #[doc = " This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
+    #[doc = " Ascii text of instruction mnemonic\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
     pub mnemonic: [libc::c_char; 32usize],
-    #[doc = " Ascii text of instruction operands"]
-    #[doc = " This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
+    #[doc = " Ascii text of instruction operands\n This information is available even when CS_OPT_DETAIL = CS_OPT_OFF"]
     pub op_str: [libc::c_char; 160usize],
-    #[doc = " Pointer to cs_detail."]
-    #[doc = " NOTE: detail pointer is only valid when both requirements below are met:"]
-    #[doc = " (1) CS_OP_DETAIL = CS_OPT_ON"]
-    #[doc = " (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)"]
-    #[doc = ""]
-    #[doc = " NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer"]
-    #[doc = "     is not NULL, its content is still irrelevant."]
+    #[doc = " Pointer to cs_detail.\n NOTE: detail pointer is only valid when both requirements below are met:\n (1) CS_OP_DETAIL = CS_OPT_ON\n (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)\n\n NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer\n     is not NULL, its content is still irrelevant."]
     pub detail: *mut cs_detail,
 }
-impl ::core::fmt::Debug for cs_insn {
-    fn fmt(&self, f: &mut ::core::fmt::Formatter<'_>) -> ::core::fmt::Result {
-        write ! (f , "cs_insn {{ id: {:?}, address: {:?}, size: {:?}, bytes: {:?}, mnemonic: [...], op_str: [...], detail: {:?} }}" , self . id , self . address , self . size , self . bytes , self . detail)
-    }
-}
-pub mod cs_err {
-    #[doc = " All type of errors encountered by Capstone API."]
-    #[doc = " These are values returned by cs_errno()"]
-    pub type Type = libc::c_uint;
+impl cs_err {
     #[doc = "< No error: everything was fine"]
-    pub const CS_ERR_OK: Type = 0;
+    pub const CS_ERR_OK: cs_err = cs_err(0);
+}
+impl cs_err {
     #[doc = "< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()"]
-    pub const CS_ERR_MEM: Type = 1;
+    pub const CS_ERR_MEM: cs_err = cs_err(1);
+}
+impl cs_err {
     #[doc = "< Unsupported architecture: cs_open()"]
-    pub const CS_ERR_ARCH: Type = 2;
+    pub const CS_ERR_ARCH: cs_err = cs_err(2);
+}
+impl cs_err {
     #[doc = "< Invalid handle: cs_op_count(), cs_op_index()"]
-    pub const CS_ERR_HANDLE: Type = 3;
+    pub const CS_ERR_HANDLE: cs_err = cs_err(3);
+}
+impl cs_err {
     #[doc = "< Invalid csh argument: cs_close(), cs_errno(), cs_option()"]
-    pub const CS_ERR_CSH: Type = 4;
+    pub const CS_ERR_CSH: cs_err = cs_err(4);
+}
+impl cs_err {
     #[doc = "< Invalid/unsupported mode: cs_open()"]
-    pub const CS_ERR_MODE: Type = 5;
+    pub const CS_ERR_MODE: cs_err = cs_err(5);
+}
+impl cs_err {
     #[doc = "< Invalid/unsupported option: cs_option()"]
-    pub const CS_ERR_OPTION: Type = 6;
+    pub const CS_ERR_OPTION: cs_err = cs_err(6);
+}
+impl cs_err {
     #[doc = "< Information is unavailable because detail option is OFF"]
-    pub const CS_ERR_DETAIL: Type = 7;
+    pub const CS_ERR_DETAIL: cs_err = cs_err(7);
+}
+impl cs_err {
     #[doc = "< Dynamic memory management uninitialized (see CS_OPT_MEM)"]
-    pub const CS_ERR_MEMSETUP: Type = 8;
+    pub const CS_ERR_MEMSETUP: cs_err = cs_err(8);
+}
+impl cs_err {
     #[doc = "< Unsupported version (bindings)"]
-    pub const CS_ERR_VERSION: Type = 9;
+    pub const CS_ERR_VERSION: cs_err = cs_err(9);
+}
+impl cs_err {
     #[doc = "< Access irrelevant data in \"diet\" engine"]
-    pub const CS_ERR_DIET: Type = 10;
+    pub const CS_ERR_DIET: cs_err = cs_err(10);
+}
+impl cs_err {
     #[doc = "< Access irrelevant data for \"data\" instruction in SKIPDATA mode"]
-    pub const CS_ERR_SKIPDATA: Type = 11;
+    pub const CS_ERR_SKIPDATA: cs_err = cs_err(11);
+}
+impl cs_err {
     #[doc = "< X86 AT&T syntax is unsupported (opt-out at compile time)"]
-    pub const CS_ERR_X86_ATT: Type = 12;
+    pub const CS_ERR_X86_ATT: cs_err = cs_err(12);
+}
+impl cs_err {
     #[doc = "< X86 Intel syntax is unsupported (opt-out at compile time)"]
-    pub const CS_ERR_X86_INTEL: Type = 13;
+    pub const CS_ERR_X86_INTEL: cs_err = cs_err(13);
+}
+impl cs_err {
     #[doc = "< X86 Masm syntax is unsupported (opt-out at compile time)"]
-    pub const CS_ERR_X86_MASM: Type = 14;
+    pub const CS_ERR_X86_MASM: cs_err = cs_err(14);
 }
+#[repr(transparent)]
+#[doc = " All type of errors encountered by Capstone API.\n These are values returned by cs_errno()"]
+#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
+pub struct cs_err(pub libc::c_uint);
 extern "C" {
-    #[doc = "Return combined API version & major and minor version numbers."]
-    #[doc = ""]
-    #[doc = "@major: major number of API version"]
-    #[doc = "@minor: minor number of API version"]
-    #[doc = ""]
-    #[doc = "@return hexical number as (major << 8 | minor), which encodes both"]
-    #[doc = "major & minor versions."]
-    #[doc = "NOTE: This returned value can be compared with version number made"]
-    #[doc = "with macro CS_MAKE_VERSION"]
-    #[doc = ""]
-    #[doc = "For example, second API version would return 1 in @major, and 1 in @minor"]
-    #[doc = "The return value would be 0x0101"]
-    #[doc = ""]
-    #[doc = "NOTE: if you only care about returned value, but not major and minor values,"]
-    #[doc = "set both @major & @minor arguments to NULL."]
+    #[doc = "Return combined API version & major and minor version numbers.\n\n@major: major number of API version\n@minor: minor number of API version\n\n@return hexical number as (major << 8 | minor), which encodes both\nmajor & minor versions.\nNOTE: This returned value can be compared with version number made\nwith macro CS_MAKE_VERSION\n\nFor example, second API version would return 1 in @major, and 1 in @minor\nThe return value would be 0x0101\n\nNOTE: if you only care about returned value, but not major and minor values,\nset both @major & @minor arguments to NULL."]
     pub fn cs_version(major: *mut libc::c_int, minor: *mut libc::c_int) -> libc::c_uint;
 }
 extern "C" {
-    #[doc = "This API can be used to either ask for archs supported by this library,"]
-    #[doc = "or check to see if the library was compile with 'diet' option (or called"]
-    #[doc = "in 'diet' mode)."]
-    #[doc = ""]
-    #[doc = "To check if a particular arch is supported by this library, set @query to"]
-    #[doc = "arch mode (CS_ARCH_* value)."]
-    #[doc = "To verify if this library supports all the archs, use CS_ARCH_ALL."]
-    #[doc = ""]
-    #[doc = "To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET."]
-    #[doc = ""]
-    #[doc = "@return True if this library supports the given arch, or in 'diet' mode."]
+    #[doc = "This API can be used to either ask for archs supported by this library,\nor check to see if the library was compile with 'diet' option (or called\nin 'diet' mode).\n\nTo check if a particular arch is supported by this library, set @query to\narch mode (CS_ARCH_* value).\nTo verify if this library supports all the archs, use CS_ARCH_ALL.\n\nTo check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.\n\n@return True if this library supports the given arch, or in 'diet' mode."]
     pub fn cs_support(query: libc::c_int) -> bool;
 }
 extern "C" {
-    #[doc = "Initialize CS handle: this must be done before any usage of CS."]
-    #[doc = ""]
-    #[doc = "@arch: architecture type (CS_ARCH_*)"]
-    #[doc = "@mode: hardware mode. This is combined of CS_MODE_*"]
-    #[doc = "@handle: pointer to handle, which will be updated at return time"]
-    #[doc = ""]
-    #[doc = "@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum"]
-    #[doc = "for detailed error)."]
-    pub fn cs_open(arch: cs_arch, mode: cs_mode, handle: *mut csh) -> cs_err::Type;
+    #[doc = "Initialize CS handle: this must be done before any usage of CS.\n\n@arch: architecture type (CS_ARCH_*)\n@mode: hardware mode. This is combined of CS_MODE_*\n@handle: pointer to handle, which will be updated at return time\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."]
+    pub fn cs_open(arch: cs_arch, mode: cs_mode, handle: *mut csh) -> cs_err;
 }
 extern "C" {
-    #[doc = "Close CS handle: MUST do to release the handle when it is not used anymore."]
-    #[doc = "NOTE: this must be only called when there is no longer usage of Capstone,"]
-    #[doc = "not even access to cs_insn array. The reason is the this API releases some"]
-    #[doc = "cached memory, thus access to any Capstone API after cs_close() might crash"]
-    #[doc = "your application."]
-    #[doc = ""]
-    #[doc = "In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0)."]
-    #[doc = ""]
-    #[doc = "@handle: pointer to a handle returned by cs_open()"]
-    #[doc = ""]
-    #[doc = "@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum"]
-    #[doc = "for detailed error)."]
-    pub fn cs_close(handle: *mut csh) -> cs_err::Type;
+    #[doc = "Close CS handle: MUST do to release the handle when it is not used anymore.\nNOTE: this must be only called when there is no longer usage of Capstone,\nnot even access to cs_insn array. The reason is the this API releases some\ncached memory, thus access to any Capstone API after cs_close() might crash\nyour application.\n\nIn fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).\n\n@handle: pointer to a handle returned by cs_open()\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."]
+    pub fn cs_close(handle: *mut csh) -> cs_err;
 }
 extern "C" {
-    #[doc = "Set option for disassembling engine at runtime"]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@type: type of option to be set"]
-    #[doc = "@value: option value corresponding with @type"]
-    #[doc = ""]
-    #[doc = "@return: CS_ERR_OK on success, or other value on failure."]
-    #[doc = "Refer to cs_err enum for detailed error."]
-    #[doc = ""]
-    #[doc = "NOTE: in the case of CS_OPT_MEM, handle's value can be anything,"]
-    #[doc = "so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called"]
-    #[doc = "even before cs_open()"]
-    pub fn cs_option(handle: csh, type_: cs_opt_type, value: usize) -> cs_err::Type;
+    #[doc = "Set option for disassembling engine at runtime\n\n@handle: handle returned by cs_open()\n@type: type of option to be set\n@value: option value corresponding with @type\n\n@return: CS_ERR_OK on success, or other value on failure.\nRefer to cs_err enum for detailed error.\n\nNOTE: in the case of CS_OPT_MEM, handle's value can be anything,\nso that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called\neven before cs_open()"]
+    pub fn cs_option(handle: csh, type_: cs_opt_type, value: usize) -> cs_err;
 }
 extern "C" {
-    #[doc = "Report the last error number when some API function fail."]
-    #[doc = "Like glibc's errno, cs_errno might not retain its old value once accessed."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = ""]
-    #[doc = "@return: error code of cs_err enum type (CS_ERR_*, see above)"]
-    pub fn cs_errno(handle: csh) -> cs_err::Type;
+    #[doc = "Report the last error number when some API function fail.\nLike glibc's errno, cs_errno might not retain its old value once accessed.\n\n@handle: handle returned by cs_open()\n\n@return: error code of cs_err enum type (CS_ERR_*, see above)"]
+    pub fn cs_errno(handle: csh) -> cs_err;
 }
 extern "C" {
-    #[doc = "Return a string describing given error code."]
-    #[doc = ""]
-    #[doc = "@code: error code (see CS_ERR_* above)"]
-    #[doc = ""]
-    #[doc = "@return: returns a pointer to a string that describes the error code"]
-    #[doc = "passed in the argument @code"]
-    pub fn cs_strerror(code: cs_err::Type) -> *const libc::c_char;
+    #[doc = "Return a string describing given error code.\n\n@code: error code (see CS_ERR_* above)\n\n@return: returns a pointer to a string that describes the error code\npassed in the argument @code"]
+    pub fn cs_strerror(code: cs_err) -> *const libc::c_char;
 }
 extern "C" {
-    #[doc = "Disassemble binary code, given the code buffer, size, address and number"]
-    #[doc = "of instructions to be decoded."]
-    #[doc = "This API dynamically allocate memory to contain disassembled instruction."]
-    #[doc = "Resulting instructions will be put into @*insn"]
-    #[doc = ""]
-    #[doc = "NOTE 1: this API will automatically determine memory needed to contain"]
-    #[doc = "output disassembled instructions in @insn."]
-    #[doc = ""]
-    #[doc = "NOTE 2: caller must free the allocated memory itself to avoid memory leaking."]
-    #[doc = ""]
-    #[doc = "NOTE 3: for system with scarce memory to be dynamically allocated such as"]
-    #[doc = "OS kernel or firmware, the API cs_disasm_iter() might be a better choice than"]
-    #[doc = "cs_disasm(). The reason is that with cs_disasm(), based on limited available"]
-    #[doc = "memory, we have to calculate in advance how many instructions to be disassembled,"]
-    #[doc = "which complicates things. This is especially troublesome for the case @count=0,"]
-    #[doc = "when cs_disasm() runs uncontrollably (until either end of input buffer, or"]
-    #[doc = "when it encounters an invalid instruction)."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@code: buffer containing raw binary code to be disassembled."]
-    #[doc = "@code_size: size of the above code buffer."]
-    #[doc = "@address: address of the first instruction in given raw code buffer."]
-    #[doc = "@insn: array of instructions filled in by this API."]
-    #[doc = "NOTE: @insn will be allocated by this function, and should be freed"]
-    #[doc = "with cs_free() API."]
-    #[doc = "@count: number of instructions to be disassembled, or 0 to get all of them"]
-    #[doc = ""]
-    #[doc = "@return: the number of successfully disassembled instructions,"]
-    #[doc = "or 0 if this function failed to disassemble the given code"]
-    #[doc = ""]
-    #[doc = "On failure, call cs_errno() for error code."]
+    #[doc = "Disassemble binary code, given the code buffer, size, address and number\nof instructions to be decoded.\nThis API dynamically allocate memory to contain disassembled instruction.\nResulting instructions will be put into @*insn\n\nNOTE 1: this API will automatically determine memory needed to contain\noutput disassembled instructions in @insn.\n\nNOTE 2: caller must free the allocated memory itself to avoid memory leaking.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, the API cs_disasm_iter() might be a better choice than\ncs_disasm(). The reason is that with cs_disasm(), based on limited available\nmemory, we have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case @count=0,\nwhen cs_disasm() runs uncontrollably (until either end of input buffer, or\nwhen it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled.\n@code_size: size of the above code buffer.\n@address: address of the first instruction in given raw code buffer.\n@insn: array of instructions filled in by this API.\nNOTE: @insn will be allocated by this function, and should be freed\nwith cs_free() API.\n@count: number of instructions to be disassembled, or 0 to get all of them\n\n@return: the number of successfully disassembled instructions,\nor 0 if this function failed to disassemble the given code\n\nOn failure, call cs_errno() for error code."]
     pub fn cs_disasm(
         handle: csh,
         code: *const u8,
@@ -15901,56 +19232,15 @@ extern "C" {
     ) -> usize;
 }
 extern "C" {
-    #[doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)"]
-    #[doc = ""]
-    #[doc = "@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()"]
-    #[doc = "@count: number of cs_insn structures returned by cs_disasm(), or 1"]
-    #[doc = "to free memory allocated by cs_malloc()."]
+    #[doc = "Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)\n\n@insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()\n@count: number of cs_insn structures returned by cs_disasm(), or 1\nto free memory allocated by cs_malloc()."]
     pub fn cs_free(insn: *mut cs_insn, count: usize);
 }
 extern "C" {
-    #[doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter()."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = ""]
-    #[doc = "NOTE: when no longer in use, you can reclaim the memory allocated for"]
-    #[doc = "this instruction with cs_free(insn, 1)"]
+    #[doc = "Allocate memory for 1 instruction to be used by cs_disasm_iter().\n\n@handle: handle returned by cs_open()\n\nNOTE: when no longer in use, you can reclaim the memory allocated for\nthis instruction with cs_free(insn, 1)"]
     pub fn cs_malloc(handle: csh) -> *mut cs_insn;
 }
 extern "C" {
-    #[doc = "Fast API to disassemble binary code, given the code buffer, size, address"]
-    #[doc = "and number of instructions to be decoded."]
-    #[doc = "This API puts the resulting instruction into a given cache in @insn."]
-    #[doc = "See tests/test_iter.c for sample code demonstrating this API."]
-    #[doc = ""]
-    #[doc = "NOTE 1: this API will update @code, @size & @address to point to the next"]
-    #[doc = "instruction in the input buffer. Therefore, it is convenient to use"]
-    #[doc = "cs_disasm_iter() inside a loop to quickly iterate all the instructions."]
-    #[doc = "While decoding one instruction at a time can also be achieved with"]
-    #[doc = "cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%"]
-    #[doc = "faster on random input."]
-    #[doc = ""]
-    #[doc = "NOTE 2: the cache in @insn can be created with cs_malloc() API."]
-    #[doc = ""]
-    #[doc = "NOTE 3: for system with scarce memory to be dynamically allocated such as"]
-    #[doc = "OS kernel or firmware, this API is recommended over cs_disasm(), which"]
-    #[doc = "allocates memory based on the number of instructions to be disassembled."]
-    #[doc = "The reason is that with cs_disasm(), based on limited available memory,"]
-    #[doc = "we have to calculate in advance how many instructions to be disassembled,"]
-    #[doc = "which complicates things. This is especially troublesome for the case"]
-    #[doc = "@count=0, when cs_disasm() runs uncontrollably (until either end of input"]
-    #[doc = "buffer, or when it encounters an invalid instruction)."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@code: buffer containing raw binary code to be disassembled"]
-    #[doc = "@size: size of above code"]
-    #[doc = "@address: address of the first insn in given raw code buffer"]
-    #[doc = "@insn: pointer to instruction to be filled in by this API."]
-    #[doc = ""]
-    #[doc = "@return: true if this API successfully decode 1 instruction,"]
-    #[doc = "or false otherwise."]
-    #[doc = ""]
-    #[doc = "On failure, call cs_errno() for error code."]
+    #[doc = "Fast API to disassemble binary code, given the code buffer, size, address\nand number of instructions to be decoded.\nThis API puts the resulting instruction into a given cache in @insn.\nSee tests/test_iter.c for sample code demonstrating this API.\n\nNOTE 1: this API will update @code, @size & @address to point to the next\ninstruction in the input buffer. Therefore, it is convenient to use\ncs_disasm_iter() inside a loop to quickly iterate all the instructions.\nWhile decoding one instruction at a time can also be achieved with\ncs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%\nfaster on random input.\n\nNOTE 2: the cache in @insn can be created with cs_malloc() API.\n\nNOTE 3: for system with scarce memory to be dynamically allocated such as\nOS kernel or firmware, this API is recommended over cs_disasm(), which\nallocates memory based on the number of instructions to be disassembled.\nThe reason is that with cs_disasm(), based on limited available memory,\nwe have to calculate in advance how many instructions to be disassembled,\nwhich complicates things. This is especially troublesome for the case\n@count=0, when cs_disasm() runs uncontrollably (until either end of input\nbuffer, or when it encounters an invalid instruction).\n\n@handle: handle returned by cs_open()\n@code: buffer containing raw binary code to be disassembled\n@size: size of above code\n@address: address of the first insn in given raw code buffer\n@insn: pointer to instruction to be filled in by this API.\n\n@return: true if this API successfully decode 1 instruction,\nor false otherwise.\n\nOn failure, call cs_errno() for error code."]
     pub fn cs_disasm_iter(
         handle: csh,
         code: *mut *const u8,
@@ -15960,123 +19250,35 @@ extern "C" {
     ) -> bool;
 }
 extern "C" {
-    #[doc = "Return friendly name of register in a string."]
-    #[doc = "Find the instruction id from header file of corresponding architecture (arm.h for ARM,"]
-    #[doc = "x86.h for X86, ...)"]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because engine does not"]
-    #[doc = "store register name."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@reg_id: register id"]
-    #[doc = ""]
-    #[doc = "@return: string name of the register, or NULL if @reg_id is invalid."]
+    #[doc = "Return friendly name of register in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM,\nx86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore register name.\n\n@handle: handle returned by cs_open()\n@reg_id: register id\n\n@return: string name of the register, or NULL if @reg_id is invalid."]
     pub fn cs_reg_name(handle: csh, reg_id: libc::c_uint) -> *const libc::c_char;
 }
 extern "C" {
-    #[doc = "Return friendly name of an instruction in a string."]
-    #[doc = "Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because the engine does not"]
-    #[doc = "store instruction name."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@insn_id: instruction id"]
-    #[doc = ""]
-    #[doc = "@return: string name of the instruction, or NULL if @insn_id is invalid."]
+    #[doc = "Return friendly name of an instruction in a string.\nFind the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore instruction name.\n\n@handle: handle returned by cs_open()\n@insn_id: instruction id\n\n@return: string name of the instruction, or NULL if @insn_id is invalid."]
     pub fn cs_insn_name(handle: csh, insn_id: libc::c_uint) -> *const libc::c_char;
 }
 extern "C" {
-    #[doc = "Return friendly name of a group id (that an instruction can belong to)"]
-    #[doc = "Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because the engine does not"]
-    #[doc = "store group name."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@group_id: group id"]
-    #[doc = ""]
-    #[doc = "@return: string name of the group, or NULL if @group_id is invalid."]
+    #[doc = "Return friendly name of a group id (that an instruction can belong to)\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nstore group name.\n\n@handle: handle returned by cs_open()\n@group_id: group id\n\n@return: string name of the group, or NULL if @group_id is invalid."]
     pub fn cs_group_name(handle: csh, group_id: libc::c_uint) -> *const libc::c_char;
 }
 extern "C" {
-    #[doc = "Check if a disassembled instruction belong to a particular group."]
-    #[doc = "Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = "Internally, this simply verifies if @group_id matches any member of insn->groups array."]
-    #[doc = ""]
-    #[doc = "NOTE: this API is only valid when detail option is ON (which is OFF by default)."]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because the engine does not"]
-    #[doc = "update @groups array."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()"]
-    #[doc = "@group_id: group that you want to check if this instruction belong to."]
-    #[doc = ""]
-    #[doc = "@return: true if this instruction indeed belongs to the given group, or false otherwise."]
+    #[doc = "Check if a disassembled instruction belong to a particular group.\nFind the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @group_id matches any member of insn->groups array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default).\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @groups array.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@group_id: group that you want to check if this instruction belong to.\n\n@return: true if this instruction indeed belongs to the given group, or false otherwise."]
     pub fn cs_insn_group(handle: csh, insn: *const cs_insn, group_id: libc::c_uint) -> bool;
 }
 extern "C" {
-    #[doc = "Check if a disassembled instruction IMPLICITLY used a particular register."]
-    #[doc = "Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = "Internally, this simply verifies if @reg_id matches any member of insn->regs_read array."]
-    #[doc = ""]
-    #[doc = "NOTE: this API is only valid when detail option is ON (which is OFF by default)"]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because the engine does not"]
-    #[doc = "update @regs_read array."]
-    #[doc = ""]
-    #[doc = "@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()"]
-    #[doc = "@reg_id: register that you want to check if this instruction used it."]
-    #[doc = ""]
-    #[doc = "@return: true if this instruction indeed implicitly used the given register, or false otherwise."]
+    #[doc = "Check if a disassembled instruction IMPLICITLY used a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_read array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_read array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction used it.\n\n@return: true if this instruction indeed implicitly used the given register, or false otherwise."]
     pub fn cs_reg_read(handle: csh, insn: *const cs_insn, reg_id: libc::c_uint) -> bool;
 }
 extern "C" {
-    #[doc = "Check if a disassembled instruction IMPLICITLY modified a particular register."]
-    #[doc = "Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = "Internally, this simply verifies if @reg_id matches any member of insn->regs_write array."]
-    #[doc = ""]
-    #[doc = "NOTE: this API is only valid when detail option is ON (which is OFF by default)"]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because the engine does not"]
-    #[doc = "update @regs_write array."]
-    #[doc = ""]
-    #[doc = "@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()"]
-    #[doc = "@reg_id: register that you want to check if this instruction modified it."]
-    #[doc = ""]
-    #[doc = "@return: true if this instruction indeed implicitly modified the given register, or false otherwise."]
+    #[doc = "Check if a disassembled instruction IMPLICITLY modified a particular register.\nFind the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\nInternally, this simply verifies if @reg_id matches any member of insn->regs_write array.\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\nWARN: when in 'diet' mode, this API is irrelevant because the engine does not\nupdate @regs_write array.\n\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@reg_id: register that you want to check if this instruction modified it.\n\n@return: true if this instruction indeed implicitly modified the given register, or false otherwise."]
     pub fn cs_reg_write(handle: csh, insn: *const cs_insn, reg_id: libc::c_uint) -> bool;
 }
 extern "C" {
-    #[doc = "Count the number of operands of a given type."]
-    #[doc = "Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = ""]
-    #[doc = "NOTE: this API is only valid when detail option is ON (which is OFF by default)"]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()"]
-    #[doc = "@op_type: Operand type to be found."]
-    #[doc = ""]
-    #[doc = "@return: number of operands of given type @op_type in instruction @insn,"]
-    #[doc = "or -1 on failure."]
+    #[doc = "Count the number of operands of a given type.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n\n@return: number of operands of given type @op_type in instruction @insn,\nor -1 on failure."]
     pub fn cs_op_count(handle: csh, insn: *const cs_insn, op_type: libc::c_uint) -> libc::c_int;
 }
 extern "C" {
-    #[doc = "Retrieve the position of operand of given type in <arch>.operands[] array."]
-    #[doc = "Later, the operand can be accessed using the returned position."]
-    #[doc = "Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)"]
-    #[doc = ""]
-    #[doc = "NOTE: this API is only valid when detail option is ON (which is OFF by default)"]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()"]
-    #[doc = "@op_type: Operand type to be found."]
-    #[doc = "@position: position of the operand to be found. This must be in the range"]
-    #[doc = "[1, cs_op_count(handle, insn, op_type)]"]
-    #[doc = ""]
-    #[doc = "@return: index of operand of given type @op_type in <arch>.operands[] array"]
-    #[doc = "in instruction @insn, or -1 on failure."]
+    #[doc = "Retrieve the position of operand of given type in <arch>.operands[] array.\nLater, the operand can be accessed using the returned position.\nFind the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)\n\nNOTE: this API is only valid when detail option is ON (which is OFF by default)\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()\n@op_type: Operand type to be found.\n@position: position of the operand to be found. This must be in the range\n[1, cs_op_count(handle, insn, op_type)]\n\n@return: index of operand of given type @op_type in <arch>.operands[] array\nin instruction @insn, or -1 on failure."]
     pub fn cs_op_index(
         handle: csh,
         insn: *const cs_insn,
@@ -16087,21 +19289,7 @@ extern "C" {
 #[doc = " Type of array to keep the list of registers"]
 pub type cs_regs = [u16; 64usize];
 extern "C" {
-    #[doc = "Retrieve all the registers accessed by an instruction, either explicitly or"]
-    #[doc = "implicitly."]
-    #[doc = ""]
-    #[doc = "WARN: when in 'diet' mode, this API is irrelevant because engine does not"]
-    #[doc = "store registers."]
-    #[doc = ""]
-    #[doc = "@handle: handle returned by cs_open()"]
-    #[doc = "@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()"]
-    #[doc = "@regs_read: on return, this array contains all registers read by instruction."]
-    #[doc = "@regs_read_count: number of registers kept inside @regs_read array."]
-    #[doc = "@regs_write: on return, this array contains all registers written by instruction."]
-    #[doc = "@regs_write_count: number of registers kept inside @regs_write array."]
-    #[doc = ""]
-    #[doc = "@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum"]
-    #[doc = "for detailed error)."]
+    #[doc = "Retrieve all the registers accessed by an instruction, either explicitly or\nimplicitly.\n\nWARN: when in 'diet' mode, this API is irrelevant because engine does not\nstore registers.\n\n@handle: handle returned by cs_open()\n@insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()\n@regs_read: on return, this array contains all registers read by instruction.\n@regs_read_count: number of registers kept inside @regs_read array.\n@regs_write: on return, this array contains all registers written by instruction.\n@regs_write_count: number of registers kept inside @regs_write array.\n\n@return CS_ERR_OK on success, or other value on failure (refer to cs_err enum\nfor detailed error)."]
     pub fn cs_regs_access(
         handle: csh,
         insn: *const cs_insn,
@@ -16109,19 +19297,14 @@ extern "C" {
         regs_read_count: *mut u8,
         regs_write: *mut u16,
         regs_write_count: *mut u8,
-    ) -> cs_err::Type;
+    ) -> cs_err;
 }
 pub type __builtin_va_list = [__va_list_tag; 1usize];
 #[repr(C)]
-#[derive(Debug, Copy)]
+#[derive(Debug, Copy, Clone)]
 pub struct __va_list_tag {
     pub gp_offset: libc::c_uint,
     pub fp_offset: libc::c_uint,
     pub overflow_arg_area: *mut libc::c_void,
     pub reg_save_area: *mut libc::c_void,
 }
-impl Clone for __va_list_tag {
-    fn clone(&self) -> Self {
-        *self
-    }
-}
diff --git a/cstool/src/bin/cstool.rs b/cstool/src/bin/cstool.rs
index e3209562..eb0cd176 100644
--- a/cstool/src/bin/cstool.rs
+++ b/cstool/src/bin/cstool.rs
@@ -7,7 +7,9 @@ use std::io::prelude::*;
 use std::process::exit;
 use std::str::FromStr;
 
-use capstone::{self, prelude::*, Arch, Endian, EnumList, ExtraMode, Mode};
+use capstone::arch::{ArchTag, DynamicArchTag};
+use capstone::prelude::*;
+use capstone::{Arch, Endian, EnumList, ExtraMode, Mode};
 use clap::{App, Arg, ArgGroup};
 use log::{debug, info};
 
@@ -33,14 +35,22 @@ where
 }
 
 /// Print register names
-fn reg_names(cs: &Capstone, regs: &[RegId]) -> String {
-    let names: Vec<String> = regs.iter().map(|&x| cs.reg_name(x).unwrap()).collect();
+fn reg_names<A, I>(cs: &Capstone<A>, regs: I) -> String
+where
+    A: ArchTag,
+    I: Iterator<Item = A::RegId>,
+{
+    let names: Vec<String> = regs.map(|x| cs.reg_name(x).unwrap()).collect();
     names.join(", ")
 }
 
 /// Print instruction group names
-fn group_names(cs: &Capstone, regs: &[InsnGroupId]) -> String {
-    let names: Vec<String> = regs.iter().map(|&x| cs.group_name(x).unwrap()).collect();
+fn group_names<A, I>(cs: &Capstone<A>, regs: I) -> String
+where
+    A: ArchTag,
+    I: Iterator<Item = A::InsnGroupId>,
+{
+    let names: Vec<String> = regs.map(|x| cs.group_name(x).unwrap()).collect();
     names.join(", ")
 }
 
@@ -80,7 +90,7 @@ fn disasm<T: Iterator<Item = ExtraMode>>(
     show_detail: bool,
 ) {
     info!("Got {} bytes", code.len());
-    let mut cs = Capstone::new_raw(arch, mode, extra_mode, endian).expect_exit();
+    let mut cs = Capstone::<DynamicArchTag>::new_raw(arch, mode, extra_mode, endian).expect_exit();
 
     if show_detail {
         cs.set_detail(true).expect("Failed to set detail");