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‎same70a/armcc/Device/Source/ARM/startup_SAME70.s

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;/**************************************************************************//**
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; * @file startup_SAME70.s
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; * @brief CMSIS Core Device Startup File for
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; * Atmel SAME70 Device Series
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; * @version V1.00
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; * @date 19. January 2015
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; *
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; * @note
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; *
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; ******************************************************************************/
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;/* Copyright (c) 2011 - 2015 ARM LIMITED
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;
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; All rights reserved.
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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; - Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; - Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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; - Neither the name of ARM nor the names of its contributors may be used
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; to endorse or promote products derived from this software without
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; specific prior written permission.
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; *
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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; ---------------------------------------------------------------------------*/
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD SUPC_Handler ; 0 Supply Controller
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DCD RSTC_Handler ; 1 Reset Controller
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DCD RTC_Handler ; 2 Real Time Clock
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DCD RTT_Handler ; 3 Real Time Timer
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DCD WDT_Handler ; 4 Watchdog Timer
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DCD PMC_Handler ; 5 Power Management Controller
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DCD EFC_Handler ; 6 Enhanced Embedded Flash Controller
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DCD UART0_Handler ; 7 UART 0
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DCD UART1_Handler ; 8 UART 1
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DCD 0 ; 9 Reserved
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DCD PIOA_Handler ; 10 Parallel I/O Controller A
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DCD PIOB_Handler ; 11 Parallel I/O Controller B
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DCD PIOC_Handler ; 12 Parallel I/O Controller C
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DCD USART0_Handler ; 13 USART 0
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DCD USART1_Handler ; 14 USART 1
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DCD USART2_Handler ; 15 USART 2
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DCD PIOD_Handler ; 16 Parallel I/O Controller D
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DCD PIOE_Handler ; 17 Parallel I/O Controller E
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DCD HSMCI_Handler ; 18 Multimedia Card Interface
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DCD TWIHS0_Handler ; 19 Two Wire Interface 0 HS
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DCD TWIHS1_Handler ; 20 Two Wire Interface 1 HS
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DCD SPI0_Handler ; 21 Serial Peripheral Interface 0
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DCD SSC_Handler ; 22 Synchronous Serial Controller
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DCD TC0_Handler ; 23 Timer/Counter 0
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DCD TC1_Handler ; 24 Timer/Counter 1
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DCD TC2_Handler ; 25 Timer/Counter 2
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DCD TC3_Handler ; 26 Timer/Counter 3
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DCD TC4_Handler ; 27 Timer/Counter 4
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DCD TC5_Handler ; 28 Timer/Counter 5
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DCD AFEC0_Handler ; 29 Analog Front End 0
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DCD DACC_Handler ; 30 Digital To Analog Converter
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DCD PWM0_Handler ; 31 Pulse Width Modulation 0
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DCD ICM_Handler ; 32 Integrity Check Monitor
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DCD ACC_Handler ; 33 Analog Comparator
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DCD USBHS_Handler ; 34 USB Host / Device Controller
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DCD MCAN0_Handler ; 35 MCAN Controller 0
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DCD 0 ; 36 Reserved
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DCD MCAN1_Handler ; 37 MCAN Controller 1
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DCD 0 ; 38 Reserved
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DCD GMAC_Handler ; 39 Ethernet MAC
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DCD AFEC1_Handler ; 40 Analog Front End 1
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DCD TWIHS2_Handler ; 41 Two Wire Interface 2 HS
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DCD SPI1_Handler ; 42 Serial Peripheral Interface 1
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DCD QSPI_Handler ; 43 Quad I/O Serial Peripheral Interface
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DCD UART2_Handler ; 44 UART 2
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DCD UART3_Handler ; 45 UART 3
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DCD UART4_Handler ; 46 UART 4
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DCD TC6_Handler ; 47 Timer/Counter 6
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DCD TC7_Handler ; 48 Timer/Counter 7
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DCD TC8_Handler ; 49 Timer/Counter 8
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DCD TC9_Handler ; 50 Timer/Counter 9
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DCD TC10_Handler ; 51 Timer/Counter 10
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DCD TC11_Handler ; 52 Timer/Counter 11
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DCD 0 ; 53 Reserved
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DCD 0 ; 54 Reserved
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DCD 0 ; 55 Reserved
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DCD AES_Handler ; 56 AES
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DCD TRNG_Handler ; 57 True Random Generator
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DCD XDMAC_Handler ; 58 DMA
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DCD ISI_Handler ; 59 Camera Interface
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DCD PWM1_Handler ; 60 Pulse Width Modulation 1
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DCD 0 ; 61 Reserved
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DCD SDRAMC_Handler ; 62 SDRAM Controller
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DCD RSWDT_Handler ; 63 Reinforced Secure Watchdog Timer
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT SUPC_Handler [WEAK]
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EXPORT RSTC_Handler [WEAK]
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EXPORT RTC_Handler [WEAK]
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EXPORT RTT_Handler [WEAK]
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EXPORT WDT_Handler [WEAK]
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EXPORT PMC_Handler [WEAK]
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EXPORT EFC_Handler [WEAK]
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EXPORT UART0_Handler [WEAK]
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EXPORT UART1_Handler [WEAK]
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EXPORT PIOA_Handler [WEAK]
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EXPORT PIOB_Handler [WEAK]
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EXPORT PIOC_Handler [WEAK]
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EXPORT USART0_Handler [WEAK]
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EXPORT USART1_Handler [WEAK]
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EXPORT USART2_Handler [WEAK]
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EXPORT PIOD_Handler [WEAK]
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EXPORT PIOE_Handler [WEAK]
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EXPORT HSMCI_Handler [WEAK]
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EXPORT TWIHS0_Handler [WEAK]
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EXPORT TWIHS1_Handler [WEAK]
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EXPORT SPI0_Handler [WEAK]
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EXPORT SSC_Handler [WEAK]
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EXPORT TC0_Handler [WEAK]
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EXPORT TC1_Handler [WEAK]
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EXPORT TC2_Handler [WEAK]
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EXPORT TC3_Handler [WEAK]
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EXPORT TC4_Handler [WEAK]
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EXPORT TC5_Handler [WEAK]
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EXPORT AFEC0_Handler [WEAK]
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EXPORT DACC_Handler [WEAK]
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EXPORT PWM0_Handler [WEAK]
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EXPORT ICM_Handler [WEAK]
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EXPORT ACC_Handler [WEAK]
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EXPORT USBHS_Handler [WEAK]
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EXPORT MCAN0_Handler [WEAK]
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EXPORT MCAN1_Handler [WEAK]
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EXPORT GMAC_Handler [WEAK]
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EXPORT AFEC1_Handler [WEAK]
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EXPORT TWIHS2_Handler [WEAK]
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EXPORT SPI1_Handler [WEAK]
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EXPORT QSPI_Handler [WEAK]
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EXPORT UART2_Handler [WEAK]
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EXPORT UART3_Handler [WEAK]
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EXPORT UART4_Handler [WEAK]
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EXPORT TC6_Handler [WEAK]
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EXPORT TC7_Handler [WEAK]
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EXPORT TC8_Handler [WEAK]
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EXPORT TC9_Handler [WEAK]
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EXPORT TC10_Handler [WEAK]
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EXPORT TC11_Handler [WEAK]
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EXPORT AES_Handler [WEAK]
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EXPORT TRNG_Handler [WEAK]
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EXPORT XDMAC_Handler [WEAK]
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EXPORT ISI_Handler [WEAK]
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EXPORT PWM1_Handler [WEAK]
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EXPORT SDRAMC_Handler [WEAK]
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EXPORT RSWDT_Handler [WEAK]
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SUPC_Handler
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RSTC_Handler
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RTC_Handler
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RTT_Handler
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WDT_Handler
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PMC_Handler
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EFC_Handler
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UART0_Handler
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UART1_Handler
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PIOA_Handler
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PIOB_Handler
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PIOC_Handler
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USART0_Handler
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USART1_Handler
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USART2_Handler
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PIOD_Handler
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PIOE_Handler
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HSMCI_Handler
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TWIHS0_Handler
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TWIHS1_Handler
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SPI0_Handler
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SSC_Handler
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TC0_Handler
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TC1_Handler
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TC2_Handler
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TC3_Handler
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TC4_Handler
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TC5_Handler
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AFEC0_Handler
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DACC_Handler
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PWM0_Handler
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ICM_Handler
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ACC_Handler
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USBHS_Handler
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MCAN0_Handler
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MCAN1_Handler
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GMAC_Handler
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AFEC1_Handler
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TWIHS2_Handler
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SPI1_Handler
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QSPI_Handler
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UART2_Handler
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UART3_Handler
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UART4_Handler
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TC6_Handler
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TC7_Handler
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TC8_Handler
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TC9_Handler
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TC10_Handler
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TC11_Handler
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AES_Handler
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TRNG_Handler
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XDMAC_Handler
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ISI_Handler
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PWM1_Handler
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SDRAMC_Handler
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RSWDT_Handler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END

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