Core.md

Rocket/tile/BaseTile

Generic core class.

---

trait CoreParams

The parameter needed by all core implementaions.

• useVM Boolean (param) whether to support virtual memory.
• useUser Boolean (param) whether to support user mode.
• useDebug Boolean (param) whether to support the run-control debug.
• useAtomics Boolean (param) whether to support the RISC-V A extension.
• useCompressed Boolean (param) whether to support the RISC-V C extension.
• mulDiv Option[MulDivParams] (param) (optional) the parameter class for the integer multiplier (divider).
• fpu Option[FPUParams] (param) (optional) the parameter class for the floating point unit.
• fetchWidth Int
  Set the instruction fetcher's data width to fetchWidth * instBits bits (currently fixed to 32 for Rocket).
• decodeWidth Int number of instructions to be decoded per cycle.
• retireWidth Int number of instructions to be commited per cycle.
• instBits Int the size of the smallest instruction (16 for RVC otherwise 32).
• nLocalInterrupts Int
  Number of local interrupt lines (which are directly fed to the MIP CSR). (is this spec compatible or Rocket special?)
• nL2TLBEntries Int number of L2 TLB entries (added by PR #849, not exactly sure what is this L2 TLB and PTW).

trait HasCoreParameters

Apply CoreParam to local variables.

trait HasCoreParameters extends HasTileParameters {
  val coreParams: CoreParams = tileParams.core

Content omitted.

abstract class CoreModule

Generic core implementation.

abstract class CoreModule(implicit val p: Parameters) extends Module
  with HasCoreParameters

abstract class CoreBundle

Base bundle for core IO.

abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
  with HasCoreParameters

trait HasCoreIO

Core IO specific to Rocket-like.

trait HasCoreIO extends HasTileParameters {
  implicit val p: Parameters
  val io = new CoreBundle()(p) with HasExternallyDrivenTileConstants {
    val interrupts = new TileInterrupts().asInput
    val imem  = new FrontendIO
    val dmem = new HellaCacheIO
    val ptw = new DatapathPTWIO().flip
    val fpu = new FPUCoreIO().flip
    val rocc = new RoCCCoreIO().flip
  }
}

• port inherited from HasExternallyDrivenTileConstants
  • hartid UInt the hartid.
    
  • resetVector UInt the reset pc address.
• interrupts TileInterrupts interrupts input.
• imem FrontendIO instruction fetch interface with the instruction cache.
• dmem HellaCacheIO data interface with the data cache / scratchpad.
• ptw DatapathPTWIO interface with the hardware page table walker.
• fpu FPUCoreIO interface with the floating point unit.
• rocc RoCCoreIO interface with the Rocket custom coprocessor.

_{Last updated: 27/07/2017
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