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vivado.log
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#-----------------------------------------------------------
# Vivado v2020.2 (64-bit)
# SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020
# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
# Start of session at: Mon May 9 11:30:44 2022
# Process ID: 25040
# Current directory: E:/Github/Simple RISC
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent8320 E:\Github\Simple RISC\simple_risc.xpr
# Log file: E:/Github/Simple RISC/vivado.log
# Journal file: E:/Github/Simple RISC\vivado.jou
#-----------------------------------------------------------
start_gui
open_project {E:/Github/Simple RISC/simple_risc.xpr}
INFO: [Project 1-313] Project file moved from 'E:/FPGA_Workspace/Simple RISC' since last save.
WARNING: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'E:/Github/Simple RISC/simple_risc.gen/sources_1', nor could it be found using path 'E:/FPGA_Workspace/Simple RISC/simple_risc.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'D:/Vivado/Vivado/2020.2/data/ip'.
update_compile_order -fileset sources_1
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7vx485tffg1157-1
Top: risc_cpu
INFO: [Device 21-403] Loading part xc7vx485tffg1157-1
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1768.609 ; gain = 242.730
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'risc_cpu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v:23]
INFO: [Synth 8-6157] synthesizing module 'clock_manager' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v:23]
Parameter S1 bound to: 8'b00000001
Parameter S2 bound to: 8'b00000010
Parameter S3 bound to: 8'b00000100
Parameter S4 bound to: 8'b00001000
Parameter S5 bound to: 8'b00010000
Parameter S6 bound to: 8'b00100000
Parameter S7 bound to: 8'b01000000
Parameter S8 bound to: 8'b10000000
Parameter IDLE bound to: 8'b00000000
INFO: [Synth 8-6155] done synthesizing module 'clock_manager' (1#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v:23]
INFO: [Synth 8-6157] synthesizing module 'command_register' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v:23]
INFO: [Synth 8-6155] done synthesizing module 'command_register' (2#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v:23]
INFO: [Synth 8-6157] synthesizing module 'accumulator' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v:23]
INFO: [Synth 8-6155] done synthesizing module 'accumulator' (3#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v:23]
INFO: [Synth 8-6157] synthesizing module 'alu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:23]
Parameter HLT bound to: 3'b000
Parameter SKZ bound to: 3'b001
Parameter ADD bound to: 3'b010
Parameter ANDD bound to: 3'b011
Parameter XORR bound to: 3'b100
Parameter LDA bound to: 3'b101
Parameter STO bound to: 3'b110
Parameter JMP bound to: 3'b111
INFO: [Synth 8-226] default block is never used [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:48]
INFO: [Synth 8-6155] done synthesizing module 'alu' (4#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:23]
INFO: [Synth 8-6157] synthesizing module 'condition_control' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:23]
Parameter HLT bound to: 3'b000
Parameter SKZ bound to: 3'b001
Parameter ADD bound to: 3'b010
Parameter ANDD bound to: 3'b011
Parameter XORR bound to: 3'b100
Parameter LDA bound to: 3'b101
Parameter STO bound to: 3'b110
Parameter JMP bound to: 3'b111
Parameter IDLE bound to: 8'b00000000
Parameter S1 bound to: 8'b00000001
Parameter S2 bound to: 8'b00000010
Parameter S3 bound to: 8'b00000100
Parameter S4 bound to: 8'b00001000
Parameter S5 bound to: 8'b00010000
Parameter S6 bound to: 8'b00100000
Parameter S7 bound to: 8'b01000000
Parameter S8 bound to: 8'b10000000
ERROR: [Synth 8-91] ambiguous clock in event control [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:91]
ERROR: [Synth 8-6156] failed synthesizing module 'condition_control' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:23]
ERROR: [Synth 8-6156] failed synthesizing module 'risc_cpu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1844.508 ; gain = 318.629
---------------------------------------------------------------------------------
RTL Elaboration failed
12 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7vx485tffg1157-1
Top: risc_cpu
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1844.508 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'risc_cpu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v:23]
INFO: [Synth 8-6157] synthesizing module 'clock_manager' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v:23]
Parameter S1 bound to: 8'b00000001
Parameter S2 bound to: 8'b00000010
Parameter S3 bound to: 8'b00000100
Parameter S4 bound to: 8'b00001000
Parameter S5 bound to: 8'b00010000
Parameter S6 bound to: 8'b00100000
Parameter S7 bound to: 8'b01000000
Parameter S8 bound to: 8'b10000000
Parameter IDLE bound to: 8'b00000000
INFO: [Synth 8-6155] done synthesizing module 'clock_manager' (1#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v:23]
INFO: [Synth 8-6157] synthesizing module 'command_register' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v:23]
INFO: [Synth 8-6155] done synthesizing module 'command_register' (2#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v:23]
INFO: [Synth 8-6157] synthesizing module 'accumulator' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v:23]
INFO: [Synth 8-6155] done synthesizing module 'accumulator' (3#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v:23]
INFO: [Synth 8-6157] synthesizing module 'alu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:23]
Parameter HLT bound to: 3'b000
Parameter SKZ bound to: 3'b001
Parameter ADD bound to: 3'b010
Parameter ANDD bound to: 3'b011
Parameter XORR bound to: 3'b100
Parameter LDA bound to: 3'b101
Parameter STO bound to: 3'b110
Parameter JMP bound to: 3'b111
INFO: [Synth 8-226] default block is never used [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:48]
INFO: [Synth 8-6155] done synthesizing module 'alu' (4#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:23]
INFO: [Synth 8-6157] synthesizing module 'condition_control' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:23]
Parameter HLT bound to: 3'b000
Parameter SKZ bound to: 3'b001
Parameter ADD bound to: 3'b010
Parameter ANDD bound to: 3'b011
Parameter XORR bound to: 3'b100
Parameter LDA bound to: 3'b101
Parameter STO bound to: 3'b110
Parameter JMP bound to: 3'b111
Parameter IDLE bound to: 8'b00000000
Parameter S1 bound to: 8'b00000001
Parameter S2 bound to: 8'b00000010
Parameter S3 bound to: 8'b00000100
Parameter S4 bound to: 8'b00001000
Parameter S5 bound to: 8'b00010000
Parameter S6 bound to: 8'b00100000
Parameter S7 bound to: 8'b01000000
Parameter S8 bound to: 8'b10000000
ERROR: [Synth 8-91] ambiguous clock in event control [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:91]
ERROR: [Synth 8-6156] failed synthesizing module 'condition_control' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:23]
ERROR: [Synth 8-6156] failed synthesizing module 'risc_cpu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1844.508 ; gain = 0.000
---------------------------------------------------------------------------------
RTL Elaboration failed
11 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Vivado_Tcl 4-5] Elaboration failed - please see the console for details
synth_design -rtl -rtl_skip_mlo -name rtl_1
Command: synth_design -rtl -rtl_skip_mlo -name rtl_1
Starting synth_design
Using part: xc7vx485tffg1157-1
Top: risc_cpu
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1844.508 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'risc_cpu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v:23]
INFO: [Synth 8-6157] synthesizing module 'clock_manager' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v:23]
Parameter S1 bound to: 8'b00000001
Parameter S2 bound to: 8'b00000010
Parameter S3 bound to: 8'b00000100
Parameter S4 bound to: 8'b00001000
Parameter S5 bound to: 8'b00010000
Parameter S6 bound to: 8'b00100000
Parameter S7 bound to: 8'b01000000
Parameter S8 bound to: 8'b10000000
Parameter IDLE bound to: 8'b00000000
INFO: [Synth 8-6155] done synthesizing module 'clock_manager' (1#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/clock_manager.v:23]
INFO: [Synth 8-6157] synthesizing module 'command_register' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v:23]
INFO: [Synth 8-6155] done synthesizing module 'command_register' (2#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/command_register.v:23]
INFO: [Synth 8-6157] synthesizing module 'accumulator' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v:23]
INFO: [Synth 8-6155] done synthesizing module 'accumulator' (3#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/accumulator.v:23]
INFO: [Synth 8-6157] synthesizing module 'alu' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:23]
Parameter HLT bound to: 3'b000
Parameter SKZ bound to: 3'b001
Parameter ADD bound to: 3'b010
Parameter ANDD bound to: 3'b011
Parameter XORR bound to: 3'b100
Parameter LDA bound to: 3'b101
Parameter STO bound to: 3'b110
Parameter JMP bound to: 3'b111
INFO: [Synth 8-226] default block is never used [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:48]
INFO: [Synth 8-6155] done synthesizing module 'alu' (4#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/alu.v:23]
INFO: [Synth 8-6157] synthesizing module 'condition_control' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:23]
Parameter HLT bound to: 3'b000
Parameter SKZ bound to: 3'b001
Parameter ADD bound to: 3'b010
Parameter ANDD bound to: 3'b011
Parameter XORR bound to: 3'b100
Parameter LDA bound to: 3'b101
Parameter STO bound to: 3'b110
Parameter JMP bound to: 3'b111
Parameter IDLE bound to: 8'b00000000
Parameter S1 bound to: 8'b00000001
Parameter S2 bound to: 8'b00000010
Parameter S3 bound to: 8'b00000100
Parameter S4 bound to: 8'b00001000
Parameter S5 bound to: 8'b00010000
Parameter S6 bound to: 8'b00100000
Parameter S7 bound to: 8'b01000000
Parameter S8 bound to: 8'b10000000
INFO: [Synth 8-6155] done synthesizing module 'condition_control' (5#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/condition_control.v:23]
INFO: [Synth 8-6157] synthesizing module 'data_controller' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/data_controller.v:23]
INFO: [Synth 8-6155] done synthesizing module 'data_controller' (6#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/data_controller.v:23]
INFO: [Synth 8-6157] synthesizing module 'address_multiplexer' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/address_multiplexer.v:23]
INFO: [Synth 8-6155] done synthesizing module 'address_multiplexer' (7#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/address_multiplexer.v:23]
INFO: [Synth 8-6157] synthesizing module 'program_counter' [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/program_counter.v:23]
INFO: [Synth 8-6155] done synthesizing module 'program_counter' (8#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/program_counter.v:23]
INFO: [Synth 8-6155] done synthesizing module 'risc_cpu' (9#1) [E:/Github/Simple RISC/simple_risc.srcs/sources_1/new/risc_cpu.v:23]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1862.461 ; gain = 17.953
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1885.402 ; gain = 40.895
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1885.402 ; gain = 40.895
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1885.402 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2020.945 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
RTL Elaboration Complete: : Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 2204.711 ; gain = 360.203
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:08 . Memory (MB): peak = 2204.711 ; gain = 360.203
exit
INFO: [Common 17-206] Exiting Vivado at Mon May 9 11:34:52 2022...