Bump Mill 0.11.1, Scala 2.13.10, and Chisel 3.6.0 (OpenXiangShan#67)

Co-authored-by: Haojin Tang <[email protected]>

Author: poemonsense

.github/workflows/main.yml

@@ -40,7 +40,7 @@ jobs:
       - name: Setup Mill
         uses: jodersky/[email protected]
         with:
-          mill-version: 0.9.8
+          mill-version: 0.11.1
 
       # - name: Check scalafmt
       #   run: make checkformat

.mill-version

@@ -1 +1 @@
-0.9.8
+0.11.1

HuanCun

@@ -4,15 +4,15 @@ import scalafmt._
 import os.Path
 import publish._
 import $file.`rocket-chip`.common
+import $file.`rocket-chip`.common
 import $file.`rocket-chip`.cde.common
 import $file.`rocket-chip`.hardfloat.build
 
 val defaultVersions = Map(
-  "chisel3" -> "3.5.4",
-  "chisel3-plugin" -> "3.5.4",
-  "chiseltest" -> "0.3.2",
-  "scala" -> "2.12.13",
-  "scalatest" -> "3.2.7"
+  "chisel3" -> "3.6.0",
+  "chisel3-plugin" -> "3.6.0",
+  "chiseltest" -> "0.6.2",
+  "scala" -> "2.13.10",
 )
 
 def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = {
@@ -23,98 +23,91 @@ def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = fa
     ivy"$org::$dep:$version"
 }
 
-trait CommonModule extends ScalaModule {
-  override def scalaVersion = defaultVersions("scala")
+trait HasChisel extends ScalaModule {
+  def chiselModule: Option[ScalaModule] = None
 
-  override def scalacOptions = Seq("-Xsource:2.11")
+  def chiselPluginJar: T[Option[PathRef]] = None
 
-  val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
-  val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.4"
+  def chiselIvy: Option[Dep] = Some(getVersion("chisel3"))
 
-  override def compileIvyDeps = Agg(macroParadise)
-  override def scalacPluginIvyDeps = Agg(macroParadise, chisel3Plugin)
+  def chiselPluginIvy: Option[Dep] = Some(getVersion("chisel3-plugin", cross=true))
 
-}
+  override def scalaVersion = defaultVersions("scala")
 
-object rocketchip extends `rocket-chip`.common.CommonRocketChip {
+  override def scalacOptions = super.scalacOptions() ++
+    Agg("-language:reflectiveCalls", "-Ymacro-annotations", "-Ytasty-reader")
 
-  val rcPath = os.pwd / "rocket-chip"
+  override def ivyDeps = super.ivyDeps() ++ Agg(chiselIvy.get)
 
-  override def scalaVersion = defaultVersions("scala")
+  override def scalacPluginIvyDeps = super.scalacPluginIvyDeps() ++ Agg(chiselPluginIvy.get)
+}
 
-  override def scalacOptions = Seq("-Xsource:2.11")
+object rocketchip extends `rocket-chip`.common.RocketChipModule with HasChisel {
 
+  val rcPath = os.pwd / "rocket-chip"
   override def millSourcePath = rcPath
 
-  object cdeRocket extends `rocket-chip`.cde.common.CDEModule with PublishModule {
-    override def millSourcePath = rcPath / "cde" / "cde"
-
-    override def scalaVersion = T {
-      rocketchip.scalaVersion()
-    }
+  def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0"
 
-    override def pomSettings = T {
-      rocketchip.pomSettings()
-    }
+  def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5"
 
-    override def publishVersion = T {
-      rocketchip.publishVersion()
-    }
+  object macros extends `rocket-chip`.common.MacrosModule with HasChisel {
+    def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${scalaVersion}"
   }
 
-  object hardfloatRocket extends `rocket-chip`.hardfloat.build.hardfloat {
-    override def millSourcePath = rcPath / "hardfloat"
-
-    override def scalaVersion = T {
-      rocketchip.scalaVersion()
-    }
-
-    def chisel3IvyDeps = if(chisel3Module.isEmpty) Agg(
-      `rocket-chip`.common.getVersion("chisel3")
-    ) else Agg.empty[Dep]
-
-    def chisel3PluginIvyDeps = Agg(`rocket-chip`.common.getVersion("chisel3-plugin", cross=true))
+  object cde extends `rocket-chip`.cde.common.CDEModule with HasChisel {
+    override def millSourcePath = rcPath / "cde" / "cde"
   }
 
-  def hardfloatModule = hardfloatRocket
+  object hardfloat extends `rocket-chip`.hardfloat.common.HardfloatModule with HasChisel {
+    override def millSourcePath = rcPath / "hardfloat" / "hardfloat"
+  }
 
-  def cdeModule = cdeRocket
+  def macrosModule = macros
 
-}
+  def hardfloatModule = hardfloat
 
-object utility extends SbtModule with ScalafmtModule with CommonModule {
+  def cdeModule = cde
 
-   override def ivyDeps = Agg(`rocket-chip`.common.getVersion("chisel3"))
+}
 
-   override def millSourcePath = os.pwd / "utility"
+object utility extends SbtModule with HasChisel {
+  override def millSourcePath = os.pwd / "utility"
 
-   override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip)
  }
 
-object huancun extends SbtModule with ScalafmtModule with CommonModule {
+object huancun extends SbtModule with HasChisel {
   override def millSourcePath = os.pwd / "HuanCun"
   override def moduleDeps = super.moduleDeps ++ Seq(
     rocketchip, utility
   )
 }
 
-object CoupledL2 extends SbtModule with ScalafmtModule with CommonModule {
+trait CoupledL2Module extends ScalaModule {
+
+  def rocketModule: ScalaModule
+
+  def utilityModule: ScalaModule
+
+  def huancunModule: ScalaModule
+
+  override def moduleDeps = super.moduleDeps ++ Seq(rocketModule, utilityModule, huancunModule)
+}
+
+object CoupledL2 extends SbtModule with HasChisel with CoupledL2Module {
 
   override def millSourcePath = millOuterCtx.millSourcePath
 
+  def rocketModule: ScalaModule = rocketchip
 
-  override def ivyDeps = super.ivyDeps() ++ Agg(
-    getVersion("chisel3"),
-    getVersion("chiseltest"),
-  )
+  def utilityModule: ScalaModule = utility
 
-  override def moduleDeps = super.moduleDeps ++ Seq(rocketchip, utility, huancun)
+  def huancunModule: ScalaModule = huancun
 
-  object test extends Tests {
+  object test extends SbtModuleTests with TestModule.ScalaTest {
     override def ivyDeps = super.ivyDeps() ++ Agg(
-      getVersion("scalatest","org.scalatest")
+      getVersion("chiseltest"),
     )
-
-    def testFramework = "org.scalatest.tools.Framework"
   }
 }

build.sc

@@ -48,12 +48,7 @@ case class L1Param
 
 // Pass virtual address of upper level cache
 case object VaddrKey extends ControlKey[UInt]("vaddr")
-case class VaddrField(width: Int) extends BundleField(VaddrKey) {
-  override def data: UInt = Output(UInt(width.W))
-  override def default(x: UInt): Unit = {
-    x := 0.U(width.W)
-  }
-}
+case class VaddrField(width: Int) extends BundleField[UInt](VaddrKey, Output(UInt(width.W)), _ := 0.U(width.W))
 
 case class L2Param
 (

rocket-chip

@@ -322,7 +322,7 @@ class TestTop_L2L3L2()(implicit p: Parameters) extends LazyModule {
   val l1d_nodes = (0 until nrL2).map(i => createClientNode(s"l1d$i", 32))
   val master_nodes = l1d_nodes
 
-  val l2_nodes = (0 until nrL2).map(i => LazyModule(new CoupledL2()(new Config((_, _, _) => {
+  val coupledL2 = (0 until nrL2).map(i => LazyModule(new CoupledL2()(new Config((_, _, _) => {
     case L2ParamKey => L2Param(
       name = s"l2$i",
       ways = 4,
@@ -331,7 +331,8 @@ class TestTop_L2L3L2()(implicit p: Parameters) extends LazyModule {
       echoField = Seq(DirtyField()),
       hartIds = Seq{i}
     )
-  }))).node)
+  }))))
+  val l2_nodes = coupledL2.map(_.node)
 
   val l3 = LazyModule(new HuanCun()(new Config((_, _, _) => {
     case HCCacheParamsKey => HCCacheParameters(
@@ -382,6 +383,7 @@ class TestTop_L2L3L2()(implicit p: Parameters) extends LazyModule {
     dontTouch(clean)
     dontTouch(dump)
 
+    coupledL2.foreach(_.module.io.debugTopDown := DontCare)
     master_nodes.zipWithIndex.foreach {
       case (node, i) =>
         node.makeIOs()(ValName(s"master_port_$i"))