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stm32f411.h
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#pragma once
// Generated enums and structures for device STM32F411 version 1.1
// Generated by genstruct, DO NOT EDIT.
#include "cortex_m4.h"
#include <stdint.h>
#define __I volatile const // 'read only' permissions
#define __O volatile // 'write only' permissions
#define __IO volatile // 'read / write' permissions
/* Analog-to-digital converter */
struct ADC1_Type {
__IO uint8_t SR; // @0 status register
uint8_t RESERVED0[3]; // @1
__IO uint32_t CR1; // @4 control register 1
__IO uint32_t CR2; // @8 control register 2
__IO uint32_t SMPR1; // @12 sample time register 1
__IO uint32_t SMPR2; // @16 sample time register 2
__IO uint16_t JOFR1; // @20 injected channel data offset register x
uint8_t RESERVED1[2]; // @22
__IO uint16_t JOFR2; // @24 injected channel data offset register x
uint8_t RESERVED2[2]; // @26
__IO uint16_t JOFR3; // @28 injected channel data offset register x
uint8_t RESERVED3[2]; // @30
__IO uint16_t JOFR4; // @32 injected channel data offset register x
uint8_t RESERVED4[2]; // @34
__IO uint16_t HTR; // @36 watchdog higher threshold register
uint8_t RESERVED5[2]; // @38
__IO uint16_t LTR; // @40 watchdog lower threshold register
uint8_t RESERVED6[2]; // @42
__IO uint32_t SQR1; // @44 regular sequence register 1
__IO uint32_t SQR2; // @48 regular sequence register 2
__IO uint32_t SQR3; // @52 regular sequence register 3
__IO uint32_t JSQR; // @56 injected sequence register
__I uint16_t JDR1; // @60 injected data register x
uint8_t RESERVED7[2]; // @62
__I uint16_t JDR2; // @64 injected data register x
uint8_t RESERVED8[2]; // @66
__I uint16_t JDR3; // @68 injected data register x
uint8_t RESERVED9[2]; // @70
__I uint16_t JDR4; // @72 injected data register x
uint8_t RESERVED10[2]; // @74
__I uint16_t DR; // @76 regular data register
};
// ADC1->SR status register
enum {
ADC1_SR_OVR = 1UL << 5, // Overrun
ADC1_SR_STRT = 1UL << 4, // Regular channel start flag
ADC1_SR_JSTRT = 1UL << 3, // Injected channel start flag
ADC1_SR_JEOC = 1UL << 2, // Injected channel end of conversion
ADC1_SR_EOC = 1UL << 1, // Regular channel end of conversion
ADC1_SR_AWD = 1UL << 0, // Analog watchdog flag
};
// ADC1->CR1 control register 1
enum {
ADC1_CR1_OVRIE = 1UL << 26, // Overrun interrupt enable
ADC1_CR1_RES = ((1UL << 2) - 1) << 24, // Resolution
ADC1_CR1_AWDEN = 1UL << 23, // Analog watchdog enable on regular channels
ADC1_CR1_JAWDEN = 1UL << 22, // Analog watchdog enable on injected channels
ADC1_CR1_DISCNUM = ((1UL << 3) - 1) << 13, // Discontinuous mode channel count
ADC1_CR1_JDISCEN = 1UL << 12, // Discontinuous mode on injected channels
ADC1_CR1_DISCEN = 1UL << 11, // Discontinuous mode on regular channels
ADC1_CR1_JAUTO = 1UL << 10, // Automatic injected group conversion
ADC1_CR1_AWDSGL = 1UL << 9, // Enable the watchdog on a single channel in scan mode
ADC1_CR1_SCAN = 1UL << 8, // Scan mode
ADC1_CR1_JEOCIE = 1UL << 7, // Interrupt enable for injected channels
ADC1_CR1_AWDIE = 1UL << 6, // Analog watchdog interrupt enable
ADC1_CR1_EOCIE = 1UL << 5, // Interrupt enable for EOC
ADC1_CR1_AWDCH = ((1UL << 5) - 1) << 0, // Analog watchdog channel select bits
};
inline void adc1_cr1_set_res(struct ADC1_Type* p, uint32_t val) { p->CR1 = (p->CR1 & ~ADC1_CR1_RES) | ((val << 24) & ADC1_CR1_RES); }
inline void adc1_cr1_set_discnum(struct ADC1_Type* p, uint32_t val) {
p->CR1 = (p->CR1 & ~ADC1_CR1_DISCNUM) | ((val << 13) & ADC1_CR1_DISCNUM);
}
inline void adc1_cr1_set_awdch(struct ADC1_Type* p, uint32_t val) { p->CR1 = (p->CR1 & ~ADC1_CR1_AWDCH) | ((val << 0) & ADC1_CR1_AWDCH); }
inline uint32_t adc1_cr1_get_res(struct ADC1_Type* p) { return (p->CR1 & ADC1_CR1_RES) >> 24; }
inline uint32_t adc1_cr1_get_discnum(struct ADC1_Type* p) { return (p->CR1 & ADC1_CR1_DISCNUM) >> 13; }
inline uint32_t adc1_cr1_get_awdch(struct ADC1_Type* p) { return (p->CR1 & ADC1_CR1_AWDCH) >> 0; }
// ADC1->CR2 control register 2
enum {
ADC1_CR2_SWSTART = 1UL << 30, // Start conversion of regular channels
ADC1_CR2_EXTEN = ((1UL << 2) - 1) << 28, // External trigger enable for regular channels
ADC1_CR2_EXTSEL = ((1UL << 4) - 1) << 24, // External event select for regular group
ADC1_CR2_JSWSTART = 1UL << 22, // Start conversion of injected channels
ADC1_CR2_JEXTEN = ((1UL << 2) - 1) << 20, // External trigger enable for injected channels
ADC1_CR2_JEXTSEL = ((1UL << 4) - 1) << 16, // External event select for injected group
ADC1_CR2_ALIGN = 1UL << 11, // Data alignment
ADC1_CR2_EOCS = 1UL << 10, // End of conversion selection
ADC1_CR2_DDS = 1UL << 9, // DMA disable selection (for single ADC mode)
ADC1_CR2_DMA = 1UL << 8, // Direct memory access mode (for single ADC mode)
ADC1_CR2_CONT = 1UL << 1, // Continuous conversion
ADC1_CR2_ADON = 1UL << 0, // A/D Converter ON / OFF
};
inline void adc1_cr2_set_exten(struct ADC1_Type* p, uint32_t val) { p->CR2 = (p->CR2 & ~ADC1_CR2_EXTEN) | ((val << 28) & ADC1_CR2_EXTEN); }
inline void adc1_cr2_set_extsel(struct ADC1_Type* p, uint32_t val) {
p->CR2 = (p->CR2 & ~ADC1_CR2_EXTSEL) | ((val << 24) & ADC1_CR2_EXTSEL);
}
inline void adc1_cr2_set_jexten(struct ADC1_Type* p, uint32_t val) {
p->CR2 = (p->CR2 & ~ADC1_CR2_JEXTEN) | ((val << 20) & ADC1_CR2_JEXTEN);
}
inline void adc1_cr2_set_jextsel(struct ADC1_Type* p, uint32_t val) {
p->CR2 = (p->CR2 & ~ADC1_CR2_JEXTSEL) | ((val << 16) & ADC1_CR2_JEXTSEL);
}
inline uint32_t adc1_cr2_get_exten(struct ADC1_Type* p) { return (p->CR2 & ADC1_CR2_EXTEN) >> 28; }
inline uint32_t adc1_cr2_get_extsel(struct ADC1_Type* p) { return (p->CR2 & ADC1_CR2_EXTSEL) >> 24; }
inline uint32_t adc1_cr2_get_jexten(struct ADC1_Type* p) { return (p->CR2 & ADC1_CR2_JEXTEN) >> 20; }
inline uint32_t adc1_cr2_get_jextsel(struct ADC1_Type* p) { return (p->CR2 & ADC1_CR2_JEXTSEL) >> 16; }
// ADC1->JOFR1 injected channel data offset register x
enum {
ADC1_JOFR1_JOFFSET1 = ((1UL << 12) - 1) << 0, // Data offset for injected channel x
};
inline void adc1_jofr1_set_joffset1(struct ADC1_Type* p, uint32_t val) {
p->JOFR1 = (p->JOFR1 & ~ADC1_JOFR1_JOFFSET1) | ((val << 0) & ADC1_JOFR1_JOFFSET1);
}
inline uint32_t adc1_jofr1_get_joffset1(struct ADC1_Type* p) { return (p->JOFR1 & ADC1_JOFR1_JOFFSET1) >> 0; }
// ADC1->JOFR2 injected channel data offset register x
enum {
ADC1_JOFR2_JOFFSET2 = ((1UL << 12) - 1) << 0, // Data offset for injected channel x
};
inline void adc1_jofr2_set_joffset2(struct ADC1_Type* p, uint32_t val) {
p->JOFR2 = (p->JOFR2 & ~ADC1_JOFR2_JOFFSET2) | ((val << 0) & ADC1_JOFR2_JOFFSET2);
}
inline uint32_t adc1_jofr2_get_joffset2(struct ADC1_Type* p) { return (p->JOFR2 & ADC1_JOFR2_JOFFSET2) >> 0; }
// ADC1->JOFR3 injected channel data offset register x
enum {
ADC1_JOFR3_JOFFSET3 = ((1UL << 12) - 1) << 0, // Data offset for injected channel x
};
inline void adc1_jofr3_set_joffset3(struct ADC1_Type* p, uint32_t val) {
p->JOFR3 = (p->JOFR3 & ~ADC1_JOFR3_JOFFSET3) | ((val << 0) & ADC1_JOFR3_JOFFSET3);
}
inline uint32_t adc1_jofr3_get_joffset3(struct ADC1_Type* p) { return (p->JOFR3 & ADC1_JOFR3_JOFFSET3) >> 0; }
// ADC1->JOFR4 injected channel data offset register x
enum {
ADC1_JOFR4_JOFFSET4 = ((1UL << 12) - 1) << 0, // Data offset for injected channel x
};
inline void adc1_jofr4_set_joffset4(struct ADC1_Type* p, uint32_t val) {
p->JOFR4 = (p->JOFR4 & ~ADC1_JOFR4_JOFFSET4) | ((val << 0) & ADC1_JOFR4_JOFFSET4);
}
inline uint32_t adc1_jofr4_get_joffset4(struct ADC1_Type* p) { return (p->JOFR4 & ADC1_JOFR4_JOFFSET4) >> 0; }
// ADC1->HTR watchdog higher threshold register
enum {
ADC1_HTR_HT = ((1UL << 12) - 1) << 0, // Analog watchdog higher threshold
};
inline void adc1_htr_set_ht(struct ADC1_Type* p, uint32_t val) { p->HTR = (p->HTR & ~ADC1_HTR_HT) | ((val << 0) & ADC1_HTR_HT); }
inline uint32_t adc1_htr_get_ht(struct ADC1_Type* p) { return (p->HTR & ADC1_HTR_HT) >> 0; }
// ADC1->LTR watchdog lower threshold register
enum {
ADC1_LTR_LT = ((1UL << 12) - 1) << 0, // Analog watchdog lower threshold
};
inline void adc1_ltr_set_lt(struct ADC1_Type* p, uint32_t val) { p->LTR = (p->LTR & ~ADC1_LTR_LT) | ((val << 0) & ADC1_LTR_LT); }
inline uint32_t adc1_ltr_get_lt(struct ADC1_Type* p) { return (p->LTR & ADC1_LTR_LT) >> 0; }
// ADC1->SQR1 regular sequence register 1
enum {
ADC1_SQR1_L = ((1UL << 4) - 1) << 20, // Regular channel sequence length
ADC1_SQR1_SQ16 = ((1UL << 5) - 1) << 15, // 16th conversion in regular sequence
ADC1_SQR1_SQ15 = ((1UL << 5) - 1) << 10, // 15th conversion in regular sequence
ADC1_SQR1_SQ14 = ((1UL << 5) - 1) << 5, // 14th conversion in regular sequence
ADC1_SQR1_SQ13 = ((1UL << 5) - 1) << 0, // 13th conversion in regular sequence
};
inline void adc1_sqr1_set_l(struct ADC1_Type* p, uint32_t val) { p->SQR1 = (p->SQR1 & ~ADC1_SQR1_L) | ((val << 20) & ADC1_SQR1_L); }
inline void adc1_sqr1_set_sq16(struct ADC1_Type* p, uint32_t val) {
p->SQR1 = (p->SQR1 & ~ADC1_SQR1_SQ16) | ((val << 15) & ADC1_SQR1_SQ16);
}
inline void adc1_sqr1_set_sq15(struct ADC1_Type* p, uint32_t val) {
p->SQR1 = (p->SQR1 & ~ADC1_SQR1_SQ15) | ((val << 10) & ADC1_SQR1_SQ15);
}
inline void adc1_sqr1_set_sq14(struct ADC1_Type* p, uint32_t val) { p->SQR1 = (p->SQR1 & ~ADC1_SQR1_SQ14) | ((val << 5) & ADC1_SQR1_SQ14); }
inline void adc1_sqr1_set_sq13(struct ADC1_Type* p, uint32_t val) { p->SQR1 = (p->SQR1 & ~ADC1_SQR1_SQ13) | ((val << 0) & ADC1_SQR1_SQ13); }
inline uint32_t adc1_sqr1_get_l(struct ADC1_Type* p) { return (p->SQR1 & ADC1_SQR1_L) >> 20; }
inline uint32_t adc1_sqr1_get_sq16(struct ADC1_Type* p) { return (p->SQR1 & ADC1_SQR1_SQ16) >> 15; }
inline uint32_t adc1_sqr1_get_sq15(struct ADC1_Type* p) { return (p->SQR1 & ADC1_SQR1_SQ15) >> 10; }
inline uint32_t adc1_sqr1_get_sq14(struct ADC1_Type* p) { return (p->SQR1 & ADC1_SQR1_SQ14) >> 5; }
inline uint32_t adc1_sqr1_get_sq13(struct ADC1_Type* p) { return (p->SQR1 & ADC1_SQR1_SQ13) >> 0; }
// ADC1->SQR2 regular sequence register 2
enum {
ADC1_SQR2_SQ12 = ((1UL << 5) - 1) << 25, // 12th conversion in regular sequence
ADC1_SQR2_SQ11 = ((1UL << 5) - 1) << 20, // 11th conversion in regular sequence
ADC1_SQR2_SQ10 = ((1UL << 5) - 1) << 15, // 10th conversion in regular sequence
ADC1_SQR2_SQ9 = ((1UL << 5) - 1) << 10, // 9th conversion in regular sequence
ADC1_SQR2_SQ8 = ((1UL << 5) - 1) << 5, // 8th conversion in regular sequence
ADC1_SQR2_SQ7 = ((1UL << 5) - 1) << 0, // 7th conversion in regular sequence
};
inline void adc1_sqr2_set_sq12(struct ADC1_Type* p, uint32_t val) {
p->SQR2 = (p->SQR2 & ~ADC1_SQR2_SQ12) | ((val << 25) & ADC1_SQR2_SQ12);
}
inline void adc1_sqr2_set_sq11(struct ADC1_Type* p, uint32_t val) {
p->SQR2 = (p->SQR2 & ~ADC1_SQR2_SQ11) | ((val << 20) & ADC1_SQR2_SQ11);
}
inline void adc1_sqr2_set_sq10(struct ADC1_Type* p, uint32_t val) {
p->SQR2 = (p->SQR2 & ~ADC1_SQR2_SQ10) | ((val << 15) & ADC1_SQR2_SQ10);
}
inline void adc1_sqr2_set_sq9(struct ADC1_Type* p, uint32_t val) { p->SQR2 = (p->SQR2 & ~ADC1_SQR2_SQ9) | ((val << 10) & ADC1_SQR2_SQ9); }
inline void adc1_sqr2_set_sq8(struct ADC1_Type* p, uint32_t val) { p->SQR2 = (p->SQR2 & ~ADC1_SQR2_SQ8) | ((val << 5) & ADC1_SQR2_SQ8); }
inline void adc1_sqr2_set_sq7(struct ADC1_Type* p, uint32_t val) { p->SQR2 = (p->SQR2 & ~ADC1_SQR2_SQ7) | ((val << 0) & ADC1_SQR2_SQ7); }
inline uint32_t adc1_sqr2_get_sq12(struct ADC1_Type* p) { return (p->SQR2 & ADC1_SQR2_SQ12) >> 25; }
inline uint32_t adc1_sqr2_get_sq11(struct ADC1_Type* p) { return (p->SQR2 & ADC1_SQR2_SQ11) >> 20; }
inline uint32_t adc1_sqr2_get_sq10(struct ADC1_Type* p) { return (p->SQR2 & ADC1_SQR2_SQ10) >> 15; }
inline uint32_t adc1_sqr2_get_sq9(struct ADC1_Type* p) { return (p->SQR2 & ADC1_SQR2_SQ9) >> 10; }
inline uint32_t adc1_sqr2_get_sq8(struct ADC1_Type* p) { return (p->SQR2 & ADC1_SQR2_SQ8) >> 5; }
inline uint32_t adc1_sqr2_get_sq7(struct ADC1_Type* p) { return (p->SQR2 & ADC1_SQR2_SQ7) >> 0; }
// ADC1->SQR3 regular sequence register 3
enum {
ADC1_SQR3_SQ6 = ((1UL << 5) - 1) << 25, // 6th conversion in regular sequence
ADC1_SQR3_SQ5 = ((1UL << 5) - 1) << 20, // 5th conversion in regular sequence
ADC1_SQR3_SQ4 = ((1UL << 5) - 1) << 15, // 4th conversion in regular sequence
ADC1_SQR3_SQ3 = ((1UL << 5) - 1) << 10, // 3rd conversion in regular sequence
ADC1_SQR3_SQ2 = ((1UL << 5) - 1) << 5, // 2nd conversion in regular sequence
ADC1_SQR3_SQ1 = ((1UL << 5) - 1) << 0, // 1st conversion in regular sequence
};
inline void adc1_sqr3_set_sq6(struct ADC1_Type* p, uint32_t val) { p->SQR3 = (p->SQR3 & ~ADC1_SQR3_SQ6) | ((val << 25) & ADC1_SQR3_SQ6); }
inline void adc1_sqr3_set_sq5(struct ADC1_Type* p, uint32_t val) { p->SQR3 = (p->SQR3 & ~ADC1_SQR3_SQ5) | ((val << 20) & ADC1_SQR3_SQ5); }
inline void adc1_sqr3_set_sq4(struct ADC1_Type* p, uint32_t val) { p->SQR3 = (p->SQR3 & ~ADC1_SQR3_SQ4) | ((val << 15) & ADC1_SQR3_SQ4); }
inline void adc1_sqr3_set_sq3(struct ADC1_Type* p, uint32_t val) { p->SQR3 = (p->SQR3 & ~ADC1_SQR3_SQ3) | ((val << 10) & ADC1_SQR3_SQ3); }
inline void adc1_sqr3_set_sq2(struct ADC1_Type* p, uint32_t val) { p->SQR3 = (p->SQR3 & ~ADC1_SQR3_SQ2) | ((val << 5) & ADC1_SQR3_SQ2); }
inline void adc1_sqr3_set_sq1(struct ADC1_Type* p, uint32_t val) { p->SQR3 = (p->SQR3 & ~ADC1_SQR3_SQ1) | ((val << 0) & ADC1_SQR3_SQ1); }
inline uint32_t adc1_sqr3_get_sq6(struct ADC1_Type* p) { return (p->SQR3 & ADC1_SQR3_SQ6) >> 25; }
inline uint32_t adc1_sqr3_get_sq5(struct ADC1_Type* p) { return (p->SQR3 & ADC1_SQR3_SQ5) >> 20; }
inline uint32_t adc1_sqr3_get_sq4(struct ADC1_Type* p) { return (p->SQR3 & ADC1_SQR3_SQ4) >> 15; }
inline uint32_t adc1_sqr3_get_sq3(struct ADC1_Type* p) { return (p->SQR3 & ADC1_SQR3_SQ3) >> 10; }
inline uint32_t adc1_sqr3_get_sq2(struct ADC1_Type* p) { return (p->SQR3 & ADC1_SQR3_SQ2) >> 5; }
inline uint32_t adc1_sqr3_get_sq1(struct ADC1_Type* p) { return (p->SQR3 & ADC1_SQR3_SQ1) >> 0; }
// ADC1->JSQR injected sequence register
enum {
ADC1_JSQR_JL = ((1UL << 2) - 1) << 20, // Injected sequence length
ADC1_JSQR_JSQ4 = ((1UL << 5) - 1) << 15, // 4th conversion in injected sequence
ADC1_JSQR_JSQ3 = ((1UL << 5) - 1) << 10, // 3rd conversion in injected sequence
ADC1_JSQR_JSQ2 = ((1UL << 5) - 1) << 5, // 2nd conversion in injected sequence
ADC1_JSQR_JSQ1 = ((1UL << 5) - 1) << 0, // 1st conversion in injected sequence
};
inline void adc1_jsqr_set_jl(struct ADC1_Type* p, uint32_t val) { p->JSQR = (p->JSQR & ~ADC1_JSQR_JL) | ((val << 20) & ADC1_JSQR_JL); }
inline void adc1_jsqr_set_jsq4(struct ADC1_Type* p, uint32_t val) {
p->JSQR = (p->JSQR & ~ADC1_JSQR_JSQ4) | ((val << 15) & ADC1_JSQR_JSQ4);
}
inline void adc1_jsqr_set_jsq3(struct ADC1_Type* p, uint32_t val) {
p->JSQR = (p->JSQR & ~ADC1_JSQR_JSQ3) | ((val << 10) & ADC1_JSQR_JSQ3);
}
inline void adc1_jsqr_set_jsq2(struct ADC1_Type* p, uint32_t val) { p->JSQR = (p->JSQR & ~ADC1_JSQR_JSQ2) | ((val << 5) & ADC1_JSQR_JSQ2); }
inline void adc1_jsqr_set_jsq1(struct ADC1_Type* p, uint32_t val) { p->JSQR = (p->JSQR & ~ADC1_JSQR_JSQ1) | ((val << 0) & ADC1_JSQR_JSQ1); }
inline uint32_t adc1_jsqr_get_jl(struct ADC1_Type* p) { return (p->JSQR & ADC1_JSQR_JL) >> 20; }
inline uint32_t adc1_jsqr_get_jsq4(struct ADC1_Type* p) { return (p->JSQR & ADC1_JSQR_JSQ4) >> 15; }
inline uint32_t adc1_jsqr_get_jsq3(struct ADC1_Type* p) { return (p->JSQR & ADC1_JSQR_JSQ3) >> 10; }
inline uint32_t adc1_jsqr_get_jsq2(struct ADC1_Type* p) { return (p->JSQR & ADC1_JSQR_JSQ2) >> 5; }
inline uint32_t adc1_jsqr_get_jsq1(struct ADC1_Type* p) { return (p->JSQR & ADC1_JSQR_JSQ1) >> 0; }
/* ADC common registers */
struct ADC_COMMON_Type {
__I uint32_t CSR; // @0 ADC Common status register
__IO uint32_t CCR; // @4 ADC common control register
};
// ADC_COMMON->CSR ADC Common status register
enum {
ADC_COMMON_CSR_OVR3 = 1UL << 21, // Overrun flag of ADC3
ADC_COMMON_CSR_STRT3 = 1UL << 20, // Regular channel Start flag of ADC 3
ADC_COMMON_CSR_JSTRT3 = 1UL << 19, // Injected channel Start flag of ADC 3
ADC_COMMON_CSR_JEOC3 = 1UL << 18, // Injected channel end of conversion of ADC 3
ADC_COMMON_CSR_EOC3 = 1UL << 17, // End of conversion of ADC 3
ADC_COMMON_CSR_AWD3 = 1UL << 16, // Analog watchdog flag of ADC 3
ADC_COMMON_CSR_OVR2 = 1UL << 13, // Overrun flag of ADC 2
ADC_COMMON_CSR_STRT2 = 1UL << 12, // Regular channel Start flag of ADC 2
ADC_COMMON_CSR_JSTRT2 = 1UL << 11, // Injected channel Start flag of ADC 2
ADC_COMMON_CSR_JEOC2 = 1UL << 10, // Injected channel end of conversion of ADC 2
ADC_COMMON_CSR_EOC2 = 1UL << 9, // End of conversion of ADC 2
ADC_COMMON_CSR_AWD2 = 1UL << 8, // Analog watchdog flag of ADC 2
ADC_COMMON_CSR_OVR1 = 1UL << 5, // Overrun flag of ADC 1
ADC_COMMON_CSR_STRT1 = 1UL << 4, // Regular channel Start flag of ADC 1
ADC_COMMON_CSR_JSTRT1 = 1UL << 3, // Injected channel Start flag of ADC 1
ADC_COMMON_CSR_JEOC1 = 1UL << 2, // Injected channel end of conversion of ADC 1
ADC_COMMON_CSR_EOC1 = 1UL << 1, // End of conversion of ADC 1
ADC_COMMON_CSR_AWD1 = 1UL << 0, // Analog watchdog flag of ADC 1
};
// ADC_COMMON->CCR ADC common control register
enum {
ADC_COMMON_CCR_TSVREFE = 1UL << 23, // Temperature sensor and VREFINT enable
ADC_COMMON_CCR_VBATE = 1UL << 22, // VBAT enable
ADC_COMMON_CCR_ADCPRE = ((1UL << 2) - 1) << 16, // ADC prescaler
ADC_COMMON_CCR_DMA = ((1UL << 2) - 1) << 14, // Direct memory access mode for multi ADC mode
ADC_COMMON_CCR_DDS = 1UL << 13, // DMA disable selection for multi-ADC mode
ADC_COMMON_CCR_DELAY = ((1UL << 4) - 1) << 8, // Delay between 2 sampling phases
};
inline void adc_common_ccr_set_adcpre(struct ADC_COMMON_Type* p, uint32_t val) {
p->CCR = (p->CCR & ~ADC_COMMON_CCR_ADCPRE) | ((val << 16) & ADC_COMMON_CCR_ADCPRE);
}
inline void adc_common_ccr_set_dma(struct ADC_COMMON_Type* p, uint32_t val) {
p->CCR = (p->CCR & ~ADC_COMMON_CCR_DMA) | ((val << 14) & ADC_COMMON_CCR_DMA);
}
inline void adc_common_ccr_set_delay(struct ADC_COMMON_Type* p, uint32_t val) {
p->CCR = (p->CCR & ~ADC_COMMON_CCR_DELAY) | ((val << 8) & ADC_COMMON_CCR_DELAY);
}
inline uint32_t adc_common_ccr_get_adcpre(struct ADC_COMMON_Type* p) { return (p->CCR & ADC_COMMON_CCR_ADCPRE) >> 16; }
inline uint32_t adc_common_ccr_get_dma(struct ADC_COMMON_Type* p) { return (p->CCR & ADC_COMMON_CCR_DMA) >> 14; }
inline uint32_t adc_common_ccr_get_delay(struct ADC_COMMON_Type* p) { return (p->CCR & ADC_COMMON_CCR_DELAY) >> 8; }
/* Cryptographic processor */
struct CRC_Type {
__IO uint32_t DR; // @0 Data register
__IO uint8_t IDR; // @4 Independent Data register
uint8_t RESERVED0[3]; // @5
__O uint8_t CR; // @8 Control register
};
// CRC->CR Control register
enum {
CRC_CR_CR = 1UL << 0, // Control regidter
};
/* Debug support */
struct DBG_Type {
__I uint32_t DBGMCU_IDCODE; // @0 IDCODE
__IO uint8_t DBGMCU_CR; // @4 Control Register
uint8_t RESERVED0[3]; // @5
__IO uint32_t DBGMCU_APB1_FZ; // @8 Debug MCU APB1 Freeze registe
__IO uint32_t DBGMCU_APB2_FZ; // @12 Debug MCU APB2 Freeze registe
};
// DBG->DBGMCU_IDCODE IDCODE
enum {
DBG_DBGMCU_IDCODE_REV_ID = ((1UL << 16) - 1) << 16, // REV_ID
DBG_DBGMCU_IDCODE_DEV_ID = ((1UL << 12) - 1) << 0, // DEV_ID
};
inline uint32_t dbg_dbgmcu_idcode_get_rev_id(struct DBG_Type* p) { return (p->DBGMCU_IDCODE & DBG_DBGMCU_IDCODE_REV_ID) >> 16; }
inline uint32_t dbg_dbgmcu_idcode_get_dev_id(struct DBG_Type* p) { return (p->DBGMCU_IDCODE & DBG_DBGMCU_IDCODE_DEV_ID) >> 0; }
// DBG->DBGMCU_CR Control Register
enum {
DBG_DBGMCU_CR_TRACE_MODE = ((1UL << 2) - 1) << 6, // TRACE_MODE
DBG_DBGMCU_CR_TRACE_IOEN = 1UL << 5, // TRACE_IOEN
DBG_DBGMCU_CR_DBG_STANDBY = 1UL << 2, // DBG_STANDBY
DBG_DBGMCU_CR_DBG_STOP = 1UL << 1, // DBG_STOP
DBG_DBGMCU_CR_DBG_SLEEP = 1UL << 0, // DBG_SLEEP
};
inline void dbg_dbgmcu_cr_set_trace_mode(struct DBG_Type* p, uint32_t val) {
p->DBGMCU_CR = (p->DBGMCU_CR & ~DBG_DBGMCU_CR_TRACE_MODE) | ((val << 6) & DBG_DBGMCU_CR_TRACE_MODE);
}
inline uint32_t dbg_dbgmcu_cr_get_trace_mode(struct DBG_Type* p) { return (p->DBGMCU_CR & DBG_DBGMCU_CR_TRACE_MODE) >> 6; }
// DBG->DBGMCU_APB1_FZ Debug MCU APB1 Freeze registe
enum {
DBG_DBGMCU_APB1_FZ_DBG_I2C3SMBUS_TIMEOUT = 1UL << 23, // DBG_J2C3SMBUS_TIMEOUT
DBG_DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT = 1UL << 22, // DBG_J2C2_SMBUS_TIMEOUT
DBG_DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT = 1UL << 21, // DBG_J2C1_SMBUS_TIMEOUT
DBG_DBGMCU_APB1_FZ_DBG_IWDEG_STOP = 1UL << 12, // DBG_IWDEG_STOP
DBG_DBGMCU_APB1_FZ_DBG_WWDG_STOP = 1UL << 11, // DBG_WWDG_STOP
DBG_DBGMCU_APB1_FZ_DBG_RTC_STOP = 1UL << 10, // RTC stopped when Core is halted
DBG_DBGMCU_APB1_FZ_DBG_TIM5_STOP = 1UL << 3, // DBG_TIM5_STOP
DBG_DBGMCU_APB1_FZ_DBG_TIM4_STOP = 1UL << 2, // DBG_TIM4_STOP
DBG_DBGMCU_APB1_FZ_DBG_TIM3_STOP = 1UL << 1, // DBG_TIM3 _STOP
DBG_DBGMCU_APB1_FZ_DBG_TIM2_STOP = 1UL << 0, // DBG_TIM2_STOP
};
// DBG->DBGMCU_APB2_FZ Debug MCU APB2 Freeze registe
enum {
DBG_DBGMCU_APB2_FZ_DBG_TIM11_STOP = 1UL << 18, // TIM11 counter stopped when core is halted
DBG_DBGMCU_APB2_FZ_DBG_TIM10_STOP = 1UL << 17, // TIM10 counter stopped when core is halted
DBG_DBGMCU_APB2_FZ_DBG_TIM9_STOP = 1UL << 16, // TIM9 counter stopped when core is halted
DBG_DBGMCU_APB2_FZ_DBG_TIM1_STOP = 1UL << 0, // TIM1 counter stopped when core is halted
};
/* DMA controller */
struct DMA2_Type {
__I uint32_t LISR; // @0 low interrupt status register
__I uint32_t HISR; // @4 high interrupt status register
__O uint32_t LIFCR; // @8 low interrupt flag clear register
__O uint32_t HIFCR; // @12 high interrupt flag clear register
__IO uint32_t S0CR; // @16 stream x configuration register
__IO uint16_t S0NDTR; // @20 stream x number of data register
uint8_t RESERVED0[2]; // @22
__IO uint32_t S0PAR; // @24 stream x peripheral address register
__IO uint32_t S0M0AR; // @28 stream x memory 0 address register
__IO uint32_t S0M1AR; // @32 stream x memory 1 address register
__IO uint8_t S0FCR; // @36 stream x FIFO control register
uint8_t RESERVED1[3]; // @37
__IO uint32_t S1CR; // @40 stream x configuration register
__IO uint16_t S1NDTR; // @44 stream x number of data register
uint8_t RESERVED2[2]; // @46
__IO uint32_t S1PAR; // @48 stream x peripheral address register
__IO uint32_t S1M0AR; // @52 stream x memory 0 address register
__IO uint32_t S1M1AR; // @56 stream x memory 1 address register
__IO uint8_t S1FCR; // @60 stream x FIFO control register
uint8_t RESERVED3[3]; // @61
__IO uint32_t S2CR; // @64 stream x configuration register
__IO uint16_t S2NDTR; // @68 stream x number of data register
uint8_t RESERVED4[2]; // @70
__IO uint32_t S2PAR; // @72 stream x peripheral address register
__IO uint32_t S2M0AR; // @76 stream x memory 0 address register
__IO uint32_t S2M1AR; // @80 stream x memory 1 address register
__IO uint8_t S2FCR; // @84 stream x FIFO control register
uint8_t RESERVED5[3]; // @85
__IO uint32_t S3CR; // @88 stream x configuration register
__IO uint16_t S3NDTR; // @92 stream x number of data register
uint8_t RESERVED6[2]; // @94
__IO uint32_t S3PAR; // @96 stream x peripheral address register
__IO uint32_t S3M0AR; // @100 stream x memory 0 address register
__IO uint32_t S3M1AR; // @104 stream x memory 1 address register
__IO uint8_t S3FCR; // @108 stream x FIFO control register
uint8_t RESERVED7[3]; // @109
__IO uint32_t S4CR; // @112 stream x configuration register
__IO uint16_t S4NDTR; // @116 stream x number of data register
uint8_t RESERVED8[2]; // @118
__IO uint32_t S4PAR; // @120 stream x peripheral address register
__IO uint32_t S4M0AR; // @124 stream x memory 0 address register
__IO uint32_t S4M1AR; // @128 stream x memory 1 address register
__IO uint8_t S4FCR; // @132 stream x FIFO control register
uint8_t RESERVED9[3]; // @133
__IO uint32_t S5CR; // @136 stream x configuration register
__IO uint16_t S5NDTR; // @140 stream x number of data register
uint8_t RESERVED10[2]; // @142
__IO uint32_t S5PAR; // @144 stream x peripheral address register
__IO uint32_t S5M0AR; // @148 stream x memory 0 address register
__IO uint32_t S5M1AR; // @152 stream x memory 1 address register
__IO uint8_t S5FCR; // @156 stream x FIFO control register
uint8_t RESERVED11[3]; // @157
__IO uint32_t S6CR; // @160 stream x configuration register
__IO uint16_t S6NDTR; // @164 stream x number of data register
uint8_t RESERVED12[2]; // @166
__IO uint32_t S6PAR; // @168 stream x peripheral address register
__IO uint32_t S6M0AR; // @172 stream x memory 0 address register
__IO uint32_t S6M1AR; // @176 stream x memory 1 address register
__IO uint8_t S6FCR; // @180 stream x FIFO control register
uint8_t RESERVED13[3]; // @181
__IO uint32_t S7CR; // @184 stream x configuration register
__IO uint16_t S7NDTR; // @188 stream x number of data register
uint8_t RESERVED14[2]; // @190
__IO uint32_t S7PAR; // @192 stream x peripheral address register
__IO uint32_t S7M0AR; // @196 stream x memory 0 address register
__IO uint32_t S7M1AR; // @200 stream x memory 1 address register
__IO uint8_t S7FCR; // @204 stream x FIFO control register
};
// DMA2->LISR low interrupt status register
enum {
DMA2_LISR_TCIF3 = 1UL << 27, // Stream x transfer complete interrupt flag (x = 3..0)
DMA2_LISR_HTIF3 = 1UL << 26, // Stream x half transfer interrupt flag (x=3..0)
DMA2_LISR_TEIF3 = 1UL << 25, // Stream x transfer error interrupt flag (x=3..0)
DMA2_LISR_DMEIF3 = 1UL << 24, // Stream x direct mode error interrupt flag (x=3..0)
DMA2_LISR_FEIF3 = 1UL << 22, // Stream x FIFO error interrupt flag (x=3..0)
DMA2_LISR_TCIF2 = 1UL << 21, // Stream x transfer complete interrupt flag (x = 3..0)
DMA2_LISR_HTIF2 = 1UL << 20, // Stream x half transfer interrupt flag (x=3..0)
DMA2_LISR_TEIF2 = 1UL << 19, // Stream x transfer error interrupt flag (x=3..0)
DMA2_LISR_DMEIF2 = 1UL << 18, // Stream x direct mode error interrupt flag (x=3..0)
DMA2_LISR_FEIF2 = 1UL << 16, // Stream x FIFO error interrupt flag (x=3..0)
DMA2_LISR_TCIF1 = 1UL << 11, // Stream x transfer complete interrupt flag (x = 3..0)
DMA2_LISR_HTIF1 = 1UL << 10, // Stream x half transfer interrupt flag (x=3..0)
DMA2_LISR_TEIF1 = 1UL << 9, // Stream x transfer error interrupt flag (x=3..0)
DMA2_LISR_DMEIF1 = 1UL << 8, // Stream x direct mode error interrupt flag (x=3..0)
DMA2_LISR_FEIF1 = 1UL << 6, // Stream x FIFO error interrupt flag (x=3..0)
DMA2_LISR_TCIF0 = 1UL << 5, // Stream x transfer complete interrupt flag (x = 3..0)
DMA2_LISR_HTIF0 = 1UL << 4, // Stream x half transfer interrupt flag (x=3..0)
DMA2_LISR_TEIF0 = 1UL << 3, // Stream x transfer error interrupt flag (x=3..0)
DMA2_LISR_DMEIF0 = 1UL << 2, // Stream x direct mode error interrupt flag (x=3..0)
DMA2_LISR_FEIF0 = 1UL << 0, // Stream x FIFO error interrupt flag (x=3..0)
};
// DMA2->HISR high interrupt status register
enum {
DMA2_HISR_TCIF7 = 1UL << 27, // Stream x transfer complete interrupt flag (x=7..4)
DMA2_HISR_HTIF7 = 1UL << 26, // Stream x half transfer interrupt flag (x=7..4)
DMA2_HISR_TEIF7 = 1UL << 25, // Stream x transfer error interrupt flag (x=7..4)
DMA2_HISR_DMEIF7 = 1UL << 24, // Stream x direct mode error interrupt flag (x=7..4)
DMA2_HISR_FEIF7 = 1UL << 22, // Stream x FIFO error interrupt flag (x=7..4)
DMA2_HISR_TCIF6 = 1UL << 21, // Stream x transfer complete interrupt flag (x=7..4)
DMA2_HISR_HTIF6 = 1UL << 20, // Stream x half transfer interrupt flag (x=7..4)
DMA2_HISR_TEIF6 = 1UL << 19, // Stream x transfer error interrupt flag (x=7..4)
DMA2_HISR_DMEIF6 = 1UL << 18, // Stream x direct mode error interrupt flag (x=7..4)
DMA2_HISR_FEIF6 = 1UL << 16, // Stream x FIFO error interrupt flag (x=7..4)
DMA2_HISR_TCIF5 = 1UL << 11, // Stream x transfer complete interrupt flag (x=7..4)
DMA2_HISR_HTIF5 = 1UL << 10, // Stream x half transfer interrupt flag (x=7..4)
DMA2_HISR_TEIF5 = 1UL << 9, // Stream x transfer error interrupt flag (x=7..4)
DMA2_HISR_DMEIF5 = 1UL << 8, // Stream x direct mode error interrupt flag (x=7..4)
DMA2_HISR_FEIF5 = 1UL << 6, // Stream x FIFO error interrupt flag (x=7..4)
DMA2_HISR_TCIF4 = 1UL << 5, // Stream x transfer complete interrupt flag (x=7..4)
DMA2_HISR_HTIF4 = 1UL << 4, // Stream x half transfer interrupt flag (x=7..4)
DMA2_HISR_TEIF4 = 1UL << 3, // Stream x transfer error interrupt flag (x=7..4)
DMA2_HISR_DMEIF4 = 1UL << 2, // Stream x direct mode error interrupt flag (x=7..4)
DMA2_HISR_FEIF4 = 1UL << 0, // Stream x FIFO error interrupt flag (x=7..4)
};
// DMA2->LIFCR low interrupt flag clear register
enum {
DMA2_LIFCR_CTCIF3 = 1UL << 27, // Stream x clear transfer complete interrupt flag (x = 3..0)
DMA2_LIFCR_CHTIF3 = 1UL << 26, // Stream x clear half transfer interrupt flag (x = 3..0)
DMA2_LIFCR_CTEIF3 = 1UL << 25, // Stream x clear transfer error interrupt flag (x = 3..0)
DMA2_LIFCR_CDMEIF3 = 1UL << 24, // Stream x clear direct mode error interrupt flag (x = 3..0)
DMA2_LIFCR_CFEIF3 = 1UL << 22, // Stream x clear FIFO error interrupt flag (x = 3..0)
DMA2_LIFCR_CTCIF2 = 1UL << 21, // Stream x clear transfer complete interrupt flag (x = 3..0)
DMA2_LIFCR_CHTIF2 = 1UL << 20, // Stream x clear half transfer interrupt flag (x = 3..0)
DMA2_LIFCR_CTEIF2 = 1UL << 19, // Stream x clear transfer error interrupt flag (x = 3..0)
DMA2_LIFCR_CDMEIF2 = 1UL << 18, // Stream x clear direct mode error interrupt flag (x = 3..0)
DMA2_LIFCR_CFEIF2 = 1UL << 16, // Stream x clear FIFO error interrupt flag (x = 3..0)
DMA2_LIFCR_CTCIF1 = 1UL << 11, // Stream x clear transfer complete interrupt flag (x = 3..0)
DMA2_LIFCR_CHTIF1 = 1UL << 10, // Stream x clear half transfer interrupt flag (x = 3..0)
DMA2_LIFCR_CTEIF1 = 1UL << 9, // Stream x clear transfer error interrupt flag (x = 3..0)
DMA2_LIFCR_CDMEIF1 = 1UL << 8, // Stream x clear direct mode error interrupt flag (x = 3..0)
DMA2_LIFCR_CFEIF1 = 1UL << 6, // Stream x clear FIFO error interrupt flag (x = 3..0)
DMA2_LIFCR_CTCIF0 = 1UL << 5, // Stream x clear transfer complete interrupt flag (x = 3..0)
DMA2_LIFCR_CHTIF0 = 1UL << 4, // Stream x clear half transfer interrupt flag (x = 3..0)
DMA2_LIFCR_CTEIF0 = 1UL << 3, // Stream x clear transfer error interrupt flag (x = 3..0)
DMA2_LIFCR_CDMEIF0 = 1UL << 2, // Stream x clear direct mode error interrupt flag (x = 3..0)
DMA2_LIFCR_CFEIF0 = 1UL << 0, // Stream x clear FIFO error interrupt flag (x = 3..0)
};
// DMA2->HIFCR high interrupt flag clear register
enum {
DMA2_HIFCR_CTCIF7 = 1UL << 27, // Stream x clear transfer complete interrupt flag (x = 7..4)
DMA2_HIFCR_CHTIF7 = 1UL << 26, // Stream x clear half transfer interrupt flag (x = 7..4)
DMA2_HIFCR_CTEIF7 = 1UL << 25, // Stream x clear transfer error interrupt flag (x = 7..4)
DMA2_HIFCR_CDMEIF7 = 1UL << 24, // Stream x clear direct mode error interrupt flag (x = 7..4)
DMA2_HIFCR_CFEIF7 = 1UL << 22, // Stream x clear FIFO error interrupt flag (x = 7..4)
DMA2_HIFCR_CTCIF6 = 1UL << 21, // Stream x clear transfer complete interrupt flag (x = 7..4)
DMA2_HIFCR_CHTIF6 = 1UL << 20, // Stream x clear half transfer interrupt flag (x = 7..4)
DMA2_HIFCR_CTEIF6 = 1UL << 19, // Stream x clear transfer error interrupt flag (x = 7..4)
DMA2_HIFCR_CDMEIF6 = 1UL << 18, // Stream x clear direct mode error interrupt flag (x = 7..4)
DMA2_HIFCR_CFEIF6 = 1UL << 16, // Stream x clear FIFO error interrupt flag (x = 7..4)
DMA2_HIFCR_CTCIF5 = 1UL << 11, // Stream x clear transfer complete interrupt flag (x = 7..4)
DMA2_HIFCR_CHTIF5 = 1UL << 10, // Stream x clear half transfer interrupt flag (x = 7..4)
DMA2_HIFCR_CTEIF5 = 1UL << 9, // Stream x clear transfer error interrupt flag (x = 7..4)
DMA2_HIFCR_CDMEIF5 = 1UL << 8, // Stream x clear direct mode error interrupt flag (x = 7..4)
DMA2_HIFCR_CFEIF5 = 1UL << 6, // Stream x clear FIFO error interrupt flag (x = 7..4)
DMA2_HIFCR_CTCIF4 = 1UL << 5, // Stream x clear transfer complete interrupt flag (x = 7..4)
DMA2_HIFCR_CHTIF4 = 1UL << 4, // Stream x clear half transfer interrupt flag (x = 7..4)
DMA2_HIFCR_CTEIF4 = 1UL << 3, // Stream x clear transfer error interrupt flag (x = 7..4)
DMA2_HIFCR_CDMEIF4 = 1UL << 2, // Stream x clear direct mode error interrupt flag (x = 7..4)
DMA2_HIFCR_CFEIF4 = 1UL << 0, // Stream x clear FIFO error interrupt flag (x = 7..4)
};
// DMA2->S0CR stream x configuration register
enum {
DMA2_S0CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S0CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S0CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S0CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S0CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S0CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S0CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S0CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S0CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S0CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S0CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S0CR_CIRC = 1UL << 8, // Circular mode
DMA2_S0CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S0CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S0CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S0CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S0CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S0CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S0CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s0cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S0CR = (p->S0CR & ~DMA2_S0CR_CHSEL) | ((val << 25) & DMA2_S0CR_CHSEL);
}
inline void dma2_s0cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S0CR = (p->S0CR & ~DMA2_S0CR_MBURST) | ((val << 23) & DMA2_S0CR_MBURST);
}
inline void dma2_s0cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S0CR = (p->S0CR & ~DMA2_S0CR_PBURST) | ((val << 21) & DMA2_S0CR_PBURST);
}
inline void dma2_s0cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S0CR = (p->S0CR & ~DMA2_S0CR_PL) | ((val << 16) & DMA2_S0CR_PL); }
inline void dma2_s0cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S0CR = (p->S0CR & ~DMA2_S0CR_MSIZE) | ((val << 13) & DMA2_S0CR_MSIZE);
}
inline void dma2_s0cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S0CR = (p->S0CR & ~DMA2_S0CR_PSIZE) | ((val << 11) & DMA2_S0CR_PSIZE);
}
inline void dma2_s0cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S0CR = (p->S0CR & ~DMA2_S0CR_DIR) | ((val << 6) & DMA2_S0CR_DIR); }
inline uint32_t dma2_s0cr_get_chsel(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_CHSEL) >> 25; }
inline uint32_t dma2_s0cr_get_mburst(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_MBURST) >> 23; }
inline uint32_t dma2_s0cr_get_pburst(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_PBURST) >> 21; }
inline uint32_t dma2_s0cr_get_pl(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_PL) >> 16; }
inline uint32_t dma2_s0cr_get_msize(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_MSIZE) >> 13; }
inline uint32_t dma2_s0cr_get_psize(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_PSIZE) >> 11; }
inline uint32_t dma2_s0cr_get_dir(struct DMA2_Type* p) { return (p->S0CR & DMA2_S0CR_DIR) >> 6; }
// DMA2->S0FCR stream x FIFO control register
enum {
DMA2_S0FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S0FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S0FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S0FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s0fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S0FCR = (p->S0FCR & ~DMA2_S0FCR_FS) | ((val << 3) & DMA2_S0FCR_FS); }
inline void dma2_s0fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S0FCR = (p->S0FCR & ~DMA2_S0FCR_FTH) | ((val << 0) & DMA2_S0FCR_FTH);
}
inline uint32_t dma2_s0fcr_get_fs(struct DMA2_Type* p) { return (p->S0FCR & DMA2_S0FCR_FS) >> 3; }
inline uint32_t dma2_s0fcr_get_fth(struct DMA2_Type* p) { return (p->S0FCR & DMA2_S0FCR_FTH) >> 0; }
// DMA2->S1CR stream x configuration register
enum {
DMA2_S1CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S1CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S1CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S1CR_ACK = 1UL << 20, // ACK
DMA2_S1CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S1CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S1CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S1CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S1CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S1CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S1CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S1CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S1CR_CIRC = 1UL << 8, // Circular mode
DMA2_S1CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S1CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S1CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S1CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S1CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S1CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S1CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s1cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S1CR = (p->S1CR & ~DMA2_S1CR_CHSEL) | ((val << 25) & DMA2_S1CR_CHSEL);
}
inline void dma2_s1cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S1CR = (p->S1CR & ~DMA2_S1CR_MBURST) | ((val << 23) & DMA2_S1CR_MBURST);
}
inline void dma2_s1cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S1CR = (p->S1CR & ~DMA2_S1CR_PBURST) | ((val << 21) & DMA2_S1CR_PBURST);
}
inline void dma2_s1cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S1CR = (p->S1CR & ~DMA2_S1CR_PL) | ((val << 16) & DMA2_S1CR_PL); }
inline void dma2_s1cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S1CR = (p->S1CR & ~DMA2_S1CR_MSIZE) | ((val << 13) & DMA2_S1CR_MSIZE);
}
inline void dma2_s1cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S1CR = (p->S1CR & ~DMA2_S1CR_PSIZE) | ((val << 11) & DMA2_S1CR_PSIZE);
}
inline void dma2_s1cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S1CR = (p->S1CR & ~DMA2_S1CR_DIR) | ((val << 6) & DMA2_S1CR_DIR); }
inline uint32_t dma2_s1cr_get_chsel(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_CHSEL) >> 25; }
inline uint32_t dma2_s1cr_get_mburst(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_MBURST) >> 23; }
inline uint32_t dma2_s1cr_get_pburst(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_PBURST) >> 21; }
inline uint32_t dma2_s1cr_get_pl(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_PL) >> 16; }
inline uint32_t dma2_s1cr_get_msize(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_MSIZE) >> 13; }
inline uint32_t dma2_s1cr_get_psize(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_PSIZE) >> 11; }
inline uint32_t dma2_s1cr_get_dir(struct DMA2_Type* p) { return (p->S1CR & DMA2_S1CR_DIR) >> 6; }
// DMA2->S1FCR stream x FIFO control register
enum {
DMA2_S1FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S1FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S1FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S1FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s1fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S1FCR = (p->S1FCR & ~DMA2_S1FCR_FS) | ((val << 3) & DMA2_S1FCR_FS); }
inline void dma2_s1fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S1FCR = (p->S1FCR & ~DMA2_S1FCR_FTH) | ((val << 0) & DMA2_S1FCR_FTH);
}
inline uint32_t dma2_s1fcr_get_fs(struct DMA2_Type* p) { return (p->S1FCR & DMA2_S1FCR_FS) >> 3; }
inline uint32_t dma2_s1fcr_get_fth(struct DMA2_Type* p) { return (p->S1FCR & DMA2_S1FCR_FTH) >> 0; }
// DMA2->S2CR stream x configuration register
enum {
DMA2_S2CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S2CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S2CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S2CR_ACK = 1UL << 20, // ACK
DMA2_S2CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S2CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S2CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S2CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S2CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S2CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S2CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S2CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S2CR_CIRC = 1UL << 8, // Circular mode
DMA2_S2CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S2CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S2CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S2CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S2CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S2CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S2CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s2cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S2CR = (p->S2CR & ~DMA2_S2CR_CHSEL) | ((val << 25) & DMA2_S2CR_CHSEL);
}
inline void dma2_s2cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S2CR = (p->S2CR & ~DMA2_S2CR_MBURST) | ((val << 23) & DMA2_S2CR_MBURST);
}
inline void dma2_s2cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S2CR = (p->S2CR & ~DMA2_S2CR_PBURST) | ((val << 21) & DMA2_S2CR_PBURST);
}
inline void dma2_s2cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S2CR = (p->S2CR & ~DMA2_S2CR_PL) | ((val << 16) & DMA2_S2CR_PL); }
inline void dma2_s2cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S2CR = (p->S2CR & ~DMA2_S2CR_MSIZE) | ((val << 13) & DMA2_S2CR_MSIZE);
}
inline void dma2_s2cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S2CR = (p->S2CR & ~DMA2_S2CR_PSIZE) | ((val << 11) & DMA2_S2CR_PSIZE);
}
inline void dma2_s2cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S2CR = (p->S2CR & ~DMA2_S2CR_DIR) | ((val << 6) & DMA2_S2CR_DIR); }
inline uint32_t dma2_s2cr_get_chsel(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_CHSEL) >> 25; }
inline uint32_t dma2_s2cr_get_mburst(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_MBURST) >> 23; }
inline uint32_t dma2_s2cr_get_pburst(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_PBURST) >> 21; }
inline uint32_t dma2_s2cr_get_pl(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_PL) >> 16; }
inline uint32_t dma2_s2cr_get_msize(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_MSIZE) >> 13; }
inline uint32_t dma2_s2cr_get_psize(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_PSIZE) >> 11; }
inline uint32_t dma2_s2cr_get_dir(struct DMA2_Type* p) { return (p->S2CR & DMA2_S2CR_DIR) >> 6; }
// DMA2->S2FCR stream x FIFO control register
enum {
DMA2_S2FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S2FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S2FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S2FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s2fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S2FCR = (p->S2FCR & ~DMA2_S2FCR_FS) | ((val << 3) & DMA2_S2FCR_FS); }
inline void dma2_s2fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S2FCR = (p->S2FCR & ~DMA2_S2FCR_FTH) | ((val << 0) & DMA2_S2FCR_FTH);
}
inline uint32_t dma2_s2fcr_get_fs(struct DMA2_Type* p) { return (p->S2FCR & DMA2_S2FCR_FS) >> 3; }
inline uint32_t dma2_s2fcr_get_fth(struct DMA2_Type* p) { return (p->S2FCR & DMA2_S2FCR_FTH) >> 0; }
// DMA2->S3CR stream x configuration register
enum {
DMA2_S3CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S3CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S3CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S3CR_ACK = 1UL << 20, // ACK
DMA2_S3CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S3CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S3CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S3CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S3CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S3CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S3CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S3CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S3CR_CIRC = 1UL << 8, // Circular mode
DMA2_S3CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S3CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S3CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S3CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S3CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S3CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S3CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s3cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S3CR = (p->S3CR & ~DMA2_S3CR_CHSEL) | ((val << 25) & DMA2_S3CR_CHSEL);
}
inline void dma2_s3cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S3CR = (p->S3CR & ~DMA2_S3CR_MBURST) | ((val << 23) & DMA2_S3CR_MBURST);
}
inline void dma2_s3cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S3CR = (p->S3CR & ~DMA2_S3CR_PBURST) | ((val << 21) & DMA2_S3CR_PBURST);
}
inline void dma2_s3cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S3CR = (p->S3CR & ~DMA2_S3CR_PL) | ((val << 16) & DMA2_S3CR_PL); }
inline void dma2_s3cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S3CR = (p->S3CR & ~DMA2_S3CR_MSIZE) | ((val << 13) & DMA2_S3CR_MSIZE);
}
inline void dma2_s3cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S3CR = (p->S3CR & ~DMA2_S3CR_PSIZE) | ((val << 11) & DMA2_S3CR_PSIZE);
}
inline void dma2_s3cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S3CR = (p->S3CR & ~DMA2_S3CR_DIR) | ((val << 6) & DMA2_S3CR_DIR); }
inline uint32_t dma2_s3cr_get_chsel(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_CHSEL) >> 25; }
inline uint32_t dma2_s3cr_get_mburst(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_MBURST) >> 23; }
inline uint32_t dma2_s3cr_get_pburst(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_PBURST) >> 21; }
inline uint32_t dma2_s3cr_get_pl(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_PL) >> 16; }
inline uint32_t dma2_s3cr_get_msize(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_MSIZE) >> 13; }
inline uint32_t dma2_s3cr_get_psize(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_PSIZE) >> 11; }
inline uint32_t dma2_s3cr_get_dir(struct DMA2_Type* p) { return (p->S3CR & DMA2_S3CR_DIR) >> 6; }
// DMA2->S3FCR stream x FIFO control register
enum {
DMA2_S3FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S3FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S3FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S3FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s3fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S3FCR = (p->S3FCR & ~DMA2_S3FCR_FS) | ((val << 3) & DMA2_S3FCR_FS); }
inline void dma2_s3fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S3FCR = (p->S3FCR & ~DMA2_S3FCR_FTH) | ((val << 0) & DMA2_S3FCR_FTH);
}
inline uint32_t dma2_s3fcr_get_fs(struct DMA2_Type* p) { return (p->S3FCR & DMA2_S3FCR_FS) >> 3; }
inline uint32_t dma2_s3fcr_get_fth(struct DMA2_Type* p) { return (p->S3FCR & DMA2_S3FCR_FTH) >> 0; }
// DMA2->S4CR stream x configuration register
enum {
DMA2_S4CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S4CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S4CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S4CR_ACK = 1UL << 20, // ACK
DMA2_S4CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S4CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S4CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S4CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S4CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S4CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S4CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S4CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S4CR_CIRC = 1UL << 8, // Circular mode
DMA2_S4CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S4CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S4CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S4CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S4CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S4CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S4CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s4cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S4CR = (p->S4CR & ~DMA2_S4CR_CHSEL) | ((val << 25) & DMA2_S4CR_CHSEL);
}
inline void dma2_s4cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S4CR = (p->S4CR & ~DMA2_S4CR_MBURST) | ((val << 23) & DMA2_S4CR_MBURST);
}
inline void dma2_s4cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S4CR = (p->S4CR & ~DMA2_S4CR_PBURST) | ((val << 21) & DMA2_S4CR_PBURST);
}
inline void dma2_s4cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S4CR = (p->S4CR & ~DMA2_S4CR_PL) | ((val << 16) & DMA2_S4CR_PL); }
inline void dma2_s4cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S4CR = (p->S4CR & ~DMA2_S4CR_MSIZE) | ((val << 13) & DMA2_S4CR_MSIZE);
}
inline void dma2_s4cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S4CR = (p->S4CR & ~DMA2_S4CR_PSIZE) | ((val << 11) & DMA2_S4CR_PSIZE);
}
inline void dma2_s4cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S4CR = (p->S4CR & ~DMA2_S4CR_DIR) | ((val << 6) & DMA2_S4CR_DIR); }
inline uint32_t dma2_s4cr_get_chsel(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_CHSEL) >> 25; }
inline uint32_t dma2_s4cr_get_mburst(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_MBURST) >> 23; }
inline uint32_t dma2_s4cr_get_pburst(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_PBURST) >> 21; }
inline uint32_t dma2_s4cr_get_pl(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_PL) >> 16; }
inline uint32_t dma2_s4cr_get_msize(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_MSIZE) >> 13; }
inline uint32_t dma2_s4cr_get_psize(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_PSIZE) >> 11; }
inline uint32_t dma2_s4cr_get_dir(struct DMA2_Type* p) { return (p->S4CR & DMA2_S4CR_DIR) >> 6; }
// DMA2->S4FCR stream x FIFO control register
enum {
DMA2_S4FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S4FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S4FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S4FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s4fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S4FCR = (p->S4FCR & ~DMA2_S4FCR_FS) | ((val << 3) & DMA2_S4FCR_FS); }
inline void dma2_s4fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S4FCR = (p->S4FCR & ~DMA2_S4FCR_FTH) | ((val << 0) & DMA2_S4FCR_FTH);
}
inline uint32_t dma2_s4fcr_get_fs(struct DMA2_Type* p) { return (p->S4FCR & DMA2_S4FCR_FS) >> 3; }
inline uint32_t dma2_s4fcr_get_fth(struct DMA2_Type* p) { return (p->S4FCR & DMA2_S4FCR_FTH) >> 0; }
// DMA2->S5CR stream x configuration register
enum {
DMA2_S5CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S5CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S5CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S5CR_ACK = 1UL << 20, // ACK
DMA2_S5CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S5CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S5CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S5CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S5CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S5CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S5CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S5CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S5CR_CIRC = 1UL << 8, // Circular mode
DMA2_S5CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S5CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S5CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S5CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S5CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S5CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S5CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s5cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S5CR = (p->S5CR & ~DMA2_S5CR_CHSEL) | ((val << 25) & DMA2_S5CR_CHSEL);
}
inline void dma2_s5cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S5CR = (p->S5CR & ~DMA2_S5CR_MBURST) | ((val << 23) & DMA2_S5CR_MBURST);
}
inline void dma2_s5cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S5CR = (p->S5CR & ~DMA2_S5CR_PBURST) | ((val << 21) & DMA2_S5CR_PBURST);
}
inline void dma2_s5cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S5CR = (p->S5CR & ~DMA2_S5CR_PL) | ((val << 16) & DMA2_S5CR_PL); }
inline void dma2_s5cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S5CR = (p->S5CR & ~DMA2_S5CR_MSIZE) | ((val << 13) & DMA2_S5CR_MSIZE);
}
inline void dma2_s5cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S5CR = (p->S5CR & ~DMA2_S5CR_PSIZE) | ((val << 11) & DMA2_S5CR_PSIZE);
}
inline void dma2_s5cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S5CR = (p->S5CR & ~DMA2_S5CR_DIR) | ((val << 6) & DMA2_S5CR_DIR); }
inline uint32_t dma2_s5cr_get_chsel(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_CHSEL) >> 25; }
inline uint32_t dma2_s5cr_get_mburst(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_MBURST) >> 23; }
inline uint32_t dma2_s5cr_get_pburst(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_PBURST) >> 21; }
inline uint32_t dma2_s5cr_get_pl(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_PL) >> 16; }
inline uint32_t dma2_s5cr_get_msize(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_MSIZE) >> 13; }
inline uint32_t dma2_s5cr_get_psize(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_PSIZE) >> 11; }
inline uint32_t dma2_s5cr_get_dir(struct DMA2_Type* p) { return (p->S5CR & DMA2_S5CR_DIR) >> 6; }
// DMA2->S5FCR stream x FIFO control register
enum {
DMA2_S5FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S5FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S5FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S5FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s5fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S5FCR = (p->S5FCR & ~DMA2_S5FCR_FS) | ((val << 3) & DMA2_S5FCR_FS); }
inline void dma2_s5fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S5FCR = (p->S5FCR & ~DMA2_S5FCR_FTH) | ((val << 0) & DMA2_S5FCR_FTH);
}
inline uint32_t dma2_s5fcr_get_fs(struct DMA2_Type* p) { return (p->S5FCR & DMA2_S5FCR_FS) >> 3; }
inline uint32_t dma2_s5fcr_get_fth(struct DMA2_Type* p) { return (p->S5FCR & DMA2_S5FCR_FTH) >> 0; }
// DMA2->S6CR stream x configuration register
enum {
DMA2_S6CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S6CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S6CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S6CR_ACK = 1UL << 20, // ACK
DMA2_S6CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S6CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S6CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S6CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S6CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S6CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S6CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S6CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S6CR_CIRC = 1UL << 8, // Circular mode
DMA2_S6CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S6CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S6CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S6CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S6CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S6CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S6CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s6cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S6CR = (p->S6CR & ~DMA2_S6CR_CHSEL) | ((val << 25) & DMA2_S6CR_CHSEL);
}
inline void dma2_s6cr_set_mburst(struct DMA2_Type* p, uint32_t val) {
p->S6CR = (p->S6CR & ~DMA2_S6CR_MBURST) | ((val << 23) & DMA2_S6CR_MBURST);
}
inline void dma2_s6cr_set_pburst(struct DMA2_Type* p, uint32_t val) {
p->S6CR = (p->S6CR & ~DMA2_S6CR_PBURST) | ((val << 21) & DMA2_S6CR_PBURST);
}
inline void dma2_s6cr_set_pl(struct DMA2_Type* p, uint32_t val) { p->S6CR = (p->S6CR & ~DMA2_S6CR_PL) | ((val << 16) & DMA2_S6CR_PL); }
inline void dma2_s6cr_set_msize(struct DMA2_Type* p, uint32_t val) {
p->S6CR = (p->S6CR & ~DMA2_S6CR_MSIZE) | ((val << 13) & DMA2_S6CR_MSIZE);
}
inline void dma2_s6cr_set_psize(struct DMA2_Type* p, uint32_t val) {
p->S6CR = (p->S6CR & ~DMA2_S6CR_PSIZE) | ((val << 11) & DMA2_S6CR_PSIZE);
}
inline void dma2_s6cr_set_dir(struct DMA2_Type* p, uint32_t val) { p->S6CR = (p->S6CR & ~DMA2_S6CR_DIR) | ((val << 6) & DMA2_S6CR_DIR); }
inline uint32_t dma2_s6cr_get_chsel(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_CHSEL) >> 25; }
inline uint32_t dma2_s6cr_get_mburst(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_MBURST) >> 23; }
inline uint32_t dma2_s6cr_get_pburst(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_PBURST) >> 21; }
inline uint32_t dma2_s6cr_get_pl(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_PL) >> 16; }
inline uint32_t dma2_s6cr_get_msize(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_MSIZE) >> 13; }
inline uint32_t dma2_s6cr_get_psize(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_PSIZE) >> 11; }
inline uint32_t dma2_s6cr_get_dir(struct DMA2_Type* p) { return (p->S6CR & DMA2_S6CR_DIR) >> 6; }
// DMA2->S6FCR stream x FIFO control register
enum {
DMA2_S6FCR_FEIE = 1UL << 7, // FIFO error interrupt enable
DMA2_S6FCR_FS = ((1UL << 3) - 1) << 3, // FIFO status
DMA2_S6FCR_DMDIS = 1UL << 2, // Direct mode disable
DMA2_S6FCR_FTH = ((1UL << 2) - 1) << 0, // FIFO threshold selection
};
inline void dma2_s6fcr_set_fs(struct DMA2_Type* p, uint32_t val) { p->S6FCR = (p->S6FCR & ~DMA2_S6FCR_FS) | ((val << 3) & DMA2_S6FCR_FS); }
inline void dma2_s6fcr_set_fth(struct DMA2_Type* p, uint32_t val) {
p->S6FCR = (p->S6FCR & ~DMA2_S6FCR_FTH) | ((val << 0) & DMA2_S6FCR_FTH);
}
inline uint32_t dma2_s6fcr_get_fs(struct DMA2_Type* p) { return (p->S6FCR & DMA2_S6FCR_FS) >> 3; }
inline uint32_t dma2_s6fcr_get_fth(struct DMA2_Type* p) { return (p->S6FCR & DMA2_S6FCR_FTH) >> 0; }
// DMA2->S7CR stream x configuration register
enum {
DMA2_S7CR_CHSEL = ((1UL << 3) - 1) << 25, // Channel selection
DMA2_S7CR_MBURST = ((1UL << 2) - 1) << 23, // Memory burst transfer configuration
DMA2_S7CR_PBURST = ((1UL << 2) - 1) << 21, // Peripheral burst transfer configuration
DMA2_S7CR_ACK = 1UL << 20, // ACK
DMA2_S7CR_CT = 1UL << 19, // Current target (only in double buffer mode)
DMA2_S7CR_DBM = 1UL << 18, // Double buffer mode
DMA2_S7CR_PL = ((1UL << 2) - 1) << 16, // Priority level
DMA2_S7CR_PINCOS = 1UL << 15, // Peripheral increment offset size
DMA2_S7CR_MSIZE = ((1UL << 2) - 1) << 13, // Memory data size
DMA2_S7CR_PSIZE = ((1UL << 2) - 1) << 11, // Peripheral data size
DMA2_S7CR_MINC = 1UL << 10, // Memory increment mode
DMA2_S7CR_PINC = 1UL << 9, // Peripheral increment mode
DMA2_S7CR_CIRC = 1UL << 8, // Circular mode
DMA2_S7CR_DIR = ((1UL << 2) - 1) << 6, // Data transfer direction
DMA2_S7CR_PFCTRL = 1UL << 5, // Peripheral flow controller
DMA2_S7CR_TCIE = 1UL << 4, // Transfer complete interrupt enable
DMA2_S7CR_HTIE = 1UL << 3, // Half transfer interrupt enable
DMA2_S7CR_TEIE = 1UL << 2, // Transfer error interrupt enable
DMA2_S7CR_DMEIE = 1UL << 1, // Direct mode error interrupt enable
DMA2_S7CR_EN = 1UL << 0, // Stream enable / flag stream ready when read low
};
inline void dma2_s7cr_set_chsel(struct DMA2_Type* p, uint32_t val) {
p->S7CR = (p->S7CR & ~DMA2_S7CR_CHSEL) | ((val << 25) & DMA2_S7CR_CHSEL);
}