@@ -48,7 +48,7 @@ Sequencer::computeBplEventTable(const SigRecorder &sr)
4848 // Update the DMA and BMCTL bits
4949 state.bmapen = agnus.bpldma (agnus.dmaconInitial );
5050 state.bplcon0 = agnus.bplcon0Initial ;
51- computeFetchUnit (state.bmctl () );
51+ computeFetchUnit (state.bplcon0 );
5252
5353 // Evaluate the current state of the vertical DIW flipflop
5454 if (!state.bpv ) { state.bprun = false ; state.cnt = 0 ; }
@@ -252,7 +252,7 @@ Sequencer::processSignal <false> (u32 signal, DDFState &state)
252252 if (signal & SIG_CON) {
253253
254254 state.bplcon0 = HI_WORD (signal);
255- computeFetchUnit (state.bmctl () );
255+ computeFetchUnit (state.bplcon0 );
256256 }
257257 switch (signal & (SIG_BMAPEN_CLR | SIG_BMAPEN_SET)) {
258258
@@ -343,7 +343,7 @@ Sequencer::processSignal <true> (u32 signal, DDFState &state)
343343 if (signal & SIG_CON) {
344344
345345 state.bplcon0 = HI_WORD (signal);
346- computeFetchUnit (state.bmctl () );
346+ computeFetchUnit (state.bplcon0 );
347347 }
348348 switch (signal & (SIG_VFLOP_SET | SIG_VFLOP_CLR)) {
349349
@@ -456,49 +456,56 @@ Sequencer::updateBplJumpTable(i16 end)
456456}
457457
458458void
459- Sequencer::computeFetchUnit (u8 dmacon )
459+ Sequencer::computeFetchUnit (u16 bplcon0 )
460460{
461- if (GET_BIT (agnus.bplcon0 , 6 )) {
462-
463- switch (dmacon & 0x7 ) {
464-
465- case 0 : computeShresFetchUnit <0 > (); break ;
466- case 1 : computeShresFetchUnit <1 > (); break ;
467- case 2 : computeShresFetchUnit <2 > (); break ;
468- case 3 : computeShresFetchUnit <0 > (); break ;
469- case 4 : computeShresFetchUnit <0 > (); break ;
470- case 5 : computeShresFetchUnit <0 > (); break ;
471- case 6 : computeShresFetchUnit <0 > (); break ;
472- case 7 : computeShresFetchUnit <0 > (); break ;
473- }
461+ auto bpu = bplcon0 >> 12 & 0b111 ;
474462
475- } else if (dmacon & 0x8 ) {
476-
477- switch (dmacon & 0x7 ) {
478-
479- case 0 : computeHiresFetchUnit <0 > (); break ;
480- case 1 : computeHiresFetchUnit <1 > (); break ;
481- case 2 : computeHiresFetchUnit <2 > (); break ;
482- case 3 : computeHiresFetchUnit <3 > (); break ;
483- case 4 : computeHiresFetchUnit <4 > (); break ;
484- case 5 : computeHiresFetchUnit <0 > (); break ;
485- case 6 : computeHiresFetchUnit <0 > (); break ;
486- case 7 : computeHiresFetchUnit <0 > (); break ;
487- }
463+ switch (agnus.resolution (bplcon0)) {
488464
489- } else {
490-
491- switch (dmacon & 0x7 ) {
492-
493- case 0 : computeLoresFetchUnit <0 > (); break ;
494- case 1 : computeLoresFetchUnit <1 > (); break ;
495- case 2 : computeLoresFetchUnit <2 > (); break ;
496- case 3 : computeLoresFetchUnit <3 > (); break ;
497- case 4 : computeLoresFetchUnit <4 > (); break ;
498- case 5 : computeLoresFetchUnit <5 > (); break ;
499- case 6 : computeLoresFetchUnit <6 > (); break ;
500- case 7 : computeLoresFetchUnit <4 > (); break ;
501- }
465+ case LORES:
466+
467+ switch (bpu) {
468+
469+ case 0 : computeLoresFetchUnit <0 > (); break ;
470+ case 1 : computeLoresFetchUnit <1 > (); break ;
471+ case 2 : computeLoresFetchUnit <2 > (); break ;
472+ case 3 : computeLoresFetchUnit <3 > (); break ;
473+ case 4 : computeLoresFetchUnit <4 > (); break ;
474+ case 5 : computeLoresFetchUnit <5 > (); break ;
475+ case 6 : computeLoresFetchUnit <6 > (); break ;
476+ case 7 : computeLoresFetchUnit <4 > (); break ;
477+ }
478+ break ;
479+
480+ case HIRES:
481+
482+ switch (bpu) {
483+
484+ case 0 : computeHiresFetchUnit <0 > (); break ;
485+ case 1 : computeHiresFetchUnit <1 > (); break ;
486+ case 2 : computeHiresFetchUnit <2 > (); break ;
487+ case 3 : computeHiresFetchUnit <3 > (); break ;
488+ case 4 : computeHiresFetchUnit <4 > (); break ;
489+ case 5 : computeHiresFetchUnit <0 > (); break ;
490+ case 6 : computeHiresFetchUnit <0 > (); break ;
491+ case 7 : computeHiresFetchUnit <0 > (); break ;
492+ }
493+ break ;
494+
495+ case SHRES:
496+
497+ switch (bpu) {
498+
499+ case 0 : computeShresFetchUnit <0 > (); break ;
500+ case 1 : computeShresFetchUnit <1 > (); break ;
501+ case 2 : computeShresFetchUnit <2 > (); break ;
502+ case 3 : computeShresFetchUnit <0 > (); break ;
503+ case 4 : computeShresFetchUnit <0 > (); break ;
504+ case 5 : computeShresFetchUnit <0 > (); break ;
505+ case 6 : computeShresFetchUnit <0 > (); break ;
506+ case 7 : computeShresFetchUnit <0 > (); break ;
507+ }
508+ break ;
502509 }
503510}
504511
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