Clean up Stopwatch a bit

[stephentoub]

• Remove unnecessary Reset call from ctor
• Remove unnecessary branch for _elapsed < 0 (Stop is now more inlineable)
• Remove some defunct comments
• Clean up style of Stop to match that of Start

Closes #66734
Related to #111829

Method	Toolchain	Mean	Ratio	Code Size	Allocated	Alloc Ratio
Time	\main\corerun.exe	38.51 ns	1.00	363 B	40 B	1.00
Time	\pr\corerun.exe	30.35 ns	0.79	156 B	-	0.00

using BenchmarkDotNet.Attributes;
using BenchmarkDotNet.Running;
using System.Diagnostics;
using System.Runtime.CompilerServices;

BenchmarkSwitcher.FromAssembly(typeof(Program).Assembly).Run(args);

[DisassemblyDiagnoser]
[MemoryDiagnoser(false)]
public partial class Tests
{
    [Benchmark]
    public TimeSpan Time()
    {
        Stopwatch sw = Stopwatch.StartNew();
        Nop();
        sw.Stop();
        return sw.Elapsed;
    }

    [MethodImpl(MethodImplOptions.NoInlining)]
    public static void Nop() { }
}

[paulbartrum]

Are the Debug.Assert(IsHighResolution); asserts still needed? These will always be true as far as I can tell.

[stephentoub]

Are the Debug.Assert(IsHighResolution); asserts still needed? These will always be true as far as I can tell.

They're not needed.

[MihaZupan]

Nice

[stephentoub]

/ba-g unrelated infra

[tannergooding]

I believe we still support CPUs that could have this issue on Linux, although such processors are increasingly rare.

The Intel Architecture Manual covers that RDTSC is tied to the processor frequency for Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4 processors, Intel Xeon processors
(family [0FH], models [00H, 01H, or 02H]); and for P6 family processors

For a constant rate that is not tied to the CPU frequency, you instead need: Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H and higher]); for Intel Core Solo
and Intel Core Duo processors (family [06H], model [0EH]); for the Intel Xeon processor 5100 series and Intel
Core 2 Duo processors (family [06H], model [0FH]); for Intel Core 2 and Intel Xeon processors (family [06H],
DisplayModel [17H]); for Intel Atom processors (family [06H], DisplayModel [1CH]).

But even more so, it is technically dependent on querying that the CPU supports Invariant TSC by querying CPUID 0x8000_0007 and then reading EDX bit 8.

QPC on Windows and CLOCK_MONOTONIC on Unix is supposed to normalize this, but historically there have been bugs.

[tannergooding]

LGTM.