From a2132ef927495cc6266c727ea4e5db465e591ad3 Mon Sep 17 00:00:00 2001 From: yangm2 Date: Sun, 18 Aug 2024 12:44:18 -0700 Subject: [PATCH] add CRAVE (AntMicro branch) to Other Simulation tools --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index a19f29c..00fd5e0 100644 --- a/README.md +++ b/README.md @@ -170,6 +170,7 @@ A curated list of amazingly awesome hardware description language projects. * [cocotb](https://github.com/potentialventures/cocotb) - A coroutine based co-simulation library for writing VHDL and Verilog testbenches in Python * [osvvm](https://github.com/OSVVM/OsvvmLibraries) - A VHDL verification framework, verification utility library, verification component library, and a simulator independent scripting flow * [uvvm](https://github.com/OSVVM/OsvvmLibraries) - A free and Open Source Methodology and Library for VHDL verification of FPGA and ASIC. +* [crave](https://github.com/antmicro/crave) - Constrained random stimuli generation for C++ and SystemC (AntMicro's fork of [crave](https://github.com/agra-uni-bremen/crave)) ## Other Design Automation tools