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vivado_hls.log
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vivado_hls.log
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@I [LIC-101] Checked out feature [HLS]
@I [HLS-10] Running 'A:/Vivado/Vivado_HLS/2014.2/bin/unwrapped/win64.o/vivado_hls.exe'
for user 'Dulanga' on host 'dulanga-pc' (Windows NT_amd64 version 6.1) on Fri Mar 31 01:28:29 +0530 2017
in directory 'A:/FYP/HLSTutorials'
@I [HLS-10] Opening project 'A:/FYP/HLSTutorials/hist_stretch'.
@I [HLS-10] Opening solution 'A:/FYP/HLSTutorials/hist_stretch/solution1'.
@I [SYN-201] Setting up clock 'default' with a period of 10ns.
@I [HLS-10] Setting target device to 'xc7z020clg484-1'
@I [IMPL-8] Exporting RTL as an IP in IP-XACT.
****** Vivado v2014.2 (64-bit)
**** SW Build 932637 on Wed Jun 11 13:30:22 MDT 2014
**** IP Build 924643 on Fri May 30 09:20:16 MDT 2014
** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
source run_ippack.tcl -notrace
CRITICAL WARNING: [Board 49-4] Problem parsing board_part file - a:/Vivado/Vivado/2014.2/data/boards/board_parts/artix7/arty/C.0/board_part.xml, The board part 'xc7a35ticsg324-1L' is either not supported or invalid.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'a:/Vivado/Vivado/2014.2/data/ip'.
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'doHistStretch_ap_fdiv_14_no_dsp'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'doHistStretch_ap_fdiv_14_no_dsp'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'doHistStretch_ap_fmul_2_max_dsp'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'doHistStretch_ap_fmul_2_max_dsp'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'doHistStretch_ap_sitofp_4_no_dsp'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'doHistStretch_ap_sitofp_4_no_dsp'...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'a:/Vivado/Vivado/2014.2/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Fri Mar 31 01:29:03 2017...
CRITICAL WARNING: [Board 49-4] Problem parsing board_part file - a:/Vivado/Vivado/2014.2/data/boards/board_parts/artix7/arty/C.0/board_part.xml, The board part 'xc7a35ticsg324-1L' is either not supported or invalid.
@I [LIC-101] Checked in feature [HLS]