Merge remote-tracking branch 'upstream/master' into 2024.2.3

Author: eddieh-xlnx

src/com/xilinx/rapidwright/eco/ECOTools.java

@@ -1209,9 +1209,9 @@ public static void createNet(Design design, List<String> paths) {
      * @return The refactored cell instance.
      */
     public static EDIFHierCellInst refactorCell(Design design, EDIFHierCellInst cell, EDIFHierCellInst newParent) {
-        // TODO - Support non-leaf cells
-        if (!cell.getCellType().isLeafCellOrBlackBox()) {
-            throw new RuntimeException("ERROR: cell refactor of a hierarchical cell not yet supported: " + cell);
+        // TODO - Support non-leaf cells in implemented contexts
+        if (!cell.getCellType().isLeafCellOrBlackBox() && design.getSiteInsts().size() > 0) {
+            throw new RuntimeException("ERROR: Refactor of a non-leaf cell in a placed/routed design not yet supported: " + cell);
         }
         EDIFHierCellInst currParent = cell.getParent();
         if (currParent.equals(newParent)) {

src/com/xilinx/rapidwright/edif/EDIFHierPortInst.java

@@ -71,6 +71,15 @@ public String getHierarchicalInstName() {
 
     }
 
+    /**
+     * Gets the full instance, including the instance of the EDIFPortInst.
+     * 
+     * @return
+     */
+    public EDIFHierCellInst getFullHierarchicalInst() {
+        return hierarchicalInst.getChild(portInst.getCellInst());
+    }
+
     /**
      * Gets the net on the port inst
      * @return The net on the port inst

src/com/xilinx/rapidwright/edif/EDIFTools.java

@@ -532,9 +532,41 @@ public static void connectPortInstsThruHier(EDIFHierPortInst src, EDIFHierPortIn
             EDIFHierCellInst hierParentInst = hierPortInst.getHierarchicalInst();
             EDIFNet currNet = hierPortInst.getNet();
             if (currNet == null && !(hierParentInst.equals(commonAncestor) && hierPortInst == snk)) {
-                if (hierPortInst == src) createdSrcNet = true;
-                currNet = createUniqueNet(hierParentInst.getCellType(), newName);
-                currNet.addPortInst(hierPortInst.getPortInst());
+                // When operating on the snk pin, we've found that it is not connected to a net.  Instead of trying to
+                // connect through the hierarchy starting at the snk, start from the common ancestor and leverage
+                // as much existing connectivity as possible.
+                List<EDIFCellInst> sinkHier = snk.getFullHierarchicalInst().getFullHierarchy();
+                boolean foundPath = false;
+                do {
+                    foundPath = false;
+                    EDIFCellInst nextTargetInst = sinkHier.get(commonAncestor.getDepth());
+                    EDIFNet evalNet = finalSrc.getPortInst().getNet();
+                    if (evalNet != null) {
+                        for (EDIFPortInst pi : evalNet.getEDIFPortInstList()) {
+                            // Does this net connect to the next instance in hierarchy?
+                            if (pi.getCellInst() == nextTargetInst) {
+                                EDIFNet internalNet = pi.getInternalNet();
+                                // Is there a net inside the cell we can follow?
+                                if (internalNet != null) {
+                                    EDIFHierCellInst nextParent = finalSrc.getHierarchicalInst()
+                                            .getChild(pi.getCellInst());
+                                    EDIFPortInst internalPortInst = internalNet.getPortInst(null, pi.getName());
+                                    finalSrc = new EDIFHierPortInst(nextParent, internalPortInst);
+                                    commonAncestor = commonAncestor.getChild(pi.getCellInst());
+                                    foundPath = true;
+                                    break;
+                                }
+                            }
+                        }
+                    }
+                } while (foundPath && snk.getHierarchicalInst().getInst() != finalSrc.getHierarchicalInst().getInst());
+                if (!foundPath) {
+                    // We still need to create some ports to get us to the end
+                    if (hierPortInst == src)
+                        createdSrcNet = true;
+                    currNet = createUniqueNet(hierParentInst.getCellType(), newName);
+                    currNet.addPortInst(hierPortInst.getPortInst());
+                }
             }
 
             while (hierParentInst.getInst() != commonAncestor.getInst()) {

test/src/com/xilinx/rapidwright/edif/TestEDIFTools.java

@@ -33,6 +33,7 @@
 import org.junit.jupiter.params.provider.ValueSource;
 
 import java.nio.charset.StandardCharsets;
+import java.util.ArrayList;
 import java.util.List;
 import java.util.Map;
 import java.util.Map.Entry;
@@ -45,8 +46,8 @@ public class TestEDIFTools {
     public static final String TEST_SRC = "base_mb_i/microblaze_0/U0/"
             + "MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Data_Flow_Logic_I/Gen_Bits[22]."
             + "MEM_EX_Result_Inst/Using_FPGA.Native/Q";
-    public static final String TEST_SNK = "u_ila_0/inst/PROBE_PIPE."
-            + "shift_probes_reg[0][7]/D";
+    public static final String TEST_SNK = "u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][7]/D";
+    public static final String TEST_SNK2 = "u_ila_0/inst/PROBE_PIPE.shift_probes_reg[0][8]/D";
 
     @ParameterizedTest
     @ValueSource(booleans = {true, false})
@@ -89,6 +90,35 @@ public void testConnectPortInstsThruHier(boolean netToPin) {
             }
         }
         Assertions.assertTrue(containsSnk);
+
+        // Now check if it will reuse ports already created
+
+        // Disconnect sink in anticipation of connecting to another net
+        EDIFHierPortInst snkPortInst2 = netlist.getHierPortInstFromName(TEST_SNK2);
+        snkPortInst2.getNet().removePortInst(snkPortInst2.getPortInst());
+
+        // Count number of ports prior to connection to ensure no additional ports were
+        // created
+        List<Integer> portCounts = new ArrayList<>();
+        List<EDIFCellInst> insts = snkPortInst2.getFullHierarchicalInst().getFullHierarchy();
+        for (EDIFCellInst i : insts) {
+            portCounts.add(i.getCellPorts().size());
+        }
+
+        if (netToPin) {
+            EDIFTools.connectPortInstsThruHier(srcPortInst.getHierarchicalNet(), snkPortInst2,
+                    UNIQUE_SUFFIX);
+        } else {
+            EDIFTools.connectPortInstsThruHier(srcPortInst, snkPortInst2, UNIQUE_SUFFIX);
+        }
+
+        // Ensure no additional ports were created
+        for (int i = 0; i < insts.size(); i++) {
+            EDIFCellInst inst = insts.get(i);
+            Assertions.assertEquals(portCounts.get(i), inst.getCellPorts().size());
+        }
+
+        Assertions.assertEquals(snkPortInst.getNet(), snkPortInst2.getNet());
     }
 
     @Test