No suitable SAI peripheral version for WB55

[tomaz-suller]

The CubeMX database assigns SAI v2.0 for the STMWB55xx family, which is mapped to the sai_v1.rs implementation:

stm32-data/stm32-data-gen/src/perimap.rs

Line 207 in 85e2c0f

(".*:SAI:sai1_v2_0", ("sai", "v1", "SAI")),

This implementation however restricts the PLL clock divisor to much fewer options (basically only even values) than the CubeMX interface, which allows arbitrary values up to 86. It also does not support the PDM interface, which the WB55 family clearly supports (e.g. RM0434 Rev 14, Section 36.4.10 "PDM interface"). Either the implementation is wrong or CubeMX is, and my assumption is Embassy is right.

This then begs the question of what the correct version is. After exploring the CubeMX database files a bit, I noticed some comments mentioning the H7 line, so I decided to check the official SAI implementations in the HALs of both the WB and the H7, and what you get is

(left is WB, right is H7)

and since the WB implementation follows from the SAI v2.1 #if block, I assumed that the actual version of the SAI is v2.1 rather than v2.0.

So far this is a lot of speculation of course, but at any rate there doesn't seem to be an established process for providing fixes to peripheral mappings as there is for register mappings. Assuming this correction should be made, how should we go about making it?

[Dirbaio]

you can change the peripheral mapping here https://github.com/embassy-rs/stm32-data/blob/main/stm32-data-gen/src/perimap.rs#L204-L211 then send a PR

[tomaz-suller]

Thanks, but I think we may need a new SAI implementation after all. I just tried changing the mapping to use sai_v4_4pdm and flashing the board but I get an invalid configuration since the WB55 doesn't have the Global Config Register. All SAI implementations other than v1 have a GCR

[Dirbaio]

Oh, that's annoying.

If there's no existing sai_xx.yaml that exactly matches the SAI registers on WB then yes we'd need a new version. To do this you can either follow the steps in the README to extract the WB SAI version from the SVD files (and then clean it up and align it with all the others), or copy an existing one then edit it.

[tomaz-suller]

I wrote a very simple Python script to diff all generated YAMLs from the SVDs and this is the result (I used difflib.SequenceMatcher.ratio)

Notice I set the low cutoff to 0.5 since I thought descriptions would already be too dissimilar below that.

The WB55 is unfortunately kind of an odd one in the W block. Fortunately however it is quite similar to the L5 family, which is supported by sai_v3_2pdm, with the only big difference being the presence of 4 PDM lines instead of 2 (but that's also supported in sai_v3_4pdm), other than the lack of GCR as I've already mentioned. Looking at the generated SVDs, I've also noticed the WB55 has the MCKEN which the L5's lack.

Adding support should be pretty straight forward in this case (knocks on wood)

Exploring the generated files I also stumbled upon #638, I'll come back to that later

[tomaz-suller]

I've made the necessary changes but will only be able to test tomorrow (or possibly this weekend)

@Dirbaio I did realise I had to add the new SAI -- I called it sai_v1_4pdm -- to the cfg gates of the embassy-stm32::sai module. I don't know how you keep tabs on versions, but I suppose I submit a PR there as well and link to this one?

[Dirbaio]

first submit a PR here, once merged you can submit one to embassy-stm32 with the code changes plus updating the stm32-data commit hash in Cargo.toml