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[/tmp/hal/plugins/verilog_parser/src/verilog_parser.cpp:1272] could not construct netlist: unable to instantiate top module
[/tmp/hal/plugins/verilog_parser/src/verilog_parser.cpp:1728] could not create instance 'top_module' of type 'tassic_top': unable to create instance 'spare_unit0' of type 'top_spare'
[/tmp/hal/plugins/verilog_parser/src/verilog_parser.cpp:1793] could not create instance 'spare_unit0' of type 'top_spare': failed to assign 'UNCONNECTED_1' to pin 'Z' of gate 'tie0_test' of type 'TIE0UM' as the assignment is invalid
[07.03.2025 14:50:47] [gui] [error] [/tmp/hal/plugins/gui/src/file_manager/file_manager.cpp:575] Failed using gate library /home/oille/<fancy_lib>.lib.
Expected behavior
Firstly, not error out, but load the netlist and create a wire out of UNCONNECTED_1.
No simulator, STA tool nor commercial netlist viewer has problems with this.
Second, the error messages are confusing. For user it adds no value to see at which line of the HAL
source code the error ocured (the first part of each error message).
Instead, there could be information about the place where the error ocured in the target netlist, So the
stream above would look like:
Error: could not construct netlist: unable to instantiate top module
Error: could not create instance 'top_module' of type 'tassic_top': unable to create instance 'spare_unit0' of type 'top_spare', <path_to_the>/netlist.v:
46: module tassic_top ( pad1 , pad2 , pad3 , pad4 ,
Error: could not create instance 'spare_unit0' of type 'top_spare': failed to assign 'UNCONNECTED_1' to pin 'Z' of gate 'tie0_test' of type 'TIE0UM' as the assignment is invalid, <path_to_the_netlist>/netlist.v:
46: top_spare spare_unit0 (
Gui-Error: Failed using gate library /home/oille/<fancy_lib>.lib.
Screenshots
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Desktop (please complete the following information):
OS: [e.g. iOS]
Version [e.g. 22]
Additional context
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The text was updated successfully, but these errors were encountered:
Describe the bug
When I try to load a post-PNR Verilog netlist that has implicit wires (created by commercial PNR tool),
the nelist loader errors out.
To Reproduce
An example is e.g. following module:
This leads to an error:
Expected behavior
Firstly, not error out, but load the netlist and create a wire out of
UNCONNECTED_1
.No simulator, STA tool nor commercial netlist viewer has problems with this.
Second, the error messages are confusing. For user it adds no value to see at which line of the HAL
source code the error ocured (the first part of each error message).
Instead, there could be information about the place where the error ocured in the target netlist, So the
stream above would look like:
Screenshots
If applicable, add screenshots to help explain your problem.
Desktop (please complete the following information):
Additional context
Add any other context about the problem here.
The text was updated successfully, but these errors were encountered: