Gate

A (logical) gate is an electronic component comprising multiple in- and outputs that implements one or more Boolean fucntion(s). It is connected to a number of nets via its pins and can thus be used in larger circuits to implement complex logic operations. Such a circuit on gate-level is usually referred to as a netlist.

Similar to all other netlist components in HAL, a gate comprises basic information such as an ID, a name, and a gate type that can be read and sometimes written using dedicated commands such as get_id, get_name, set_name, and get_type. A gate can be created by using create_gate on the netlist while specifying its gate type and name. Furthermore, a gate can return the module and the grouping is is assigned to using get_module and get_grouping.

gt = GateType("example_type")                 # create an empty gate type
g = netlist.create_gate(gt, "example_gate")   # create a new gate
id = g.get_id()                               # get the gate's ID
name = g.get_name()                           # get the gate's name
grouping = g.get_grouping()                   # get the gate's grouping

Additionally, a gate can be retrieved from the netlist by ID using get_gate_by_id and may be deleted using delete_gate. Deleting a gate may result in dangling wires.

g = netlist.get_gate_by_id(3)   # get the gate with ID 3 from the netlist
netlist.delete_gate(g)          # delete the gate