diff --git a/README.md b/README.md index f4558ce..ed8ab5a 100644 --- a/README.md +++ b/README.md @@ -2,7 +2,15 @@ TinyGarble ======= **Caution: Pre-Alpha version and under construction!** -TinyGarble project consists of two main parts: netlist generation (/genNetlist) and two-party secure function evaluation (SFE). Netlist generation is partially describe in TinyGarble paper in IEEE S&P'15 (see References). It is based on upon hardware synthesis and sequential circuits. The other part of TinyGarble, hereafter called "TinyGarble", is implemented based on [JustGarble](http://cseweb.ucsd.edu/groups/justgarble/) project developed in UCSD. Beside Free-XOR, Row-reduction, OT extension, and Fixed-key block cipher, TinyGarble includes Half Gates which is the most recent optimization in garbled circuit (GC) protocol and reduces the communication 33%. +TinyGarble project consists of two main parts: netlist generation (/genNetlist) +and two-party secure function evaluation (SFE). Netlist generation is partially +describe in TinyGarble paper in IEEE S&P'15 (see References). It is based on +upon hardware synthesis and sequential circuits. The other part of TinyGarble, +hereafter called "TinyGarble", is implemented based on +[JustGarble](http://cseweb.ucsd.edu/groups/justgarble/) project developed in +UCSD. Beside Free-XOR, Row-reduction, OT extension, and Fixed-key block cipher, +TinyGarble includes Half Gates which is the most recent optimization in garbled +circuit (GC) protocol and reduces the communication 33%. ## TinyGarble @@ -11,33 +19,56 @@ TinyGarble project consists of two main parts: netlist generation (/genNetlist) `$ sudo apt-get install g++ libssl-dev libboost-all-dev` -2. Compile TinyGarble by executing `make` in `eval_netlist/` directory (for dumping labels, use `USER_FLAGS=-DDUMP_HEX`): +2. Compile TinyGarble by executing `make` in `eval_netlist/` directory +(for dumping labels, use `USER_FLAGS=-DDUMP_HEX`): ``` $ cd eval_netlist $ make ``` -###Test + +### Test ``` - $ debug/tinygarble --alice & - $ debug/tinygarble --bob + $ bin/tinygarble --alice & + $ bin/tinygarble --bob +``` + +### Arguments +``` + -h [ --help ] produce help message + -a [ --alice ] Run as Alice (server). + -b [ --bob ] Run as Bob (client). + --deterministic Run with deterministic random + generator. + -i [ --scd_file ] arg (=../read_netlist/netlists/test.scd) + Simple circuit description (.scd) file + address. + -p [ --port ] arg (=1234) socket port + -s [ --server_ip ] arg (=127.0.0.1) Server's (Alice's) IP, required when + running as Bob. + --dump_hex arg Directory for dumping memory hex files. + --input_data arg Hexadecimal input data, if not + provided, it is randomly chosen. ``` ## Netlist Generation ### Prerequisites -Netlist generation requires Synopsys Design Compiler or Yosys-ABC synthesis tools. +Netlist generation requires Synopsys Design Compiler or Yosys-ABC synthesis +tools. ### Manual for Synopsys Design Compiler -1. Compile library [This part is mentioned only for documentation and it is already done, please skip.] +1. Compile library [This part is mentioned only for documentation and it is +already done, please skip.] Go to `gen_netlist/lib/dff_full` and compile the library: ``` $ cd gen_netlist/lib/dff_full $ ./compile ``` -_Advanced detailed_: Let's suppose that our_lib.lib is located in /path/to/our_lib. +_Advanced detailed_: Let's suppose that our\_lib.lib is located in +/path/to/our\_lib. -- Go inside /path/to/our_lib and run: +- Go inside /path/to/our\_lib and run: ``` $ lc_shell lc_shell> set search_path [concat /path/to/our_lib/] @@ -45,18 +76,21 @@ _Advanced detailed_: Let's suppose that our_lib.lib is located in /path/to/our_l lc_shell> write_lib our_lib -format db lc_shell> exit ``` -[Note: commands starting with "lc_shell>" should be called inside `lc_shell`. Please ignore "lc_shell>" for them]. +[Note: commands starting with "lc_shell>" should be called inside `lc_shell`. +Please ignore "lc_shell>" for them]. 2. Compile a benchmark: -Go inside `genNetlist/benchmark`, where benchmark is the name of the function and compile the benchmark to generate the nestlist: +Go inside `genNetlist/benchmark`, where benchmark is the name of the function +and compile the benchmark to generate the nestlist: ``` $ cd gen_netlist/benchmark $ ./compile ``` You can edit `benchmark.dcsh` file to change synthesis parameters. -_Advanced detailed_: Let's suppose that `our_lib.db` is compiled and located in `/path/to/our_lib` and benchmark.v is located in `/path/to/benchmark/`. +_Advanced detailed_: Let's suppose that `our_lib.db` is compiled and located +in `/path/to/our_lib` and benchmark.v is located in `/path/to/benchmark/`. - Go to `/path/to/benchmark/` and run: ``` @@ -71,17 +105,24 @@ _Advanced detailed_: Let's suppose that `our_lib.db` is compiled and located in design_vision> write -hierarchy -format verilog -output benchmark_syn.v design_vision> exit ``` -It creates `benchmark_syn.v` in the current directory. [Note: commands starting with "design\_vision>" should be called inside `design_vision`. Please ignore "design\_vision>" for them.] +It creates `benchmark_syn.v` in the current directory. [Note: commands +starting with "design\_vision>" should be called inside `design_vision`. +Please ignore "design\_vision>" for them.] 3.Counting number of gates -You can use `gen_netlist/script/count.sh` to count the number of gates in the genetrated netlist file. For counting gates in `/path/to/benchmark/benchmark_syn.v`, simply run: +You can use `gen_netlist/script/count.sh` to count the number of gates in +the genetrated netlist file. For counting gates in +`/path/to/benchmark/benchmark_syn.v`, simply run: ``` $ gen_netlist/script/count.sh /path/to/benchmark/benchmark_syn.v ``` -###Manual for Yosys +### Manual for Yosys -Here is how to compile a verilog file named "benchmark.v" using the custom library "asic\_cell.lib". We assume that the files are inside a folder named "Synthesis\_yosys-abc" inside the "yosys" directory. The final output will be written in "benchmark\_syn.v" +Here is how to compile a verilog file named "benchmark.v" using the custom +library "asic\_cell.lib". We assume that the files are inside a folder named +"Synthesis\_yosys-abc" inside the "yosys" directory. The final output will be +written in "benchmark\_syn.v" ``` $ cd ~/yosys $ ./yosys @@ -93,17 +134,62 @@ Here is how to compile a verilog file named "benchmark.v" using the custom libra yosys> write_verilog Synthesis_yosys-abc/benchmark_syn.v yosys> exit ``` -[Note: commands starting with "yosys>" should be called inside design_vision. Please ignore "yosys>" for them.] +[Note: commands starting with "yosys>" should be called inside design_vision. +Please ignore "yosys>" for them.] + + +## Read Netlis +To transform a verilog netlist file which is generated by synthesis process to +a file readble by TinyGarble, one should use `read_netlist`. It transforms a +netlist verilog file to a Simple Circuit Descreption (SCD) file. The format of +the SCD file allows TinyGarble to load the circuit without dealing with +complicated gate transformation and string matching. + +### Prerequisites +1. Install dependencies: g++, boost, for Ubuntu run: + + `$ sudo apt-get install g++ libboost-all-dev` + +2. Compile `read_netlist` by executing `make` in `read_netlist/` directory: +``` + $ cd read_netlist + $ make +``` + +### Test +``` + $ bin/read_netlist.out --netlist netlists/test.v --scd netlists/test.scd +``` + +### Arguments +``` + -h [ --help ] produce help message. + -i [ --netlist ] arg (=netlists/test.v) + Input netlist (verilog .v) file + address. + -o [ --scd ] arg (=netlists/test.scd) Output simple circuit description (scd) + file address. + -c [ --clock ] arg (=1) Number of clock cycles for sequential + circuits +``` -##References -- Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Thomas Schneider and Farinaz Koushanfar, ["TinyGarble: Highly Compressed and Scalable Sequential Garbled Circuits."](http://esonghori.github.io/file/TinyGarble.pdf) Security and Privacy, 2015 IEEE Symposium on May, 2015. -- Mihir Bellare, Viet Tung Hoang, Sriram Keelveedhi, and Phillip Rogaway. Efficient garbling from a fixed-key blockcipher. In S&P, pages 478–492. IEEE, 2013. -- Samee Zahur, Mike Rosulek, and David Evans. ["Two halves make a whole: Reducing data transfer in garbled circuits using half gates."](http://eprint.iacr.org/2014/756) In Eurocrypt, 2015. -- G. Asharov, Y. Lindell, T. Schneider and M. Zohner: More Efficient Oblivious Transfer and Extensions for Faster Secure Computation In CCS'13. +## References +- Ebrahim M. Songhori, Siam U. Hussain, Ahmad-Reza Sadeghi, Thomas Schneider +and Farinaz Koushanfar, ["TinyGarble: Highly Compressed and Scalable Sequential +Garbled Circuits."](http://esonghori.github.io/file/TinyGarble.pdf) Security +and Privacy, 2015 IEEE Symposium on May, 2015. +- Mihir Bellare, Viet Tung Hoang, Sriram Keelveedhi, and Phillip Rogaway. +Efficient garbling from a fixed-key blockcipher. In S&P, pages 478–492. +IEEE, 2013. +- Samee Zahur, Mike Rosulek, and David Evans. ["Two halves make a whole: +Reducing data transfer in garbled circuits using half +gates."](http://eprint.iacr.org/2014/756) +In Eurocrypt, 2015. +- G. Asharov, Y. Lindell, T. Schneider and M. Zohner: More Efficient Oblivious +Transfer and Extensions for Faster Secure Computation In CCS'13. ##TODOs -- Add read\_netlist documentation. - Add OT. - Update README.md. - Add synthesis library. diff --git a/eval_netlist/tinygarble.cpp b/eval_netlist/tinygarble.cpp index 8cf0114..44eb802 100644 --- a/eval_netlist/tinygarble.cpp +++ b/eval_netlist/tinygarble.cpp @@ -216,29 +216,35 @@ int bob(GarbledCircuit& garbledCircuit, bool random_input, int connfd) { int main(int argc, char* argv[]) { - po::options_description desc("Allowed options"); + po::options_description desc( + "Evaluate Netlist, TinyGarble version 0.1\nAllowed options"); desc.add_options() // - ("help", "produce help message") // - ("alice", "Run as Alice (server).") // - ("bob", "Run as Bob (client).") // + ("help,h", "produce help message") // + ("alice,a", "Run as Alice (server).") // + ("bob,b", "Run as Bob (client).") // ("deterministic", "Run with deterministic random generator.") // - ("scd_file", + ("scd_file,i", po::value()->default_value("../read_netlist/netlists/test.scd"), "Simple circuit description (.scd) file address.") // - ("port", po::value()->default_value(1234), "socket port") // - ("server_ip", po::value()->default_value("127.0.0.1"), + ("port,p", po::value()->default_value(1234), "socket port") // + ("server_ip,s", po::value()->default_value("127.0.0.1"), "Server's (Alice's) IP, required when running as Bob.") // ("dump_hex", po::value(), "Directory for dumping memory hex files.") // ("input_data", po::value(), "Hexadecimal input data, if not provided, it is randomly chosen."); po::variables_map vm; - po::store(po::parse_command_line(argc, argv, desc), vm); - po::notify(vm); - - if (vm.count("help")) { - cout << desc << endl; - return 1; + try { + po::store(po::parse_command_line(argc, argv, desc), vm); + if (vm.count("help")) { + cout << desc << endl; + return 0; + } + po::notify(vm); + } catch (po::error& e) { + cerr << "ERROR: " << e.what() << endl << endl; + cerr << desc << endl; + return -1; } block R; @@ -258,20 +264,19 @@ int main(int argc, char* argv[]) { if (vm.count("scd_file")) { scd_file_address = vm["scd_file"].as(); } else { - cerr << "SCD file should be specified." << endl; + cerr << "SCD file should be specified." << endl << endl; + cerr << desc << endl; return -1; } int port; if (vm.count("port")) { port = vm["port"].as(); - } else { - cerr << "Socket port should be specified." << endl; - return -1; } if (vm.count("alice") == 0 && vm.count("bob") == 0) { - cerr << "One of --alice or --bob mode flag should be used." << endl; + cerr << "One of --alice or --bob mode flag should be used." << endl << endl; + cerr << desc << endl; return -1; } if (vm.count("dump_hex")) { @@ -312,7 +317,9 @@ int main(int argc, char* argv[]) { if (vm.count("server_ip")) { server_ip = vm["server_ip"].as(); } else { - cerr << "Server IP should be specified, when running as Bob." << endl; + cerr << "Server IP should be specified, when running as Bob." << endl + << endl; + cerr << desc << endl; return -1; } diff --git a/read_netlist/read_netlist.cpp b/read_netlist/read_netlist.cpp index 5842386..9dc751d 100644 --- a/read_netlist/read_netlist.cpp +++ b/read_netlist/read_netlist.cpp @@ -132,23 +132,29 @@ int writeSCD(const ReadCircuit &readCircuit, int c_, const string &fileName) { int main(int argc, char** argv) { - po::options_description desc("Allowed options"); + po::options_description desc( + "Read Netlist, TinyGarble version 0.1\nAllowed options"); desc.add_options() // - ("help", "produce help message.") // - ("netlist", po::value()->default_value("netlists/test.v"), + ("help,h", "produce help message.") // + ("netlist,i", po::value()->default_value("netlists/test.v"), "Input netlist (verilog .v) file address.") // - ("scd", po::value()->default_value("netlists/test.scd"), - "Output simple circuit descreption (scd) file address.") // - ("clock", po::value()->default_value(1), + ("scd,o", po::value()->default_value("netlists/test.scd"), + "Output simple circuit description (scd) file address.") // + ("clock,c", po::value()->default_value(1), "Number of clock cycles for sequential circuits"); po::variables_map vm; - po::store(po::parse_command_line(argc, argv, desc), vm); - po::notify(vm); - - if (vm.count("help")) { - cout << desc << endl; - return 1; + try { + po::store(po::parse_command_line(argc, argv, desc), vm); + if (vm.count("help")) { + cout << desc << endl; + return 0; + } + po::notify(vm); + } catch (po::error& e) { + cerr << "ERROR: " << e.what() << endl << endl; + cerr << desc << endl; + return -1; } string input_netlist_file;