The division example does not work

[andremmvgabriel]

Hello,

I'm using Yosys to read and make the synthesis of the Division Verilogs. However, for these verilogs, the "hierarchy -check -top top_module" step is not working. As so, the circuit synthesis for example is not achievable... Can you verify if everything is correct for this example?

In addition, I went to the other repository that one of you have (by the user name of @siamumar), the Tiny Garble Circuit Synthesis, and tried to make the synthesis of the Division that is inside the benchmarks2 folder (a .sv file).
With that one I was able to make it and then able to convert it to a .scd file. However, when I was testing that circuit, the outputs were mostly incorrect... For example, these 2 tests:

• Dividing 73 and 05 gives 17, which is correct (decimal is 115/5 = 23)
• Dividing 82 and 05 gives E7, which is not correct (decimal is 130/5 = 231)

@siamumar, if you don't mind, can you also check that circuit?

Thanks for your attention.

Best regards,
André Gabriel