Remove more legacy clock code

Author: bugadani

esp-hal/CHANGELOG.md

@@ -60,6 +60,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - The `ESP_HAL_CONFIG_XTAL_FREQUENCY` configuration option has been removed (#4517)
 - `Clocks::{i2c_clock, pwm_clock, crypto_clock}` fields (#4636, #4647)
 - `RtcClock::xtal_freq()` and the `XtalClock` enum (#4724)
+- `Rtc::estimate_xtal_frequency()` (#4851)
+- `RtcFastClock`, `RtcSlowClock` (#4851)
 
 ## [v1.0.0] - 2025-10-30
 

esp-hal/src/clock/mod.rs

@@ -67,7 +67,7 @@ use crate::peripherals::IEEE802154;
 use crate::peripherals::WIFI;
 use crate::{
     ESP_HAL_LOCK,
-    peripherals::{LPWR, TIMG0},
+    peripherals::TIMG0,
     private::Sealed,
     soc::clocks::{self, ClockTree, Timg0CalibrationClockConfig},
     time::Rate,
@@ -82,23 +82,6 @@ use crate::{
 #[cfg_attr(esp32s3, path = "clocks_ll/esp32s3.rs")]
 pub(crate) mod clocks_ll;
 
-/// Clock properties
-#[doc(hidden)]
-pub trait Clock {
-    /// Frequency of the clock in [Rate].
-    fn frequency(&self) -> Rate;
-
-    /// Frequency of the clock in Megahertz
-    fn mhz(&self) -> u32 {
-        self.frequency().as_mhz()
-    }
-
-    /// Frequency of the clock in Hertz
-    fn hz(&self) -> u32 {
-        self.frequency().as_hz()
-    }
-}
-
 #[cfg(feature = "unstable")]
 #[cfg_attr(docsrs, doc(cfg(feature = "unstable")))]
 pub use crate::soc::clocks::ClockConfig;
@@ -134,82 +117,6 @@ impl CpuClock {
     }
 }
 
-/// RTC FAST_CLK frequency values
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[instability::unstable]
-pub enum RtcFastClock {
-    /// Main XTAL, divided by 4
-    #[cfg(not(any(esp32c6, esp32h2)))]
-    XtalD4,
-
-    /// Select XTAL_D2_CLK as RTC_FAST_CLK source
-    #[cfg(any(esp32c6, esp32h2))]
-    XtalD2,
-
-    /// Internal fast RC oscillator
-    RcFast,
-}
-
-impl Clock for RtcFastClock {
-    fn frequency(&self) -> Rate {
-        match self {
-            #[cfg(not(any(esp32c6, esp32h2)))]
-            RtcFastClock::XtalD4 => Clocks::get().xtal_clock / 4,
-            #[cfg(any(esp32c6, esp32h2))]
-            RtcFastClock::XtalD2 => Clocks::get().xtal_clock / 2,
-
-            RtcFastClock::RcFast => Rate::from_hz(property!("soc.rc_fast_clk_default")),
-        }
-    }
-}
-
-/// RTC SLOW_CLK frequency values
-#[cfg(not(any(esp32c6, esp32h2)))]
-#[cfg_attr(feature = "defmt", derive(defmt::Format))]
-#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
-#[non_exhaustive]
-#[instability::unstable]
-pub enum RtcSlowClock {
-    /// Internal slow RC oscillator
-    RcSlow   = 0,
-    /// External 32 KHz XTAL
-    _32kXtal = 1,
-    /// Internal fast RC oscillator, divided by 256
-    _8mD256  = 2,
-}
-
-/// RTC SLOW_CLK frequency values
-#[cfg(any(esp32c6, esp32h2))]
-#[derive(Debug, Clone, Copy)]
-#[non_exhaustive]
-#[instability::unstable]
-pub enum RtcSlowClock {
-    /// Select RC_SLOW_CLK as RTC_SLOW_CLK source
-    RcSlow   = 0,
-    /// Select XTAL32K_CLK as RTC_SLOW_CLK source
-    _32kXtal = 1,
-    /// Select RC32K_CLK as RTC_SLOW_CLK source
-    _32kRc   = 2,
-    /// Select OSC_SLOW_CLK (external slow clock) as RTC_SLOW_CLK source
-    OscSlow  = 3,
-}
-
-impl Clock for RtcSlowClock {
-    fn frequency(&self) -> Rate {
-        match self {
-            RtcSlowClock::RcSlow => Rate::from_hz(property!("soc.rc_slow_clock")),
-            RtcSlowClock::_32kXtal => Rate::from_hz(32_768),
-            #[cfg(any(esp32c6, esp32h2))]
-            RtcSlowClock::_32kRc => Rate::from_hz(32_768),
-            #[cfg(not(any(esp32c6, esp32h2)))]
-            RtcSlowClock::_8mD256 => RtcFastClock::RcFast.frequency() / 256,
-            #[cfg(any(esp32c6, esp32h2))]
-            RtcSlowClock::OscSlow => Rate::from_hz(32_768),
-        }
-    }
-}
-
 /// RTC Clocks.
 #[instability::unstable]
 pub struct RtcClock;
@@ -219,26 +126,15 @@ impl RtcClock {
     const CAL_FRACT: u32 = 19;
 
     /// Get the RTC_SLOW_CLK source.
-    #[cfg(not(any(esp32c6, esp32h2)))]
-    pub fn slow_freq() -> RtcSlowClock {
-        match LPWR::regs().clk_conf().read().ana_clk_rtc_sel().bits() {
-            0 => RtcSlowClock::RcSlow,
-            1 => RtcSlowClock::_32kXtal,
-            2 => RtcSlowClock::_8mD256,
-            _ => unreachable!(),
-        }
-    }
-
-    /// Get the RTC_SLOW_CLK source
-    #[cfg(any(esp32h2, esp32c6))]
-    pub fn slow_freq() -> RtcSlowClock {
-        match LPWR::regs().lp_clk_conf().read().slow_clk_sel().bits() {
-            0 => RtcSlowClock::RcSlow,
-            1 => RtcSlowClock::_32kXtal,
-            2 => RtcSlowClock::_32kRc,
-            3 => RtcSlowClock::OscSlow,
-            _ => unreachable!(),
+    pub fn slow_freq() -> Rate {
+        cfg_if::cfg_if! {
+            if #[cfg(soc_has_clock_node_rtc_slow_clk)] {
+                let getter = clocks::rtc_slow_clk_frequency;
+            } else {
+                let getter = clocks::lp_slow_clk_frequency;
+            }
         }
+        Rate::from_hz(ClockTree::with(getter))
     }
 
     /// Measure the frequency of one of the TIMG0 calibration clocks,
@@ -299,48 +195,6 @@ impl RtcClock {
 
         (100_000_000 * 1000 / period) as u16
     }
-
-    /// Return estimated XTAL frequency in MHz.
-    pub(crate) fn estimate_xtal_frequency() -> u32 {
-        const SLOW_CLOCK_CYCLES: u32 = 100;
-
-        let calibration_clock = RtcSlowClock::RcSlow;
-
-        // Make sure the process doesn't time out due to some spooky configuration.
-        #[cfg(not(esp32))]
-        TIMG0::regs().rtccalicfg2().reset();
-
-        TIMG0::regs()
-            .rtccalicfg()
-            .modify(|_, w| w.rtc_cali_start().clear_bit());
-
-        TIMG0::regs().rtccalicfg().write(|w| unsafe {
-            w.rtc_cali_clk_sel().bits(calibration_clock as u8);
-            w.rtc_cali_max().bits(SLOW_CLOCK_CYCLES as u16);
-            w.rtc_cali_start_cycling().clear_bit();
-            w.rtc_cali_start().set_bit()
-        });
-
-        // Delay, otherwise the CPU may read back the previous state of the completion flag and skip
-        // waiting.
-        ets_delay_us(SLOW_CLOCK_CYCLES * 1_000_000 / calibration_clock.frequency().as_hz());
-
-        // Wait for the calibration to finish
-        while TIMG0::regs()
-            .rtccalicfg()
-            .read()
-            .rtc_cali_rdy()
-            .bit_is_clear()
-        {}
-
-        let cali_value = TIMG0::regs().rtccalicfg1().read().rtc_cali_value().bits();
-
-        TIMG0::regs()
-            .rtccalicfg()
-            .modify(|_, w| w.rtc_cali_start().clear_bit());
-
-        (cali_value * (calibration_clock.frequency().as_hz() / SLOW_CLOCK_CYCLES)) / 1_000_000
-    }
 }
 
 /// Clock frequencies.

esp-hal/src/rtc_cntl/mod.rs

@@ -116,7 +116,7 @@ use crate::efuse::Efuse;
 #[cfg(sleep)]
 use crate::rtc_cntl::sleep::{RtcSleepConfig, WakeSource, WakeTriggers};
 use crate::{
-    clock::{Clock, RtcClock},
+    clock::RtcClock,
     interrupt::{self, InterruptHandler},
     peripherals::{Interrupt, LPWR},
     system::{Cpu, SleepSource},
@@ -211,11 +211,6 @@ impl<'d> Rtc<'d> {
         }
     }
 
-    /// Return estimated XTAL frequency in MHz.
-    pub fn estimate_xtal_frequency(&mut self) -> u32 {
-        RtcClock::estimate_xtal_frequency()
-    }
-
     /// Get the time since boot in the raw register units.
     fn time_since_boot_raw(&self) -> u64 {
         let rtc_cntl = LP_TIMER::regs();
@@ -256,8 +251,7 @@ impl<'d> Rtc<'d> {
     /// reset the RTC timer.
     pub fn time_since_power_up(&self) -> Duration {
         Duration::from_micros(
-            self.time_since_boot_raw() * 1_000_000
-                / RtcClock::slow_freq().frequency().as_hz() as u64,
+            self.time_since_boot_raw() * 1_000_000 / RtcClock::slow_freq().as_hz() as u64,
         )
     }
 

esp-hal/src/rtc_cntl/sleep/esp32.rs

@@ -2,7 +2,7 @@ use super::{Ext0WakeupSource, Ext1WakeupSource, TimerWakeupSource, WakeSource, W
 use crate::{
     gpio::{RtcFunction, RtcPin},
     peripherals::{BB, DPORT, I2S0, LPWR, NRX, RTC_IO},
-    rtc_cntl::{Clock, Rtc, RtcClock, sleep::WakeupLevel},
+    rtc_cntl::{Rtc, RtcClock, sleep::WakeupLevel},
 };
 
 // Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
@@ -79,7 +79,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustlemnt like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();

esp-hal/src/rtc_cntl/sleep/esp32c2.rs

@@ -2,7 +2,7 @@ use super::{TimerWakeupSource, WakeSource, WakeTriggers, WakeupLevel};
 use crate::{
     gpio::{RtcFunction, RtcPinWithResistors},
     peripherals::{APB_CTRL, BB, EXTMEM, GPIO, IO_MUX, LPWR, SPI0, SPI1, SYSTEM},
-    rtc_cntl::{Clock, Rtc, RtcClock, sleep::RtcioWakeupSource},
+    rtc_cntl::{Rtc, RtcClock, sleep::RtcioWakeupSource},
     soc::regi2c,
 };
 
@@ -100,7 +100,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustlemnt like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();

esp-hal/src/rtc_cntl/sleep/esp32c3.rs

@@ -2,7 +2,7 @@ use super::{TimerWakeupSource, WakeSource, WakeTriggers, WakeupLevel};
 use crate::{
     gpio::{RtcFunction, RtcPinWithResistors},
     peripherals::{APB_CTRL, BB, EXTMEM, FE, FE2, GPIO, IO_MUX, LPWR, NRX, SPI0, SPI1, SYSTEM},
-    rtc_cntl::{Clock, Rtc, RtcClock, sleep::RtcioWakeupSource},
+    rtc_cntl::{Rtc, RtcClock, sleep::RtcioWakeupSource},
     soc::regi2c,
 };
 
@@ -99,7 +99,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustlemnt like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();

esp-hal/src/rtc_cntl/sleep/esp32c6.rs

@@ -1,7 +1,6 @@
 use core::ops::Not;
 
 use crate::{
-    clock::Clock,
     gpio::RtcFunction,
     rtc_cntl::{
         Rtc,
@@ -32,7 +31,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustment like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();

esp-hal/src/rtc_cntl/sleep/esp32h2.rs

@@ -1,7 +1,6 @@
 use core::ops::Not;
 
 use crate::{
-    clock::Clock,
     gpio::{AnyPin, Input, InputConfig, Pull, RtcPin},
     peripherals::APB_SARADC,
     rtc_cntl::{
@@ -26,7 +25,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustment like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();

esp-hal/src/rtc_cntl/sleep/esp32s2.rs

@@ -9,7 +9,7 @@ use super::{
 use crate::{
     gpio::{RtcFunction, RtcPin},
     peripherals::{EXTMEM, LPWR, RTC_IO, SENS, SPI0, SPI1, SYSTEM},
-    rtc_cntl::{Clock, Rtc, RtcClock, sleep::RtcioWakeupSource},
+    rtc_cntl::{Rtc, RtcClock, sleep::RtcioWakeupSource},
     soc::regi2c,
 };
 
@@ -85,7 +85,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustlemnt like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();

esp-hal/src/rtc_cntl/sleep/esp32s3.rs

@@ -9,7 +9,7 @@ use super::{
 use crate::{
     gpio::{RtcFunction, RtcPin},
     peripherals::{APB_CTRL, EXTMEM, LPWR, RTC_IO, SPI0, SPI1, SYSTEM},
-    rtc_cntl::{Clock, Rtc, RtcClock, sleep::RtcioWakeupSource},
+    rtc_cntl::{Rtc, RtcClock, sleep::RtcioWakeupSource},
     soc::regi2c,
 };
 
@@ -93,7 +93,7 @@ impl WakeSource for TimerWakeupSource {
         let clock_freq = RtcClock::slow_freq();
         // TODO: maybe add sleep time adjustlemnt like idf
         // TODO: maybe add check to prevent overflow?
-        let clock_hz = clock_freq.frequency().as_hz() as u64;
+        let clock_hz = clock_freq.as_hz() as u64;
         let ticks = self.duration.as_micros() as u64 * clock_hz / 1_000_000u64;
         // "alarm" time in slow rtc ticks
         let now = rtc.time_since_boot_raw();