Add RISC-V Vector (RVV) Support for XXH3 #4471
Description
Description
Background
Zstandard (Zstd) is a widely used high-performance compression algorithm that relies on the xxhash hash function for fast data hashing during compression and decompression. While XXH3 in Zstd already supports modern CPUs with SIMD instructions for acceleration, it does not yet take advantage of the RISC-V Vector Extension (RVV), which provides more flexible vectorization capabilities compared to traditional SIMD.
RVV enables efficient large-scale data parallel computation on RISC-V hardware, allowing significant performance improvements for algorithms like XXH3 that process large datasets. By leveraging RVV, we can accelerate key step in Zstd, improving overall compression and decompression speed on RISC-V platforms.
Objective
Integrate RVV instructions into the XXH3 hash function, vectorizing core computations to significantly enhance performance on RISC-V platforms, particularly for large-scale datasets.
Expected Outcomes
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Performance Gains: Significantly increase hashing speed in XXH3 on RISC-V hardware supporting RVV, with more pronounced improvements on large datasets.
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Scalability: Enable further RVV-based optimizations for other Zstd components if successful.
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Community Feedback: Solicit feedback from Zstd developers and testers to refine RVV optimization and ensure robust integration.
Conclusion
We have initiated RVV optimization for XXH3 within Zstd and achieved initial results. Further tuning and testing are required, but we expect notable performance improvements for Zstd compression and decompression when leveraging RISC-V vector extensions. Community input is welcome to guide and refine this optimization.
Labels:
enhancementperformanceriscvoptimizationxxh3