From 5f94a5a5d1b0cf7feff8ad4938631d7648c52ba3 Mon Sep 17 00:00:00 2001 From: GitHub Action Date: Mon, 2 Dec 2024 20:42:27 +0000 Subject: [PATCH] Update RGBDS master documentation --- docs/gbz80.7.html | 301 ++++++++++++++++++++++++--------------------- docs/gbz80.7.pdf | Bin 62264 -> 64105 bytes docs/rgbasm.1.pdf | Bin 49889 -> 49889 bytes docs/rgbasm.5.pdf | Bin 107885 -> 107885 bytes docs/rgbds.5.pdf | Bin 49662 -> 49662 bytes docs/rgbds.7.pdf | Bin 28531 -> 28531 bytes docs/rgbfix.1.pdf | Bin 39837 -> 39837 bytes docs/rgbgfx.1.pdf | Bin 63450 -> 63450 bytes docs/rgblink.1.pdf | Bin 38758 -> 38758 bytes docs/rgblink.5.pdf | Bin 37523 -> 37523 bytes 10 files changed, 162 insertions(+), 139 deletions(-) diff --git a/docs/gbz80.7.html b/docs/gbz80.7.html index 22d1c824..9fc3b15e 100644 --- a/docs/gbz80.7.html +++ b/docs/gbz80.7.html @@ -3,21 +3,22 @@

rgbasm(1), including a short description, the number of bytes needed to encode them and the number of CPU - cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete them.

+ cycles at 1MHz (or 2MHz in GBC double speed mode) needed to complete + them.

Note: All arithmetic and logic instructions that use register A as a destination can omit the destination, since it is assumed to be register A by default. So the following two lines have the same effect:

-
OR A,B
-OR B
+
    OR A,B
+    OR B

Furthermore, the CPL instruction can take an optional A destination, since it can only be register A. So the following two lines have the same effect:

-
CPL
-CPL A
+
    CPL
+    CPL A
@@ -37,18 +38,22 @@

(, , HL). -
n8
-
8-bit integer constant.
-
n16
-
16-bit integer constant.
+
n8
+
8-bit integer constant (signed or unsigned, -128 to + ).
+
n16
+
16-bit integer constant (signed or unsigned, + to + ).
e8
-
8-bit offset (-128 to 127).
-
u3
-
3-bit unsigned integer constant - ( to - ).
+
8-bit signed offset (-128 to + 127).
+
u3
+
3-bit unsigned bit index (0 to + , with + 0 as the least significant bit).
cc
-
Condition codes: +
A condition code:
Execute if Z is set.
@@ -61,8 +66,8 @@

vec
-
One of the - vectors (0x00, 0x08, +
An vector + (0x00, 0x08, 0x10, 0x18, 0x20, 0x28, 0x30, and 0x38).
@@ -475,8 +480,8 @@

-

Bitwise AND between the value in r8 and - A.

+

Set A to the bitwise AND between the value in + r8 and A.

Cycles: 1

Bytes: 1

Flags:

@@ -494,8 +499,8 @@

-

Bitwise AND between the byte pointed to by HL - and A.

+

Set A to the bitwise AND between the byte + pointed to by HL and A.

Cycles: 2

Bytes: 1

Flags: See AND A,r8

@@ -503,8 +508,8 @@

-

Bitwise AND between the value in n8 and - A.

+

Set A to the bitwise AND between the value + n8 and A.

Cycles: 2

Bytes: 2

Flags: See AND A,r8

@@ -538,11 +543,11 @@

-

Call address n16. This pushes the address of - the instruction after the - on - the stack, such that RET can pop it later; - then, it executes an implicit JP n16.

+

Call address n16.

+

This pushes the address of the instruction after the + on the stack, + such that RET can pop it later; then, it + executes an implicit JP n16.

Cycles: 6

Bytes: 3

Flags: None affected.

@@ -574,9 +579,10 @@

-

Subtract the value in r8 from - A and set flags accordingly, but don't store the result. - This is useful for ComParing values.

+

ComPare the value in A with the value in + r8.

+

This subtracts the value in r8 from + A and sets flags accordingly, but discards the result.

Cycles: 1

Bytes: 1

Flags:

@@ -595,9 +601,10 @@

-

Subtract the byte pointed to by HL from - A and set flags accordingly, but don't store the - result.

+

ComPare the value in A with the byte pointed to + by HL.

+

This subtracts the byte pointed to by HL from + A and sets flags accordingly, but discards the result.

Cycles: 2

Bytes: 1

Flags: See CP A,r8

@@ -605,9 +612,10 @@

-

Subtract the value n8 from - A and set flags accordingly, but don't store the - result.

+

ComPare the value in A with the value + n8.

+

This subtracts the value n8 from + A and sets flags accordingly, but discards the result.

Cycles: 2

Bytes: 2

Flags: See CP A,r8

@@ -615,7 +623,8 @@

ComPLement accumulator (A = - ).

+ ); also + called bitwise NOT.

Cycles: 1

Bytes: 1

Flags:

@@ -636,7 +645,8 @@

) whose inputs were in Binary-Coded Decimal (BCD), adjusting the result to likewise be in BCD.

-

The exact behavior of this instruction is as follows:

+

The exact behavior of this instruction depends on the state of the + subtract flag N:

If the subtract flag N is @@ -685,7 +695,7 @@

-

Decrement value in register r8 by 1.

+

Decrement the value in register r8 by 1.

Cycles: 1

Bytes: 1

Flags:

@@ -709,14 +719,15 @@

-

Decrement value in register r16 by 1.

+

Decrement the value in register r16 by + 1.

Cycles: 2

Bytes: 1

Flags: None affected.

-

Decrement value in register SP by 1.

+

Decrement the value in register SP by 1.

Cycles: 2

Bytes: 1

Flags: None affected.

@@ -730,49 +741,46 @@

-

Enable Interrupts by setting the IME flag. The - flag is only set after the instruction following - EI.

+

Enable Interrupts by setting the IME flag.

+

The flag is only set after the instruction + following EI.

Cycles: 1

Bytes: 1

Flags: None affected.

-

Enter CPU low-power consumption mode until an interrupt occurs. - The exact behavior of this instruction depends on the state of the - IME flag.

+

Enter CPU low-power consumption mode until an interrupt + occurs.

+

The exact behavior of this instruction depends on the state of the + IME flag, and whether interrupts are pending (i.e. whether + ‘[IE] & [IF]’ is non-zero):

+
-
- set
+
If the IME flag is set:
The CPU enters low-power mode until after an interrupt is about to be serviced. The handler is executed normally, and the CPU resumes execution after the HALT when that returns.
-
- not set
-
The behavior depends on whether an interrupt is pending (i.e. - ‘[IE] & [IF]’ is non-zero). -
-
None pending
-
As soon as an interrupt becomes pending, the CPU resumes execution. - This is like the above, except that the handler is - - called.
-
Some pending
-
The CPU continues execution after the HALT, - but the byte after it is read twice in a row (PC is - not incremented, due to a hardware bug).
-
-
+
If the IME flag is not set, + and no interrupts are pending:
+
As soon as an interrupt becomes pending, the CPU resumes execution. This + is like the above, except that the handler is + called.
+
If the IME flag is not set, and some + interrupt is pending:
+
The CPU continues execution after the HALT, but + the byte after it is read twice in a row (PC is not + incremented, due to a hardware bug).
+

Cycles: -

Bytes: 1

Flags: None affected.

-

Increment value in register r8 by 1.

+

Increment the value in register r8 by 1.

Cycles: 1

Bytes: 1

Flags:

@@ -796,21 +804,22 @@

-

Increment value in register r16 by 1.

+

Increment the value in register r16 by + 1.

Cycles: 2

Bytes: 1

Flags: None affected.

-

Increment value in register SP by 1.

+

Increment the value in register SP by 1.

Cycles: 2

Bytes: 1

Flags: None affected.

-

Jump to address n16; effectively, store +

Jump to address n16; effectively, copy n16 into PC.

Cycles: 4

Bytes: 3

@@ -827,19 +836,20 @@

-

Jump to address in HL; effectively, load - PC with value in register HL.

+

Jump to address in HL; effectively, copy the + value in register HL into PC.

Cycles: 1

Bytes: 1

Flags: None affected.

-

Relative Jump to address n16. The address is - encoded as a signed 8-bit offset from the address immediately following the - JR instruction, so the target address - n16 must be between -128 and - 127 bytes away. For example:

+

Relative Jump to address n16.

+

The address is encoded as a signed 8-bit offset from the address + immediately following the JR instruction, so the + target address n16 must be between + -128 and 127 bytes away. For + example:

    JR Label  ; no-op; encoded offset of 0
 Label:
@@ -861,8 +871,12 @@ 

-
Load (copy) value in register on the right into register on the
-    left.

+
Copy (aka Load) the value in register on the right into the
+    register on the left.

+
Storing a register into itself is a no-op; however, some Game Boy
+    emulators interpret LD B,B as a breakpoint, or
+    LD D,D as a debug message (such as
+    BGB).

 
Cycles: 1

 
Bytes: 1

 
Flags: None affected.

@@ -870,7 +884,7 @@ 

-
Load value n8 into register
+
Copy the value n8 into register
     r8.

 
Cycles: 2

 
Bytes: 2

@@ -879,7 +893,7 @@ 

-
Load value n16 into register
+
Copy the value n16 into register
     r16.

 
Cycles: 3

 
Bytes: 3

@@ -888,8 +902,8 @@ 

-
Store value in register r8 into the byte
-    pointed to by register HL.

+
Copy the value in register r8 into the byte
+    pointed to by HL.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -897,8 +911,8 @@ 

-
Store value n8 into the byte pointed to by
-    register HL.

+
Copy the value n8 into the byte pointed to
+    by HL.

 
Cycles: 3

 
Bytes: 2

 
Flags: None affected.

@@ -906,8 +920,8 @@ 

-
Load value into register r8 from the byte
-    pointed to by register HL.

+
Copy the value pointed to by HL into register
+    r8.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -915,8 +929,8 @@ 

-
Store value in register A into the byte pointed
-    to by register r16.

+
Copy the value in register A into the byte
+    pointed to by r16.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -924,7 +938,7 @@ 

-
Store value in register A into the byte at
+
Copy the value in register A into the byte at
     address n16.

 
Cycles: 4

 
Bytes: 3

@@ -933,7 +947,7 @@ 

-
Store value in register A into the byte at
+
Copy the value in register A into the byte at
     address n16, provided the address is between
     $FF00 and $FFFF.

 
Cycles: 3

@@ -946,7 +960,7 @@ 

-
Store value in register A into the byte at
+
Copy the value in register A into the byte at
     address $FF00+C.

 
Cycles: 2

 
Bytes: 1

@@ -958,8 +972,8 @@ 

-
Load value in register A from the byte pointed
-    to by register r16.

+
Copy the byte pointed to by r16 into
+    register A.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -967,8 +981,8 @@ 

-
Load value in register A from the byte at
-    address n16.

+
Copy the byte at address n16 into register
+    A.

 
Cycles: 4

 
Bytes: 3

 
Flags: None affected.

@@ -976,8 +990,8 @@ 

-
Load value in register A from the byte at
-    address n16, provided the address is between
+
Copy the byte at address n16 into register
+    A, provided the address is between
     $FF00 and $FFFF.

 
Cycles: 3

 
Bytes: 2

@@ -989,8 +1003,8 @@ 

-
Load value in register A from the byte at
-    address $FF00+c.

+
Copy the byte at address $FF00+c into
+    register A.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -1001,8 +1015,9 @@ 

-
Store value in register A into the byte pointed
-    by HL and increment HL afterwards.

+
Copy the value in register A into the byte
+    pointed by HL and increment HL
+    afterwards.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -1013,8 +1028,9 @@ 

-
Store value in register A into the byte pointed
-    by HL and decrement HL afterwards.

+
Copy the value in register A into the byte
+    pointed by HL and decrement HL
+    afterwards.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -1025,8 +1041,8 @@ 

-
Load value into register A from the byte pointed
-    by HL and decrement HL afterwards.

+
Copy the byte pointed to by HL into register
+    A, and decrement HL afterwards.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -1037,8 +1053,8 @@ 

-
Load value into register A from the byte pointed
-    by HL and increment HL afterwards.

+
Copy the byte pointed to by HL into register
+    A, and increment HL afterwards.

 
Cycles: 2

 
Bytes: 1

 
Flags: None affected.

@@ -1049,7 +1065,7 @@ 

-
Load value n16 into register
+
Copy the value n16 into register
     SP.

 
Cycles: 3

 
Bytes: 3

@@ -1058,7 +1074,7 @@ 

-
Store SP & $FF at
+
Copy SP & $FF at
     address n16 and SP >> 8 at
     address n16 + 1.

 
Cycles: 5

@@ -1069,7 +1085,7 @@ 

 
Add the signed value e8 to
-    SP and store the result in HL.

+    SP and copy the result in HL.

 
Cycles: 3

 
Bytes: 2

 
Flags:

@@ -1087,7 +1103,7 @@ 

-
Load register HL into register
+
Copy register HL into register
     SP.

 
Cycles: 2

 
Bytes: 1

@@ -1103,7 +1119,7 @@ 

 

 

-
Store into A the bitwise OR of the value in
+
Set A to the bitwise OR between the value in
     r8 and A.

 
Cycles: 1

 
Bytes: 1

@@ -1122,7 +1138,7 @@ 

-
Store into A the bitwise OR of the byte pointed
+
Set A to the bitwise OR between the byte pointed
     to by HL and A.

 
Cycles: 2

 
Bytes: 1

@@ -1131,7 +1147,7 @@ 

-
Store into A the bitwise OR of
+
Set A to the bitwise OR between the value
     n8 and A.

 
Cycles: 2

 
Bytes: 2

@@ -1142,10 +1158,10 @@ 

 
Pop register AF from the stack. This is roughly
     equivalent to the following imaginary instructions:

 

-
ld f, [sp] ; See below for individual flags
-inc sp
-ld a, [sp]
-inc sp

+
    LD F, [SP]  ; See below for individual flags
+    INC SP
+    LD A, [SP]
+    INC SP

 

 
Cycles: 3

 
Bytes: 1

@@ -1168,10 +1184,10 @@ 

-
Enter CPU very low power mode. Also used to switch between double
-    and normal speed CPU modes in GBC.

+
Enter CPU very low power mode. Also used to switch between GBC
+    double speed and normal speed CPU modes.

+
The exact behavior of this instruction is fragile and may
+    interpret its second byte as a separate instruction (see
+    the
+    Pan Docs), which is why rgbasm(1)
+    allows explicitly specifying the second byte (STOP
+    n8) to override the default of
+    $00 (a NOP instruction).

 
Cycles: -

 
Bytes: 2

 
Flags: None affected.

@@ -1772,8 +1795,8 @@ 

-
Bitwise XOR between the value in r8 and
-    A.

+
Set A to the bitwise XOR between the value in
+    r8 and A.

 
Cycles: 1

 
Bytes: 1

 
Flags:

@@ -1791,8 +1814,8 @@ 

-
Bitwise XOR between the byte pointed to by HL
-    and A.

+
Set A to the bitwise XOR between the byte
+    pointed to by HL and A.

 
Cycles: 2

 
Bytes: 1

 
Flags: See XOR A,r8

@@ -1800,8 +1823,8 @@ 

-
Bitwise XOR between the value in n8 and
-    A.

+
Set A to the bitwise XOR between the value
+    n8 and A.

 
Cycles: 2

 
Bytes: 2

 
Flags: See XOR A,r8

diff --git a/docs/gbz80.7.pdf b/docs/gbz80.7.pdf
index 92d256080b3b35c75bb8a47ca1c8eb6c19c48725..4a8c60113da5675b455c9cc8d556ec5445c7c246 100644
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diff --git a/docs/rgbasm.1.pdf b/docs/rgbasm.1.pdf
index 0ace0d482b53a8f0336c10dbf3e6c115da2143d7..2973e76fb0b69632e039eadcc97fb4a73cb955ff 100644
GIT binary patch
delta 38
lcmaFZ%KWgEd4s+Yr;&k?k%5Vkk=bMmBP#@NbG1?01OVb13kv`M

delta 38
lcmaFZ%KWgEd4s+Yr=gLhp{a?Hsl{XqBP#@NbG1?01OVh%3oQTu

diff --git a/docs/rgbasm.5.pdf b/docs/rgbasm.5.pdf
index b46bd0c56fa9f3a3eaa22bb99a07befdc2b8987f..1925872f2d8e8e27669c28ab2d2be5d3e32fc96a 100644
GIT binary patch
delta 42
qcmaERitX(wwuUW?Cj~f-42+BnOpJ`ore6|Zv_f#ViwZJEOaTBq@eH8=

delta 42
qcmaERitX(wwuUW?Cj~eSjVujKO^i$}re6|Zv_f#ViwZJEOaTBtVhqCo

diff --git a/docs/rgbds.5.pdf b/docs/rgbds.5.pdf
index aabf31c00391899a92334bbbc123d0565be39f28..0665c4edb1bced88a71accb0deaac0bbe53deef9 100644
GIT binary patch
delta 38
lcmey@%>1vJd4r50r;&k?k%5Vkk=bNbLn{PtbB5ux2>|903pD@$

delta 38
lcmey@%>1vJd4r50r=gLhp{a?Hsl{YfLn{PtbB5ux2>|F$3s(RD

diff --git a/docs/rgbds.7.pdf b/docs/rgbds.7.pdf
index cbd36fac52cd4503165af0acdccd63321dca642b..31480c3d829f6be6beeee58b560365d64edf2256 100644
GIT binary patch
delta 38
mcmex-kMZ+8#tkz$IE@U9j0{YSjLau5;;=&SHb3R)O9KE6ZVa6O

delta 38
mcmex-kMZ+8#tkz$I1P;~4NXmqOf4rb;;=&SHb3R)O9KE8tPH;Z

diff --git a/docs/rgbfix.1.pdf b/docs/rgbfix.1.pdf
index 78c24ca845db93d816c5ca9cabace65b1898640c..e46305575aa662dabe96b09cd8f9f255d6162c76 100644
GIT binary patch
delta 38
mcmbQcooViNrVRxOoJIylMg}HEM&^?%6|4}v&3hCcRsjI#It$qV

delta 38
mcmbQcooViNrVRxOoQ6i0hNdP)rk0Z{6|4}v&3hCcRsjI%cnkXg

diff --git a/docs/rgbgfx.1.pdf b/docs/rgbgfx.1.pdf
index 121673a77b0ba434ddbd0216d627564274297d46..52a454bbf8459536a44ef753a44b272726ada78b 100644
GIT binary patch
delta 38
mcmcchp83{$<_$B_IE@U9j0{YSjLau5OtV7pHa|)GHUR)0uMRo@

delta 38
mcmcchp83{$<_$B_I1P;~4NXmqOf4rbOtV7pHa|)GHUR)2?G9W3

diff --git a/docs/rgblink.1.pdf b/docs/rgblink.1.pdf
index 548f5ed748aeb0814c3018efb37abb13347ea73c..f3cfc9b44fed032625d333d928dc2de75c6bb958 100644
GIT binary patch
delta 38
lcmaF1j_KJtrVW-doJIylMg}HEM&^^9WULUp&8;#Is{rj`3#b49

delta 38
lcmaF1j_KJtrVW-doQ6i0hNdP)rk0bPWULUp&8;#Is{rqx3(5ch

diff --git a/docs/rgblink.5.pdf b/docs/rgblink.5.pdf
index 1410f1d5755d9d7cad6ca4f974d8e3ad65b7152e..15c2bc0f9f6dab6984c787ef000c656ce05c5165 100644
GIT binary patch
delta 38
mcmbQdlxgx(rVZ1?IgJdAj0{YSjLav`7q>$2Ha`;ISOoy(9t+3-

delta 38
mcmbQdlxgx(rVZ1?ISq|04NXmqOf4tR7q>$2Ha`;ISOoy*Tnp*|