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MarijnS95MarijnS95
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Regenerate on sdk-1.4.328.1 
1 parent b364681 commit 47da63d

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14 files changed

+1031
-101
lines changed

14 files changed

+1031
-101
lines changed

‎autogen/external/SPIRV-Headers‎

Submodule SPIRV-Headers updated 22 files

‎autogen/src/sr.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -491,7 +491,7 @@ pub fn gen_sr_code_from_instruction_grammar(
491491
};
492492

493493
let ops = quote! {
494-
use crate::sr::{module::Jump, storage::Token, Type};
494+
use crate::sr::{module::Jump, storage::Token, Constant, Type};
495495

496496
#[derive(Clone, Debug, Eq, PartialEq)]
497497
pub enum Branch {

‎rspirv/binary/autogen_parse_operand.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -660,6 +660,7 @@ impl Parser<'_, '_> {
660660
spirv::Decoration::ImplementInRegisterMapINTEL => {
661661
vec![dr::Operand::LiteralBit32(self.decoder.bit32()?)]
662662
}
663+
spirv::Decoration::ConditionalINTEL => vec![dr::Operand::IdRef(self.decoder.id()?)],
663664
spirv::Decoration::CacheControlLoadINTEL => vec![
664665
dr::Operand::LiteralBit32(self.decoder.bit32()?),
665666
dr::Operand::LoadCacheControl(self.decoder.load_cache_control()?),

‎rspirv/dr/autogen_operand.rs‎

Lines changed: 33 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,14 +1137,12 @@ impl Operand {
11371137
},
11381138
Self::ExecutionMode(v) => match v {
11391139
s::ExecutionMode::LocalSize | s::ExecutionMode::LocalSizeId => vec![],
1140-
s::ExecutionMode::DerivativeGroupLinearKHR => vec![
1141-
spirv::Capability::ComputeDerivativeGroupLinearNV,
1142-
spirv::Capability::ComputeDerivativeGroupLinearKHR,
1143-
],
1144-
s::ExecutionMode::DerivativeGroupQuadsKHR => vec![
1145-
spirv::Capability::ComputeDerivativeGroupQuadsNV,
1146-
spirv::Capability::ComputeDerivativeGroupQuadsKHR,
1147-
],
1140+
s::ExecutionMode::DerivativeGroupLinearKHR => {
1141+
vec![spirv::Capability::ComputeDerivativeGroupLinearKHR]
1142+
}
1143+
s::ExecutionMode::DerivativeGroupQuadsKHR => {
1144+
vec![spirv::Capability::ComputeDerivativeGroupQuadsKHR]
1145+
}
11481146
s::ExecutionMode::DenormFlushToZero => vec![spirv::Capability::DenormFlushToZero],
11491147
s::ExecutionMode::DenormPreserve => vec![spirv::Capability::DenormPreserve],
11501148
s::ExecutionMode::NumSIMDWorkitemsINTEL
@@ -1691,6 +1689,7 @@ impl Operand {
16911689
vec![spirv::Capability::ShaderStereoViewNV]
16921690
}
16931691
s::Decoration::ViewportRelativeNV => vec![spirv::Capability::ShaderViewportMaskNV],
1692+
s::Decoration::ConditionalINTEL => vec![spirv::Capability::SpecConditionalINTEL],
16941693
s::Decoration::Patch => vec![spirv::Capability::Tessellation],
16951694
s::Decoration::XfbBuffer | s::Decoration::XfbStride => {
16961695
vec![spirv::Capability::TransformFeedback]
@@ -2057,6 +2056,7 @@ impl Operand {
20572056
| s::Capability::Subgroup2DBlockIOINTEL
20582057
| s::Capability::SubgroupMatrixMultiplyAccumulateINTEL
20592058
| s::Capability::TernaryBitwiseFunctionINTEL
2059+
| s::Capability::SpecConditionalINTEL
20602060
| s::Capability::GroupUniformArithmeticKHR
20612061
| s::Capability::TensorFloat32RoundingINTEL
20622062
| s::Capability::MaskedGatherScatterINTEL
@@ -2070,6 +2070,9 @@ impl Operand {
20702070
spirv::Capability::BFloat16TypeKHR,
20712071
spirv::Capability::CooperativeMatrixKHR,
20722072
],
2073+
s::Capability::CooperativeMatrixConversionQCOM => {
2074+
vec![spirv::Capability::CooperativeMatrixKHR]
2075+
}
20732076
s::Capability::SubgroupDispatch => vec![spirv::Capability::DeviceEnqueue],
20742077
s::Capability::FPGAClusterAttributesV2INTEL => {
20752078
vec![spirv::Capability::FPGAClusterAttributesINTEL]
@@ -2228,6 +2231,9 @@ impl Operand {
22282231
vec![spirv::Capability::ShaderViewportIndexLayerEXT]
22292232
}
22302233
s::Capability::ShaderStereoViewNV => vec![spirv::Capability::ShaderViewportMaskNV],
2234+
s::Capability::FunctionVariantsINTEL => {
2235+
vec![spirv::Capability::SpecConditionalINTEL]
2236+
}
22312237
s::Capability::UniformAndStorageBuffer16BitAccess => {
22322238
vec![spirv::Capability::StorageBuffer16BitAccess]
22332239
}
@@ -2239,6 +2245,10 @@ impl Operand {
22392245
vec![spirv::Capability::Subgroup2DBlockIOINTEL]
22402246
}
22412247
s::Capability::TessellationPointSize => vec![spirv::Capability::Tessellation],
2248+
s::Capability::UntypedVariableLengthArrayINTEL => vec![
2249+
spirv::Capability::VariableLengthArrayINTEL,
2250+
spirv::Capability::UntypedPointersKHR,
2251+
],
22422252
s::Capability::VariablePointers => {
22432253
vec![spirv::Capability::VariablePointersStorageBuffer]
22442254
}
@@ -2894,6 +2904,7 @@ impl Operand {
28942904
| s::Decoration::HostAccessINTEL
28952905
| s::Decoration::InitModeINTEL
28962906
| s::Decoration::ImplementInRegisterMapINTEL
2907+
| s::Decoration::ConditionalINTEL
28972908
| s::Decoration::CacheControlLoadINTEL
28982909
| s::Decoration::CacheControlStoreINTEL => vec![],
28992910
s::Decoration::ExplicitInterpAMD => {
@@ -3296,6 +3307,9 @@ impl Operand {
32963307
s::Capability::FunctionPointersINTEL | s::Capability::IndirectReferencesINTEL => {
32973308
vec!["SPV_INTEL_function_pointers"]
32983309
}
3310+
s::Capability::SpecConditionalINTEL | s::Capability::FunctionVariantsINTEL => {
3311+
vec!["SPV_INTEL_function_variants"]
3312+
}
32993313
s::Capability::GlobalVariableFPGADecorationsINTEL => {
33003314
vec!["SPV_INTEL_global_variable_fpga_decorations"]
33013315
}
@@ -3343,7 +3357,10 @@ impl Operand {
33433357
vec!["SPV_INTEL_unstructured_loop_controls"]
33443358
}
33453359
s::Capability::USMStorageClassesINTEL => vec!["SPV_INTEL_usm_storage_classes"],
3346-
s::Capability::VariableLengthArrayINTEL => vec!["SPV_INTEL_variable_length_array"],
3360+
s::Capability::VariableLengthArrayINTEL
3361+
| s::Capability::UntypedVariableLengthArrayINTEL => {
3362+
vec!["SPV_INTEL_variable_length_array"]
3363+
}
33473364
s::Capability::VectorComputeINTEL | s::Capability::VectorAnyINTEL => {
33483365
vec!["SPV_INTEL_vector_compute"]
33493366
}
@@ -3465,6 +3482,9 @@ impl Operand {
34653482
s::Capability::ShaderStereoViewNV => vec!["SPV_NV_stereo_view_rendering"],
34663483
s::Capability::TensorAddressingNV => vec!["SPV_NV_tensor_addressing"],
34673484
s::Capability::ShaderViewportMaskNV => vec!["SPV_NV_viewport_array2"],
3485+
s::Capability::CooperativeMatrixConversionQCOM => {
3486+
vec!["SPV_QCOM_cooperative_matrix_conversion"]
3487+
}
34683488
s::Capability::TextureSampleWeightedQCOM
34693489
| s::Capability::TextureBoxFilterQCOM
34703490
| s::Capability::TextureBlockMatchQCOM => vec!["SPV_QCOM_image_processing"],
@@ -3956,6 +3976,10 @@ impl Operand {
39563976
kind: crate::grammar::OperandKind::IdRef,
39573977
quantifier: crate::grammar::OperandQuantifier::One,
39583978
}],
3979+
s::Decoration::ConditionalINTEL => vec![crate::grammar::LogicalOperand {
3980+
kind: crate::grammar::OperandKind::IdRef,
3981+
quantifier: crate::grammar::OperandQuantifier::One,
3982+
}],
39593983
s::Decoration::CounterBuffer => vec![crate::grammar::LogicalOperand {
39603984
kind: crate::grammar::OperandKind::IdRef,
39613985
quantifier: crate::grammar::OperandQuantifier::One,

‎rspirv/dr/build/autogen_constant.rs‎

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,4 +168,68 @@ impl Builder {
168168
self.module.types_global_values.push(inst);
169169
id
170170
}
171+
#[doc = "Appends an OpSpecConstantTargetINTEL instruction."]
172+
pub fn spec_constant_target_intel(
173+
&mut self,
174+
result_type: spirv::Word,
175+
target: u32,
176+
features: impl IntoIterator<Item = u32>,
177+
) -> spirv::Word {
178+
let id = self.id();
179+
#[allow(unused_mut)]
180+
let mut inst = dr::Instruction::new(
181+
spirv::Op::SpecConstantTargetINTEL,
182+
Some(result_type),
183+
Some(id),
184+
vec![dr::Operand::LiteralBit32(target)],
185+
);
186+
inst.operands
187+
.extend(features.into_iter().map(dr::Operand::LiteralBit32));
188+
self.module.types_global_values.push(inst);
189+
id
190+
}
191+
#[doc = "Appends an OpSpecConstantArchitectureINTEL instruction."]
192+
pub fn spec_constant_architecture_intel(
193+
&mut self,
194+
result_type: spirv::Word,
195+
category: u32,
196+
family: u32,
197+
opcode: u32,
198+
architecture: u32,
199+
) -> spirv::Word {
200+
let id = self.id();
201+
#[allow(unused_mut)]
202+
let mut inst = dr::Instruction::new(
203+
spirv::Op::SpecConstantArchitectureINTEL,
204+
Some(result_type),
205+
Some(id),
206+
vec![
207+
dr::Operand::LiteralBit32(category),
208+
dr::Operand::LiteralBit32(family),
209+
dr::Operand::LiteralBit32(opcode),
210+
dr::Operand::LiteralBit32(architecture),
211+
],
212+
);
213+
self.module.types_global_values.push(inst);
214+
id
215+
}
216+
#[doc = "Appends an OpSpecConstantCapabilitiesINTEL instruction."]
217+
pub fn spec_constant_capabilities_intel(
218+
&mut self,
219+
result_type: spirv::Word,
220+
capabilities: impl IntoIterator<Item = spirv::Capability>,
221+
) -> spirv::Word {
222+
let id = self.id();
223+
#[allow(unused_mut)]
224+
let mut inst = dr::Instruction::new(
225+
spirv::Op::SpecConstantCapabilitiesINTEL,
226+
Some(result_type),
227+
Some(id),
228+
vec![],
229+
);
230+
inst.operands
231+
.extend(capabilities.into_iter().map(dr::Operand::Capability));
232+
self.module.types_global_values.push(inst);
233+
id
234+
}
171235
}

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