GF180MCU Oklahoma State University Standard-Cell Library characterized with TT corner at 25 C #2
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…es in syn directory
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stineje
changed the title
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Signed-off-by: James E. Stine <[email protected]>
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…9t3v3 directories respectively.
… the drive strength in the cell directory names.
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Noticed that the PDK docs shows an area of |
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Hi @mithro , is there anything else keeping this from moving forward? All the issues I see mentioned in this conversation appear to be resolved (aside from the CLA) |
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Like discussed in the PR review comments, would be nice to get an update on the README that describe how this standard cell library differ from the one included in the PDK (reference voltage, feature size): |
…nd added in tlef for both 12t and 9t variants.
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…u_osu_sc_gp12t3v3 and gf180mcu_osu_sc_gp9t3v3 tlef subdirectories respectively.
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First thing that I noted, is that there are no CDL netlist. I can only see spice netlist. Any chance we can add CDL netlist as well. Spice netlists are used for simulation. Also, I recommend adding CI for running DRC and LVS of the GDS against the CDL netlist provided to make sure that netlist always match the GDS. Here is the recommended PV repo for running LVS: https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pv I haven't finished my review. But I'll take a closer look tomorrow. |
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@stineje area = 0 is common in all cells. And any comment on one cell applies to all of the generated output.
Extra common files need to be added per cell:
- CDL files for all cells.
- Different Verilog files (Functional, Behavioral, With Power, Without Power)
- Xschem symbol files for each cell.
Also, if we can include the following CI for this repo would be great:
- Run Klayout/magic DRC on all cells.
- Run klayout LVS on all cells.
- Add a CI that randomly pick 10 cells and run ngspice simulation on the spice netlist using models and match the measurement with the values in the "lib". I'm not sure if there an automated way in CI to detect which files has changed. And if there a lib file that has changed in this commit. It only runs that on that specific file. May be @proppy would know better about this.
There is one thing else related to LEF against GDS comparison. But I need to think about it and get back to you.
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| cell (gf180mcu_osu_sc_gp12t3v3__addf_1) { | ||
| area : 0; |
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@stineje Area is set to zero?
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| cell (gf180mcu_osu_sc_gp12t3v3__addh_1) { | ||
| area : 0; |
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Area is set to zero?
| * See the License for the specific language governing permissions and | ||
| * limitations under the License. | ||
| cell (gf180mcu_osu_sc_gp12t3v3__clkbuf_1) { | ||
| area : 0; |
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@stineje Area is set to zero?
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@stineje Could you please name them according to the naming scheme similar to this one?
I believe this file is behavioral without power supply
Behavioral pp for behavioral implementation with power supply:
https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0/blob/main/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.behavioral.pp.v
Behavioral for behavioral implementation without power supply:
https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0/blob/main/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.behavioral.v
Functional pp for behavioral implementation with power supply:
https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0/blob/main/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.functional.pp.v
Functional for behavioral implementation without power supply:
https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0/blob/main/cells/addf/gf180mcu_fd_sc_mcu9t5v0__addf_2.functional.v
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@stineje Could you please add symbol files for xschem for all cells? You could borrow them from: https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0/tree/main/cells
I believe there is a script that could generate that as well. May be @proppy and @mithro has it.
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@stineje area = 0 is common in all cells. And any comment on one cell applies to all of the generated output.
Extra common files need to be added per cell:
- CDL files for all cells.
- Different Verilog files (Functional, Behavioral, With Power, Without Power)
- Xschem symbol files for each cell.
Also, if we can include the following CI for this repo would be great:
- Run Klayout/magic DRC on all cells.
- Run klayout LVS on all cells.
- Add a CI that randomly pick 10 cells and run ngspice simulation on the spice netlist using models and match the measurement with the values in the "lib". I'm not sure if there an automated way in CI to detect which files has changed. And if there a lib file that has changed in this commit. It only runs that on that specific file. May be @proppy would know better about this.
There is one thing else related to LEF against GDS comparison. But I need to think about it and get back to you.
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| * NGSPICE file created from gf180mcu_osu_sc_gp12t3v3__aoi22_1.ext - technology: gf180mcuC | ||
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| .subckt gf180mcu_osu_sc_gp12t3v3__aoi22_1 Y A0 A1 B0 B1 |
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This subcircuit definition appears to be missing the VDD and VSS inputs.
Fixes #<issue_number_goes_here>