[XLS] Enable internal FIFO materialization for several examples

ericastor · copybara-github · commit 9dfd0b42ed3d · 2025-01-03T15:24:18.000-08:00
We currently require an external FIFO definition by default, and these targets only passed due to not requiring a definition for depth-0 FIFOs before commit 4b262b0 We're planning to land a more batteries-included solution soon. PiperOrigin-RevId: 711868494
diff --git a/xls/examples/BUILD b/xls/examples/BUILD
@@ -834,6 +834,7 @@ xls_ir_verilog(
         "streaming_channel_ready_suffix": "_ready",
         "streaming_channel_valid_suffix": "_valid",
         "use_system_verilog": "true",
+        "materialize_internal_fifos": "true",
     },
     verilog_file = "delay.sv",
 )
diff --git a/xls/modules/zstd/memory/BUILD b/xls/modules/zstd/memory/BUILD
@@ -386,6 +386,7 @@ mem_reader_codegen_args = common_codegen_args | {
     "flop_inputs_kind": "skid",
     "flop_outputs_kind": "skid",
     "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,
+    "materialize_internal_fifos": "true",
 }
 
 xls_dslx_verilog(
@@ -440,6 +441,7 @@ mem_reader_adv_codegen_args = common_codegen_args | {
     "flop_inputs_kind": "skid",
     "flop_outputs_kind": "skid",
     "clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,
+    "materialize_internal_fifos": "true",
 }
 
 xls_dslx_verilog(
@@ -668,6 +670,7 @@ mem_writer_codegen_args = common_codegen_args | {
     "flop_inputs_kind": "skid",
     "flop_outputs_kind": "skid",
     "worst_case_throughput": "1",
+    "materialize_internal_fifos": "true",
 }
 
 xls_dslx_verilog(

Original file line number	Diff line number	Diff line change
`@@ -834,6 +834,7 @@ xls_ir_verilog(`
`834`	`834`	`"streaming_channel_ready_suffix": "_ready",`
`835`	`835`	`"streaming_channel_valid_suffix": "_valid",`
`836`	`836`	`"use_system_verilog": "true",`
	`837`	`+ "materialize_internal_fifos": "true",`
`837`	`838`	`},`
`838`	`839`	`verilog_file = "delay.sv",`
`839`	`840`	`)`
Original file line number	Diff line number	Diff line change
`@@ -386,6 +386,7 @@ mem_reader_codegen_args = common_codegen_args \| {`
`386`	`386`	`"flop_inputs_kind": "skid",`
`387`	`387`	`"flop_outputs_kind": "skid",`
`388`	`388`	`"clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,`
	`389`	`+ "materialize_internal_fifos": "true",`
`389`	`390`	`}`
`390`	`391`
`391`	`392`	`xls_dslx_verilog(`
`@@ -440,6 +441,7 @@ mem_reader_adv_codegen_args = common_codegen_args \| {`
`440`	`441`	`"flop_inputs_kind": "skid",`
`441`	`442`	`"flop_outputs_kind": "skid",`
`442`	`443`	`"clock_period_ps": MEM_READER_CLOCK_PERIOD_PS,`
	`444`	`+ "materialize_internal_fifos": "true",`
`443`	`445`	`}`
`444`	`446`
`445`	`447`	`xls_dslx_verilog(`
`@@ -668,6 +670,7 @@ mem_writer_codegen_args = common_codegen_args \| {`
`668`	`670`	`"flop_inputs_kind": "skid",`
`669`	`671`	`"flop_outputs_kind": "skid",`
`670`	`672`	`"worst_case_throughput": "1",`
	`673`	`+ "materialize_internal_fifos": "true",`
`671`	`674`	`}`
`672`	`675`
`673`	`676`	`xls_dslx_verilog(`