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Inter-proc channel operations where data is ignored #1928

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grebe opened this issue Feb 13, 2025 · 0 comments
Open

Inter-proc channel operations where data is ignored #1928

grebe opened this issue Feb 13, 2025 · 0 comments
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codegen Related to emitting (System)Verilog. optimizer Related to IR optimization or analysis 🧦 sox stitching Issues related to stitching, multi-proc codegen, and integration with external verilog modules

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@grebe
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grebe commented Feb 13, 2025

Consider the situation where a receive is performed and the data is ignored- one scenario where this could happen is a top proc with an array of channels where it receives from each of N identical child procs and for whatever reason the top proc drops the data on the floor for half of the children.

Currently, this results in a few different not-great things:

  1. we don't narrow the channels where data is ignored (they could be zero-width)
  2. we don't DCE the unread ports1
  3. we don't waive the unread ports

This problem is currently manifesting for me as unread ports (3), but ideally we'd also have (1) and/or (2) to obviate the need for waivers.

Footnotes

  1. is it a good thing to DCE ports? It might be useful to keep them around to facilitate testing internal blocks, but I don't think we have a strong contract wrt what internal blocks look like.

@grebe grebe added codegen Related to emitting (System)Verilog. optimizer Related to IR optimization or analysis stitching Issues related to stitching, multi-proc codegen, and integration with external verilog modules 🧦 sox labels Feb 13, 2025
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Labels
codegen Related to emitting (System)Verilog. optimizer Related to IR optimization or analysis 🧦 sox stitching Issues related to stitching, multi-proc codegen, and integration with external verilog modules
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