OHCI host driver support for cache operations

[ArcaneNibble]

Related area

ohci, cache

Hardware specification

ohci, TI AM1808

Is your feature request related to a problem?

Hi, I am currently contributing to the Pybricks project to port MicroPython to the Lego Mindstorms EV3. This is built around a TI Sitara AM1808 SoC. We run our own bare-metal code without Linux on this chip.

As part of this effort, we need a USB host stack for the OHCI controller, and we were hoping to use TinyUSB. However, the existing OHCI driver does not handle the requirements to clean/invalidate CPU caches. Caches are very important for performance on a chip such as this because it uses external SDRAM.

Describe the solution you'd like

I currently have a local patchset which appears to function correctly with cache support. The overall approach I've chosen involved:

• Aligning each TD to a cache line. This unfortunately uses up twice the memory.
• Refactoring such that the CPU never tries to read TDs it doesn't "own" (which required removing the data stashed in reserved bits of word0 and moving them elsewhere)
• Performing correct cache operations on user buffers and TDs
• Accessing EDs exclusively through a memory mirror which is set up in the MMU to be an uncached view of system RAM. This is a functionality that is specific to our platform and that TinyUSB currently doesn't expect platforms to generally have available.

Before I open a PR, I wanted to see if such an approach would be acceptable in TinyUSB. If you want to actually take a look at the code in question, you can find it here

I have checked existing issues, dicussion and documentation

• I confirm I have checked existing issues, dicussion and documentation.

[hathach]

yeah sure, you can take the peek of EHCI driver, it already supports and use dcache clean/invalidae API. Cache line size is cpu depent, you gonna need to add CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT to tusb_mcu.h accordingly.