Minimize TLB pressure

[mkroening]

We are currently identity-mapping using these page sizes:

Architecture	Page Size
AArch64	4 KiB
64-bit RISC-V	1 GiB
x86-64	2 MiB

It would be good to use the larges page size possible on each architecture instead.
This would make the memory layout simpler while minimizing TLB pressure.