-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathinfo.yaml
164 lines (138 loc) · 8.99 KB
/
info.yaml
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
---
# TinyTapeout project information
project:
wokwi_id: 0 # If using wokwi, set this to your project's ID
# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here.
# Source files must be in ./src and you must list each source file separately
source_files:
- sky130_blackbox.v
- tile.v
- grid.v
- tt_um_htfab_rotfpga2.v
top_module: "tt_um_htfab_rotfpga2" # put the name of your top module here, make it unique by prepending your github username
# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 4x2 or 8x2
# Keep a track of the submission yaml
yaml_version: 4
# As everyone will have access to all designs, try to make it easy for someone new to your design to know what
# it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
#
# Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
documentation:
author: "htfab"
title: "ROTFPGA v2"
language: "Verilog"
description: "A reconfigurable logic circuit made of identical rotatable tiles"
# Longer description of how the project works. You can use standard markdown format.
how_it_works: |
ROTFPGA v2 is a reconfigurable logic circuit built from identical copies of the tile in
Figure _(a)_ containing a NAND gate, a D flip-flop and a buffer, with each
tile individually rotated or reflected as described by the FPGA configuration. It is a port
of the original [ROTFPGA](https://github.com/htfab/rotfpga) from Caravel to TinyTapeout.
Porting the design required a 50-fold decrease in chip area which was achieved using a
combination of cutting corners, heavy optimization and a few design changes. In particular:
- The FPGA was reduced from 24×24 to 8×8 tiles.
There are 8 inputs and 8 outputs instead of 12 each.
- To compensate for smaller size, tiles can also be mirrored in addition to rotation.
- Tiles (being the most repeated part of the design) were rewritten as hand-optimized
gate-level Verilog.
- Each tile only contains 1 flip-flop (the one exposed to the user). Configuration is
now stored in latches.
- Configuration and reset are performed using a routing-efficient scan chain, so the design
is no longer routing constrained. This allows standard cells to be placed with >80% density.
- Openlane and its components are 2 years more mature, hardening the same HDL more efficiently.
### Configuration
Each tile can be configured in 8 possible orientations. Bits 0, 1 and 2 correspond to a diagonal,
horizontal and vertical flip respectively. Any rotation or reflection can be described as a
combination as shown in Figure _(d)_. (The bottom row looks somewhat different,
but we just rearranged the wires so that the inputs and outputs line up with the unmirrored tiles.)
Tiles are arranged in an 8×8 grid:
- Top, bottom, left and right inputs and outputs are connected to the tile in the respective direction.
- Tiles mostly wrap around, e.g. the bottom output of a cell in the last line connects to the top input
of the cell in the first line.
- As an exception to the wrapping rules, left inputs in the first column correspond to chip inputs and
right outputs in the last column correspond to chip outputs.
- There is a scan chain meandering through all the tiles, visiting lines from top to bottom and within
each line going from left to right.
Figure _(c)_ shows a 4×4 model of the tile grid. When the _scan enable_ input is 0,
the FPGA operates normally and each tile sets its flip-flop to the input it receives from one of
the neighboring tiles according to its current rotation/reflection (black arrows).
When _scan enable_ is 1, it sets the flip-flop to the value received through the scan chain instead
(grey arrows). This allows us to set the initial state of each flip-flop and also to query their
state later for debugging. With some extra machinery it also allows us to change the rotations/reflections.
When the 2-bit _configuration_ input is is 01, each cell updates its _vertical flip_ bit to the
current value of its flip-flop. Similarly, for 10 it sets the _horizontal flip_ and for 11 it
sets the _diagonal flip_. When _configuration_ is 00, all three flip bits are latched and the
orientation doesn't change.
One can thus configure the FPGA by sending the sequence of all _diagonal flip_ bits through the
scan chain, then setting _configuration_ to 11 and back to 00, then sending all _horizontal flip_
bits, setting _configuration_ to 10 and back to 00, and finally sending the _vertical flip_ bits
and setting _configuration_ to 01 and back to 00.
Note that in order to save space the flip bits are stored in latches, not registers. Changing the
_configuration_ input from 00 to 11 or vice versa can cause a race condition where it is
temporarily 01 or 10, overwriting the horizontal or vertical flip bits. Therefore one should
configure the diagonal flips first.
### Loop breaker
The user design may intentionally or inadvertantly contain combinational loops such as ring
oscillators. To help debug such designs, the chip has a loop breaker mechanism using
a _loop breaker enable_ input as well as a 2-bit _loop breaker class_ input.
Tiles are assigned to loop breaker classes according to Figure _(b)_.
The loop breaker latches a tile output if and only if the following conditions are all met:
- The _loop breaker enable_ input is 1.
- The current tile has a non-empty class that is different from the _loop breaker class_ input.
- The output doesn't come from the tile's flip-flop.
The loop breaker has the following properties:
- If _loop breaker enable_ is 1 and _loop breaker class_ is constant, there are no combinational
loops running. If we also pause the clock, the circuit keeps a steady state.
- If _loop breaker enable_ is 1 and we cycle _loop breaker class_ through all possible
values repeatedly while the clock is paused, everything will eventually propagate.
If we also assume that the design has no race conditions, it will behave in the same
way as if _loop breaker enable_ was 0.
### Reset
Setting the _active-low reset_ input to 0 has the following effect:
- Override _scan enable_ to 1, _scan chain_ input to 0 and disengage the latches for
vertical, horizontal and diagonal flips. When kept low for 64 clock cycles this will reset
the state and configuration in every tile.
- Override _loop breaker enable_ to 1 and _loop breaker class_ to 00.
This ensures that we play nice with other designs on TinyTapeout and keep a steady
state while our design is not selected.
# Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
how_to_test: |
Follow the test suite in `src/test.py`.
# A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc).
inputs:
- tile(0,0) left in
- tile(0,1) left in
- tile(0,2) left in
- tile(0,3) left in
- tile(0,4) left in
- tile(0,5) left in
- tile(0,6) left in
- tile(0,7) left in
# A description of what the outputs do (e.g. status LED, SPI MISO, etc)
outputs:
- tile(7,0) right out
- tile(7,1) right out
- tile(7,2) right out
- tile(7,3) right out
- tile(7,4) right out
- tile(7,5) right out
- tile(7,6) right out
- tile(7,7) right out
# A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc)
bidirectional:
- _scan enable_ input
- _scan chain_ input
- _configuration_ input bit 0
- _configuration_ input bit 1
- _loop breaker enable_ input
- _loop breaker class_ input bit 0
- _loop breaker class_ input bit 1
- _scan chain_ output
# The following fields are optional
tag: "fpga, puzzle" # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
external_hw: "" # Describe any external hardware needed
discord: "h.tamas" # Your discord handle, used for communication and automatically assigning tapeout role after a submission
doc_link: "https://github.com/htfab/rotfpga2/blob/main/README.md" # URL to longer form documentation, eg the README.md in your repository
clock_hz: 10000000 # Clock frequency in Hz (if required)
picture: "img/rotfpga-comb.png" # relative path to a picture in your repository