nrf/51: Initial commit to unicore-mx project

Makefile

@@ -29,6 +29,7 @@ TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/f7 \
 	  stm32/l0 stm32/l1 stm32/l4 \
 	  lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 lm3s lm4f \
 	  efm32/tg efm32/g efm32/lg efm32/gg \
+	  nrf/51 \
 	  sam/3a sam/3n sam/3s sam/3u sam/3x sam/4l \
 	  vf6xx
 

README.md

@@ -13,6 +13,7 @@ Currently (at least partly) supported microcontrollers:
  - TI (Tiva) LM4F series (continuing as TM4F, pin and peripheral compatible)
  - EFM32 Gecko series (only core support)
  - NXP Vybrid VF6xx (formerly Freescale)
+ - Nordic Semiconductor nRF51
 
 The library is a fork of [libopencm3](https://github.com/libopencm3/libopencm3).
 We highly value all the work done in libopencm3, but for our projects we need a higher

include/unicore-mx/dispatch/nvic.h

@@ -39,6 +39,9 @@
 #elif defined(LPC43XX_M0)
 #	include <unicore-mx/lpc43xx/m0/nvic.h>
 
+#elif defined(NRF51)
+#	include <unicore-mx/nrf/51/nvic.h>
+
 #elif defined(SAM3A)
 #	include <unicore-mx/sam/3a/nvic.h>
 #elif defined(SAM3N)

include/unicore-mx/nrf/51/clock.h

@@ -0,0 +1,92 @@
+/*
+ * This file is part of the unicore-mx project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef NRF51_CLOCK_H
+#define NRF51_CLOCK_H
+
+#include <stdbool.h>
+
+#include <unicore-mx/cm3/common.h>
+#include <unicore-mx/nrf/memorymap.h>
+
+/* Clock tasks */
+#define CLOCK_TASK_HFCLKSTART			MMIO32(CLOCK_BASE + 0x000)
+#define CLOCK_TASK_HFCLKSTOP			MMIO32(CLOCK_BASE + 0x004)
+#define CLOCK_TASK_LFCLKSTART			MMIO32(CLOCK_BASE + 0x008)
+#define CLOCK_TASK_LFCLKSTOP			MMIO32(CLOCK_BASE + 0x00C)
+#define CLOCK_TASK_CAL			MMIO32(CLOCK_BASE + 0x010)
+#define CLOCK_TASK_CTSTART			MMIO32(CLOCK_BASE + 0x014)
+#define CLOCK_TASK_CTSTOP			MMIO32(CLOCK_BASE + 0x018)
+
+/* Clock events */
+#define CLOCK_EVENT_HFCLKSTARTED			MMIO32(CLOCK_BASE + 0x100)
+#define CLOCK_EVENT_LFCLKSTARTED			MMIO32(CLOCK_BASE + 0x104)
+#define CLOCK_EVENT_DONE			MMIO32(CLOCK_BASE + 0x10C)
+#define CLOCK_EVENT_CTTO			MMIO32(CLOCK_BASE + 0x110)
+
+/* Clock registers */
+#define CLOCK_INTENSET			MMIO32(CLOCK_BASE + 0x304)
+#define CLOCK_INTENCLR			MMIO32(CLOCK_BASE + 0x308)
+#define CLOCK_HFCLKRUN			MMIO32(CLOCK_BASE + 0x408)
+#define CLOCK_HFCLKSTAT			MMIO32(CLOCK_BASE + 0x40C)
+#define CLOCK_LFCLKRUN			MMIO32(CLOCK_BASE + 0x414)
+#define CLOCK_LFCLKSTAT			MMIO32(CLOCK_BASE + 0x418)
+#define CLOCK_LFCLKSRCCOPY			MMIO32(CLOCK_BASE + 0x41C)
+#define CLOCK_LFCLKSRC			MMIO32(CLOCK_BASE + 0x518)
+#define CLOCK_CTIV			MMIO32(CLOCK_BASE + 0x538)
+#define CLOCK_XTALFREQ			MMIO32(CLOCK_BASE + 0x550)
+
+/* Register contents */
+#define CLOCK_INTEN_HFCLKSTARTED			(1 << 0)
+#define CLOCK_INTEN_LFCLKSTARTED			(1 << 1)
+#define CLOCK_INTEN_DONE			(1 << 3)
+#define CLOCK_INTEN_CTTO			(1 << 4)
+
+#define CLOCK_HFCLKRUN_STATUS			(1 << 0)
+
+#define CLOCK_HFCLKSTAT_SRC			(1 << 0)
+#define CLOCK_HFCLKSTAT_STATE			(1 << 16)
+
+#define CLOCK_LFCLKRUN_STATUS			(1 << 0)
+
+#define CLOCK_LFCLK_SRC_SHIFT			(0)
+#define CLOCK_LFCLK_SRC_MASK			(3 << CLOCK_LFCLKSTAT_SRC_SHIFT)
+#define CLOCK_LFCLK_SRC_MASKED(V)			(((V) << CLOCK_LFCLKSTAT_SRC_SHIFT) & CLOCK_LFCLKSTAT_SRC_MASK)
+
+#define CLOCK_LFCLKSTAT_STATE			(1 << 16)
+
+enum clock_lfclk_src {
+	CLOCK_LFCLK_SRC_RC,
+	CLOCK_LFCLK_SRC_XTAL,
+	CLOCK_LFCLK_SRC_SYNTH,
+};
+
+enum clock_xtal_freq {
+	CLOCK_XTAL_FREQ_32MHZ,
+	CLOCK_XTAL_FREQ_16MHZ = 0xff,
+};
+
+BEGIN_DECLS
+
+void clock_lfclk_start(bool wait);
+void clock_hfclk_start(bool wait);
+void clock_set_xtal_freq(enum clock_xtal_freq freq);
+void clock_set_lfclk_src(enum clock_lfclk_src lfclk_src);
+
+END_DECLS
+
+#endif  /* NRF51_CLOCK_H */

include/unicore-mx/nrf/51/ficr.h

@@ -0,0 +1,84 @@
+/*
+ * This file is part of the unicore-mx project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef NRF51_FICR_H
+#define NRF51_FICR_H
+
+#include <unicore-mx/cm3/common.h>
+#include <unicore-mx/nrf/memorymap.h>
+
+/* Factory Information Configuration Register */
+
+#define FICR_CODEPAGESIZE			MMIO32(FICR_BASE + 0x010)
+#define FICR_CODESIZE			MMIO32(FICR_BASE + 0x014)
+
+/* Deprecated */
+#define FICR_CLENR0			MMIO32(FICR_BASE + 0x028)
+/* Deprecated */
+#define FICR_PPFC			MMIO32(FICR_BASE + 0x02C)
+
+#define FICR_NUMRAMBLOCK			MMIO32(FICR_BASE + 0x034)
+#define FICR_SIZERAMBLOCKS			MMIO32(FICR_BASE + 0x038)
+
+/* Deprecated */
+#define FICR_SIZERAMBLOCK(n)			MMIO32(FICR_BASE + 0x038 + 0x4 * (n))
+
+#define FICR_CONFIGID			MMIO32(FICR_BASE + 0x05C)
+
+#define FICR_DEVICEID0				MMIO32(FICR_BASE + 0x060)
+#define FICR_DEVICEID1				MMIO32(FICR_BASE + 0x064)
+
+/* Encryption Root */
+#define FICR_ER(n)			MMIO32(FICR_BASE + 0x080 + 0x4 * (n))
+#define FICR_ER0			FICR_ER(0)
+#define FICR_ER1			FICR_ER(1)
+#define FICR_ER2			FICR_ER(2)
+#define FICR_ER3			FICR_ER(3)
+
+/* Identity Root */
+#define FICR_IR(n)			MMIO32(FICR_BASE + 0x090 + 0x4 * (n))
+#define FICR_IR0			FICR_IR(0)
+#define FICR_IR1			FICR_IR(1)
+#define FICR_IR2			FICR_IR(2)
+#define FICR_IR3			FICR_IR(3)
+
+#define FICR_DEVICEADDRTYPE			MMIO32(FICR_BASE + 0x0A0)
+#define FICR_DEVICEADDR0			MMIO32(FICR_BASE + 0x0A4)
+#define FICR_DEVICEADDR1			MMIO32(FICR_BASE + 0x0A8)
+
+#define FICR_OVERRIDEEN			MMIO32(FICR_BASE + 0x0AC)
+
+/* Override values for Nordic Semi proprietary NRF 1Mbit mode */
+#define FICR_NRF_1MBIT(n)			MMIO32(FICR_BASE + 0x0B0 + 0x4 * (n))
+#define FICR_NRF_1MBIT0			FICR_NRF_1MBIT(0)
+#define FICR_NRF_1MBIT1			FICR_NRF_1MBIT(1)
+#define FICR_NRF_1MBIT2			FICR_NRF_1MBIT(2)
+#define FICR_NRF_1MBIT3			FICR_NRF_1MBIT(3)
+#define FICR_NRF_1MBIT4			FICR_NRF_1MBIT(4)
+
+/* Override values for BLE 1Mbit mode */
+#define FICR_BLE_1MBIT(n)			MMIO32(FICR_BASE + 0x0EC + 0x4 * (n))
+#define FICR_BLE_1MBIT0			FICR_BLE_1MBIT(0)
+#define FICR_BLE_1MBIT1			FICR_BLE_1MBIT(1)
+#define FICR_BLE_1MBIT2			FICR_BLE_1MBIT(2)
+#define FICR_BLE_1MBIT3			FICR_BLE_1MBIT(3)
+#define FICR_BLE_1MBIT4			FICR_BLE_1MBIT(4)
+
+#define FICR_OVERRIDEEN_NRF_1MBIT			(1 << 0)
+#define FICR_OVERRIDEEN_BLE_1MBIT			(1 << 3)
+
+#endif  /* NRF51_FICR_H */

include/unicore-mx/nrf/51/gpio.h

@@ -0,0 +1,187 @@
+/*
+ * This file is part of the unicore-mx project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBUCMX_GPIO_H
+#define LIBUCMX_GPIO_H
+
+#include <unicore-mx/cm3/common.h>
+#include <unicore-mx/nrf/memorymap.h>
+
+#define GPIO			(GPIO_BASE)
+
+#define GPIO_OUT			MMIO32(GPIO_BASE + 0x504)
+#define GPIO_OUTSET			MMIO32(GPIO_BASE + 0x508)
+#define GPIO_OUTCLR			MMIO32(GPIO_BASE + 0x50C)
+
+#define GPIO_IN			MMIO32(GPIO_BASE + 0x510)
+
+#define GPIO_DIR			MMIO32(GPIO_BASE + 0x514)
+#define GPIO_DIRSET			MMIO32(GPIO_BASE + 0x518)
+#define GPIO_DIRCLR			MMIO32(GPIO_BASE + 0x51C)
+
+#define GPIO_PIN_CNF(N)			MMIO32(GPIO_BASE + 0x700 + 0x4 * (N))
+
+#define GPIOPIN0			(1 << 0)
+#define GPIOPIN1			(1 << 1)
+#define GPIOPIN2			(1 << 2)
+#define GPIOPIN3			(1 << 3)
+#define GPIOPIN4			(1 << 4)
+#define GPIOPIN5			(1 << 5)
+#define GPIOPIN6			(1 << 6)
+#define GPIOPIN7			(1 << 7)
+#define GPIOPIN8			(1 << 8)
+#define GPIOPIN9			(1 << 9)
+#define GPIOPIN10			(1 << 10)
+#define GPIOPIN11			(1 << 11)
+#define GPIOPIN12			(1 << 12)
+#define GPIOPIN13			(1 << 13)
+#define GPIOPIN14			(1 << 14)
+#define GPIOPIN15			(1 << 15)
+#define GPIOPIN16			(1 << 16)
+#define GPIOPIN17			(1 << 17)
+#define GPIOPIN18			(1 << 18)
+#define GPIOPIN19			(1 << 19)
+#define GPIOPIN20			(1 << 20)
+#define GPIOPIN21			(1 << 21)
+#define GPIOPIN22			(1 << 22)
+#define GPIOPIN23			(1 << 23)
+#define GPIOPIN24			(1 << 24)
+#define GPIOPIN25			(1 << 25)
+#define GPIOPIN26			(1 << 26)
+#define GPIOPIN27			(1 << 27)
+#define GPIOPIN28			(1 << 28)
+#define GPIOPIN29			(1 << 29)
+#define GPIOPIN30			(1 << 30)
+#define GPIOPIN31			(1 << 31)
+
+#define GPIOPINN(n)			(1 << (n))
+
+#define PIN_CNF_DIR			(1 << 0)
+#define PIN_CNF_INPUT			(1 << 1)
+
+#define PIN_CNF_PULL_SHIFT			(2)
+#define PIN_CNF_PULL_MASK			(3 << PIN_CNF_PULL_SHIFT)
+#define PIN_CNF_PULL_MASKED(V)			(((V) << PIN_CNF_PULL_SHIFT) & PIN_CNF_PULL_MASK)
+
+#define PIN_CNF_DRIVE_SHIFT			(8)
+#define PIN_CNF_DRIVE_MASK			(7 << PIN_CNF_DRIVE_SHIFT)
+#define PIN_CNF_DRIVE_MASKED(V)			(((V) << PIN_CNF_DRIVE_SHIFT) & PIN_CNF_DRIVE_MASK)
+
+#define PIN_CNF_SENSE_SHIFT			(16)
+#define PIN_CNF_SENSE_MASK			(3 << PIN_CNF_SENSE_SHIFT)
+#define PIN_CNF_SENSE_MASKED(V)			(((V) << PIN_CNF_SENSE_SHIFT) & PIN_CNF_SENSE_MASK)
+
+/* GPIO Tasks and Events (GPIOTE) */
+#define GPIO_TASK_OUT(n)			MMIO32(GPIOTE_BASE + 0x4 * (n))
+#define GPIO_TASK_OUT0			GPIO_TASK_OUT(0)
+#define GPIO_TASK_OUT1			GPIO_TASK_OUT(1)
+#define GPIO_TASK_OUT2			GPIO_TASK_OUT(2)
+#define GPIO_TASK_OUT3			GPIO_TASK_OUT(3)
+
+#define GPIO_EVENT_IN(n)			MMIO32(GPIOTE_BASE + 0x100 + 0x4 * (n))
+#define GPIO_EVENT_IN0			GPIO_EVENT_IN(0)
+#define GPIO_EVENT_IN1			GPIO_EVENT_IN(1)
+#define GPIO_EVENT_IN2			GPIO_EVENT_IN(2)
+#define GPIO_EVENT_IN3			GPIO_EVENT_IN(3)
+
+#define GPIO_EVENT_PORT			MMIO32(GPIOTE_BASE + 0x17C)
+
+#define GPIO_INTEN			MMIO32(GPIOTE_BASE + 0x300)
+#define GPIO_INTENSET			MMIO32(GPIOTE_BASE + 0x304)
+#define GPIO_INTENCLR			MMIO32(GPIOTE_BASE + 0x308)
+
+#define GPIO_TE_CONFIG(n)			MMIO32(GPIOTE_BASE + 0x510 + 0x4 * (n))
+#define GPIO_TE_CONFIG0			GPIO_TE_CONFIG(0)
+#define GPIO_TE_CONFIG1			GPIO_TE_CONFIG(1)
+#define GPIO_TE_CONFIG2			GPIO_TE_CONFIG(2)
+#define GPIO_TE_CONFIG3			GPIO_TE_CONFIG(3)
+
+/* Register Details */
+#define GPIO_INTEN_IN(n)			(1 << (n))
+#define GPIO_INTEN_IN0			(1 << 0)
+#define GPIO_INTEN_IN1			(1 << 1)
+#define GPIO_INTEN_IN2			(1 << 2)
+#define GPIO_INTEN_IN3			(1 << 3)
+
+#define GPIO_INTEN_PORT			(1 << 31)
+
+#define GPIO_TE_CONFIG_MODE_SHIFT			(0)
+#define GPIO_TE_CONFIG_MODE_MASK			(3 << GPIO_TE_CONFIG_MODE_SHIFT)
+#define GPIO_TE_CONFIG_MODE_MASKED(V)			(((V) << GPIO_TE_CONFIG_MODE_SHIFT) & GPIO_TE_CONFIG_MODE_MASK)
+
+#define GPIO_TE_CONFIG_PSEL_SHIFT			(8)
+#define GPIO_TE_CONFIG_PSEL_MASK			(0x1f << GPIO_TE_CONFIG_PSEL_SHIFT)
+#define GPIO_TE_CONFIG_PSEL_MASKED(V)			(((V) << GPIO_TE_CONFIG_PSEL_SHIFT) & GPIO_TE_CONFIG_PSEL_MASK)
+
+#define GPIO_TE_CONFIG_POLARITY_SHIFT			(16)
+#define GPIO_TE_CONFIG_POLARITY_MASK			(3 << GPIO_TE_CONFIG_POLARITY_SHIFT)
+#define GPIO_TE_CONFIG_POLARITY_MASKED(V)			(((V) << GPIO_TE_CONFIG_POLARITY_SHIFT) & GPIO_TE_CONFIG_POLARITY_MASK)
+
+#define GPIO_TE_CONFIG_OUTINIT			(1 << 20)
+
+#define GPIO_DIR_INPUT			(0)
+#define GPIO_DIR_OUTPUT			(1)
+
+#define GPIO_INPUT_CONNECT			(0)
+#define GPIO_INPUT_DISCONNECT		(1)
+
+#define GPIO_PULL_NONE			(0)
+#define GPIO_PULL_DOWN			(1)
+#define GPIO_PULL_UP			(3)
+
+#define GPIO_DRIVE_S0S1			(0)
+#define GPIO_DRIVE_H0S1			(1)
+#define GPIO_DRIVE_S0H1			(2)
+#define GPIO_DRIVE_H0H1			(3)
+#define GPIO_DRIVE_D0S1			(4)
+#define GPIO_DRIVE_D0H1			(5)
+#define GPIO_DRIVE_S0D1			(6)
+#define GPIO_DRIVE_H0D1			(7)
+
+#define GPIO_TE_MODE_DISABLED			(0)
+#define GPIO_TE_MODE_EVENT			(1)
+#define GPIO_TE_MODE_TASK			(3)
+
+#define GPIO_TE_POLARITY_NONE			(0)
+#define GPIO_TE_POLARITY_LO_TO_HI			(1)
+#define GPIO_TE_POLARITY_HI_TO_LO			(2)
+#define GPIO_TE_POLARITY_TOGGLE			(3)
+
+#define GPIO_TE_OUTINIT_LOW			(1)
+#define GPIO_TE_OUTINIT_HIGH			GPIO_TE_CONFIG_OUTINIT
+
+BEGIN_DECLS
+
+void gpio_set(uint32_t gpios);
+void gpio_clear(uint32_t gpios);
+void gpio_toggle(uint32_t gpios);
+uint32_t gpio_get(uint32_t gpios);
+
+void gpio_setup_mode(uint32_t gpios, uint8_t dir, uint8_t pull);
+
+void gpio_configure_task(uint8_t task_num,
+		uint8_t pin_num, uint8_t polarity, uint8_t init);
+
+void gpio_configure_event(uint8_t event_num, uint8_t pin_num, uint8_t polarity);
+
+void gpio_enable_interrupts(uint32_t mask);
+void gpio_disable_interrupts(uint32_t mask);
+void gpio_clear_interrupts(void);
+
+END_DECLS
+
+#endif	/* LIBUCMX_GPIO_H */