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Add + as an argument indicator #425

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amal-khailtash opened this issue Mar 25, 2024 · 0 comments

amal-khailtash commented Mar 25, 2024

Although not a standard way and rarely seen, but some tools (Verilog simulators, UVM, ...) use + to indicate custom arguments. Examples are:

+TEST=AXI_TEST
+UVM_TESTNAME=read_modify_write_test
+UVM_MAX_QUIT_COUNT=5,NO
+UVM_TIMEOUT=200000,NO
+UVM_PHASE_TRACE

This would be a great addition.

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