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6502_functional_test.ca65
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6502_functional_test.ca65
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;
; 6 5 0 2 F U N C T I O N A L T E S T
;
; Copyright (C) 2012-2015 Klaus Dormann
;
; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation, either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program. If not, see <http://www.gnu.org/licenses/>.
; This program is designed to test all opcodes of a 6502 emulator using all
; addressing modes with focus on propper setting of the processor status
; register bits.
;
; version 01-aug-2019
; contact info at http://2m5.de or email [email protected]
;
; assembled with CA65, linked with LD65 (cc65.github.io):
; ca65 -l 6502_functional_test.lst 6502_functional_test.ca65
; ld65 6502_functional_test.o -o 6502_functional_test.bin \
; -m 6502_functional_test.map -C example.cfg
; example linker config (example.cfg):
; MEMORY {
; RAM: start = $0000, size=$8000, type = rw, fill = yes, \
; fillval = $FF, file = %O;
; ROM: start = $8000, size=$7FFA, type = ro, fill = yes, \
; fillval = $FF, file = %O;
; ROM_VECTORS: start = $FFFA, size=6, type = ro, fill = yes, \
; fillval = $FF, file = %O;
; }
; SEGMENTS {
; ZEROPAGE: load=RAM, type=rw;
; DATA: load=RAM, type=rw, offset=$0200;
; CODE: load=RAM, type=rw, offset=$0400;
; VECTORS: load=ROM_VECTORS, type=ro;
; }
;
; No IO - should be run from a monitor with access to registers.
; To run load intel hex image with a load command, than alter PC to 400 hex
; (code_segment) and enter a go command.
; Loop on program counter determines error or successful completion of test.
; Check listing for relevant traps (jump/branch *).
; Please note that in early tests some instructions will have to be used before
; they are actually tested!
;
; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled.
; Tests documented behavior of the original NMOS 6502 only! No unofficial
; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will
; not be tested. Decimal ops will only be tested with valid BCD operands and
; N V Z flags will be ignored.
;
; Debugging hints:
; Most of the code is written sequentially. if you hit a trap, check the
; immediately preceeding code for the instruction to be tested. Results are
; tested first, flags are checked second by pushing them onto the stack and
; pulling them to the accumulator after the result was checked. The "real"
; flags are no longer valid for the tested instruction at this time!
; If the tested instruction was indexed, the relevant index (X or Y) must
; also be checked. Opposed to the flags, X and Y registers are still valid.
;
; versions:
; 28-jul-2012 1st version distributed for testing
; 29-jul-2012 fixed references to location 0, now #0
; added license - GPLv3
; 30-jul-2012 added configuration options
; 01-aug-2012 added trap macro to allow user to change error handling
; 01-dec-2012 fixed trap in branch field must be a branch
; 02-mar-2013 fixed PLA flags not tested
; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0
; added test sequence check to detect if tests jump their fence
; 23-jul-2013 added RAM integrity check option
; 16-aug-2013 added error report to standard output option
; 13-dec-2014 added binary/decimal opcode table switch test
; 14-dec-2014 improved relative address test
; 23-aug-2015 added option to disable self modifying tests
; 24-aug-2015 all self modifying immediate opcodes now execute in data RAM
; added small branch offset pretest
; 21-oct-2015 added option to disable decimal mode ADC & SBC tests
; 04-dec-2017 fixed BRK only tested with interrupts enabled
; added option to skip the remainder of a failing test
; in report.i65
; C O N F I G U R A T I O N
;ROM_vectors writable (0=no, 1=yes)
;if ROM vectors can not be used interrupts will not be trapped
;as a consequence BRK can not be tested but will be emulated to test RTI
ROM_vectors = 1
;load_data_direct (0=move from code segment, 1=load directly)
;loading directly is preferred but may not be supported by your platform
;0 produces only consecutive object code, 1 is not suitable for a binary image
load_data_direct = 1
;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
;change) 2 requires extra code and is not recommended. SEI & CLI can only be
;tested if you allow changing the interrupt status (I_flag = 3)
I_flag = 3
;configure memory - try to stay away from memory used by the system
;zero_page memory start address, $50 (80) consecutive Bytes required
; add 2 if I_flag = 2
zero_page = $a
;data_segment memory start address, $6A (106) consecutive Bytes required
; check that this matches the linker configuration file
data_segment = $200
.if (data_segment & $ff) <> 0
.error "low byte of data_segment MUST be $00 !!"
.endif
;code_segment memory start address, 13kB of consecutive space required
; add 2.5 kB if I_flag = 2
; check that this matches the linker configuration file
code_segment = $400
;self modifying code may be disabled to allow running in ROM
;0=part of the code is self modifying and must reside in RAM
;1=tests disabled: branch range
disable_selfmod = 0
;report errors through I/O channel (0=use standard self trap loops, 1=include
;report.i65 as I/O channel, add 3.5 kB)
report = 0
;RAM integrity test option. Checks for undesired RAM writes.
;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)
;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM
ram_top = -1
;disable test decimal mode ADC & SBC, 0=enable, 1=disable,
;2=disable including decimal flag in processor status
disable_decimal = 0
;macros for error & success traps to allow user modification
;example:
; .macro trap
; jsr my_error_handler
; .endmacro
; .macro trap_eq
; bne :+
; trap ;failed equal (zero)
;:
; .endmacro
;
; my_error_handler should pop the calling address from the stack and report it.
; putting larger portions of code (more than 3 bytes) inside the trap macro
; may lead to branch range problems for some tests.
.if report = 0
.macro trap
jmp * ;failed anyway
.endmacro
.macro trap_eq
beq * ;failed equal (zero)
.endmacro
.macro trap_ne
bne * ;failed not equal (non zero)
.endmacro
.macro trap_cs
bcs * ;failed carry set
.endmacro
.macro trap_cc
bcc * ;failed carry clear
.endmacro
.macro trap_mi
bmi * ;failed minus (bit 7 set)
.endmacro
.macro trap_pl
bpl * ;failed plus (bit 7 clear)
.endmacro
.macro trap_vs
bvs * ;failed overflow set
.endmacro
.macro trap_vc
bvc * ;failed overflow clear
.endmacro
; please observe that during the test the stack gets invalidated
; therefore a RTS inside the success macro is not possible
.macro success
jmp * ;test passed, no errors
.endmacro
.endif
.if report = 1
.macro trap
jsr report_error
.endmacro
.macro trap_eq
bne :+
trap ;failed equal (zero)
:
.endmacro
.macro trap_ne
beq :+
trap ;failed not equal (non zero)
:
.endmacro
.macro trap_cs
bcc :+
trap ;failed carry set
:
.endmacro
.macro trap_cc
bcs :+
trap ;failed carry clear
:
.endmacro
.macro trap_mi
bpl :+
trap ;failed minus (bit 7 set)
:
.endmacro
.macro trap_pl
bmi :+
trap ;failed plus (bit 7 clear)
:
.endmacro
.macro trap_vs
bvc :+
trap ;failed overflow set
:
.endmacro
.macro trap_vc
bvs :+
trap ;failed overflow clear
:
.endmacro
; please observe that during the test the stack gets invalidated
; therefore a RTS inside the success macro is not possible
.macro success
jsr report_success
.endmacro
.endif
.define equ =
carry equ %00000001 ;flag bits in status
zero equ %00000010
intdis equ %00000100
decmode equ %00001000
break equ %00010000
reserv equ %00100000
overfl equ %01000000
minus equ %10000000
fc equ carry
fz equ zero
fzc equ carry+zero
fv equ overfl
fvz equ overfl+zero
fn equ minus
fnc equ minus+carry
fnz equ minus+zero
fnzc equ minus+zero+carry
fnv equ minus+overfl
fao equ break+reserv ;bits always on after PHP, BRK
fai equ fao+intdis ;+ forced interrupt disable
faod equ fao+decmode ;+ ignore decimal
faid equ fai+decmode ;+ ignore decimal
m8 equ $ff ;8 bit mask
m8i equ $ff&~intdis ;8 bit mask - interrupt disable
;macros to allow masking of status bits.
;masking test of decimal bit
;masking of interrupt enable/disable on load and compare
;masking of always on bits after PHP or BRK (unused & break) on compare
.if disable_decimal < 2
.if I_flag = 0
.macro load_flag p1
lda #p1&m8i ;force enable interrupts (mask I)
.endmacro
.macro cmp_flag p1
cmp #(p1|fao)&m8i ;I_flag is always enabled + always on bits
.endmacro
.macro eor_flag p1
eor #(p1&m8i|fao) ;mask I, invert expected flags + always on bits
.endmacro
.endif
.if I_flag = 1
.macro load_flag p1
lda #p1|intdis ;force disable interrupts
.endmacro
.macro cmp_flag p1
cmp #(p1|fai)&m8 ;I_flag is always disabled + always on bits
.endmacro
.macro eor_flag p1
eor #(p1|fai) ;invert expected flags + always on bits + I
.endmacro
.endif
.if I_flag = 2
.macro load_flag p1
lda #p1
ora flag_I_on ;restore I-flag
and flag_I_off
.endmacro
.macro cmp_flag p1
eor flag_I_on ;I_flag is never changed
cmp #(p1|fao)&m8i ;expected flags + always on bits, mask I
.endmacro
.macro eor_flag p1
eor flag_I_on ;I_flag is never changed
eor #(p1&m8i|fao) ;mask I, invert expected flags + always on bits
.endmacro
.endif
.if I_flag = 3
.macro load_flag p1
lda #p1 ;allow test to change I-flag (no mask)
.endmacro
.macro cmp_flag p1
cmp #(p1|fao)&m8 ;expected flags + always on bits
.endmacro
.macro eor_flag p1
eor #p1|fao ;invert expected flags + always on bits
.endmacro
.endif
.else
.if I_flag = 0
.macro load_flag p1
lda #p1&m8i ;force enable interrupts (mask I)
.endmacro
.macro cmp_flag p1
ora #decmode ;ignore decimal mode bit
cmp #(p1|faod)&m8i ;I_flag is always enabled + always on bits
.endmacro
.macro eor_flag p1
ora #decmode ;ignore decimal mode bit
eor #(p1&m8i|faod) ;mask I, invert expected flags + always on bits
.endmacro
.endif
.if I_flag = 1
.macro load_flag p1
lda #p1|intdis ;force disable interrupts
.endmacro
.macro cmp_flag p1
ora #decmode ;ignore decimal mode bit
cmp #(p1|faid)&m8 ;I_flag is always disabled + always on bits
.endmacro
.macro eor_flag p1
ora #decmode ;ignore decimal mode bit
eor #(p1|faid) ;invert expected flags + always on bits + I
.endmacro
.endif
.if I_flag = 2
.macro load_flag p1
lda #p1
ora flag_I_on ;restore I-flag
and flag_I_off
.endmacro
.macro cmp_flag p1
eor flag_I_on ;I_flag is never changed
ora #decmode ;ignore decimal mode bit
cmp #(p1|faod)&m8i ;expected flags + always on bits, mask I
.endmacro
.macro eor_flag p1
eor flag_I_on ;I_flag is never changed
ora #decmode ;ignore decimal mode bit
eor #(p1&m8i|faod) ;mask I, invert expected flags + always on bits
.endmacro
.endif
.if I_flag = 3
.macro load_flag p1
lda #p1 ;allow test to change I-flag (no mask)
.endmacro
.macro cmp_flag p1
ora #decmode ;ignore decimal mode bit
cmp #(p1|faod)&m8 ;expected flags + always on bits
.endmacro
.macro eor_flag p1
ora #decmode ;ignore decimal mode bit
eor #p1|faod ;invert expected flags + always on bits
.endmacro
.endif
.endif
;macros to set (register|memory|zeropage) & status
.macro set_stat p1 ;setting flags in the processor status register
load_flag p1
pha ;use stack to load status
plp
.endmacro
.macro set_a p1,p2 ;precharging accu & status
load_flag p2
pha ;use stack to load status
lda #p1 ;precharge accu
plp
.endmacro
.macro set_x p1,p2 ;precharging index & status
load_flag p2
pha ;use stack to load status
ldx #p1 ;precharge index x
plp
.endmacro
.macro set_y p1,p2 ;precharging index & status
load_flag p2
pha ;use stack to load status
ldy #p1 ;precharge index y
plp
.endmacro
.macro set_ax p1,p2 ;precharging indexed accu & immediate status
load_flag p2
pha ;use stack to load status
lda p1,x ;precharge accu
plp
.endmacro
.macro set_ay p1,p2 ;precharging indexed accu & immediate status
load_flag p2
pha ;use stack to load status
lda p1,y ;precharge accu
plp
.endmacro
.macro set_z p1,p2 ;precharging indexed zp & immediate status
load_flag p2
pha ;use stack to load status
lda p1,x ;load to zeropage
sta zpt
plp
.endmacro
.macro set_zx p1,p2 ;precharging zp,x & immediate status
load_flag p2
pha ;use stack to load status
lda p1,x ;load to indexed zeropage
sta zpt,x
plp
.endmacro
.macro set_abs p1,p2 ;precharging indexed memory & immediate status
load_flag p2
pha ;use stack to load status
lda p1,x ;load to memory
sta abst
plp
.endmacro
.macro set_absx p1,p2 ;precharging abs,x & immediate status
load_flag p2
pha ;use stack to load status
lda p1,x ;load to indexed memory
sta abst,x
plp
.endmacro
;macros to test (register|memory|zeropage) & status & (mask)
.macro tst_stat p1 ;testing flags in the processor status register
php ;save status
pla ;use stack to retrieve status
pha
cmp_flag p1
trap_ne
plp ;restore status
.endmacro
.macro tst_a p1,p2 ;testing result in accu & flags
php ;save flags
cmp #p1 ;test result
trap_ne
pla ;load status
pha
cmp_flag p2
trap_ne
plp ;restore status
.endmacro
.macro tst_x p1,p2 ;testing result in x index & flags
php ;save flags
cpx #p1 ;test result
trap_ne
pla ;load status
pha
cmp_flag p2
trap_ne
plp ;restore status
.endmacro
.macro tst_y p1,p2 ;testing result in y index & flags
php ;save flags
cpy #p1 ;test result
trap_ne
pla ;load status
pha
cmp_flag p2
trap_ne
plp ;restore status
.endmacro
.macro tst_ax p1,p2,p3 ;indexed testing result in accu & flags
php ;save flags
cmp p1,x ;test result
trap_ne
pla ;load status
eor_flag p3
cmp p2,x ;test flags
trap_ne ;
.endmacro
.macro tst_ay p1,p2,p3 ;indexed testing result in accu & flags
php ;save flags
cmp p1,y ;test result
trap_ne ;
pla ;load status
eor_flag p3
cmp p2,y ;test flags
trap_ne
.endmacro
.macro tst_z p1,p2,p3 ;indexed testing result in zp & flags
php ;save flags
lda zpt
cmp p1,x ;test result
trap_ne
pla ;load status
eor_flag p3
cmp p2,x ;test flags
trap_ne
.endmacro
.macro tst_zx p1,p2,p3 ;testing result in zp,x & flags
php ;save flags
lda zpt,x
cmp p1,x ;test result
trap_ne
pla ;load status
eor_flag p3
cmp p2,x ;test flags
trap_ne
.endmacro
.macro tst_abs p1,p2,p3 ;indexed testing result in memory & flags
php ;save flags
lda abst
cmp p1,x ;test result
trap_ne
pla ;load status
eor_flag p3
cmp p2,x ;test flags
trap_ne
.endmacro
.macro tst_absx p1,p2,p3 ;testing result in abs,x & flags
php ;save flags
lda abst,x
cmp p1,x ;test result
trap_ne
pla ;load status
eor_flag p3
cmp p2,x ;test flags
trap_ne
.endmacro
; RAM integrity test
; verifies that none of the previous tests has altered RAM outside of the
; designated write areas.
; uses zpt word as indirect pointer, zpt+2 word as checksum
.if ram_top > -1
check_ram macro
cld
lda #0
sta zpt ;set low byte of indirect pointer
sta zpt+3 ;checksum high byte
.if disable_selfmod = 0
sta range_adr ;reset self modifying code
.endif
clc
ldx #zp_bss-zero_page ;zeropage - write test area
ccs3: adc zero_page,x
bcc ccs2
inc zpt+3 ;carry to high byte
clc
ccs2: inx
bne ccs3
ldx #hi(abs1) ;set high byte of indirect pointer
stx zpt+1
ldy #lo(abs1) ;data after write & execute test area
ccs5: adc (zpt),y
bcc ccs4
inc zpt+3 ;carry to high byte
clc
ccs4: iny
bne ccs5
inx ;advance RAM high address
stx zpt+1
cpx #ram_top
bne ccs5
sta zpt+2 ;checksum low is
cmp ram_chksm ;checksum low expected
trap_ne ;checksum mismatch
lda zpt+3 ;checksum high is
cmp ram_chksm+1 ;checksum high expected
trap_ne ;checksum mismatch
.endmacro
.else
.macro check_ram
;RAM check disabled - RAM size not set
.endmacro
.endif
.macro next_test ;make sure, tests don't jump the fence
lda test_case ;previous test
cmp #test_num
trap_ne ;test is out of sequence
test_num .set test_num + 1
lda #test_num ;*** next tests' number
sta test_case
;check_ram ;uncomment to find altered RAM after each test
.endmacro
.ZEROPAGE
.res zero_page, 0
.org zero_page
;break test interrupt save
irq_a: .res 1,0 ;a register
irq_x: .res 1,0 ;x register
.if I_flag = 2
;masking for I bit in status
flag_I_on: .res 1,0 ;or mask to load flags
flag_I_off: .res 1,0 ;and mask to load flags
.endif
zpt: ;5 bytes store/modify test area
;add/subtract operand generation and result/flag prediction
adfc: .res 1,0 ;carry flag before op
ad1: .res 1,0 ;operand 1 - accumulator
ad2: .res 1,0 ;operand 2 - memory / immediate
adrl: .res 1,0 ;expected result bits 0-7
adrh: .res 1,0 ;expected result bit 8 (carry)
adrf: .res 1,0 ;expected flags NV0000ZC (only binary mode)
sb2: .res 1,0 ;operand 2 complemented for subtract
zp_bss:
zp1: .byte $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
zp7f: .byte $7f ;test pattern for compare
;logical zeropage operands
zpOR: .byte 0,$1f,$71,$80 ;test pattern for OR
zpAN: .byte $0f,$ff,$7f,$80 ;test pattern for AND
zpEO: .byte $ff,$0f,$8f,$8f ;test pattern for EOR
;indirect addressing pointers
ind1: .word abs1 ;indirect pointer to pattern in absolute memory
.word abs1+1
.word abs1+2
.word abs1+3
.word abs7f
inw1: .word abs1-$f8 ;indirect pointer for wrap-test pattern
indt: .word abst ;indirect pointer to store area in absolute memory
.word abst+1
.word abst+2
.word abst+3
inwt: .word abst-$f8 ;indirect pointer for wrap-test store
indAN: .word absAN ;indirect pointer to AND pattern in absolute memory
.word absAN+1
.word absAN+2
.word absAN+3
indEO: .word absEO ;indirect pointer to EOR pattern in absolute memory
.word absEO+1
.word absEO+2
.word absEO+3
indOR: .word absOR ;indirect pointer to OR pattern in absolute memory
.word absOR+1
.word absOR+2
.word absOR+3
;add/subtract indirect pointers
adi2: .word ada2 ;indirect pointer to operand 2 in absolute memory
sbi2: .word sba2 ;indirect pointer to complemented operand 2 (SBC)
adiy2: .word ada2-$ff ;with offset for indirect indexed
sbiy2: .word sba2-$ff
zp_bss_end:
.DATA
.org data_segment
test_case: .res 1,0 ;current test number
ram_chksm: .res 2,0 ;checksum for RAM integrity test
;add/subtract operand copy - abs tests write area
abst: ;5 bytes store/modify test area
ada2: .res 1,0 ;operand 2
sba2: .res 1,0 ;operand 2 complemented for subtract
.res 3,0 ;fill remaining bytes
data_bss:
.if load_data_direct = 1
ex_andi:and #0 ;execute immediate opcodes
rts
ex_eori:eor #0 ;execute immediate opcodes
rts
ex_orai:ora #0 ;execute immediate opcodes
rts
ex_adci:adc #0 ;execute immediate opcodes
rts
ex_sbci:sbc #0 ;execute immediate opcodes
rts
.else
ex_andi:.res 3
ex_eori:.res 3
ex_orai:.res 3
ex_adci:.res 3
ex_sbci:.res 3
.endif
abs1: .byte $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
abs7f: .byte $7f ;test pattern for compare
;loads
fLDx: .byte fn,fn,0,fz ;expected flags for load
;shifts
rASL: ;expected result ASL & ROL -carry
rROL: .byte $86,$04,$82,0 ; "
rROLc: .byte $87,$05,$83,1 ;expected result ROL +carry
rLSR: ;expected result LSR & ROR -carry
rROR: .byte $61,$41,$20,0 ; "
rRORc: .byte $e1,$c1,$a0,$80 ;expected result ROR +carry
fASL: ;expected flags for shifts
fROL: .byte fnc,fc,fn,fz ;no carry in
fROLc: .byte fnc,fc,fn,0 ;carry in
fLSR:
fROR: .byte fc,0,fc,fz ;no carry in
fRORc: .byte fnc,fn,fnc,fn ;carry in
;increments (decrements)
rINC: .byte $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC: .byte 0,fn,fn,fz,0 ;expected flags for INC/DEC
;logical memory operand
absOR: .byte 0,$1f,$71,$80 ;test pattern for OR
absAN: .byte $0f,$ff,$7f,$80 ;test pattern for AND
absEO: .byte $ff,$0f,$8f,$8f ;test pattern for EOR
;logical accu operand
absORa: .byte 0,$f1,$1f,0 ;test pattern for OR
absANa: .byte $f0,$ff,$ff,$ff ;test pattern for AND
absEOa: .byte $ff,$f0,$f0,$0f ;test pattern for EOR
;logical results
absrlo: .byte 0,$ff,$7f,$80
absflo: .byte fz,fn,0,fn
data_bss_end:
.CODE
.org code_segment
.P02 ; disable 65SC02, 65C02 and 65816 instructions
start: cld
ldx #$ff
txs
lda #0 ;*** test 0 = initialize
sta test_case
test_num .set 0
;stop interrupts before initializing BSS
.if I_flag = 1
sei
.endif
;initialize I/O for report channel
.if report = 1
jsr report_init
.endif
;pretest small branch offset
ldx #5
jmp psb_test
psb_bwok:
ldy #5
bne psb_forw
trap ;branch should be taken
dey ;forward landing zone
dey
dey
dey
dey
psb_forw:
dey
dey
dey
dey
dey
beq psb_fwok
trap ;forward offset
dex ;backward landing zone
dex
dex
dex
dex
psb_back:
dex
dex
dex
dex
dex
beq psb_bwok
trap ;backward offset
psb_test:
bne psb_back
trap ;branch should be taken
psb_fwok:
;initialize BSS segment
.if load_data_direct <> 1
ldx #zp_end-zp_init-1
ld_zp: lda zp_init,x
sta zp_bss,x
dex
bpl ld_zp
ldx #data_end-data_init-1
ld_data:lda data_init,x
sta data_bss,x
dex
bpl ld_data
.if ROM_vectors = 1
ldx #5
ld_vect:lda vec_init,x
sta vec_bss,x
dex
bpl ld_vect
.endif
.endif
;retain status of interrupt flag
.if I_flag = 2
php
pla
and #4 ;isolate flag
sta flag_I_on ;or mask
eor #lo(~4) ;reverse
sta flag_I_off ;and mask
.endif
;generate checksum for RAM integrity test
.if ram_top > -1
lda #0
sta zpt ;set low byte of indirect pointer
sta ram_chksm+1 ;checksum high byte
.if disable_selfmod = 0
sta range_adr ;reset self modifying code
.endif
clc
ldx #zp_bss-zero_page ;zeropage - write test area
gcs3: adc zero_page,x
bcc gcs2
inc ram_chksm+1 ;carry to high byte
clc
gcs2: inx
bne gcs3
ldx #hi(abs1) ;set high byte of indirect pointer
stx zpt+1
ldy #lo(abs1) ;data after write & execute test area
gcs5: adc (zpt),y
bcc gcs4
inc ram_chksm+1 ;carry to high byte
clc
gcs4: iny
bne gcs5
inx ;advance RAM high address
stx zpt+1
cpx #ram_top
bne gcs5
sta ram_chksm ;checksum complete
.endif
next_test
.if disable_selfmod = 0
;testing relative addressing with BEQ
ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr)
range_loop:
dey ;next relative address
tya
tax ;precharge count to end of loop
bpl range_fw ;calculate relative address
clc ;avoid branch self or to relative address of branch
adc #2
nop ;offset landing zone - tolerate +/-5 offset to branch
nop
nop
nop
nop
range_fw:
nop
nop
nop
nop
nop
eor #$7f ;complement except sign
sta range_adr ;load into test target
lda #0 ;should set zero flag in status register
jmp range_op
dex ; offset landing zone - backward branch too far
dex
dex
dex
dex
;relative address target field with branch under test in the middle
dex ;-128 - max backward
dex
dex
dex
dex
dex
dex
dex
dex ;-120
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-110
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-100
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-90
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-80
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-70
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-60
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-50
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-40
dex
dex
dex
dex
dex
dex
dex
dex
dex
dex ;-30
dex
dex