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0667-Add-PIC16F153xx-processors.patch
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0667-Add-PIC16F153xx-processors.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Michael Huebler <[email protected]>
Date: Sat, 8 Jun 2019 17:04:07 +0200
Subject: [PATCH] 0667: Add PIC16F153xx processors.
Squashed:
Add PIC processor support for the PIC16F153xx range.
---
.gitignore | 1 +
Ghidra/Processors/PIC/certification.manifest | 4 +
.../Processors/PIC/data/languages/pic16.ldefs | 12 +
.../Processors/PIC/data/languages/pic16.sinc | 2 +-
.../data/languages/pic16_instructions.sinc | 67 ++-
.../PIC/data/languages/pic16f.cspec | 2 -
.../PIC/data/languages/pic16f.pspec | 2 -
.../PIC/data/languages/pic16f153xx.cspec | 165 +++++++
.../PIC/data/languages/pic16f153xx.pspec | 466 ++++++++++++++++++
.../PIC/data/languages/pic16f153xx.slaspec | 6 +
.../PIC/data/manuals/PIC-16F153xx.idx | 51 ++
11 files changed, 753 insertions(+), 25 deletions(-)
create mode 100644 Ghidra/Processors/PIC/data/languages/pic16f153xx.cspec
create mode 100644 Ghidra/Processors/PIC/data/languages/pic16f153xx.pspec
create mode 100644 Ghidra/Processors/PIC/data/languages/pic16f153xx.slaspec
create mode 100644 Ghidra/Processors/PIC/data/manuals/PIC-16F153xx.idx
diff --git a/.gitignore b/.gitignore
index d829c0067e..e85592f865 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,6 +7,7 @@ dependencies/
flatRepo/
Ghidra/.ghidraSvrKeys
wrapper.log*
+*.launch
Thumbs.db
.DS_Store
diff --git a/Ghidra/Processors/PIC/certification.manifest b/Ghidra/Processors/PIC/certification.manifest
index e60fb77053..e30f12ed83 100644
--- a/Ghidra/Processors/PIC/certification.manifest
+++ b/Ghidra/Processors/PIC/certification.manifest
@@ -33,6 +33,9 @@ data/languages/pic16c5x.slaspec||GHIDRA||reviewed||END|
data/languages/pic16f.cspec||GHIDRA||||END|
data/languages/pic16f.pspec||GHIDRA||||END|
data/languages/pic16f.slaspec||GHIDRA||||END|
+data/languages/pic16f153xx.cspec||GHIDRA||||END|
+data/languages/pic16f153xx.pspec||GHIDRA||||END|
+data/languages/pic16f153xx.slaspec||GHIDRA||||END|
data/languages/pic17c7xx.cspec||GHIDRA||||END|
data/languages/pic17c7xx.ldefs||GHIDRA||reviewed||END|
data/languages/pic17c7xx.pspec||GHIDRA||||END|
@@ -48,6 +51,7 @@ data/languages/pic18_instructions.sinc||GHIDRA||||END|
data/manuals/PIC-12.idx||GHIDRA||||END|
data/manuals/PIC-16.idx||GHIDRA||||END|
data/manuals/PIC-16F.idx||GHIDRA||||END|
+data/manuals/PIC-16F153xx.idx||GHIDRA||||END|
data/manuals/PIC-17.idx||GHIDRA||||END|
data/manuals/PIC-18.idx||GHIDRA||||END|
data/manuals/PIC24.idx||GHIDRA||||END|
diff --git a/Ghidra/Processors/PIC/data/languages/pic16.ldefs b/Ghidra/Processors/PIC/data/languages/pic16.ldefs
index 94d988f255..72476078f9 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16.ldefs
+++ b/Ghidra/Processors/PIC/data/languages/pic16.ldefs
@@ -27,4 +27,16 @@
<compiler name="default" spec="pic16f.cspec" id="default"/>
<external_name tool="IDA-PRO" name="pic16fxx"/>
</language>
+ <language processor="PIC-16"
+ endian="little"
+ size="16"
+ variant="PIC-16F153XX"
+ version="1.0"
+ slafile="pic16f153xx.sla"
+ processorspec="pic16f153xx.pspec"
+ manualindexfile="../manuals/PIC-16F153xx.idx"
+ id="PIC-16:LE:16:PIC-16F153xx">
+ <description>PIC-16(L)F153XX</description>
+ <compiler name="default" spec="pic16f153xx.cspec" id="default"/>
+ </language>
</language_definitions>
diff --git a/Ghidra/Processors/PIC/data/languages/pic16.sinc b/Ghidra/Processors/PIC/data/languages/pic16.sinc
index 68207af119..41c88b16b1 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16.sinc
+++ b/Ghidra/Processors/PIC/data/languages/pic16.sinc
@@ -8,7 +8,7 @@ define alignment=2;
# Instruction Memory (ROM-based)
define space CODE type=ram_space wordsize=2 size=2 default;
-# General Purpose Register Memory consists of 4-banks of 255-bytes for PIC16,
+# General Purpose RAM Memory consists of 4-banks of 255-bytes for PIC16,
# or 32-banks of 255 bytes each for PIC_16F.
# Bank selection occurs using STATUS register bits RP0 & RP1
define space DATA type=ram_space size=2;
diff --git a/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc b/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
index 4d31346ed3..0a3fc67f75 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
+++ b/Ghidra/Processors/PIC/data/languages/pic16_instructions.sinc
@@ -6,6 +6,7 @@
# Little-endian bit numbering
define token instr16(16)
+ op16 = (0,15)
op14 = (0,13)
op12 = (2,13)
op11 = (3,13)
@@ -243,15 +244,15 @@ destREG: "1" is d=1 & f7=0x02 { export PCL; } # PCL (special behavior reqd)
D: "w" is d=0 { }
D: "f" is d=1 { }
-# Absolute address generated from k11 and PCLATH<4:3>
+# Absolute address generated from k11 and PCLATH<6:3>
absAddr11: k11 is k11 {
- addr:2 = ((zext(PCLATH) & 0x18) << 8) | k11;
- export addr;
+ local addr:2 = ((zext(PCLATH) & 0x18) << 8) | k11;
+ export *[const]:2 addr;
}
@if PROCESSOR == "PIC_16F"
-# Relative address
+# Relative address generated from sk9
relAddr9: addr is sk9 [ addr = inst_next + sk9; ] {
export *[CODE]:2 addr;
}
@@ -261,7 +262,6 @@ relAddr9: addr is sk9 [ addr = inst_next + sk9; ] {
# Immediate Data (Literal operation)
imm8: "#"k8 is k8 { export *[const]:1 k8; }
-@if PROCESSOR == "PIC_16F"
# Immediate Data (Literal operation)
imm7: "#"k7 is k7 { export *[const]:1 k7; }
@@ -271,8 +271,6 @@ imm6: "#"k6 is k6 { export *[const]:1 k6; }
# Immediate Data (Literal operation)
imm5: "#"k5 is k5 { export *[const]:1 k5; }
-@endif
-
# Bit identifier
bit: "#"b3 is b3 { export *[const]:1 b3; }
@@ -282,9 +280,15 @@ trisREG: "5" is l5=5 { local trl:2 = 0x89; export *[DATA]:1 trl; } #
trisREG: "6" is l5=6 { local trl:2 = 0x187; export *[DATA]:1 trl; } # TRISB
trisREG: "7" is l5=7 { local trl:2 = 0x188; export *[DATA]:1 trl; } # TRISC
@elif PROCESSOR == "PIC_16F"
-trisREG: "5" is l5=5 { local trl:2 = 0x10C; export *[DATA]:1 trl; } # TRISA
-trisREG: "6" is l5=6 { local trl:2 = 0x10D; export *[DATA]:1 trl; } # TRISB
-trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } # TRISC
+@ifndef PIC16F153XX
+trisREG: "5" is l5=5 { local trl:2 = 0x08C; export *[DATA]:1 trl; } # TRISA
+trisREG: "6" is l5=6 { local trl:2 = 0x08D; export *[DATA]:1 trl; } # TRISB
+trisREG: "7" is l5=7 { local trl:2 = 0x08E; export *[DATA]:1 trl; } # TRISC
+@else
+trisREG: "5" is l5=5 { local trl:2 = 0x012; export *[DATA]:1 trl; } # TRISA
+trisREG: "6" is l5=6 { local trl:2 = 0x013; export *[DATA]:1 trl; } # TRISB
+trisREG: "7" is l5=7 { local trl:2 = 0x014; export *[DATA]:1 trl; } # TRISC
+@endif
@endif
:^instruction is possibleSkip=1 & instruction [ possibleSkip=0; ] {
@@ -329,7 +333,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
:ADDWF PC, D is op6=0x07 & D & d=1 & f7=0x02 & PC {
# --00 0111 dfff ffff
# 0000 0111 1000 0010 -> ADDWF PCL, w, ACCESS
- addr:2 = inst_start >> 1; # Compenstate for CODE wordsize
+ addr:2 = inst_start >> 1; # Compensate for CODE wordsize
PCLATH = addr(1);
tmp:1 = addr:1;
setAddFlags(tmp, W);
@@ -359,7 +363,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
:ADDWFC PC, D is op6=0x3D & D & d=1 & f7=0x02 & PC {
# --00 0111 dfff ffff
# 0000 0111 1000 0010 -> ADDWF PCL, w, ACCESS
- addr:2 = inst_start >> 1; # Compenstate for CODE wordsize
+ addr:2 = inst_start >> 1; # Compensate for CODE wordsize
PCLATH = addr(1);
val:1 = addr:1;
@@ -438,7 +442,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
$(Z) = 0;
}
-
+@if PROCESSOR == "PIC_16"
:BCF STATUS, "RP0" is op4=0x4 & b3=5 & f7=0x3 & STATUS & bit {
# --01 00bb bfff ffff
# 0001 0010 1000 0011 -> BCF STATUS, #RP0
@@ -464,6 +468,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
local bitmask = ~(1 << bit);
STATUS = STATUS & bitmask;
}
+@endif
:BSF srcREG, bit is op4=0x5 & bit & srcREG {
# --01 01bb bfff ffff
@@ -496,6 +501,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
$(Z) = 1;
}
+@if PROCESSOR == "PIC_16"
:BSF STATUS, "RP0" is op4=0x5 & b3=5 & f7=0x3 & STATUS & bit {
# --01 01bb bfff ffff
# 0001 0110 1000 0011 -> BSF STATUS, #RP0
@@ -520,6 +526,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
local bitmask = 1 << bit;
STATUS = STATUS | bitmask;
}
+@endif
:BTFSC srcREG, bit is op4=0x6 & bit & srcREG [ possibleSkip = 1; globalset(inst_next,possibleSkip); ] {
# --01 10bb bfff ffff
@@ -633,12 +640,13 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
call [absAddr11];
}
-:CALLW is op14=0x000a {
- # --00 0000 0000 1010
+:CALLW is op16=0x0006 {
+ # 0000 0000 0000 1010
+ local loc:2 = (zext(PCLATH) << 8) | zext(W);
push(&:2 inst_next);
- call [W];
+ call [loc];
}
-
+
:CLRF srcREG is op6=0x01 & d=1 & srcREG {
# --00 0001 1fff ffff
# 0000 0001 1000 0000 -> CLRF INDF
@@ -647,6 +655,7 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
$(Z) = 1;
}
+@if PROCESSOR == "PIC_16"
:CLRF STATUS is op6=0x01 & d=1 & f7=0x3 & STATUS {
# --00 0001 1fff ffff
# 0000 0001 1000 0011 -> CLRF STATUS
@@ -657,6 +666,16 @@ trisREG: "7" is l5=7 { local trl:2 = 0x10E; export *[DATA]:1 trl; } #
$(DC) = 0;
$(C) = 0;
}
+@elif PROCESSOR == "PIC_16F"
+:CLRF STATUS is op6=0x01 & d=1 & f7=0x3 & STATUS {
+ # --00 0001 1fff ffff
+ # 0000 0001 1000 0011 -> CLRF STATUS
+ STATUS = 0;
+ $(Z) = 0;
+ $(DC) = 0;
+ $(C) = 0;
+}
+@endif
:CLRW is op12=0b000001000000 & mm {
# --00 0001 0xxx xxxx
@@ -796,18 +815,26 @@ srcFSRk: sk6"["fsrk"]" is fsrk & sk6 {
srcFSRk = W;
}
+:MOVLP imm7 is op7=0x63 & imm7 {
+ PCLATH = imm7;
+}
+@endif
+
+@if PROCESSOR == "PIC_16F"
+
+@ifndef PIC16F153XX
:MOVLB imm5 is op9=0x1 & imm5 {
BSR = imm5;
}
+@else
# Alternate variant in certain pic16f variants
:MOVLB imm6 is op8=0x5 & imm6 {
BSR = imm6;
}
-:MOVLP imm7 is op7=0x63 & imm7 {
- PCLATH = imm7 & 0x1F;
-}
+@endif
+
@endif
:MOVLW imm8 is op6=0x30 & imm8 {
diff --git a/Ghidra/Processors/PIC/data/languages/pic16f.cspec b/Ghidra/Processors/PIC/data/languages/pic16f.cspec
index 5ec51e0526..ebcea9ed52 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16f.cspec
+++ b/Ghidra/Processors/PIC/data/languages/pic16f.cspec
@@ -29,8 +29,6 @@
</output>
<unaffected>
<register name="STATUS"/>
- <register name="IRP"/>
- <register name="RP"/>
<register name="PC"/>
<register name="PCL"/>
<register name="PCLATH"/>
diff --git a/Ghidra/Processors/PIC/data/languages/pic16f.pspec b/Ghidra/Processors/PIC/data/languages/pic16f.pspec
index a821ddbec2..3579b6290d 100644
--- a/Ghidra/Processors/PIC/data/languages/pic16f.pspec
+++ b/Ghidra/Processors/PIC/data/languages/pic16f.pspec
@@ -121,8 +121,6 @@
</volatile>
<register_data>
<register name="STATUS" group="STATUS"/>
- <register name="IRP" group="STATUS"/>
- <register name="RP" group="STATUS"/>
<register name="PC" group="PC"/>
<register name="PCL" group="PC"/>
<register name="PCLATH" group="PC"/>
diff --git a/Ghidra/Processors/PIC/data/languages/pic16f153xx.cspec b/Ghidra/Processors/PIC/data/languages/pic16f153xx.cspec
new file mode 100644
index 0000000000..aa6e579a98
--- /dev/null
+++ b/Ghidra/Processors/PIC/data/languages/pic16f153xx.cspec
@@ -0,0 +1,165 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<compiler_spec>
+ <global>
+ <range space="CODE" first="0x0000" last="0x1fff"/>
+
+ <range space="DATA" first="0x0020" last="0x007f"/>
+ <range space="DATA" first="0x00a0" last="0x00ff"/>
+ <range space="DATA" first="0x0120" last="0x017f"/>
+ <range space="DATA" first="0x01a0" last="0x01ff"/>
+ <range space="DATA" first="0x0220" last="0x027f"/>
+ <range space="DATA" first="0x02a0" last="0x02ff"/>
+ <range space="DATA" first="0x0320" last="0x037f"/>
+ <range space="DATA" first="0x03a0" last="0x03ff"/>
+ <range space="DATA" first="0x0420" last="0x047f"/>
+ <range space="DATA" first="0x04a0" last="0x04ff"/>
+ <range space="DATA" first="0x0520" last="0x057f"/>
+ <range space="DATA" first="0x05a0" last="0x05ff"/>
+ <range space="DATA" first="0x0620" last="0x064f"/>
+ <range space="DATA" first="0x0670" last="0x067f"/>
+ <range space="DATA" first="0x06f0" last="0x06ff"/>
+ <range space="DATA" first="0x0770" last="0x077f"/>
+ <range space="DATA" first="0x07f0" last="0x07ff"/>
+ <range space="DATA" first="0x0870" last="0x087f"/>
+ <range space="DATA" first="0x08f0" last="0x08ff"/>
+ <range space="DATA" first="0x0970" last="0x097f"/>
+ <range space="DATA" first="0x09f0" last="0x09ff"/>
+ <range space="DATA" first="0x0a70" last="0x0a7f"/>
+ <range space="DATA" first="0x0af0" last="0x0aff"/>
+ <range space="DATA" first="0x0b70" last="0x0b7f"/>
+ <range space="DATA" first="0x0bf0" last="0x0bff"/>
+ <range space="DATA" first="0x0c70" last="0x0c7f"/>
+ <range space="DATA" first="0x0cf0" last="0x0cff"/>
+ <range space="DATA" first="0x0d70" last="0x0d7f"/>
+ <range space="DATA" first="0x0df0" last="0x0dff"/>
+ <range space="DATA" first="0x0e70" last="0x0e7f"/>
+ <range space="DATA" first="0x0ef0" last="0x0eff"/>
+ <range space="DATA" first="0x0f70" last="0x0f7f"/>
+ <range space="DATA" first="0x0ff0" last="0x0fff"/>
+ <range space="DATA" first="0x1070" last="0x107f"/>
+ <range space="DATA" first="0x10f0" last="0x10ff"/>
+ <range space="DATA" first="0x1170" last="0x117f"/>
+ <range space="DATA" first="0x11f0" last="0x11ff"/>
+ <range space="DATA" first="0x1270" last="0x127f"/>
+ <range space="DATA" first="0x12f0" last="0x12ff"/>
+ <range space="DATA" first="0x1370" last="0x137f"/>
+ <range space="DATA" first="0x13f0" last="0x13ff"/>
+ <range space="DATA" first="0x1470" last="0x147f"/>
+ <range space="DATA" first="0x14f0" last="0x14ff"/>
+ <range space="DATA" first="0x1570" last="0x157f"/>
+ <range space="DATA" first="0x15f0" last="0x15ff"/>
+ <range space="DATA" first="0x1670" last="0x167f"/>
+ <range space="DATA" first="0x16f0" last="0x16ff"/>
+ <range space="DATA" first="0x1770" last="0x177f"/>
+ <range space="DATA" first="0x17f0" last="0x17ff"/>
+ <range space="DATA" first="0x1870" last="0x187f"/>
+ <range space="DATA" first="0x18f0" last="0x18ff"/>
+ <range space="DATA" first="0x1970" last="0x197f"/>
+ <range space="DATA" first="0x19f0" last="0x19ff"/>
+ <range space="DATA" first="0x1a70" last="0x1a7f"/>
+ <range space="DATA" first="0x1af0" last="0x1aff"/>
+ <range space="DATA" first="0x1b70" last="0x1b7f"/>
+ <range space="DATA" first="0x1bf0" last="0x1bff"/>
+ <range space="DATA" first="0x1c70" last="0x1c7f"/>
+ <range space="DATA" first="0x1cf0" last="0x1cff"/>
+ <range space="DATA" first="0x1d70" last="0x1d7f"/>
+ <range space="DATA" first="0x1df0" last="0x1dff"/>
+ <range space="DATA" first="0x1e70" last="0x1e7f"/>
+ <range space="DATA" first="0x1ef0" last="0x1eff"/>
+ <range space="DATA" first="0x1f70" last="0x1f7f"/>
+ <range space="DATA" first="0x1ff0" last="0x1fff"/>
+ </global>
+ <nohighptr>
+ <range space="DATA" first="0x0000" last="0x001f"/>
+ <range space="DATA" first="0x0080" last="0x009f"/>
+ <range space="DATA" first="0x0100" last="0x011f"/>
+ <range space="DATA" first="0x0180" last="0x019f"/>
+ <range space="DATA" first="0x0200" last="0x021f"/>
+ <range space="DATA" first="0x0280" last="0x029f"/>
+ <range space="DATA" first="0x0300" last="0x031f"/>
+ <range space="DATA" first="0x0380" last="0x039f"/>
+ <range space="DATA" first="0x0400" last="0x041f"/>
+ <range space="DATA" first="0x0480" last="0x049f"/>
+ <range space="DATA" first="0x0500" last="0x051f"/>
+ <range space="DATA" first="0x0580" last="0x059f"/>
+ <range space="DATA" first="0x0600" last="0x061f"/>
+ <range space="DATA" first="0x0680" last="0x069f"/>
+ <range space="DATA" first="0x0700" last="0x071f"/>
+ <range space="DATA" first="0x0780" last="0x079f"/>
+ <range space="DATA" first="0x0800" last="0x081f"/>
+ <range space="DATA" first="0x0880" last="0x089f"/>
+ <range space="DATA" first="0x0900" last="0x091f"/>
+ <range space="DATA" first="0x0980" last="0x099f"/>
+ <range space="DATA" first="0x0a00" last="0x0a1f"/>
+ <range space="DATA" first="0x0a80" last="0x0a9f"/>
+ <range space="DATA" first="0x0b00" last="0x0b1f"/>
+ <range space="DATA" first="0x0b80" last="0x0b9f"/>
+ <range space="DATA" first="0x0c00" last="0x0c1f"/>
+ <range space="DATA" first="0x0c80" last="0x0c9f"/>
+ <range space="DATA" first="0x0d00" last="0x0d1f"/>
+ <range space="DATA" first="0x0d80" last="0x0d9f"/>
+ <range space="DATA" first="0x0e00" last="0x0e1f"/>
+ <range space="DATA" first="0x0e80" last="0x0e9f"/>
+ <range space="DATA" first="0x0f00" last="0x0f1f"/>
+ <range space="DATA" first="0x0f80" last="0x0f9f"/>
+ <range space="DATA" first="0x1000" last="0x101f"/>
+ <range space="DATA" first="0x1080" last="0x109f"/>
+ <range space="DATA" first="0x1100" last="0x111f"/>
+ <range space="DATA" first="0x1180" last="0x119f"/>
+ <range space="DATA" first="0x1200" last="0x121f"/>
+ <range space="DATA" first="0x1280" last="0x129f"/>
+ <range space="DATA" first="0x1300" last="0x131f"/>
+ <range space="DATA" first="0x1380" last="0x139f"/>
+ <range space="DATA" first="0x1400" last="0x141f"/>
+ <range space="DATA" first="0x1480" last="0x149f"/>
+ <range space="DATA" first="0x1500" last="0x151f"/>
+ <range space="DATA" first="0x1580" last="0x159f"/>
+ <range space="DATA" first="0x1600" last="0x161f"/>
+ <range space="DATA" first="0x1680" last="0x169f"/>
+ <range space="DATA" first="0x1700" last="0x171f"/>
+ <range space="DATA" first="0x1780" last="0x179f"/>
+ <range space="DATA" first="0x1800" last="0x181f"/>
+ <range space="DATA" first="0x1880" last="0x189f"/>
+ <range space="DATA" first="0x1900" last="0x191f"/>
+ <range space="DATA" first="0x1980" last="0x199f"/>
+ <range space="DATA" first="0x1a00" last="0x1a1f"/>
+ <range space="DATA" first="0x1a80" last="0x1a9f"/>
+ <range space="DATA" first="0x1b00" last="0x1b1f"/>
+ <range space="DATA" first="0x1b80" last="0x1b9f"/>
+ <range space="DATA" first="0x1c00" last="0x1c1f"/>
+ <range space="DATA" first="0x1c80" last="0x1c9f"/>
+ <range space="DATA" first="0x1d00" last="0x1d1f"/>
+ <range space="DATA" first="0x1d80" last="0x1d9f"/>
+ <range space="DATA" first="0x1e00" last="0x1e6f"/>
+ <range space="DATA" first="0x1e80" last="0x1eef"/>
+ <range space="DATA" first="0x1f00" last="0x1f6f"/>
+ <range space="DATA" first="0x1f80" last="0x1fef"/>
+ </nohighptr>
+ <stackpointer register="STKPTR" space="HWSTACK" growth="positive"/>
+ <default_proto>
+ <prototype name="__stdcall" extrapop="-2" stackshift="-2">
+ <input>
+ <pentry minsize="1" maxsize="1">
+ <register name="W"/>
+ </pentry>
+ </input>
+ <output>
+ <pentry minsize="1" maxsize="1">
+ <register name="W"/>
+ </pentry>
+ </output>
+ <unaffected>
+ <register name="STATUS"/>
+ <register name="PC"/>
+ <register name="PCL"/>
+ <register name="PCLATH"/>
+ <register name="STKPTR"/>
+ <register name="BSR"/>
+ </unaffected>
+ <localrange>
+ <range space="stack" first="0x0" last="0xf"/>
+ </localrange>
+ </prototype>
+ </default_proto>
+</compiler_spec>
diff --git a/Ghidra/Processors/PIC/data/languages/pic16f153xx.pspec b/Ghidra/Processors/PIC/data/languages/pic16f153xx.pspec
new file mode 100644
index 0000000000..bbaa04f619
--- /dev/null
+++ b/Ghidra/Processors/PIC/data/languages/pic16f153xx.pspec
@@ -0,0 +1,466 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+ <programcounter register="PC"/>
+ <data_space space="DATA"/>
+ <context_data>
+ <context_set space="CODE">
+ <set name="doPseudo" val="0"/>
+ </context_set>
+ <tracked_set space="CODE">
+ <set name="BSR" val="0"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0000" last="0x01ff">
+ <set name="PCLATH" val="0x00"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0200" last="0x03ff">
+ <set name="PCLATH" val="0x01"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0400" last="0x05ff">
+ <set name="PCLATH" val="0x02"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0600" last="0x07ff">
+ <set name="PCLATH" val="0x03"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0800" last="0x09ff">
+ <set name="PCLATH" val="0x04"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0a00" last="0x0bff">
+ <set name="PCLATH" val="0x05"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0c00" last="0x0dff">
+ <set name="PCLATH" val="0x06"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x0e00" last="0x0fff">
+ <set name="PCLATH" val="0x07"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1000" last="0x11ff">
+ <set name="PCLATH" val="0x08"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1200" last="0x13ff">
+ <set name="PCLATH" val="0x09"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1400" last="0x15ff">
+ <set name="PCLATH" val="0x0a"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1600" last="0x17ff">
+ <set name="PCLATH" val="0x0b"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1800" last="0x19ff">
+ <set name="PCLATH" val="0x0c"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1a00" last="0x1bff">
+ <set name="PCLATH" val="0x0d"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1c00" last="0x1dff">
+ <set name="PCLATH" val="0x0e"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x1e00" last="0x1fff">
+ <set name="PCLATH" val="0x0f"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2000" last="0x21ff">
+ <set name="PCLATH" val="0x10"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2200" last="0x23ff">
+ <set name="PCLATH" val="0x11"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2400" last="0x25ff">
+ <set name="PCLATH" val="0x12"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2600" last="0x27ff">
+ <set name="PCLATH" val="0x13"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2800" last="0x29ff">
+ <set name="PCLATH" val="0x14"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2a00" last="0x2bff">
+ <set name="PCLATH" val="0x15"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2c00" last="0x2dff">
+ <set name="PCLATH" val="0x16"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x2e00" last="0x2fff">
+ <set name="PCLATH" val="0x17"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3000" last="0x31ff">
+ <set name="PCLATH" val="0x18"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3200" last="0x33ff">
+ <set name="PCLATH" val="0x19"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3400" last="0x35ff">
+ <set name="PCLATH" val="0x1a"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3600" last="0x37ff">
+ <set name="PCLATH" val="0x1b"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3800" last="0x39ff">
+ <set name="PCLATH" val="0x1c"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3a00" last="0x3bff">
+ <set name="PCLATH" val="0x1d"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3c00" last="0x3dff">
+ <set name="PCLATH" val="0x1e"/>
+ </tracked_set>
+ <tracked_set space="CODE" first="0x3e00" last="0x3fff">
+ <set name="PCLATH" val="0x1f"/>
+ </tracked_set>
+ </context_data>
+ <volatile outputop="write_sfr" inputop="read_sfr">
+ <range space="DATA" first="0x00c" last="0x01f"/>
+ <range space="DATA" first="0x08c" last="0x094"/>
+ <range space="DATA" first="0x10c" last="0x11f"/>
+ <range space="DATA" first="0x18c" last="0x19f"/>
+ <range space="DATA" first="0x20c" last="0x21f"/>
+ <range space="DATA" first="0x28c" last="0x29f"/>
+ <range space="DATA" first="0x30c" last="0x31f"/>
+ <range space="DATA" first="0x38c" last="0x39f"/>
+ <range space="DATA" first="0x40c" last="0x41f"/>
+ <range space="DATA" first="0x48c" last="0x49f"/>
+ <range space="DATA" first="0x50c" last="0x51f"/>
+ <range space="DATA" first="0x58c" last="0x59f"/>
+ <range space="DATA" first="0x60c" last="0x61f"/>
+ <range space="DATA" first="0x68c" last="0x69f"/>
+ <range space="DATA" first="0x70c" last="0x71f"/>
+ <range space="DATA" first="0x78c" last="0x79f"/>
+ <range space="DATA" first="0x80c" last="0x81f"/>
+ <range space="DATA" first="0x88c" last="0x89f"/>
+ <range space="DATA" first="0x90c" last="0x91f"/>
+ <range space="DATA" first="0x98c" last="0x99f"/>
+ <range space="DATA" first="0xa0c" last="0xa1f"/>
+ <range space="DATA" first="0x1e0c" last="0x1e6f"/>
+ <range space="DATA" first="0x1e8c" last="0x1eef"/>
+ <range space="DATA" first="0x1f0c" last="0x1f6f"/>
+ <range space="DATA" first="0x1f8c" last="0x1fef"/>
+ </volatile>
+ <register_data>
+ <register name="STATUS" group="STATUS"/>
+ <register name="PC" group="PC"/>
+ <register name="PCL" group="PC"/>
+ <register name="PCLATH" group="PC"/>
+ </register_data>
+ <default_symbols>
+ <symbol name="Reset" address="CODE:0000" entry="true"/>
+ <symbol name="Interrupt" address="CODE:0004" entry="true"/>
+
+ <symbol name="PORTA" address="DATA:0C" entry="false"/>
+ <symbol name="PORTB" address="DATA:0D" entry="false"/>
+ <symbol name="PORTC" address="DATA:0E" entry="false"/>
+
+ <symbol name="TRISA" address="DATA:12" entry="false"/>
+ <symbol name="TRISB" address="DATA:13" entry="false"/>
+ <symbol name="TRISC" address="DATA:14" entry="false"/>
+
+ <symbol name="LATA" address="DATA:18" entry="false"/>
+ <symbol name="LATB" address="DATA:19" entry="false"/>
+ <symbol name="LATB" address="DATA:1A" entry="false"/>
+
+ <symbol name="ADRESL" address="DATA:9b" entry="false"/>
+ <symbol name="ASRESH" address="DATA:9c" entry="false"/>
+ <symbol name="ADCON0" address="DATA:9d" entry="false"/>
+ <symbol name="ADCON1" address="DATA:9e" entry="false"/>
+ <symbol name="ADACT" address="DATA:9f" entry="false"/>
+
+ <symbol name="RC1REG1" address="DATA:119" entry="false"/>
+ <symbol name="TX1REG1" address="DATA:11A" entry="false"/>
+ <symbol name="SP1BRG1L" address="DATA:11B" entry="false"/>
+ <symbol name="SP1BRG1H" address="DATA:11C" entry="false"/>
+ <symbol name="RC1STA1" address="DATA:11D" entry="false"/>
+ <symbol name="TX1STA1" address="DATA:11E" entry="false"/>
+ <symbol name="BAUD1CON1" address="DATA:11F" entry="false"/>
+
+ <symbol name="SSP1BUF" address="DATA:18C" entry="false"/>
+ <symbol name="SSP1ADD" address="DATA:18D" entry="false"/>
+ <symbol name="SSP1MSK" address="DATA:18E" entry="false"/>
+ <symbol name="SSP1STAT" address="DATA:18F" entry="false"/>
+ <symbol name="SSP1CON1" address="DATA:190" entry="false"/>
+ <symbol name="SSP1CON2" address="DATA:191" entry="false"/>
+ <symbol name="SSP1CON3" address="DATA:192" entry="false"/>
+
+ <symbol name="TMR1L" address="DATA:20C" entry="false"/>
+ <symbol name="TMR1H" address="DATA:20D" entry="false"/>
+ <symbol name="T1CON" address="DATA:20E" entry="false"/>
+ <symbol name="T1GCON" address="DATA:20F" entry="false"/>
+ <symbol name="T1GATE" address="DATA:210" entry="false"/>
+ <symbol name="T1CLK" address="DATA:211" entry="false"/>
+
+ <symbol name="TMR2" address="DATA:28C" entry="false"/>
+ <symbol name="PR2" address="DATA:28D" entry="false"/>
+ <symbol name="T2CON" address="DATA:28E" entry="false"/>
+ <symbol name="T2HLT" address="DATA:28F" entry="false"/>
+ <symbol name="T2CLK" address="DATA:290" entry="false"/>
+ <symbol name="T2ERS" address="DATA:291" entry="false"/>
+
+ <symbol name="CCPR1L" address="DATA:30C" entry="false"/>
+ <symbol name="CCPR1H" address="DATA:30D" entry="false"/>
+ <symbol name="CCP1CON" address="DATA:30E" entry="false"/>
+ <symbol name="CCP1CAP" address="DATA:30F" entry="false"/>
+ <symbol name="CCPR2L" address="DATA:310" entry="false"/>
+ <symbol name="CCPR2H" address="DATA:311" entry="false"/>
+ <symbol name="CCP2CON" address="DATA:312" entry="false"/>
+ <symbol name="CCP2CAP" address="DATA:313" entry="false"/>
+ <symbol name="PWM3DCL" address="DATA:314" entry="false"/>
+ <symbol name="PWM3DCH" address="DATA:315" entry="false"/>
+ <symbol name="PWM3CON" address="DATA:316" entry="false"/>
+
+ <symbol name="PWM4DCL" address="DATA:318" entry="false"/>
+ <symbol name="PWM4DCH" address="DATA:319" entry="false"/>
+ <symbol name="PWM4CON" address="DATA:31A" entry="false"/>
+
+ <symbol name="PWM5DCL" address="DATA:32C" entry="false"/>
+ <symbol name="PWM5DCH" address="DATA:32D" entry="false"/>
+ <symbol name="PWM5CON" address="DATA:32E" entry="false"/>
+
+ <symbol name="PWM6DCL" address="DATA:38C" entry="false"/>
+ <symbol name="PWM6DCH" address="DATA:38D" entry="false"/>
+ <symbol name="PWM6CON" address="DATA:38E" entry="false"/>
+
+ <symbol name="NCO1ACCL" address="DATA:58C" entry="false"/>
+ <symbol name="NCO1ACCH" address="DATA:58D" entry="false"/>
+ <symbol name="NCO1ACCU" address="DATA:58E" entry="false"/>
+ <symbol name="NCO1INCL" address="DATA:58F" entry="false"/>
+ <symbol name="NCO1INCH" address="DATA:590" entry="false"/>
+ <symbol name="NCO1INCU" address="DATA:591" entry="false"/>
+ <symbol name="NCO1CON" address="DATA:592" entry="false"/>
+ <symbol name="NCO1CLK" address="DATA:593" entry="false"/>
+
+ <symbol name="TMR0" address="DATA:59C" entry="false"/>
+ <symbol name="PR0" address="DATA:59D" entry="false"/>
+ <symbol name="TMR0CON0" address="DATA:59E" entry="false"/>
+ <symbol name="TMR0CON1" address="DATA:59F" entry="false"/>
+
+ <symbol name="CWG1CLK" address="DATA:60C" entry="false"/>
+ <symbol name="CWG1DAT" address="DATA:60D" entry="false"/>
+ <symbol name="CWG1DBR" address="DATA:60E" entry="false"/>
+ <symbol name="CWG1DBF" address="DATA:60F" entry="false"/>
+ <symbol name="CWG1CON0" address="DATA:610" entry="false"/>
+ <symbol name="CWG1CON1" address="DATA:611" entry="false"/>
+ <symbol name="CWG1AS0" address="DATA:612" entry="false"/>
+ <symbol name="CWG1AS1" address="DATA:613" entry="false"/>
+ <symbol name="CWG1STR" address="DATA:614" entry="false"/>
+
+ <symbol name="PIR0" address="DATA:70C" entry="false"/>
+ <symbol name="PIR1" address="DATA:70D" entry="false"/>
+ <symbol name="PIR2" address="DATA:70E" entry="false"/>
+ <symbol name="PIR3" address="DATA:70F" entry="false"/>
+ <symbol name="PIR4" address="DATA:710" entry="false"/>
+ <symbol name="PIR5" address="DATA:711" entry="false"/>
+ <symbol name="PIR6" address="DATA:712" entry="false"/>
+ <symbol name="PIR7" address="DATA:713" entry="false"/>
+
+ <symbol name="PIE0" address="DATA:716" entry="false"/>
+ <symbol name="PIE1" address="DATA:717" entry="false"/>
+ <symbol name="PIE2" address="DATA:718" entry="false"/>
+ <symbol name="PIE3" address="DATA:719" entry="false"/>
+ <symbol name="PIE4" address="DATA:71A" entry="false"/>
+ <symbol name="PIE5" address="DATA:71B" entry="false"/>
+ <symbol name="PIE6" address="DATA:71C" entry="false"/>
+ <symbol name="PIE7" address="DATA:71D" entry="false"/>
+
+ <symbol name="PMD0" address="DATA:796" entry="false"/>
+ <symbol name="PMD1" address="DATA:797" entry="false"/>
+ <symbol name="PMD2" address="DATA:798" entry="false"/>
+ <symbol name="PMD3" address="DATA:799" entry="false"/>
+ <symbol name="PMD4" address="DATA:79A" entry="false"/>
+ <symbol name="PMD5" address="DATA:79B" entry="false"/>
+
+ <symbol name="WDTCON0" address="DATA:80C" entry="false"/>
+ <symbol name="WDTCON1" address="DATA:80D" entry="false"/>
+ <symbol name="WDTL" address="DATA:80E" entry="false"/>
+ <symbol name="WDTH" address="DATA:80F" entry="false"/>
+ <symbol name="WDTU" address="DATA:810" entry="false"/>
+ <symbol name="BORCON" address="DATA:811" entry="false"/>
+ <symbol name="VREGCON" address="DATA:812" entry="false"/>
+ <symbol name="PCON0" address="DATA:813" entry="false"/>
+ <symbol name="PCON1" address="DATA:814" entry="false"/>
+
+ <symbol name="NVMADRL" address="DATA:81A" entry="false"/>
+ <symbol name="NVMADRH" address="DATA:81B" entry="false"/>
+ <symbol name="NVMDATL" address="DATA:81C" entry="false"/>
+ <symbol name="NVMDATH" address="DATA:81D" entry="false"/>
+ <symbol name="NVMCON1" address="DATA:81E" entry="false"/>
+ <symbol name="NVMCON2" address="DATA:81F" entry="false"/>
+
+ <symbol name="CPUDOZE" address="DATA:88C" entry="false"/>
+ <symbol name="OSCCON1" address="DATA:88D" entry="false"/>
+ <symbol name="OSCCON2" address="DATA:88E" entry="false"/>
+ <symbol name="OSCCON3" address="DATA:88F" entry="false"/>
+ <symbol name="OSCSTAT1" address="DATA:890" entry="false"/>
+ <symbol name="OSCEN" address="DATA:891" entry="false"/>
+ <symbol name="OSCTUNE" address="DATA:892" entry="false"/>
+ <symbol name="OSCFRQ" address="DATA:893" entry="false"/>
+
+ <symbol name="CLKRCON" address="DATA:895" entry="false"/>
+ <symbol name="CLKCLK" address="DATA:896" entry="false"/>
+
+ <symbol name="FVRCON" address="DATA:90C" entry="false"/>
+
+ <symbol name="DAC1CON0" address="DATA:90E" entry="false"/>
+ <symbol name="DAC1CON1" address="DATA:90F" entry="false"/>
+
+ <symbol name="ZCDCON" address="DATA:91F" entry="false"/>
+
+ <symbol name="CMOUT" address="DATA:98F" entry="false"/>
+ <symbol name="CM1CON0" address="DATA:990" entry="false"/>
+ <symbol name="CM1CON1" address="DATA:991" entry="false"/>
+ <symbol name="CM1NCH" address="DATA:992" entry="false"/>
+ <symbol name="CM1PCH" address="DATA:993" entry="false"/>
+ <symbol name="CM2CON0" address="DATA:994" entry="false"/>
+ <symbol name="CM2CON1" address="DATA:995" entry="false"/>
+ <symbol name="CM2NCH" address="DATA:996" entry="false"/>
+ <symbol name="CM2PCH" address="DATA:997" entry="false"/>
+
+ <symbol name="RC2REG" address="DATA:A19" entry="false"/>
+ <symbol name="TX2REG" address="DATA:A1A" entry="false"/>
+ <symbol name="SP2BRGL" address="DATA:A1B" entry="false"/>
+ <symbol name="SP2BRGH" address="DATA:A1C" entry="false"/>
+ <symbol name="RC2STA" address="DATA:A1D" entry="false"/>
+ <symbol name="TX2STA" address="DATA:A1E" entry="false"/>
+ <symbol name="BAUD2CON" address="DATA:A1F" entry="false"/>
+
+ <symbol name="CLC_CONTROLS" address="DATA:1E0C" entry="false"/>
+
+ <symbol name="CLCDATA" address="DATA:1E0F" entry="false"/>
+ <symbol name="CLC1CON" address="DATA:1E10" entry="false"/>
+ <symbol name="CLC1POL" address="DATA:1E11" entry="false"/>
+ <symbol name="CLC1SEL0" address="DATA:1E12" entry="false"/>
+ <symbol name="CLC1SEL1" address="DATA:1E13" entry="false"/>
+ <symbol name="CLC1SEL2" address="DATA:1E14" entry="false"/>
+ <symbol name="CLC1SEL3" address="DATA:1E15" entry="false"/>
+ <symbol name="CLC1GLS0" address="DATA:1E16" entry="false"/>
+ <symbol name="CLC1GLS1" address="DATA:1E17" entry="false"/>
+ <symbol name="CLC1GLS2" address="DATA:1E18" entry="false"/>
+ <symbol name="CLC1GLS3" address="DATA:1E19" entry="false"/>
+ <symbol name="CLC2CON" address="DATA:1E1A" entry="false"/>
+ <symbol name="CLC2POL" address="DATA:1E1B" entry="false"/>
+ <symbol name="CLC2SEL0" address="DATA:1E1C" entry="false"/>
+ <symbol name="CLC2SEL1" address="DATA:1E1D" entry="false"/>
+ <symbol name="CLC2SEL2" address="DATA:1E1E" entry="false"/>
+ <symbol name="CLC2SEL3" address="DATA:1E1F" entry="false"/>
+ <symbol name="CLC2GLS0" address="DATA:1E20" entry="false"/>
+ <symbol name="CLC2GLS1" address="DATA:1E21" entry="false"/>
+ <symbol name="CLC2GLS2" address="DATA:1E22" entry="false"/>
+ <symbol name="CLC2GLS3" address="DATA:1E23" entry="false"/>
+ <symbol name="CLC3CON" address="DATA:1E24" entry="false"/>
+ <symbol name="CLC3POL" address="DATA:1E25" entry="false"/>
+ <symbol name="CLC3SEL0" address="DATA:1E26" entry="false"/>
+ <symbol name="CLC3SEL1" address="DATA:1E27" entry="false"/>
+ <symbol name="CLC3SEL2" address="DATA:1E28" entry="false"/>
+ <symbol name="CLC3SEL3" address="DATA:1E29" entry="false"/>
+ <symbol name="CLC3GLS0" address="DATA:1E2A" entry="false"/>
+ <symbol name="CLC3GLS1" address="DATA:1E2B" entry="false"/>
+ <symbol name="CLC3GLS2" address="DATA:1E2C" entry="false"/>
+ <symbol name="CLC3GLS3" address="DATA:1E2D" entry="false"/>
+ <symbol name="CLC4CON" address="DATA:1E2E" entry="false"/>
+ <symbol name="CLC4POL" address="DATA:1E2F" entry="false"/>
+ <symbol name="CLC4SEL0" address="DATA:1E30" entry="false"/>
+ <symbol name="CLC4SEL1" address="DATA:1E31" entry="false"/>
+ <symbol name="CLC4SEL2" address="DATA:1E32" entry="false"/>
+ <symbol name="CLC4SEL3" address="DATA:1E33" entry="false"/>
+ <symbol name="CLC4GLS0" address="DATA:1E34" entry="false"/>
+ <symbol name="CLC4GLS1" address="DATA:1E35" entry="false"/>
+ <symbol name="CLC4GLS2" address="DATA:1E36" entry="false"/>
+ <symbol name="CLC4GLS3" address="DATA:1E37" entry="false"/>
+
+ <symbol name="NNNPPS_CONTROLS" address="DATA:1E8C" entry="false"/>
+
+ <symbol name="PPSLOCK" address="DATA:1E8F" entry="false"/>
+ <symbol name="INTPPS" address="DATA:1E90" entry="false"/>
+ <symbol name="T0CKIPPS" address="DATA:1E91" entry="false"/>
+ <symbol name="T1CKIPPS" address="DATA:1E92" entry="false"/>
+ <symbol name="T1GPPS" address="DATA:1E93" entry="false"/>
+
+ <symbol name="T2INPPS" address="DATA:1E9C" entry="false"/>
+
+ <symbol name="CCP1PPS" address="DATA:1EA1" entry="false"/>
+ <symbol name="CCP2PPS" address="DATA:1EA2" entry="false"/>
+
+ <symbol name="CWG1PPS" address="DATA:1EB1" entry="false"/>
+
+ <symbol name="CLCIN0PPS" address="DATA:1EBB" entry="false"/>
+ <symbol name="CLCIN1PPS" address="DATA:1EBC" entry="false"/>
+ <symbol name="CLCIN2PPS" address="DATA:1EBD" entry="false"/>
+ <symbol name="CLCIN3PPS" address="DATA:1EBE" entry="false"/>
+
+ <symbol name="ADACTPPS" address="DATA:1EC3" entry="false"/>
+
+ <symbol name="SSP1CLKPPS" address="DATA:1EC5" entry="false"/>
+ <symbol name="SSP1DATPPS" address="DATA:1EC6" entry="false"/>
+ <symbol name="SSP1SSPPS" address="DATA:1EC7" entry="false"/>
+
+ <symbol name="RX1DTPPS" address="DATA:1ECB" entry="false"/>
+ <symbol name="TX1CKPPS" address="DATA:1ECC" entry="false"/>
+ <symbol name="RX2DTPPS" address="DATA:1ECD" entry="false"/>
+ <symbol name="TX2CKPPS" address="DATA:1ECE" entry="false"/>
+
+ <symbol name="RXYPPS_CONTROLS" address="DATA:1F0C" entry="false"/>
+
+ <symbol name="RA0PPS" address="DATA:1F10" entry="false"/>
+ <symbol name="RA1PPS" address="DATA:1F11" entry="false"/>
+ <symbol name="RA2PPS" address="DATA:1F12" entry="false"/>
+ <symbol name="RA3PPS" address="DATA:1F13" entry="false"/>
+ <symbol name="RA4PPS" address="DATA:1F14" entry="false"/>
+ <symbol name="RA5PPS" address="DATA:1F15" entry="false"/>
+
+ <symbol name="RB4PPS" address="DATA:1F1C" entry="false"/>
+ <symbol name="RB5PPS" address="DATA:1F1D" entry="false"/>
+ <symbol name="RB6PPS" address="DATA:1F1E" entry="false"/>
+ <symbol name="RB7PPS" address="DATA:1F1F" entry="false"/>
+ <symbol name="RC0PPS" address="DATA:1F20" entry="false"/>
+ <symbol name="RC1PPS" address="DATA:1F21" entry="false"/>
+ <symbol name="RC2PPS" address="DATA:1F22" entry="false"/>
+ <symbol name="RC3PPS" address="DATA:1F23" entry="false"/>
+ <symbol name="RC4PPS" address="DATA:1F24" entry="false"/>
+ <symbol name="RC5PPS" address="DATA:1F25" entry="false"/>
+ <symbol name="RC6PPS" address="DATA:1F26" entry="false"/>
+ <symbol name="RC7PPS" address="DATA:1F27" entry="false"/>
+
+ <symbol name="ANSELA" address="DATA:1F38" entry="false"/>
+ <symbol name="WPUA" address="DATA:1F39" entry="false"/>
+ <symbol name="ODCONA" address="DATA:1F3A" entry="false"/>
+ <symbol name="SLRCONA" address="DATA:1F3B" entry="false"/>
+ <symbol name="INLVLA" address="DATA:1F3C" entry="false"/>
+ <symbol name="IOCAP" address="DATA:1F3D" entry="false"/>
+ <symbol name="IOCAN" address="DATA:1F3E" entry="false"/>
+ <symbol name="IOCAF" address="DATA:1F3F" entry="false"/>
+
+ <symbol name="ANSELB" address="DATA:1F43" entry="false"/>
+ <symbol name="WPUB" address="DATA:1F44" entry="false"/>
+ <symbol name="ODCONB" address="DATA:1F45" entry="false"/>
+ <symbol name="SLRCONB" address="DATA:1F46" entry="false"/>
+ <symbol name="INLVLB" address="DATA:1F47" entry="false"/>
+ <symbol name="IOCBP" address="DATA:1F48" entry="false"/>
+ <symbol name="IOCBN" address="DATA:1F49" entry="false"/>
+ <symbol name="IOCBF" address="DATA:1F4A" entry="false"/>
+
+ <symbol name="ANSELC" address="DATA:1F4E" entry="false"/>
+ <symbol name="WPUC" address="DATA:1F4F" entry="false"/>
+ <symbol name="ODCONC" address="DATA:1F50" entry="false"/>
+ <symbol name="SLRCONC" address="DATA:1F51" entry="false"/>
+ <symbol name="INLVLC" address="DATA:1F52" entry="false"/>
+ <symbol name="IOCCP" address="DATA:1F53" entry="false"/>
+ <symbol name="IOCCN" address="DATA:1F54" entry="false"/>
+ <symbol name="IOCCF" address="DATA:1F55" entry="false"/>
+
+ <symbol name="OTHER_REGISTERS" address="DATA:1F8C" entry="false"/>
+
+ <symbol name="BSR_ICDSHAD" address="DATA:1FE3" entry="false"/>
+ <symbol name="STATUS_SHAD" address="DATA:1FE4" entry="false"/>
+ <symbol name="WREG_SHAD" address="DATA:1FE5" entry="false"/>
+ <symbol name="BSR_SHAD" address="DATA:1FE6" entry="false"/>
+ <symbol name="PCLATH_SHAD" address="DATA:1FE7" entry="false"/>
+ <symbol name="FSR0L_SHAD" address="DATA:1FE8" entry="false"/>
+ <symbol name="FSR0H_SHAD" address="DATA:1FE9" entry="false"/>
+ <symbol name="FSR1L_SHAD" address="DATA:1FEA" entry="false"/>
+ <symbol name="FSR1H_SHAD" address="DATA:1FEB" entry="false"/>
+
+ <symbol name="STKPTR" address="DATA:1FED" entry="false"/>
+ <symbol name="TOSL" address="DATA:1FEE" entry="false"/>
+ <symbol name="TOSH" address="DATA:1FEF" entry="false"/>
+
+ </default_symbols>
+ <default_memory_blocks>
+ <memory_block name="GPR" start_address="DATA:0000" mode="rw" length="0x2000" initialized="false"/>
+ </default_memory_blocks>
+</processor_spec>
diff --git a/Ghidra/Processors/PIC/data/languages/pic16f153xx.slaspec b/Ghidra/Processors/PIC/data/languages/pic16f153xx.slaspec
new file mode 100644
index 0000000000..40b1b60d6a
--- /dev/null
+++ b/Ghidra/Processors/PIC/data/languages/pic16f153xx.slaspec
@@ -0,0 +1,6 @@
+@define PROCESSOR "PIC_16F"
+@define PIC16F153XX ""
+
+@include "pic16.sinc"
+
+@include "pic16_instructions.sinc"
diff --git a/Ghidra/Processors/PIC/data/manuals/PIC-16F153xx.idx b/Ghidra/Processors/PIC/data/manuals/PIC-16F153xx.idx
new file mode 100644
index 0000000000..962eea7711
--- /dev/null
+++ b/Ghidra/Processors/PIC/data/manuals/PIC-16F153xx.idx
@@ -0,0 +1,51 @@
[email protected] [Microchip PIC16(L)F15325/45 (DS40001865D)]
+ADDFSR , 458
+ADDLW , 458
+ADDWF , 458
+ADDWFC , 458
+ANDLW , 458
+ANDWF , 458
+ASRF , 458
+BCF , 459
+BRA , 459
+BRW , 459
+BSF , 459
+BTFSC , 459
+BTFSS , 459
+CALL , 460
+CALLW , 460
+CLRF , 460
+CLRW , 460
+CLRWDT , 460
+COMF , 460
+DECF , 460
+DECFSZ , 461
+GOTO , 461
+INCF , 461
+INCFSZ , 461
+IORLW , 461
+IORWF , 461
+LSLF , 462