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1452-Intel-80960.patch
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1452-Intel-80960.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: mumbel <[email protected]>
Date: Sun, 21 Nov 2021 12:49:38 -0600
Subject: [PATCH] 1452: Intel 80960
squash i960
cspec
---
Ghidra/Processors/i960/Module.manifest | 0
Ghidra/Processors/i960/build.gradle | 27 +
Ghidra/Processors/i960/certification.manifest | 12 +
.../Processors/i960/data/languages/i960.cspec | 121 +
.../Processors/i960/data/languages/i960.ldefs | 29 +
.../i960/data/languages/i960.opinion | 16 +
.../Processors/i960/data/languages/i960.pspec | 43 +
.../Processors/i960/data/languages/i960.sinc | 1958 +++++++++++++++++
.../i960/data/languages/i960.slaspec | 4 +
.../i960/data/patterns/i960_patterns.xml | 50 +
.../i960/data/patterns/patternconstraints.xml | 5 +
Ghidra/Processors/i960/scripts/scrape.py | 1163 ++++++++++
.../format/elf/extend/I960_ElfExtension.java | 27 +
.../I960_ElfRelocationConstants.java | 27 +
.../relocation/I960_ElfRelocationHandler.java | 104 +
.../test/processors/I960_O0_EmulatorTest.java | 39 +
.../test/processors/I960_O3_EmulatorTest.java | 39 +
17 files changed, 3664 insertions(+)
create mode 100644 Ghidra/Processors/i960/Module.manifest
create mode 100644 Ghidra/Processors/i960/build.gradle
create mode 100644 Ghidra/Processors/i960/certification.manifest
create mode 100644 Ghidra/Processors/i960/data/languages/i960.cspec
create mode 100644 Ghidra/Processors/i960/data/languages/i960.ldefs
create mode 100644 Ghidra/Processors/i960/data/languages/i960.opinion
create mode 100644 Ghidra/Processors/i960/data/languages/i960.pspec
create mode 100644 Ghidra/Processors/i960/data/languages/i960.sinc
create mode 100644 Ghidra/Processors/i960/data/languages/i960.slaspec
create mode 100644 Ghidra/Processors/i960/data/patterns/i960_patterns.xml
create mode 100644 Ghidra/Processors/i960/data/patterns/patternconstraints.xml
create mode 100644 Ghidra/Processors/i960/scripts/scrape.py
create mode 100644 Ghidra/Processors/i960/src/main/java/ghidra/app/util/bin/format/elf/extend/I960_ElfExtension.java
create mode 100644 Ghidra/Processors/i960/src/main/java/ghidra/app/util/bin/format/elf/relocation/I960_ElfRelocationConstants.java
create mode 100644 Ghidra/Processors/i960/src/main/java/ghidra/app/util/bin/format/elf/relocation/I960_ElfRelocationHandler.java
create mode 100644 Ghidra/Processors/i960/src/test.processors/java/ghidra/test/processors/I960_O0_EmulatorTest.java
create mode 100644 Ghidra/Processors/i960/src/test.processors/java/ghidra/test/processors/I960_O3_EmulatorTest.java
diff --git a/Ghidra/Processors/i960/Module.manifest b/Ghidra/Processors/i960/Module.manifest
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/Ghidra/Processors/i960/build.gradle b/Ghidra/Processors/i960/build.gradle
new file mode 100644
index 0000000000..d3daf860b0
--- /dev/null
+++ b/Ghidra/Processors/i960/build.gradle
@@ -0,0 +1,27 @@
+/* ###
+ * IP: GHIDRA
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle"
+apply from: "$rootProject.projectDir/gradle/javaProject.gradle"
+apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle"
+apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle"
+apply from: "$rootProject.projectDir/gradle/processorProject.gradle"
+apply plugin: 'eclipse'
+eclipse.project.name = 'Processors i960'
+
+
+dependencies {
+ api project(':Base')
+}
diff --git a/Ghidra/Processors/i960/certification.manifest b/Ghidra/Processors/i960/certification.manifest
new file mode 100644
index 0000000000..dddb98acf4
--- /dev/null
+++ b/Ghidra/Processors/i960/certification.manifest
@@ -0,0 +1,12 @@
+##VERSION: 2.0
+Module.manifest||GHIDRA||||END|
+data/languages/i960.cspec||GHIDRA||||END|
+data/languages/i960.ldefs||GHIDRA||||END|
+data/languages/i960.opinion||GHIDRA||||END|
+data/languages/i960.pspec||GHIDRA||||END|
+data/languages/i960.sinc||GHIDRA||||END|
+data/languages/i960.slaspec||GHIDRA||||END|
+data/patterns/patternconstraints.xml||GHIDRA||||END|
+data/patterns/i960_patterns.xml||GHIDRA||||END|
+scripts/scrape.py||GHIDRA||||END|
+src/main/java/ghidra/app/util/bin/format/elf/extend/I960_ElfExtension.java||GHIDRA||||END|
diff --git a/Ghidra/Processors/i960/data/languages/i960.cspec b/Ghidra/Processors/i960/data/languages/i960.cspec
new file mode 100644
index 0000000000..d0f3510949
--- /dev/null
+++ b/Ghidra/Processors/i960/data/languages/i960.cspec
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<compiler_spec>
+ <data_organization>
+ <absolute_max_alignment value="0" />
+ <machine_alignment value="8" />
+ <default_alignment value="1" />
+ <default_pointer_alignment value="4" />
+ <pointer_size value="4" />
+ <short_size value="2" />
+ <integer_size value="4" />
+ <long_size value="4" />
+ <long_long_size value="8" />
+ <float_size value="4" />
+ <double_size value="8" />
+ <size_alignment_map>
+ <entry size="1" alignment="1" />
+ <entry size="2" alignment="2" />
+ <entry size="4" alignment="4" />
+ <entry size="8" alignment="4" />
+ </size_alignment_map>
+ </data_organization>
+ <global>
+ <range space="ram"/>
+ <!-- <register name="g0" /> -->
+ <!-- <register name="g1" /> -->
+ <!-- <register name="g2" /> -->
+ <!-- <register name="g3" /> -->
+ <!-- <register name="g4" /> -->
+ <!-- <register name="g5" /> -->
+ <!-- <register name="g6" /> -->
+ <!-- <register name="g7" /> -->
+ <!-- <register name="g8" /> -->
+ <!-- <register name="g9" /> -->
+ <!-- <register name="g10" /> -->
+ <!-- <register name="g11" /> -->
+ <!-- Up to 12 parameters can be passed by value -->
+ <register name="g12" />
+ <register name="g13" />
+ <register name="g14" />
+ <register name="fp" />
+ <register name="pc" />
+ <register name="ac" />
+ <register name="tc" />
+ </global>
+ <returnaddress>
+ <register name="rip"/>
+ </returnaddress>
+ <!-- <stackpointer register="sp" space="ram" growth="positive"/> -->
+ <stackpointer register="sp" space="ram" growth="positive"/>
+ <default_proto>
+ <prototype name="__stdcall" extrapop="0" stackshift="64">
+ <input>
+ <pentry minsize="1" maxsize="4">
+ <register name="g0"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g1"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g2"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g3"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g4"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g5"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g6"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g7"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g8"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g9"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g10"/>
+ </pentry>
+ <pentry minsize="1" maxsize="4">
+ <register name="g11"/>
+ </pentry>
+ </input>
+ <output>
+ <pentry minsize="1" maxsize="4">
+ <register name="g0"/>
+ </pentry>
+ <pentry minsize="5" maxsize="8">
+ <addr space="join" piece1="g1" piece2="g0" />
+ </pentry>
+ <!-- TODO g2 and g3 -->
+ </output>
+ <unaffected>
+ <register name="fp"/>
+ <register name="pfp"/>
+ <register name="sp"/>
+ <register name="rip"/>
+ <register name="r3"/>
+ <register name="r4"/>
+ <register name="r5"/>
+ <register name="r6"/>
+ <register name="r7"/>
+ <register name="r8"/>
+ <register name="r9"/>
+ <register name="r10"/>
+ <register name="r11"/>
+ <register name="r12"/>
+ <register name="r13"/>
+ <register name="r14"/>
+ <register name="r15"/>
+ </unaffected>
+ </prototype>
+ </default_proto>
+</compiler_spec>
diff --git a/Ghidra/Processors/i960/data/languages/i960.ldefs b/Ghidra/Processors/i960/data/languages/i960.ldefs
new file mode 100644
index 0000000000..ad22b352ec
--- /dev/null
+++ b/Ghidra/Processors/i960/data/languages/i960.ldefs
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<language_definitions>
+
+ <language processor="i960"
+ endian="little"
+ size="32"
+ variant="default"
+ version="1.2"
+ slafile="i960.sla"
+ processorspec="i960.pspec"
+ id="i960:LE:32:default">
+ <description>i960 80960</description>
+ <compiler name="default" spec="i960.cspec" id="default"/>
+ </language>
+ <language processor="i960"
+ endian="big"
+ instructionEndian="little"
+ size="32"
+ variant="lebe"
+ version="1.2"
+ slafile="i960.sla"
+ processorspec="i960.pspec"
+ id="i960:LEBE:32:lebe">
+ <description>i960 80960 LE instruction and BE data</description>
+ <compiler name="default" spec="i960.cspec" id="default"/>
+ </language>
+
+</language_definitions>
diff --git a/Ghidra/Processors/i960/data/languages/i960.opinion b/Ghidra/Processors/i960/data/languages/i960.opinion
new file mode 100644
index 0000000000..559996c50c
--- /dev/null
+++ b/Ghidra/Processors/i960/data/languages/i960.opinion
@@ -0,0 +1,16 @@
+<opinions>
+ <constraint loader="Executable and Linking Format (ELF)" compilerSpecID="default">
+ <constraint primary="19" processor="i960" endian="little" />
+ </constraint>
+ <constraint loader="Common Object File Format (COFF)" compilerSpecID="default">
+ <!-- CORE/CORE1 0x1000 -->
+ <!-- KB/SB 0x2000 -->
+ <!-- CA/CX 0x5000 -->
+ <!-- KA/SA 0x6000 -->
+ <!-- JX 0x7000 -->
+ <!-- HX 0x8000 -->
+ <!-- CORE2 0x9000 -->
+ <constraint primary="352" processor="i960" endian="little" /> <!-- RO text -->
+ <constraint primary="353" processor="i960" endian="little" /> <!-- RW text -->
+ </constraint>
+</opinions>
diff --git a/Ghidra/Processors/i960/data/languages/i960.pspec b/Ghidra/Processors/i960/data/languages/i960.pspec
new file mode 100644
index 0000000000..d1e44c9015
--- /dev/null
+++ b/Ghidra/Processors/i960/data/languages/i960.pspec
@@ -0,0 +1,43 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+<processor_spec>
+ <programcounter register="ip"/>
+
+ <default_symbols>
+ <symbol name="DLMCON" address="ram:0xFF008100" />
+ <symbol name="LMADR0" address="ram:0xFF008108" />
+ <symbol name="LMMR0" address="ram:0xFF00810C" />
+ <symbol name="LMADR1" address="ram:0xFF008110" />
+ <symbol name="LMMR1" address="ram:0xFF008114" />
+ <symbol name="IPB0" address="ram:0xFF008400" />
+ <symbol name="IPB1" address="ram:0xFF008404" />
+ <symbol name="DAB0" address="ram:0xFF008420" />
+ <symbol name="DAB1" address="ram:0xFF008424" />
+ <symbol name="BPCON" address="ram:0xFF008440" />
+ <symbol name="IPND" address="ram:0xFF008500" />
+ <symbol name="IMSK" address="ram:0xFF008504" />
+ <symbol name="ICON" address="ram:0xFF008510" />
+ <symbol name="IMAP0" address="ram:0xFF008520" />
+ <symbol name="IMAP1" address="ram:0xFF008524" />
+ <symbol name="IMAP2" address="ram:0xFF008528" />
+ <symbol name="PMCON0_1" address="ram:0xFF008600" />
+ <symbol name="PMCON2_3" address="ram:0xFF008608" />
+ <symbol name="PMCON4_5" address="ram:0xFF008610" />
+ <symbol name="PMCON6_7" address="ram:0xFF008618" />
+ <symbol name="PMCON8_9" address="ram:0xFF008620" />
+ <symbol name="PMCON10_11" address="ram:0xFF008628" />
+ <symbol name="PMCON12_13" address="ram:0xFF008630" />
+ <symbol name="PMCON14_15" address="ram:0xFF008638" />
+ <symbol name="BCON" address="ram:0xFF0086FC" />
+ <symbol name="PRCB" address="ram:0xFF008700" />
+ <symbol name="ISP" address="ram:0xFF008704" />
+ <symbol name="SSP" address="ram:0xFF008708" />
+ <symbol name="DEVICEID" address="ram:0xFF008710" />
+ <symbol name="TRR0" address="ram:0xFF000300" />
+ <symbol name="TCR0" address="ram:0xFF000304" />
+ <symbol name="TMR0" address="ram:0xFF000308" />
+ <symbol name="TRR1" address="ram:0xFF000310" />
+ <symbol name="TCR1" address="ram:0xFF000314" />
+ <symbol name="TMR1" address="ram:0xFF000318" />
+ </default_symbols>
+</processor_spec>
diff --git a/Ghidra/Processors/i960/data/languages/i960.sinc b/Ghidra/Processors/i960/data/languages/i960.sinc
new file mode 100644
index 0000000000..434ae77b2f
--- /dev/null
+++ b/Ghidra/Processors/i960/data/languages/i960.sinc
@@ -0,0 +1,1958 @@
+# i960 / 80960
+
+define alignment=4;
+
+define space ram type=ram_space size=4 default;
+
+define space register type=register_space size=4;
+
+#TODO slaspec or context value instead?
+@define SALIGN 4
+
+# Local Registers
+# r0 - pfp - previous frame pointer
+# r1 - sp - stack pointer
+# r2 - rip - return instruction pointer
+define register offset=0x00 size=4 [ pfp sp rip r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 ];
+
+# Global Registers
+# g15 - fp - frame pointer
+define register offset=0x40 size=4 [ g0 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 fp ];
+
+# SF
+define register offset=0x100 size=4 [ sf0 sf1 sf2 sf3 sf4 sf5 sf6 sf7 sf8 sf9 sf10 sf11 sf12 sf13 sf14 sf15 sf16 sf17 sf18 sf19 sf20 sf21 sf22 sf23 sf24 sf25 sf26 sf27 sf28 sf29 sf30 sf31 ];
+
+# 80-bit registers extended-real format
+define register offset=0x300 size=10 [ fp0 fp1 fp2 fp3 ];
+
+define register offset=0x200 size=4 [ pc ac ip tc ];
+
+
+# PFP return status
+# 000 - local/super call from super, local return
+# 001 - fault call, fault return
+# 011 - super call from user, trace enabled, super return, trace enable, PC=0 mode=0
+# 100 - reserved
+# 101 - reserved
+# 110 - stopped-interrupt call, stopped-interrupt return
+# 111 - interrupt call, interrupt return
+
+
+# PC Process Controls Register
+# PC [0,1] # Trace-Enable Bit
+# PC [1,1] # Execution-Mode Flag
+# PC [9,1] # Resume
+# PC [10,1] # Trace-Fault-Pending
+# PC [13,1] # State Flag
+# PC [16,5] # Priority Field
+# PC [21,11] # internal state
+
+# AC Arithmetic Controls Register
+# AC [0,3] # Condition Code Bits
+# AC [3,4] # Arithmetic status
+# AC [8,1] # Integer-Overflow Flag
+# AC [12,1] # Integer Overflow Mask Bit
+# AC [15,1] # No-Imprecise-Faults Bit
+# AC [16,1] # Floating overflow flag
+# AC [17,1] # Floating underflow flag
+# AC [18,1] # Floating invalid-op flag
+# AC [19,1] # Floating zero-divide flag
+# AC [20,1] # Floating inexct flag
+# AC [24,1] # Floating overflow mask
+# AC [25,1] # Floating underflow mask
+# AC [26,1] # Floating invalid-op mask
+# AC [27,1] # Floating zero-divide mask
+# AC [28,1] # Floating inexact mask
+# AC [29,1] # Floating-Point Normalizing Mode
+# AC [30,2] # Floating-Point Rounding Control
+
+# TC Trace-Controls
+# TC[1,1] # instruction trace mode
+# TC[2,1] # branch trace mode
+# TC[3,1] # call trace mode
+# TC[4,1] # return trace mode
+# TC[5,1] # prereturn trace mode
+# TC[6,1] # supervise trace mode
+# TC[7,1] # breakpoint trace mode
+# TC[17,1] # instruction trace event
+# TC[18,1] # branch trace event
+# TC[19,1] # call trace event
+# TC[20,1] # return trace event
+# TC[21,1] # prereturn trace event
+# TC[22,1] # supervisor trace event
+# TC[23,1] # breakpoint trace event
+
+# condition codes
+# 010 true
+# 000 false
+# 000 unordered
+# 001 gt
+# 010 eq
+# 011 gte
+# 100 lt
+# 101 ne
+# 110 lte
+# 111 ordered
+# 01X carry out
+# 0X1 overflow
+
+# arithmetic status, s=sign
+# s000 Zero
+# s001 Denom
+# s010 Normal
+# s011 inf
+# s100 quiet
+# s101 signal
+# s110 resv
+
+
+define token instr (32)
+ op2731=(27,31)
+ op2431=(24,31)
+ op2426=(24,26)
+ op1923=(19,23)
+ freg1923=(19,23)
+ reg1923=(19,23)
+ sfr1923=(19,23)
+ freg1418=(14,18)
+ reg1418=(14,18)
+ sfr1418=(14,18)
+ op1418=(14,18)
+ M1=(13,13)
+ m3=(13,13)
+ m2=(12,12)
+ m1=(11,11)
+ op0710=(7,10)
+ s2=(6,6)
+ s1=(5,5)
+ freg0004=(0,4)
+ reg0004=(0,4)
+ sfr0004=(0,4)
+ op0004=(0,4)
+ sop0212=(2,12) signed
+ t=(1,1)
+ S2=(0,0)
+ sop0223=(2,23) signed
+ op0000=(0,0)
+ mode1213=(12,13)
+ mode1011=(10,11)
+ offset0011=(0,11)
+ op0709=(7,9)
+ op0506=(5,6)
+;
+
+
+define token instr2 (32)
+ sop3263=(0,31) signed
+ op3263=(0,31)
+;
+
+attach variables [ reg0004 reg1418 reg1923 ]
+ [ pfp sp rip r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 g0 g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 fp ];
+
+attach variables [ sfr0004 sfr1418 sfr1923 ]
+ [ sf0 sf1 sf2 sf3 sf4 sf5 sf6 sf7 sf8 sf9 sf10 sf11 sf12 sf13 sf14 sf15 sf16 sf17 sf18 sf19 sf20 sf21 sf22 sf23 sf24 sf25 sf26 sf27 sf28 sf29 sf30 sf31 ];
+
+attach variables [ freg0004 freg1418 freg1923 ]
+ [ fp0 fp1 fp2 fp3 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ];
+
+
+macro f_cmp_set_ac(v0, v1) {
+ ac[2,1] = v0 f< v1;
+ ac[1,1] = v0 f== v1;
+ ac[0,1] = v0 f> v1;
+}
+
+macro s_cmp_set_ac(v0, v1) {
+ ac[2,1] = v0 s< v1;
+ ac[1,1] = v0 == v1;
+ ac[0,1] = v0 s> v1;
+}
+
+macro cmp_set_ac(v0, v1) {
+ ac[2,1] = v0 < v1;
+ ac[1,1] = v0 == v1;
+ ac[0,1] = v0 > v1;
+}
+
+#TODO does it make sense to make macros for 4-byte?
+
+macro l_copy_efa_to_reg(sefa, dreg) {
+ *[register]:4 (dreg + 0x0) = *[ram]:4 (sefa + 0x0);
+ *[register]:4 (dreg + 0x4) = *[ram]:4 (sefa + 0x4);
+}
+
+macro t_copy_efa_to_reg(sefa, dreg) {
+ l_copy_efa_to_reg(sefa, dreg);
+ *[register]:4 (dreg + 0x8) = *[ram]:4 (sefa + 0x8);
+}
+
+macro q_copy_efa_to_reg(sefa, dreg) {
+ t_copy_efa_to_reg(sefa, dreg);
+ *[register]:4 (dreg + 0xc) = *[ram]:4 (sefa + 0xc);
+}
+
+macro l_copy_reg_to_efa(sreg, defa) {
+ *[ram]:4 (defa + 0x0) = *[register]:4 (sreg + 0x0);
+ *[ram]:4 (defa + 0x4) = *[register]:4 (sreg + 0x4);
+}
+
+macro t_copy_reg_to_efa(sreg, defa) {
+ l_copy_reg_to_efa(sreg, defa);
+ *[ram]:4 (defa + 0x8) = *[register]:4 (sreg + 0x8);
+}
+
+macro q_copy_reg_to_efa(sreg, defa) {
+ t_copy_reg_to_efa(sreg, defa);
+ *[ram]:4 (defa + 0xc) = *[register]:4 (sreg + 0xc);
+}
+
+macro l_copy_reg_to_reg(sreg, dreg) {
+ *[register]:4 (dreg + 0x0) = *[register]:4 (sreg + 0x0);
+ *[register]:4 (dreg + 0x4) = *[register]:4 (sreg + 0x4);
+}
+
+macro t_copy_reg_to_reg(sreg, dreg) {
+ l_copy_reg_to_reg(sreg, dreg);
+ *[register]:4 (dreg + 0x8) = *[register]:4 (sreg + 0x8);
+}
+
+macro q_copy_reg_to_reg(sreg, dreg) {
+ t_copy_reg_to_reg(sreg, dreg);
+ *[register]:4 (dreg + 0xc) = *[register]:4 (sreg + 0xc);
+}
+
+macro l_copy_efa_to_efa(sefa, defa) {
+ *[ram]:4 (defa + 0x0) = *[ram]:4 (sefa + 0x0);
+ *[ram]:4 (defa + 0x4) = *[ram]:4 (sefa + 0x4);
+}
+
+macro t_copy_efa_to_efa(sefa, defa) {
+ l_copy_efa_to_efa(sefa, defa);
+ *[ram]:4 (defa + 0x8) = *[ram]:4 (sefa + 0x8);
+}
+
+macro q_copy_efa_to_efa(sefa, defa) {
+ t_copy_efa_to_efa(sefa, defa);
+ *[ram]:4 (defa + 0xc) = *[ram]:4 (sefa + 0xc);
+}
+
+macro l_copy_lit_to_reg(slit, dreg) {
+ *[register]:4 (dreg + 0x0) = slit[0,32];
+ *[register]:4 (dreg + 0x4) = slit[32,32];
+}
+
+macro t_copy_lit_to_reg(slit, dreg) {
+ l_copy_lit_to_reg(slit, dreg);
+ *[register]:4 (dreg + 0x8) = slit[64,32];
+}
+
+macro q_copy_lit_to_reg(slit, dreg) {
+ t_copy_lit_to_reg(slit, dreg);
+ *[register]:4 (dreg + 0xc) = slit[96,32];
+}
+
+macro l_copy_reg_to_lit(sreg, dlit) {
+ dlit = zext(*[register]:4 (sreg + 0x0));
+ dlit = dlit | zext((*[register]:4 (sreg + 0x0)) << 32);
+}
+
+macro t_copy_reg_to_lit(sreg, dlit) {
+ l_copy_reg_to_lit(sreg, dlit);
+ dlit = dlit | zext((*[register]:4 (sreg + 0x0)) << 64);
+}
+
+macro q_copy_reg_to_lit(sreg, dlit) {
+ t_copy_reg_to_lit(sreg, dlit);
+ dlit = dlit | zext((*[register]:4 (sreg + 0x0)) << 96);
+}
+
+
+
+regS1: op0004 is op0004 & m1=1 & s1=0 { local tmp:4 = op0004; export tmp; }
+regS1: reg0004 is reg0004 & m1=0 & s1=0 { export reg0004; }
+regS1: sfr0004 is sfr0004 & m1=0 & s1=1 { export sfr0004; }
+
+regS2: op1418 is op1418 & m2=1 & s2=0 { local tmp:4 = op1418; export tmp; }
+regS2: reg1418 is reg1418 & m2=0 & s2=0 { export reg1418; }
+regS2: sfr1418 is sfr1418 & m2=0 & s2=1 { export sfr1418; }
+
+regS2l: op1418 is op1418 & m2=1 & s2=0 { local tmp:8 = op1418; export tmp; }
+regS2l: reg1418 is reg1418 & m2=0 & s2=0 { local tmp:4 = ®1418; export *[register]:8 tmp; }
+regS2l: sfr1418 is sfr1418 & m2=0 & s2=1 { local tmp:4 = &sfr1418; export *[register]:8 tmp; }
+
+regSD: reg1923 is reg1923 & m3=0 { export reg1923; }
+#TODO This looks awful to handle
+# regSDl: reg1923 is reg1923 & m3=0 { local tmp:4 = ®1923; export *[register]:8 tmp; }
+# regSDq: reg1923 is reg1923 & m3=0 { local tmp:4 = ®1923; export *[register]:12 tmp; }
+
+#SEE Encoding of Src1 and Src2 Fields in REG Format
+# Same encoding is used for COBR
+#TODO The FP encoding still looks off and probably needs the same table look ups
+# as fregS1
+cobrS1: reg1923 is reg1923 & M1=0 & S2=0 { export reg1923; }
+cobrS2: reg1418 is reg1418 & M1=0 & S2=0 { export reg1418; }
+cobrSD: reg1923 is reg1923 & M1=0 & S2=0 { export reg1923; }
+
+cobrS1: op1923 is op1923 & M1=1 & S2=0 { local tmp:4 = op1923; export tmp; }
+cobrS2: reg1418 is reg1418 & M1=1 & S2=0 { export reg1418; }
+
+cobrS1: sfr1923 is sfr1923 & M1=0 & S2=1 { export sfr1923; }
+cobrS2: sfr1418 is sfr1418 & M1=0 & S2=1 { export sfr1418; }
+#TODO not sure if this can happend
+cobrSD: sfr1923 is sfr1923 & M1=0 & S2=1 { export sfr1923; }
+
+cobrS1: op1923 is op1923 & M1=1 & S2=1 & t=0 { local tmp:4 = op1923; export tmp; }
+cobrS2: sfr1418 is sfr1418 & M1=1 & S2=1 & t=0 { export sfr1418; }
+
+
+# reals: 1 reg (Real), 2 regs (Long Real), or 3 regs (Extended Real)
+
+#TODO int2float is not correct, maybe float2float?
+fregS1: reg0004 is reg0004 & m1=0 & s1=0 { local tmp:10 = int2float(reg0004); export tmp; }
+fregS1: freg0004 is freg0004 & m1=1 & s1=0 & op0004 < 4 { local tmp:10 = freg0004; export tmp; }
+fregS1: "+0.0" is m1=1 & s1=0 & op0004=0x10 { local tmp:10 = int2float(0:1); export tmp; }
+fregS1: "+1.0" is m1=1 & s1=0 & op0004=0x16 { local tmp:10 = int2float(1:1); export tmp; }
+fregS1l: reg0004 is reg0004 & m1=0 & s1=0 { local reg:4 = ®0004; local val:8 = *[register]:8 reg; local tmp:10 = int2float(val); export tmp; }
+fregS1l: freg0004 is freg0004 & m1=1 & s1=0 & op0004 < 4 { local tmp:10 = freg0004; export tmp; }
+fregS1l: "+0.0" is m1=1 & s1=0 & op0004=0x10 { local tmp:10 = int2float(0:1); export tmp; }
+fregS1l: "+1.0" is m1=1 & s1=0 & op0004=0x16 { local tmp:10 = int2float(1:1); export tmp; }
+fregS1e: reg0004 is reg0004 & m1=0 & s1=0 { local reg:4 = ®0004; local val:12 = *[register]:12 reg; local tmp:10 = int2float(val); export tmp; }
+fregS1e: freg0004 is freg0004 & m1=1 & s1=0 & op0004 < 4 { local tmp:10 = freg0004; export tmp; }
+fregS1e: "+0.0" is m1=1 & s1=0 & op0004=0x10 { local tmp:10 = int2float(0:1); export tmp; }
+fregS1e: "+1.0" is m1=1 & s1=0 & op0004=0x16 { local tmp:10 = int2float(1:1); export tmp; }
+
+
+fregS2: reg1418 is reg1418 & m2=0 & s2=0 { local tmp:10 = int2float(reg1418); export tmp; }
+fregS2: freg1418 is freg1418 & m2=1 & s2=0 & op1418 < 4 { local tmp:10 = freg1418; export tmp; }
+fregS2: "+0.0" is m2=1 & s2=0 & op1418=0x10 { local tmp:10 = int2float(0:1); export tmp; }
+fregS2: "+1.0" is m2=1 & s2=0 & op1418=0x16 { local tmp:10 = int2float(1:1); export tmp; }
+fregS2l: reg1418 is reg1418 & m2=0 & s2=0 { local reg:4 = ®1418; local val:8 = *[register]:8 reg; local tmp:10 = int2float(val); export tmp; }
+fregS2l: freg1418 is freg1418 & m2=1 & s2=0 & op1418 < 4 { local tmp:10 = freg1418; export tmp; }
+fregS2l: "+0.0" is m2=1 & s2=0 & op1418=0x10 { local tmp:10 = int2float(0:1); export tmp; }
+fregS2l: "+1.0" is m2=1 & s2=0 & op1418=0x16 { local tmp:10 = int2float(1:1); export tmp; }
+fregS2e: reg1418 is reg1418 & m2=0 & s2=0 { local reg:4 = ®1418; local val:12 = *[register]:12 reg; local tmp:10 = int2float(val); export tmp; }
+fregS2e: freg1418 is freg1418 & m2=1 & s2=0 & op1418 < 4 { local tmp:10 = freg1418; export tmp; }
+fregS2e: "+0.0" is m2=1 & s2=0 & op1418=0x10 { local tmp:10 = int2float(0:1); export tmp; }
+fregS2e: "+1.0" is m2=1 & s2=0 & op1418=0x16 { local tmp:10 = int2float(1:1); export tmp; }
+
+#TODO This looks awful to handle
+fregSD: reg1923 is reg1923 & m3=0 { local tmp:4 = ®1923; export *[register]:10 tmp; }
+fregSD: freg1923 is freg1923 & m3=1 & op1923 < 4 { export freg1923; }
+
+fregSDl: reg1923 is reg1923 & m3=0 { local tmp:10 = int2float(reg1923); export tmp; }
+fregSDl: freg1923 is freg1923 & m3=1 & op1923 < 4 { local tmp:10 = freg1923; export tmp; }
+
+fregSDe: reg1923 is reg1923 & m3=0 { local tmp:10 = int2float(reg1923); export tmp; }
+fregSDe: freg1923 is freg1923 & m3=1 & op1923 < 4 { local tmp:10 = freg1923; export tmp; }
+
+
+scale: imm is (op0709=0|op0709=1|op0709=2|op0709=3|op0709=4) & op0709 [ imm = 1 << op0709; ] { export *[const]:4 imm; }
+
+efa: offset0011 is offset0011 & mode1213=0 { local tmp:4 = offset0011; export tmp;}
+efa: op3263 is mode1213=3 & mode1011=0 & op0506=0 ; op3263 { local tmp:4 = op3263; export tmp; }
+
+efa: offset0011 (reg1418) is offset0011 & reg1418 & mode1213=2 { local tmp:4 = reg1418 + offset0011; export tmp; }
+efa: (reg1418) is reg1418 & mode1213=1 & mode1011=0 & op0506=0 { local tmp:4 = reg1418; export tmp; }
+efa: reloc (ip) is ip & mode1213=1 & mode1011=1 & op0506=0 ; sop3263 [ reloc = sop3263 + 8; ] { local tmp:4 = reloc + inst_start; export tmp; }
+efa: (reg1418) [reg0004 * scale] is scale & reg0004 & reg1418 & mode1213=1 & mode1011=3 & op0506=0 { local tmp:4 = (scale * reg0004) + reg1418; export tmp; }
+efa: sop3263 (reg1418) is reg1418 & mode1213=3 & mode1011=1 & op0506=0 ; sop3263 { local tmp:4 = sop3263 + reg1418; export tmp; }
+efa: sop3263 [reg0004 * scale] is reg0004 & scale & mode1213=3 & mode1011=2 & op0506=0 ; sop3263 { local tmp:4 = sop3263 + (reg0004 * scale); export tmp; }
+efa: sop3263 (reg1418) [reg0004 * scale] is reg1418 & reg0004 & scale & mode1213=3 & mode1011=3 & op0506=0 ; sop3263 { local tmp:4 = sop3263 + reg1418 + (reg0004 * scale); export tmp; }
+
+
+
+disp0212: reloc is sop0212 [ reloc = ((sop0212 << 2) + inst_start) & 0xfffffffc; ] { export *[ram]:4 reloc; }
+
+disp0223: reloc is sop0223 [ reloc = ((sop0223 << 2) + inst_start) & 0xfffffffc; ] { export *[ram]:4 reloc; }
+
+# conditions
+cc: "no" is op2426=0 { local tmp:1 = 0; export tmp; }
+cc: "g" is op2426=1 { local tmp:1 = (ac[0,1] == 1); export tmp; }
+cc: "e" is op2426=2 { local tmp:1 = (ac[1,1] == 1); export tmp; }
+cc: "ge" is op2426=3 { local tmp:1 = ((ac[0,1] | ac[1,1]) == 1); export tmp; }
+cc: "l" is op2426=4 { local tmp:1 = (ac[2,1] == 1); export tmp; }
+cc: "ne" is op2426=5 { local tmp:1 = ((ac[0,1] | ac[2,1]) == 1); export tmp; }
+cc: "le" is op2426=6 { local tmp:1 = ((ac[1,1] | ac[2,1]) == 1); export tmp; }
+cc: "o" is op2426=7 { local tmp:1 = 1; export tmp; }
+
+
+define pcodeop atan;
+define pcodeop cos;
+define pcodeop sin;
+define pcodeop tan;
+define pcodeop log2;
+define pcodeop flushreg;
+define pcodeop syscall;
+define pcodeop syncf;
+define pcodeop scanbit;
+define pcodeop spanbit;
+define pcodeop send;
+define pcodeop fault;
+
+# addc
+:addc regS1, regS2, regSD is op2431=0x5b & op0710=0x0 & regS1 & regS2 & regSD
+{
+ local tmp:5 = zext(regS1) + zext(regS2) + zext(ac[1,1]);
+ ac[0,3] = 0;
+ ac[0,1] = (regS1[31,1] == regS2[31,1]) & (regS2[31,1] != tmp[31,1]);
+ ac[1,1] = tmp[32,1];
+ regSD = tmp:4;
+}
+
+
+# addi
+:addi regS1, regS2, regSD is op2431=0x59 & op0710=0x1 & regS1 & regS2 & regSD
+{
+ ac[8,1] = scarry(regS1, regS2);
+ regSD = regS1 + regS2;
+}
+
+
+# addino op2431=0x78
+# addig op2431=0x79
+# addie op2431=0x7a
+# addige op2431=0x7b
+# addil op2431=0x7c
+# addine op2431=0x7d
+# addile op2431=0x7e
+# addio op2431=0x7f
+:addi^cc regS1, regS2, regSD is op2731=0b01111 & cc & op0710=0x1 & regS1 & regS2 & regSD
+{
+ if (!cc) goto inst_next;
+ ac[8,1] = scarry(regS1, regS2);
+ regSD = regS1 + regS2;
+}
+
+
+# addo
+:addo regS1, regS2, regSD is op2431=0x59 & op0710=0x0 & regS1 & regS2 & regSD
+{
+ regSD = regS1 + regS2;
+}
+
+
+# addono op2431=0x78
+# addog op2431=0x79
+# addoe op2431=0x7a
+# addoge op2431=0x7b
+# addol op2431=0x7c
+# addone op2431=0x7d
+# addole op2431=0x7e
+# addoo op2431=0x7f
+:addo^cc regS1, regS2, regSD is op2731=0b01111 & cc & op0710=0x0 & regS1 & regS2 & regSD
+{
+ if (!cc) goto inst_next;
+ regSD = regS1 + regS2;
+}
+
+
+# addr
+:addr fregS1, fregS2, fregSD is op2431=0x78 & op0710=0xf & fregS1 & fregS2 & fregSD
+{
+ fregSD = fregS1 f+ fregS2;
+}
+
+
+# addrl 8,8,8
+:addrl fregS1l, fregS2l, fregSDl is op2431=0x79 & op0710=0xf & fregS1l & fregS2l & fregSDl
+{
+ fregSDl = fregS1l f+ fregS2l;
+}
+
+
+# alterbit
+:alterbit regS1, regS2, regSD is op2431=0x58 & op0710=0xf & regS1 & regS2 & regSD
+{
+ local bitpos = 1 << regS1;
+ local tmp0:4 = regS2 & ~bitpos;
+ local tmp1:4 = regS2 | bitpos;
+ regSD = tmp1;
+ if (ac[1,1]) goto inst_next;
+ regSD = tmp0;
+}
+
+
+# and
+:and regS1, regS2, regSD is op2431=0x58 & op0710=0x1 & regS1 & regS2 & regSD
+{
+ regSD = regS2 & regS1;
+}
+
+
+# andnot
+:andnot regS1, regS2, regSD is op2431=0x58 & op0710=0x2 & regS1 & regS2 & regSD
+{
+ regSD = regS2 & ~regS1;
+}
+
+
+# atadd
+:atadd regS1, regS2, regSD is op2431=0x61 & op0710=0x2 & regS1 & regS2 & regSD
+{
+ local addr:4 = regS1 & 0xfffffffc;
+ local tmp:4 = *[ram]:4 addr;
+ *[ram]:4 addr = (tmp + regS2);
+ regSD = tmp;
+}
+
+
+# atanr
+:atanr fregS1, fregS2, fregSD is op2431=0x68 & op0710=0x0 & fregS1 & fregS2 & fregSD
+{
+ local tmp:10 = fregS2 f/ fregS1;
+ fregSD = atan(tmp);
+}
+
+
+# atanrl 8,8,8
+:atanrl fregS1l, fregS2l, fregSDl is op2431=0x69 & op0710=0x0 & fregS1l & fregS2l & fregSDl
+{
+ local tmp:10 = fregS2l f/ fregS1l;
+ fregSDl = atan(tmp);
+}
+
+
+# atmod
+:atmod regS1, regS2, regSD is op2431=0x61 & op0710=0x0 & regS1 & regS2 & regSD
+{
+ local addr = regS1 & 0xfffffffc;
+ local tmp:4 = *[ram]:4 addr;
+ *[ram]:4 addr = (tmp & ~regS2) | (regSD & regS2);
+ regSD = tmp;
+}
+
+
+# b
+:b disp0223 is op2431=0x8 & op0000=0x0 & disp0223
+{
+ goto disp0223;
+}
+
+
+# bal
+:bal disp0223 is op2431=0xb & op0000=0x0 & disp0223
+{
+ g14 = inst_next;
+ goto disp0223;
+}
+
+
+# balx
+:balx efa, reg1923 is ( op2431=0x85 & reg1923 ) ... & efa
+{
+ local ea:4 = efa;
+ reg1923 = inst_next;
+ goto [ea];
+}
+
+
+# bbc
+:bbc cobrS1, cobrS2, disp0212 is op2431=0x30 & cobrS1 & cobrS2 & disp0212
+{
+ ac[0,3] = 2;
+ if (((1<<cobrS1) & cobrS2) != 0) goto disp0212;
+ ac[1,1] = 0;
+}
+
+
+# bbs
+:bbs cobrS1, cobrS2, disp0212 is op2431=0x37 & cobrS1 & cobrS2 & disp0212
+{
+ ac[0,3] = 2;
+ if (((1<<cobrS1) & cobrS2) == 0) goto disp0212;
+ ac[1,1] = 0;
+}
+
+
+# bno op2431=0x10
+# bg op2431=0x11
+# be op2431=0x12
+# bge op2431=0x13
+# bl op2431=0x14
+# bne op2431=0x15
+# ble op2431=0x16
+# bo op2431=0x17
+:b^cc disp0223 is op2731=0b00010 & cc & op0000=0x0 & disp0223
+{
+ if (cc) goto disp0223;
+}
+
+
+# bswap
+:bswap regS1, regSD is op2431=0x5a & op0710=0xd & regS1 & regSD
+{
+ local tmp:4 = regS1;
+ regSD = ((tmp & 0xff) << 24) | ((tmp & 0xff00) << 8) | ((tmp & 0xff0000) >> 8) | ((tmp & 0xff000000) >> 24);
+}
+
+
+# bx
+:bx efa is ( op2431=0x84 ) ... & efa
+{
+ goto [efa];
+}
+
+# Local Call Operation ( call or callx )
+# 1. Stores the RIP in current local-register r2.
+# 2. Allocates a new set of local registers for the called procedure.
+# 3. Allocates a new frame on the procedure stack.
+# 4. Changes the instruction pointer to point to the first instruction in the called procedure.
+# 5. Stores the PFP in new local-register rOo
+# 6. Stores the FP for the new frame in global register g15.
+# 7. Allocates a save area for the new local registers in the new stack frame.
+# 8. Stores the SP in new local-register r1
+
+# Local Return Operation
+# 1. Sets the FP in global register g15 to the value of the PFP in current local-register rOo
+# 2. Deallocates the current local registers for the procedure that initiated the return and
+# switches to the local registers assigned to the procedure being returned to.
+# 3. Deallocates the stack frame for the procedure that initiated the return.
+# 4. Sets the IP to the value of the RIP in new local~register r2.
+
+macro alloc_register_set() {
+ local regtmp = &pfp;
+ local alignfp = fp & 0xffffffc0;
+ *[ram]:0x40 alignfp = *[register]:0x40 regtmp;
+}
+
+macro dealloc_register_set() {
+ local regtmp = &pfp;
+ local alignfp = fp & 0xffffffc0;
+ *[register]:0x40 regtmp = *[ram]:0x40 alignfp;
+}
+
+
+# call
+:call disp0223 is op2431=0x9 & op0000=0x0 & disp0223
+{
+ local temp:4 = (sp + ($(SALIGN) * 16 - 1)) & ~($(SALIGN) * 16 - 1);
+ rip = inst_next;
+ alloc_register_set();
+ ip = disp0223;
+ pfp = fp;
+ fp = temp;
+ sp = temp + 64;
+ call disp0223;
+}
+
+
+# calls
+:calls regS1 is op2431=0x66 & op0710=0x0 & regS1
+{
+ #TODO impl
+ syscall(regS1);
+}
+
+
+# callx
+:callx efa is ( op2431=0x86 ) ... & efa
+{
+ local temp:4 = (sp + ($(SALIGN) * 16 - 1)) & ~($(SALIGN) * 16 - 1);
+ local targ:4 = efa;
+ rip = inst_next;
+ alloc_register_set();
+ ip = targ;
+ pfp = fp;
+ fp = temp;
+ sp = temp + 64;
+ call [targ];
+}
+
+